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Use arrays or initializer lists to feed ArrayRefs instead of SmallVector where possible.
No functionality change intended. llvm-svn: 274431
1 parent 270cf12 commit 3bc1edf

9 files changed

+28
-55
lines changed

llvm/lib/Analysis/ScalarEvolution.cpp

+2-6
Original file line numberDiff line numberDiff line change
@@ -3022,9 +3022,7 @@ ScalarEvolution::getGEPExpr(Type *PointeeType, const SCEV *BaseExpr,
30223022

30233023
const SCEV *ScalarEvolution::getSMaxExpr(const SCEV *LHS,
30243024
const SCEV *RHS) {
3025-
SmallVector<const SCEV *, 2> Ops;
3026-
Ops.push_back(LHS);
3027-
Ops.push_back(RHS);
3025+
SmallVector<const SCEV *, 2> Ops = {LHS, RHS};
30283026
return getSMaxExpr(Ops);
30293027
}
30303028

@@ -3125,9 +3123,7 @@ ScalarEvolution::getSMaxExpr(SmallVectorImpl<const SCEV *> &Ops) {
31253123

31263124
const SCEV *ScalarEvolution::getUMaxExpr(const SCEV *LHS,
31273125
const SCEV *RHS) {
3128-
SmallVector<const SCEV *, 2> Ops;
3129-
Ops.push_back(LHS);
3130-
Ops.push_back(RHS);
3126+
SmallVector<const SCEV *, 2> Ops = {LHS, RHS};
31313127
return getUMaxExpr(Ops);
31323128
}
31333129

llvm/lib/Target/AArch64/AArch64CollectLOH.cpp

+4-11
Original file line numberDiff line numberDiff line change
@@ -628,10 +628,7 @@ static void computeADRP(const InstrToInstrs &UseToDefs,
628628
continue;
629629
}
630630
DEBUG(dbgs() << "Record AdrpAdrp:\n" << *L2 << '\n' << *L1 << '\n');
631-
SmallVector<const MachineInstr *, 2> Args;
632-
Args.push_back(L2);
633-
Args.push_back(L1);
634-
AArch64FI.addLOHDirective(MCLOH_AdrpAdrp, Args);
631+
AArch64FI.addLOHDirective(MCLOH_AdrpAdrp, {L1, L2});
635632
++NumADRPSimpleCandidate;
636633
}
637634
#ifdef DEBUG
@@ -765,13 +762,9 @@ static bool registerADRCandidate(const MachineInstr &Use,
765762
"ADD already involved in LOH.");
766763
DEBUG(dbgs() << "Record AdrpAdd\n" << Def << '\n' << Use << '\n');
767764

768-
SmallVector<const MachineInstr *, 2> Args;
769-
Args.push_back(&Def);
770-
Args.push_back(&Use);
771-
772-
AArch64FI.addLOHDirective(Use.getOpcode() == AArch64::ADDXri ? MCLOH_AdrpAdd
773-
: MCLOH_AdrpLdrGot,
774-
Args);
765+
AArch64FI.addLOHDirective(
766+
Use.getOpcode() == AArch64::ADDXri ? MCLOH_AdrpAdd : MCLOH_AdrpLdrGot,
767+
{&Def, &Use});
775768
return true;
776769
}
777770

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

+6-8
Original file line numberDiff line numberDiff line change
@@ -3535,11 +3535,8 @@ SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,
35353535
SDValue Chain = DAG.getEntryNode();
35363536
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
35373537

3538-
SmallVector<SDValue, 2> Ops;
3539-
Ops.push_back(Chain);
3540-
Ops.push_back(SymAddr);
3541-
3542-
Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3538+
Chain =
3539+
DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, {Chain, SymAddr});
35433540
SDValue Glue = Chain.getValue(1);
35443541

35453542
return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
@@ -8931,9 +8928,10 @@ static SDValue performPostLD1Combine(SDNode *N,
89318928
LoadSDN->getMemOperand());
89328929

89338930
// Update the uses.
8934-
SmallVector<SDValue, 2> NewResults;
8935-
NewResults.push_back(SDValue(LD, 0)); // The result of load
8936-
NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8931+
SDValue NewResults[] = {
8932+
SDValue(LD, 0), // The result of load
8933+
SDValue(UpdN.getNode(), 2) // Chain
8934+
};
89378935
DCI.CombineTo(LD, NewResults);
89388936
DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
89398937
DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h

+4-4
Original file line numberDiff line numberDiff line change
@@ -166,15 +166,15 @@ class AArch64FunctionInfo : public MachineFunctionInfo {
166166
SmallVector<const MachineInstr *, 3> Args;
167167

168168
public:
169-
typedef SmallVectorImpl<const MachineInstr *> LOHArgs;
169+
typedef ArrayRef<const MachineInstr *> LOHArgs;
170170

171-
MILOHDirective(MCLOHType Kind, const LOHArgs &Args)
171+
MILOHDirective(MCLOHType Kind, LOHArgs Args)
172172
: Kind(Kind), Args(Args.begin(), Args.end()) {
173173
assert(isValidMCLOHType(Kind) && "Invalid LOH directive type!");
174174
}
175175

176176
MCLOHType getKind() const { return Kind; }
177-
const LOHArgs &getArgs() const { return Args; }
177+
LOHArgs getArgs() const { return Args; }
178178
};
179179

180180
typedef MILOHDirective::LOHArgs MILOHArgs;
@@ -183,7 +183,7 @@ class AArch64FunctionInfo : public MachineFunctionInfo {
183183
const MILOHContainer &getLOHContainer() const { return LOHContainerSet; }
184184

185185
/// Add a LOH directive of this @p Kind and this @p Args.
186-
void addLOHDirective(MCLOHType Kind, const MILOHArgs &Args) {
186+
void addLOHDirective(MCLOHType Kind, MILOHArgs Args) {
187187
LOHContainerSet.push_back(MILOHDirective(Kind, Args));
188188
LOHRelated.insert(Args.begin(), Args.end());
189189
}

llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp

+1-4
Original file line numberDiff line numberDiff line change
@@ -182,11 +182,8 @@ Value *GenericToNVVM::getOrInsertCVTA(Module *M, Function *F,
182182
// Insert the address space conversion.
183183
Type *ResultType =
184184
PointerType::get(Type::getInt8Ty(Context), llvm::ADDRESS_SPACE_GENERIC);
185-
SmallVector<Type *, 2> ParamTypes;
186-
ParamTypes.push_back(ResultType);
187-
ParamTypes.push_back(DestTy);
188185
Function *CVTAFunction = Intrinsic::getDeclaration(
189-
M, Intrinsic::nvvm_ptr_global_to_gen, ParamTypes);
186+
M, Intrinsic::nvvm_ptr_global_to_gen, {ResultType, DestTy});
190187
CVTA = Builder.CreateCall(CVTAFunction, CVTA, "cvta");
191188
// Another bitcast from i8 * to <the element type of GVType> * is
192189
// required.

llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp

+1-4
Original file line numberDiff line numberDiff line change
@@ -73,10 +73,7 @@ namespace {
7373
DebugLoc DL = MI->getDebugLoc();
7474
unsigned GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
7575
unsigned Opc1, Opc2;
76-
SmallVector<unsigned, 4> OrigRegs;
77-
OrigRegs.push_back(OutReg);
78-
OrigRegs.push_back(InReg);
79-
OrigRegs.push_back(GPR3);
76+
const unsigned OrigRegs[] = {OutReg, InReg, GPR3};
8077

8178
switch (MI->getOpcode()) {
8279
default:

llvm/lib/Target/Sparc/SparcISelLowering.cpp

+6-7
Original file line numberDiff line numberDiff line change
@@ -2076,16 +2076,15 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
20762076
SDValue Symbol = withTargetFlags(Op, callTF, DAG);
20772077

20782078
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2079-
SmallVector<SDValue, 4> Ops;
2080-
Ops.push_back(Chain);
2081-
Ops.push_back(Callee);
2082-
Ops.push_back(Symbol);
2083-
Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
20842079
const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
20852080
DAG.getMachineFunction(), CallingConv::C);
20862081
assert(Mask && "Missing call preserved mask for calling convention");
2087-
Ops.push_back(DAG.getRegisterMask(Mask));
2088-
Ops.push_back(InFlag);
2082+
SDValue Ops[] = {Chain,
2083+
Callee,
2084+
Symbol,
2085+
DAG.getRegister(SP::O0, PtrVT),
2086+
DAG.getRegisterMask(Mask),
2087+
InFlag};
20892088
Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
20902089
InFlag = Chain.getValue(1);
20912090
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true),

llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp

+2-6
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,6 @@ static bool isZeroLengthArray(Type *Ty) {
179179

180180
bool XCoreLowerThreadLocal::lowerGlobal(GlobalVariable *GV) {
181181
Module *M = GV->getParent();
182-
LLVMContext &Ctx = M->getContext();
183182
if (!GV->isThreadLocal())
184183
return false;
185184

@@ -210,11 +209,8 @@ bool XCoreLowerThreadLocal::lowerGlobal(GlobalVariable *GV) {
210209
Function *GetID = Intrinsic::getDeclaration(GV->getParent(),
211210
Intrinsic::xcore_getid);
212211
Value *ThreadID = Builder.CreateCall(GetID, {});
213-
SmallVector<Value *, 2> Indices;
214-
Indices.push_back(Constant::getNullValue(Type::getInt64Ty(Ctx)));
215-
Indices.push_back(ThreadID);
216-
Value *Addr =
217-
Builder.CreateInBoundsGEP(NewGV->getValueType(), NewGV, Indices);
212+
Value *Addr = Builder.CreateInBoundsGEP(NewGV->getValueType(), NewGV,
213+
{Builder.getInt64(0), ThreadID});
218214
U->replaceUsesOfWith(GV, Addr);
219215
}
220216

llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp

+2-5
Original file line numberDiff line numberDiff line change
@@ -633,11 +633,8 @@ bool GCOVProfiler::emitProfileArcs() {
633633
Value *Sel = Builder.CreateSelect(BI->getCondition(),
634634
Builder.getInt64(Edge),
635635
Builder.getInt64(Edge + 1));
636-
SmallVector<Value *, 2> Idx;
637-
Idx.push_back(Builder.getInt64(0));
638-
Idx.push_back(Sel);
639-
Value *Counter = Builder.CreateInBoundsGEP(Counters->getValueType(),
640-
Counters, Idx);
636+
Value *Counter = Builder.CreateInBoundsGEP(
637+
Counters->getValueType(), Counters, {Builder.getInt64(0), Sel});
641638
Value *Count = Builder.CreateLoad(Counter);
642639
Count = Builder.CreateAdd(Count, Builder.getInt64(1));
643640
Builder.CreateStore(Count, Counter);

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