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Richard Osborne
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Add instruction encodings / disassembly support for 2r instructions.
llvm-svn: 170323
1 parent 016967e commit 3a0d5cc

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4 files changed

+222
-70
lines changed

4 files changed

+222
-70
lines changed

‎llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

+66-1
Original file line numberDiff line numberDiff line change
@@ -67,12 +67,26 @@ static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
6767
return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
6868
}
6969

70-
7170
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
7271
unsigned RegNo,
7372
uint64_t Address,
7473
const void *Decoder);
7574

75+
static DecodeStatus Decode2RInstruction(MCInst &Inst,
76+
unsigned RegNo,
77+
uint64_t Address,
78+
const void *Decoder);
79+
80+
static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
81+
unsigned RegNo,
82+
uint64_t Address,
83+
const void *Decoder);
84+
85+
static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
86+
unsigned RegNo,
87+
uint64_t Address,
88+
const void *Decoder);
89+
7690
#include "XCoreGenDisassemblerTables.inc"
7791

7892
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@@ -87,6 +101,57 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
87101
return MCDisassembler::Success;
88102
}
89103

104+
static DecodeStatus
105+
Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
106+
unsigned Combined = fieldFromInstruction(Insn, 6, 5) +
107+
fieldFromInstruction(Insn, 5, 1) * 5 - 27;
108+
if (Combined >= 9)
109+
return MCDisassembler::Fail;
110+
111+
unsigned Op1High = Combined % 3;
112+
unsigned Op2High = Combined / 3;
113+
Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
114+
Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
115+
return MCDisassembler::Success;
116+
}
117+
118+
static DecodeStatus
119+
Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
120+
const void *Decoder) {
121+
unsigned Op1, Op2;
122+
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
123+
if (S == MCDisassembler::Success) {
124+
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
125+
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
126+
}
127+
return S;
128+
}
129+
130+
static DecodeStatus
131+
DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
132+
const void *Decoder) {
133+
unsigned Op1, Op2;
134+
DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
135+
if (S == MCDisassembler::Success) {
136+
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
137+
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
138+
}
139+
return S;
140+
}
141+
142+
static DecodeStatus
143+
Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
144+
const void *Decoder) {
145+
unsigned Op1, Op2;
146+
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
147+
if (S == MCDisassembler::Success) {
148+
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
149+
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
150+
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
151+
}
152+
return S;
153+
}
154+
90155
MCDisassembler::DecodeStatus
91156
XCoreDisassembler::getInstruction(MCInst &instr,
92157
uint64_t &Size,

‎llvm/lib/Target/XCore/XCoreInstrFormats.td

+16-1
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,23 @@ class _FLU10<dag outs, dag ins, string asmstr, list<dag> pattern>
7373
: InstXCore<4, outs, ins, asmstr, pattern> {
7474
}
7575

76-
class _F2R<dag outs, dag ins, string asmstr, list<dag> pattern>
76+
class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
7777
: InstXCore<2, outs, ins, asmstr, pattern> {
78+
let Inst{15-11} = opc{5-1};
79+
let Inst{4} = opc{0};
80+
let DecoderMethod = "Decode2RInstruction";
81+
}
82+
83+
// 2R with first operand as both a source and a destination.
84+
class _F2RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
85+
list<dag> pattern> : _F2R<opc, outs, ins, asmstr, pattern> {
86+
let DecoderMethod = "Decode2RSrcDstInstruction";
87+
}
88+
89+
// Same as 2R with last two operands swapped
90+
class _FR2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
91+
: _F2R<opc, outs, ins, asmstr, pattern> {
92+
let DecoderMethod = "DecodeR2RInstruction";
7893
}
7994

8095
class _FRUS<dag outs, dag ins, string asmstr, list<dag> pattern>

‎llvm/lib/Target/XCore/XCoreInstrInfo.td

+66-68
Original file line numberDiff line numberDiff line change
@@ -344,10 +344,9 @@ multiclass FU10_LU10_np<string OpcStr> {
344344

345345
// Two operand short
346346

347-
class F2R_np<string OpcStr> : _F2R<
348-
(outs GRRegs:$dst), (ins GRRegs:$b),
349-
!strconcat(OpcStr, " $dst, $b"),
350-
[]>;
347+
class F2R_np<bits<6> opc, string OpcStr> :
348+
_F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
349+
!strconcat(OpcStr, " $dst, $b"), []>;
351350

352351
// Two operand long
353352

@@ -753,13 +752,11 @@ def BL_lu10 : _FLU10<
753752

754753
// Two operand short
755754
// TODO eet, eef, tsetmr
756-
def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
757-
"not $dst, $b",
758-
[(set GRRegs:$dst, (not GRRegs:$b))]>;
755+
def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
756+
"not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
759757

760-
def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
761-
"neg $dst, $b",
762-
[(set GRRegs:$dst, (ineg GRRegs:$b))]>;
758+
def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
759+
"neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
763760

764761
let Constraints = "$src1 = $dst" in {
765762
def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
@@ -777,114 +774,119 @@ def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
777774
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
778775
immBitp:$src2))]>;
779776

780-
def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
777+
def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src2, GRRegs:$src1),
781778
"zext $dst, $src2",
782779
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
783780
GRRegs:$src2))]>;
784781

785-
def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
786-
"andnot $dst, $src2",
787-
[(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
782+
def ANDNOT_2r :
783+
_F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
784+
"andnot $dst, $src2",
785+
[(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
788786
}
789787

790788
let isReMaterializable = 1, neverHasSideEffects = 1 in
791789
def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
792790
"mkmsk $dst, $size",
793791
[]>;
794792

795-
def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
796-
"mkmsk $dst, $size",
797-
[(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
793+
def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
794+
"mkmsk $dst, $size",
795+
[(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
798796

799797
def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type),
800798
"getr $dst, $type",
801799
[(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
802800

803-
def GETTS_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
804-
"getts $dst, res[$r]",
805-
[(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
801+
def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
802+
"getts $dst, res[$r]",
803+
[(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
806804

807-
def SETPT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
808-
"setpt res[$r], $val",
809-
[(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
805+
def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
806+
"setpt res[$r], $val",
807+
[(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
810808

811-
def OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
812-
"outct res[$r], $val",
813-
[(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
809+
def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
810+
"outct res[$r], $val",
811+
[(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
814812

815-
def OUTCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val),
816-
"outct res[$r], $val",
817-
[(int_xcore_outct GRRegs:$r, immUs:$val)]>;
813+
def OUTCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
814+
"outct res[$r], $val",
815+
[(int_xcore_outct GRRegs:$r, immUs:$val)]>;
818816

819-
def OUTT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
820-
"outt res[$r], $val",
821-
[(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
817+
def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
818+
"outt res[$r], $val",
819+
[(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
822820

823-
def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
824-
"out res[$r], $val",
825-
[(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
821+
def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
822+
"out res[$r], $val",
823+
[(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
826824

827825
let Constraints = "$src = $dst" in
828-
def OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
829-
"outshr res[$r], $src",
830-
[(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r,
831-
GRRegs:$src))]>;
826+
def OUTSHR_2r :
827+
_F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
828+
"outshr res[$r], $src",
829+
[(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
832830

833-
def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
834-
"inct $dst, res[$r]",
835-
[(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
831+
def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
832+
"inct $dst, res[$r]",
833+
[(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
836834

837-
def INT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
838-
"int $dst, res[$r]",
839-
[(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
835+
def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
836+
"int $dst, res[$r]",
837+
[(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
840838

841-
def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
839+
def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
842840
"in $dst, res[$r]",
843841
[(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
844842

845843
let Constraints = "$src = $dst" in
846-
def INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
847-
"inshr $dst, res[$r]",
848-
[(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r,
849-
GRRegs:$src))]>;
844+
def INSHR_2r :
845+
_F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
846+
"inshr $dst, res[$r]",
847+
[(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
850848

851-
def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
852-
"chkct res[$r], $val",
853-
[(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
849+
def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
850+
"chkct res[$r], $val",
851+
[(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
854852

855-
def CHKCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val),
853+
def CHKCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
856854
"chkct res[$r], $val",
857855
[(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
858856

859-
def TESTCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src),
857+
def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
860858
"testct $dst, res[$src]",
861859
[(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
862860

863-
def TESTWCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src),
861+
def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
864862
"testwct $dst, res[$src]",
865863
[(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
866864

867-
def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
868-
"setd res[$r], $val",
869-
[(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
865+
def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
866+
"setd res[$r], $val",
867+
[(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
870868

871-
def GETST_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
869+
def SETPSC_l2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
870+
"setpsc res[$src1], $src2",
871+
[(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
872+
873+
def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
872874
"getst $dst, res[$r]",
873875
[(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
874876

875-
def INITSP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
877+
def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
876878
"init t[$t]:sp, $src",
877879
[(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
878880

879-
def INITPC_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
881+
def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
880882
"init t[$t]:pc, $src",
881883
[(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
882884

883-
def INITCP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
885+
def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
884886
"init t[$t]:cp, $src",
885887
[(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
886888

887-
def INITDP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
889+
def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
888890
"init t[$t]:dp, $src",
889891
[(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
890892

@@ -930,10 +932,6 @@ def SETRDY_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
930932
"setrdy res[$src1], $src2",
931933
[(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
932934

933-
def SETPSC_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
934-
"setpsc res[$src1], $src2",
935-
[(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
936-
937935
def PEEK_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
938936
"peek $dst, res[$src]",
939937
[(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;

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