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MC] Provide an MCTargetOptions to implementors of MCAsmBackendCtorTy, NFC
Some targets, notably AArch64 for ILP32, have different relocation encodings based upon the ABI. This is an enabling change, so a future patch can use the ABIName from MCTargetOptions to chose which relocations to use. Tested using check-llvm. The corresponding change to clang is in: http://reviews.llvm.org/D16538 Patch by: Joel Jones Differential Revision: https://reviews.llvm.org/D16213 llvm-svn: 276654
1 parent fe58327 commit 373d7d3

25 files changed

+114
-55
lines changed

‎llvm/include/llvm/Support/TargetRegistry.h

+8-4
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,8 @@ class Target {
112112
TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
113113
typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
114114
const MCRegisterInfo &MRI,
115-
const Triple &TT, StringRef CPU);
115+
const Triple &TT, StringRef CPU,
116+
const MCTargetOptions &Options);
116117
typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
117118
const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
118119
const MCTargetOptions &Options);
@@ -365,10 +366,12 @@ class Target {
365366
///
366367
/// \param TheTriple The target triple string.
367368
MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
368-
StringRef TheTriple, StringRef CPU) const {
369+
StringRef TheTriple, StringRef CPU,
370+
const MCTargetOptions &Options)
371+
const {
369372
if (!MCAsmBackendCtorFn)
370373
return nullptr;
371-
return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU);
374+
return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU, Options);
372375
}
373376

374377
/// createMCAsmParser - Create a target specific assembly parser.
@@ -1071,7 +1074,8 @@ template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
10711074

10721075
private:
10731076
static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,
1074-
const Triple &TheTriple, StringRef CPU) {
1077+
const Triple &TheTriple, StringRef CPU,
1078+
const MCTargetOptions &Options) {
10751079
return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
10761080
}
10771081
};

‎llvm/lib/CodeGen/LLVMTargetMachine.cpp

+6-3
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,8 @@ bool LLVMTargetMachine::addPassesToEmitFile(
224224
MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
225225

226226
MCAsmBackend *MAB =
227-
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
227+
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
228+
Options.MCOptions);
228229
auto FOut = llvm::make_unique<formatted_raw_ostream>(Out);
229230
MCStreamer *S = getTarget().createAsmStreamer(
230231
*Context, std::move(FOut), Options.MCOptions.AsmVerbose,
@@ -238,7 +239,8 @@ bool LLVMTargetMachine::addPassesToEmitFile(
238239
// emission fails.
239240
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
240241
MCAsmBackend *MAB =
241-
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
242+
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
243+
Options.MCOptions);
242244
if (!MCE || !MAB)
243245
return true;
244246

@@ -293,7 +295,8 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
293295
MCCodeEmitter *MCE =
294296
getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
295297
MCAsmBackend *MAB =
296-
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
298+
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
299+
Options.MCOptions);
297300
if (!MCE || !MAB)
298301
return true;
299302

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

+5-4
Original file line numberDiff line numberDiff line change
@@ -574,7 +574,8 @@ void ELFAArch64AsmBackend::processFixupValue(
574574
MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
575575
const MCRegisterInfo &MRI,
576576
const Triple &TheTriple,
577-
StringRef CPU) {
577+
StringRef CPU,
578+
const MCTargetOptions &Options) {
578579
if (TheTriple.isOSBinFormatMachO())
579580
return new DarwinAArch64AsmBackend(T, MRI);
580581

@@ -586,10 +587,10 @@ MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
586587
MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
587588
const MCRegisterInfo &MRI,
588589
const Triple &TheTriple,
589-
StringRef CPU) {
590+
StringRef CPU,
591+
const MCTargetOptions &Options) {
590592
assert(TheTriple.isOSBinFormatELF() &&
591593
"Big endian is only supported for ELF targets!");
592594
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
593-
return new ELFAArch64AsmBackend(T, OSABI,
594-
/*IsLittleEndian=*/false);
595+
return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/false);
595596
}

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

+5-2
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ class MCRegisterInfo;
2727
class MCObjectWriter;
2828
class MCStreamer;
2929
class MCSubtargetInfo;
30+
class MCTargetOptions;
3031
class MCTargetStreamer;
3132
class StringRef;
3233
class Target;
@@ -43,10 +44,12 @@ MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
4344
MCContext &Ctx);
4445
MCAsmBackend *createAArch64leAsmBackend(const Target &T,
4546
const MCRegisterInfo &MRI,
46-
const Triple &TT, StringRef CPU);
47+
const Triple &TT, StringRef CPU,
48+
const MCTargetOptions &Options);
4749
MCAsmBackend *createAArch64beAsmBackend(const Target &T,
4850
const MCRegisterInfo &MRI,
49-
const Triple &TT, StringRef CPU);
51+
const Triple &TT, StringRef CPU,
52+
const MCTargetOptions &Options);
5053

5154
MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
5255
uint8_t OSABI,

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -171,7 +171,8 @@ class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
171171

172172
MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
173173
const MCRegisterInfo &MRI,
174-
const Triple &TT, StringRef CPU) {
174+
const Triple &TT, StringRef CPU,
175+
const MCTargetOptions &Options) {
175176
// Use 64-bit ELF for amdgcn
176177
return new ELFAMDGPUAsmBackend(T, TT);
177178
}

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h

+3-1
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ class MCInstrInfo;
2727
class MCObjectWriter;
2828
class MCRegisterInfo;
2929
class MCSubtargetInfo;
30+
class MCTargetOptions;
3031
class Target;
3132
class Triple;
3233
class raw_pwrite_stream;
@@ -44,7 +45,8 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
4445
MCContext &Ctx);
4546

4647
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
47-
const Triple &TT, StringRef CPU);
48+
const Triple &TT, StringRef CPU,
49+
const MCTargetOptions &Options);
4850

4951
MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
5052
bool HasRelocationAddend,

‎llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

+13-8
Original file line numberDiff line numberDiff line change
@@ -1111,6 +1111,7 @@ static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {
11111111
MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
11121112
const MCRegisterInfo &MRI,
11131113
const Triple &TheTriple, StringRef CPU,
1114+
const MCTargetOptions &Options,
11141115
bool isLittle) {
11151116
switch (TheTriple.getObjectFormat()) {
11161117
default:
@@ -1131,24 +1132,28 @@ MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
11311132

11321133
MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
11331134
const MCRegisterInfo &MRI,
1134-
const Triple &TT, StringRef CPU) {
1135-
return createARMAsmBackend(T, MRI, TT, CPU, true);
1135+
const Triple &TT, StringRef CPU,
1136+
const MCTargetOptions &Options) {
1137+
return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
11361138
}
11371139

11381140
MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
11391141
const MCRegisterInfo &MRI,
1140-
const Triple &TT, StringRef CPU) {
1141-
return createARMAsmBackend(T, MRI, TT, CPU, false);
1142+
const Triple &TT, StringRef CPU,
1143+
const MCTargetOptions &Options) {
1144+
return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
11421145
}
11431146

11441147
MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
11451148
const MCRegisterInfo &MRI,
1146-
const Triple &TT, StringRef CPU) {
1147-
return createARMAsmBackend(T, MRI, TT, CPU, true);
1149+
const Triple &TT, StringRef CPU,
1150+
const MCTargetOptions &Options) {
1151+
return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
11481152
}
11491153

11501154
MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
11511155
const MCRegisterInfo &MRI,
1152-
const Triple &TT, StringRef CPU) {
1153-
return createARMAsmBackend(T, MRI, TT, CPU, false);
1156+
const Triple &TT, StringRef CPU,
1157+
const MCTargetOptions &Options) {
1158+
return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
11541159
}

‎llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

+10-4
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ class MCObjectWriter;
2828
class MCRegisterInfo;
2929
class MCSubtargetInfo;
3030
class MCStreamer;
31+
class MCTargetOptions;
3132
class MCRelocationInfo;
3233
class MCTargetStreamer;
3334
class StringRef;
@@ -66,21 +67,26 @@ MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
6667

6768
MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
6869
const Triple &TT, StringRef CPU,
70+
const MCTargetOptions &Options,
6971
bool IsLittleEndian);
7072

7173
MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
72-
const Triple &TT, StringRef CPU);
74+
const Triple &TT, StringRef CPU,
75+
const MCTargetOptions &Options);
7376

7477
MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
75-
const Triple &TT, StringRef CPU);
78+
const Triple &TT, StringRef CPU,
79+
const MCTargetOptions &Options);
7680

7781
MCAsmBackend *createThumbLEAsmBackend(const Target &T,
7882
const MCRegisterInfo &MRI,
79-
const Triple &TT, StringRef CPU);
83+
const Triple &TT, StringRef CPU,
84+
const MCTargetOptions &Options);
8085

8186
MCAsmBackend *createThumbBEAsmBackend(const Target &T,
8287
const MCRegisterInfo &MRI,
83-
const Triple &TT, StringRef CPU);
88+
const Triple &TT, StringRef CPU,
89+
const MCTargetOptions &Options);
8490

8591
// Construct a PE/COFF machine code streamer which will generate a PE/COFF
8692
// object file.

‎llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -96,12 +96,14 @@ MCObjectWriter *BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
9696

9797
MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
9898
const MCRegisterInfo &MRI,
99-
const Triple &TT, StringRef CPU) {
99+
const Triple &TT, StringRef CPU,
100+
const MCTargetOptions&) {
100101
return new BPFAsmBackend(/*IsLittleEndian=*/true);
101102
}
102103

103104
MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
104105
const MCRegisterInfo &MRI,
105-
const Triple &TT, StringRef CPU) {
106+
const Triple &TT, StringRef CPU,
107+
const MCTargetOptions&) {
106108
return new BPFAsmBackend(/*IsLittleEndian=*/false);
107109
}

‎llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h

+5-2
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ class MCInstrInfo;
2525
class MCObjectWriter;
2626
class MCRegisterInfo;
2727
class MCSubtargetInfo;
28+
class MCTargetOptions;
2829
class StringRef;
2930
class Target;
3031
class Triple;
@@ -43,9 +44,11 @@ MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
4344
MCContext &Ctx);
4445

4546
MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
46-
const Triple &TT, StringRef CPU);
47+
const Triple &TT, StringRef CPU,
48+
const MCTargetOptions &Options);
4749
MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
48-
const Triple &TT, StringRef CPU);
50+
const Triple &TT, StringRef CPU,
51+
const MCTargetOptions &Options);
4952

5053
MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS,
5154
uint8_t OSABI, bool IsLittleEndian);

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -745,7 +745,8 @@ class HexagonAsmBackend : public MCAsmBackend {
745745
namespace llvm {
746746
MCAsmBackend *createHexagonAsmBackend(Target const &T,
747747
MCRegisterInfo const & /*MRI*/,
748-
const Triple &TT, StringRef CPU) {
748+
const Triple &TT, StringRef CPU,
749+
const MCTargetOptions &Options) {
749750
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
750751
return new HexagonAsmBackend(T, OSABI, CPU);
751752
}

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h

+3-1
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ class MCInstrInfo;
2828
class MCObjectWriter;
2929
class MCRegisterInfo;
3030
class MCSubtargetInfo;
31+
class MCTargetOptions;
3132
class Target;
3233
class Triple;
3334
class StringRef;
@@ -47,7 +48,8 @@ MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
4748

4849
MCAsmBackend *createHexagonAsmBackend(const Target &T,
4950
const MCRegisterInfo &MRI,
50-
const Triple &TT, StringRef CPU);
51+
const Triple &TT, StringRef CPU,
52+
const MCTargetOptions &Options);
5153

5254
MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
5355
uint8_t OSABI, StringRef CPU);

‎llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

+8-4
Original file line numberDiff line numberDiff line change
@@ -482,27 +482,31 @@ void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
482482
// MCAsmBackend
483483
MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
484484
const MCRegisterInfo &MRI,
485-
const Triple &TT, StringRef CPU) {
485+
const Triple &TT, StringRef CPU,
486+
const MCTargetOptions &Options) {
486487
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
487488
/*Is64Bit*/ false);
488489
}
489490

490491
MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
491492
const MCRegisterInfo &MRI,
492-
const Triple &TT, StringRef CPU) {
493+
const Triple &TT, StringRef CPU,
494+
const MCTargetOptions &Options) {
493495
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
494496
/*Is64Bit*/ false);
495497
}
496498

497499
MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
498500
const MCRegisterInfo &MRI,
499-
const Triple &TT, StringRef CPU) {
501+
const Triple &TT, StringRef CPU,
502+
const MCTargetOptions &Options) {
500503
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
501504
}
502505

503506
MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
504507
const MCRegisterInfo &MRI,
505-
const Triple &TT, StringRef CPU) {
508+
const Triple &TT, StringRef CPU,
509+
const MCTargetOptions &Options) {
506510
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
507511
/*Is64Bit*/ true);
508512
}

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

+9-4
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ class MCInstrInfo;
2424
class MCObjectWriter;
2525
class MCRegisterInfo;
2626
class MCSubtargetInfo;
27+
class MCTargetOptions;
2728
class StringRef;
2829
class Target;
2930
class Triple;
@@ -44,16 +45,20 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
4445

4546
MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
4647
const MCRegisterInfo &MRI,
47-
const Triple &TT, StringRef CPU);
48+
const Triple &TT, StringRef CPU,
49+
const MCTargetOptions &Options);
4850
MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
4951
const MCRegisterInfo &MRI,
50-
const Triple &TT, StringRef CPU);
52+
const Triple &TT, StringRef CPU,
53+
const MCTargetOptions &Options);
5154
MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
5255
const MCRegisterInfo &MRI,
53-
const Triple &TT, StringRef CPU);
56+
const Triple &TT, StringRef CPU,
57+
const MCTargetOptions &Options);
5458
MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
5559
const MCRegisterInfo &MRI,
56-
const Triple &TT, StringRef CPU);
60+
const Triple &TT, StringRef CPU,
61+
const MCTargetOptions &Options);
5762

5863
MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
5964
bool IsLittleEndian, bool Is64Bit);

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -230,7 +230,8 @@ namespace {
230230

231231
MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
232232
const MCRegisterInfo &MRI,
233-
const Triple &TT, StringRef CPU) {
233+
const Triple &TT, StringRef CPU,
234+
const MCTargetOptions &Options) {
234235
if (TT.isOSDarwin())
235236
return new DarwinPPCAsmBackend(T);
236237

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

+3-1
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ class MCInstrInfo;
2828
class MCObjectWriter;
2929
class MCRegisterInfo;
3030
class MCSubtargetInfo;
31+
class MCTargetOptions;
3132
class Target;
3233
class Triple;
3334
class StringRef;
@@ -43,7 +44,8 @@ MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
4344
MCContext &Ctx);
4445

4546
MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
46-
const Triple &TT, StringRef CPU);
47+
const Triple &TT, StringRef CPU,
48+
const MCTargetOptions &Options);
4749

4850
/// Construct an PPC ELF object writer.
4951
MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -300,6 +300,7 @@ namespace {
300300

301301
MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
302302
const MCRegisterInfo &MRI,
303-
const Triple &TT, StringRef CPU) {
303+
const Triple &TT, StringRef CPU,
304+
const MCTargetOptions &Options) {
304305
return new ELFSparcAsmBackend(T, TT.getOS());
305306
}

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