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[llvm] Use true/false instead of 1/0 (NFC)
Identified with modernize-use-bool-literals.
1 parent 34646a2 commit 2aed081

39 files changed

+72
-70
lines changed

‎llvm/examples/Kaleidoscope/Chapter9/toy.cpp

+5-5
Original file line numberDiff line numberDiff line change
@@ -477,7 +477,7 @@ static std::unique_ptr<ExprAST> ParseIdentifierExpr() {
477477
getNextToken(); // eat (
478478
std::vector<std::unique_ptr<ExprAST>> Args;
479479
if (CurTok != ')') {
480-
while (1) {
480+
while (true) {
481481
if (auto Arg = ParseExpression())
482482
Args.push_back(std::move(Arg));
483483
else
@@ -587,7 +587,7 @@ static std::unique_ptr<ExprAST> ParseVarExpr() {
587587
if (CurTok != tok_identifier)
588588
return LogError("expected identifier after var");
589589

590-
while (1) {
590+
while (true) {
591591
std::string Name = IdentifierStr;
592592
getNextToken(); // eat identifier.
593593

@@ -671,7 +671,7 @@ static std::unique_ptr<ExprAST> ParseUnary() {
671671
static std::unique_ptr<ExprAST> ParseBinOpRHS(int ExprPrec,
672672
std::unique_ptr<ExprAST> LHS) {
673673
// If this is a binop, find its precedence.
674-
while (1) {
674+
while (true) {
675675
int TokPrec = GetTokPrecedence();
676676

677677
// If this is a binop that binds at least as tightly as the current binop,
@@ -1365,7 +1365,7 @@ static void HandleTopLevelExpression() {
13651365

13661366
/// top ::= definition | external | expression | ';'
13671367
static void MainLoop() {
1368-
while (1) {
1368+
while (true) {
13691369
switch (CurTok) {
13701370
case tok_eof:
13711371
return;
@@ -1447,7 +1447,7 @@ int main() {
14471447
// but we'd like actual source locations.
14481448
KSDbgInfo.TheCU = DBuilder->createCompileUnit(
14491449
dwarf::DW_LANG_C, DBuilder->createFile("fib.ks", "."),
1450-
"Kaleidoscope Compiler", 0, "", 0);
1450+
"Kaleidoscope Compiler", false, "", 0);
14511451

14521452
// Run the main "interpreter loop" now.
14531453
MainLoop();

‎llvm/include/llvm/LTO/legacy/LTOModule.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ struct LTOModule {
4040
struct NameAndAttributes {
4141
StringRef name;
4242
uint32_t attributes = 0;
43-
bool isFunction = 0;
43+
bool isFunction = false;
4444
const GlobalValue *symbol = nullptr;
4545
};
4646

‎llvm/include/llvm/Transforms/IPO/Attributor.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -2361,8 +2361,8 @@ struct DecIntegerState : public IntegerStateBase<base_ty, 0, ~base_ty(0)> {
23612361
};
23622362

23632363
/// Simple wrapper for a single bit (boolean) state.
2364-
struct BooleanState : public IntegerStateBase<bool, 1, 0> {
2365-
using super = IntegerStateBase<bool, 1, 0>;
2364+
struct BooleanState : public IntegerStateBase<bool, true, false> {
2365+
using super = IntegerStateBase<bool, true, false>;
23662366
using base_t = IntegerStateBase::base_t;
23672367

23682368
BooleanState() : super() {}

‎llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -781,7 +781,7 @@ Error BitcodeAnalyzer::parseBlock(unsigned BlockID, unsigned IndentLevel,
781781
uint64_t MetadataIndexOffset = 0;
782782

783783
// Read all the records for this block.
784-
while (1) {
784+
while (true) {
785785
if (Stream.AtEndOfStream())
786786
return reportError("Premature end of bitstream");
787787

‎llvm/lib/Bitcode/Reader/MetadataLoader.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1105,7 +1105,7 @@ void MetadataLoader::MetadataLoaderImpl::lazyLoadOneMetadata(
11051105
void MetadataLoader::MetadataLoaderImpl::resolveForwardRefsAndPlaceholders(
11061106
PlaceholderQueue &Placeholders) {
11071107
DenseSet<unsigned> Temporaries;
1108-
while (1) {
1108+
while (true) {
11091109
// Populate Temporaries with the placeholders that haven't been loaded yet.
11101110
Placeholders.getTemporaries(MetadataList, Temporaries);
11111111

@@ -1632,7 +1632,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata(
16321632
Record.size() <= 16 ? true : Record[16],
16331633
Record.size() <= 17 ? false : Record[17],
16341634
Record.size() <= 18 ? 0 : Record[18],
1635-
Record.size() <= 19 ? 0 : Record[19],
1635+
Record.size() <= 19 ? false : Record[19],
16361636
Record.size() <= 20 ? nullptr : getMDString(Record[20]),
16371637
Record.size() <= 21 ? nullptr : getMDString(Record[21]));
16381638

‎llvm/lib/CodeGen/LiveDebugVariables.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ class DbgVariableValue {
152152
}
153153
}
154154

155-
DbgVariableValue() : LocNoCount(0), WasIndirect(0), WasList(0) {}
155+
DbgVariableValue() : LocNoCount(0), WasIndirect(false), WasList(false) {}
156156
DbgVariableValue(const DbgVariableValue &Other)
157157
: LocNoCount(Other.LocNoCount), WasIndirect(Other.getWasIndirect()),
158158
WasList(Other.getWasList()), Expression(Other.getExpression()) {

‎llvm/lib/CodeGen/ModuloSchedule.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1704,7 +1704,7 @@ void PeelingModuloScheduleExpander::peelPrologAndEpilogs() {
17041704
// Peel out the prologs.
17051705
LS.reset();
17061706
for (int I = 0; I < Schedule.getNumStages() - 1; ++I) {
1707-
LS[I] = 1;
1707+
LS[I] = true;
17081708
Prologs.push_back(peelKernel(LPD_Front));
17091709
LiveStages[Prologs.back()] = LS;
17101710
AvailableStages[Prologs.back()] = LS;
@@ -1752,7 +1752,7 @@ void PeelingModuloScheduleExpander::peelPrologAndEpilogs() {
17521752
// Move stage one block at a time so that Phi nodes are updated correctly.
17531753
for (size_t K = Iteration; K > I; K--)
17541754
moveStageBetweenBlocks(Epilogs[K - 1], Epilogs[K], Stage);
1755-
LS[Stage] = 1;
1755+
LS[Stage] = true;
17561756
}
17571757
LiveStages[Epilogs[I]] = LS;
17581758
AvailableStages[Epilogs[I]] = AS;

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -4613,7 +4613,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
46134613
// SelectionDAG::FoldSymbolOffset because it expects the GA to be accessible
46144614
// while in this case the GA may be furthest from the root node which is
46154615
// likely an ISD::ADD.
4616-
while (1) {
4616+
while (true) {
46174617
if ((GA = dyn_cast<GlobalAddressSDNode>(Op)) && ConstraintLetter != 'n') {
46184618
Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
46194619
GA->getValueType(0),

‎llvm/lib/CodeGen/TargetRegisterInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -552,7 +552,7 @@ bool TargetRegisterInfo::getCoveringSubRegIndexes(
552552

553553
// Abort if we cannot possibly implement the COPY with the given indexes.
554554
if (BestIdx == 0)
555-
return 0;
555+
return false;
556556

557557
NeededIndexes.push_back(BestIdx);
558558

@@ -581,7 +581,7 @@ bool TargetRegisterInfo::getCoveringSubRegIndexes(
581581
}
582582

583583
if (BestIdx == 0)
584-
return 0; // Impossible to handle
584+
return false; // Impossible to handle
585585

586586
NeededIndexes.push_back(BestIdx);
587587

‎llvm/lib/CodeGen/VLIWMachineScheduler.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -293,7 +293,7 @@ void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) {
293293

294294
const std::vector<unsigned> &MaxPressure =
295295
DAG->getRegPressure().MaxSetPressure;
296-
HighPressureSets.assign(MaxPressure.size(), 0);
296+
HighPressureSets.assign(MaxPressure.size(), false);
297297
for (unsigned i = 0, e = MaxPressure.size(); i < e; ++i) {
298298
unsigned Limit = DAG->getRegClassInfo()->getRegPressureSetLimit(i);
299299
HighPressureSets[i] =

‎llvm/lib/DWARFLinker/DWARFLinker.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1935,7 +1935,7 @@ uint32_t DWARFLinker::DIECloner::hashFullyQualifiedName(DWARFDie DIE,
19351935
CompileUnit *CU = &U;
19361936
Optional<DWARFFormValue> Ref;
19371937

1938-
while (1) {
1938+
while (true) {
19391939
if (const char *CurrentName = DIE.getName(DINameKind::ShortName))
19401940
Name = CurrentName;
19411941

‎llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -173,15 +173,15 @@ bool DWARFVerifier::verifyName(const DWARFDie &Die) {
173173
Die.getFullName(OS, &OriginalFullName);
174174
OS.flush();
175175
if (OriginalFullName.empty() || OriginalFullName == ReconstructedName)
176-
return 0;
176+
return false;
177177

178178
error() << "Simplified template DW_AT_name could not be reconstituted:\n"
179179
<< formatv(" original: {0}\n"
180180
" reconstituted: {1}\n",
181181
OriginalFullName, ReconstructedName);
182182
dump(Die) << '\n';
183183
dump(Die.getDwarfUnit()->getUnitDIE()) << '\n';
184-
return 1;
184+
return true;
185185
}
186186

187187
unsigned DWARFVerifier::verifyUnitContents(DWARFUnit &Unit,

‎llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -791,7 +791,7 @@ Error CompactUnwindSplitter::operator()(LinkGraph &G) {
791791
E.getTarget().getName() + " is an external symbol");
792792
auto &TgtBlock = E.getTarget().getBlock();
793793
auto &CURecSym =
794-
G.addAnonymousSymbol(CURec, 0, CURecordSize, 0, false);
794+
G.addAnonymousSymbol(CURec, 0, CURecordSize, false, false);
795795
TgtBlock.addEdge(Edge::KeepAlive, 0, CURecSym, 0);
796796
AddedKeepAlive = true;
797797
} else if (E.getOffset() != PersonalityEdgeOffset &&

‎llvm/lib/ExecutionEngine/Orc/Core.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -2201,7 +2201,7 @@ void ExecutionSession::dump(raw_ostream &OS) {
22012201

22022202
void ExecutionSession::dispatchOutstandingMUs() {
22032203
LLVM_DEBUG(dbgs() << "Dispatching MaterializationUnits...\n");
2204-
while (1) {
2204+
while (true) {
22052205
Optional<std::pair<std::unique_ptr<MaterializationUnit>,
22062206
std::unique_ptr<MaterializationResponsibility>>>
22072207
JMU;

‎llvm/lib/FileCheck/FileCheck.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -2215,7 +2215,7 @@ static Error reportMatchResult(bool ExpectedMatch, const SourceMgr &SM,
22152215
static unsigned CountNumNewlinesBetween(StringRef Range,
22162216
const char *&FirstNewLine) {
22172217
unsigned NumNewLines = 0;
2218-
while (1) {
2218+
while (true) {
22192219
// Scan for newline.
22202220
Range = Range.substr(Range.find_first_of("\n\r"));
22212221
if (Range.empty())

‎llvm/lib/ProfileData/GCOV.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -346,7 +346,7 @@ StringRef GCOVFunction::getName(bool demangle) const {
346346
}
347347
}
348348
demangled = Name;
349-
} while (0);
349+
} while (false);
350350
}
351351
return demangled;
352352
}

‎llvm/lib/Support/CodeGenCoverage.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ CodeGenCoverage::CodeGenCoverage() {}
2727

2828
void CodeGenCoverage::setCovered(uint64_t RuleID) {
2929
if (RuleCoverage.size() <= RuleID)
30-
RuleCoverage.resize(RuleID + 1, 0);
30+
RuleCoverage.resize(RuleID + 1, false);
3131
RuleCoverage[RuleID] = true;
3232
}
3333

‎llvm/lib/Support/DivisionByConstantInfo.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ UnsignedDivisonByConstantInfo::get(const APInt &D, unsigned LeadingZeros) {
6767
unsigned P;
6868
APInt NC, Delta, Q1, R1, Q2, R2;
6969
struct UnsignedDivisonByConstantInfo Retval;
70-
Retval.IsAdd = 0; // initialize "add" indicator
70+
Retval.IsAdd = false; // initialize "add" indicator
7171
APInt AllOnes = APInt::getAllOnes(D.getBitWidth()).lshr(LeadingZeros);
7272
APInt SignedMin = APInt::getSignedMinValue(D.getBitWidth());
7373
APInt SignedMax = APInt::getSignedMaxValue(D.getBitWidth());
@@ -89,12 +89,12 @@ UnsignedDivisonByConstantInfo::get(const APInt &D, unsigned LeadingZeros) {
8989
}
9090
if ((R2 + 1).uge(D - R2)) {
9191
if (Q2.uge(SignedMax))
92-
Retval.IsAdd = 1;
92+
Retval.IsAdd = true;
9393
Q2 = Q2 + Q2 + 1; // update Q2
9494
R2 = R2 + R2 + 1 - D; // update R2
9595
} else {
9696
if (Q2.uge(SignedMin))
97-
Retval.IsAdd = 1;
97+
Retval.IsAdd = true;
9898
Q2 = Q2 + Q2; // update Q2
9999
R2 = R2 + R2 + 1; // update R2
100100
}

‎llvm/lib/TableGen/TGParser.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -3203,7 +3203,8 @@ bool TGParser::ParseIf(MultiClass *CurMultiClass) {
32033203
// iteration variable being assigned.
32043204

32053205
ListInit *EmptyList = ListInit::get({}, BitRecTy::get());
3206-
ListInit *SingletonList = ListInit::get({BitInit::get(1)}, BitRecTy::get());
3206+
ListInit *SingletonList =
3207+
ListInit::get({BitInit::get(true)}, BitRecTy::get());
32073208
RecTy *BitListTy = ListRecTy::get(BitRecTy::get());
32083209

32093210
// The foreach containing the then-clause selects SingletonList if

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1493,9 +1493,9 @@ static bool parseTexFail(uint64_t TexFailCtrl, bool &TFE, bool &LWE,
14931493
if (TexFailCtrl)
14941494
IsTexFail = true;
14951495

1496-
TFE = (TexFailCtrl & 0x1) ? 1 : 0;
1496+
TFE = (TexFailCtrl & 0x1) ? true : false;
14971497
TexFailCtrl &= ~(uint64_t)0x1;
1498-
LWE = (TexFailCtrl & 0x2) ? 1 : 0;
1498+
LWE = (TexFailCtrl & 0x2) ? true : false;
14991499
TexFailCtrl &= ~(uint64_t)0x2;
15001500

15011501
return TexFailCtrl == 0;

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

+3-1
Original file line numberDiff line numberDiff line change
@@ -11130,7 +11130,9 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1113011130
unsigned TFEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::tfe) - 1;
1113111131
unsigned LWEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::lwe) - 1;
1113211132
bool UsesTFC = ((int(TFEIdx) >= 0 && Node->getConstantOperandVal(TFEIdx)) ||
11133-
Node->getConstantOperandVal(LWEIdx)) ? 1 : 0;
11133+
Node->getConstantOperandVal(LWEIdx))
11134+
? true
11135+
: false;
1113411136
unsigned TFCLane = 0;
1113511137
bool HasChain = Node->getNumValues() > 1;
1113611138

‎llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -3227,7 +3227,7 @@ bool ARMDAGToDAGISel::transformFixedFloatingPointConversion(SDNode *N,
32273227
if (!ImmAPF.getExactInverse(&ToConvert))
32283228
return false;
32293229
}
3230-
APSInt Converted(64, 0);
3230+
APSInt Converted(64, false);
32313231
bool IsExact;
32323232
ToConvert.convertToInteger(Converted, llvm::RoundingMode::NearestTiesToEven,
32333233
&IsExact);

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -15426,13 +15426,13 @@ static SDValue PerformShuffleVMOVNCombine(ShuffleVectorSDNode *N,
1542615426
return SDValue();
1542715427

1542815428
SDLoc DL(Trunc);
15429-
if (isVMOVNTruncMask(N->getMask(), VT, 0))
15429+
if (isVMOVNTruncMask(N->getMask(), VT, false))
1543015430
return DAG.getNode(
1543115431
ARMISD::VMOVN, DL, VT,
1543215432
DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(0)),
1543315433
DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(1)),
1543415434
DAG.getConstant(1, DL, MVT::i32));
15435-
else if (isVMOVNTruncMask(N->getMask(), VT, 1))
15435+
else if (isVMOVNTruncMask(N->getMask(), VT, true))
1543615436
return DAG.getNode(
1543715437
ARMISD::VMOVN, DL, VT,
1543815438
DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(1)),
@@ -18232,13 +18232,13 @@ SDValue ARMTargetLowering::PerformMVETruncCombine(
1823218232
SmallVector<int, 8> Mask(S0->getMask().begin(), S0->getMask().end());
1823318233
Mask.append(S1->getMask().begin(), S1->getMask().end());
1823418234

18235-
if (isVMOVNTruncMask(Mask, VT, 0))
18235+
if (isVMOVNTruncMask(Mask, VT, false))
1823618236
return DAG.getNode(
1823718237
ARMISD::VMOVN, DL, VT,
1823818238
DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(0)),
1823918239
DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(1)),
1824018240
DAG.getConstant(1, DL, MVT::i32));
18241-
if (isVMOVNTruncMask(Mask, VT, 1))
18241+
if (isVMOVNTruncMask(Mask, VT, true))
1824218242
return DAG.getNode(
1824318243
ARMISD::VMOVN, DL, VT,
1824418244
DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(1)),

‎llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1402,12 +1402,12 @@ bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14021402

14031403
bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14041404
// MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1405-
return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1405+
return false && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
14061406
}
14071407

14081408
bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14091409
// MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1410-
return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1410+
return false && VT1 == MVT::i8 && VT2 == MVT::i16;
14111411
}
14121412

14131413
bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {

‎llvm/lib/Target/Mips/Mips16ISelLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -451,7 +451,7 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
451451
// So for now we always save S2. The optimization will be done
452452
// in a follow-on patch.
453453
//
454-
if (1 || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
454+
if (true || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
455455
FuncInfo->setSaveS2();
456456
}
457457
// one more look at list of intrinsics

‎llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

+1-2
Original file line numberDiff line numberDiff line change
@@ -1178,7 +1178,7 @@ static unsigned getIncomingRegForBlock(MachineInstr *Phi,
11781178
static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1,
11791179
MachineBasicBlock *BB2, MachineRegisterInfo *MRI) {
11801180
unsigned SrcReg = Reg;
1181-
while (1) {
1181+
while (true) {
11821182
unsigned NextReg = SrcReg;
11831183
MachineInstr *Inst = MRI->getVRegDef(SrcReg);
11841184
if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) {
@@ -1737,4 +1737,3 @@ INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE,
17371737
char PPCMIPeephole::ID = 0;
17381738
FunctionPass*
17391739
llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }
1740-

‎llvm/lib/Target/VE/VEISelLowering.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -2750,7 +2750,7 @@ SDValue VETargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
27502750
SDValue Idx = Op.getOperand(1);
27512751
SDLoc DL(Op);
27522752
SDValue Result = Op;
2753-
if (0 /* Idx->isConstant() */) {
2753+
if (false /* Idx->isConstant() */) {
27542754
// TODO: optimized implementation using constant values
27552755
} else {
27562756
SDValue Const1 = DAG.getConstant(1, DL, MVT::i64);
@@ -2808,7 +2808,7 @@ SDValue VETargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
28082808
Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
28092809

28102810
SDValue Result = Op;
2811-
if (0 /* Idx->isConstant()*/) {
2811+
if (false /* Idx->isConstant()*/) {
28122812
// TODO: optimized implementation using constant values
28132813
} else {
28142814
SDValue Const1 = DAG.getConstant(1, DL, MVT::i64);

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