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InstrRefLDVTest.cpp
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//===------------- llvm/unittest/CodeGen/InstrRefLDVTest.cpp --------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MIRParser/MIRParser.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DIBuilder.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "../lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h"
#include "gtest/gtest.h"
using namespace llvm;
using namespace LiveDebugValues;
// Include helper functions to ease the manipulation of MachineFunctions
#include "MFCommon.inc"
class InstrRefLDVTest : public testing::Test {
public:
friend class InstrRefBasedLDV;
using MLocTransferMap = InstrRefBasedLDV::MLocTransferMap;
LLVMContext Ctx;
std::unique_ptr<Module> Mod;
std::unique_ptr<TargetMachine> Machine;
std::unique_ptr<MachineFunction> MF;
std::unique_ptr<MachineDominatorTree> DomTree;
std::unique_ptr<MachineModuleInfo> MMI;
DICompileUnit *OurCU;
DIFile *OurFile;
DISubprogram *OurFunc;
DILexicalBlock *OurBlock, *AnotherBlock;
DISubprogram *ToInlineFunc;
DILexicalBlock *ToInlineBlock;
DILocalVariable *FuncVariable;
DIBasicType *LongInt;
DIExpression *EmptyExpr;
LiveDebugValues::OverlapMap Overlaps;
DebugLoc OutermostLoc, InBlockLoc, NotNestedBlockLoc, InlinedLoc;
MachineBasicBlock *MBB0, *MBB1, *MBB2, *MBB3, *MBB4;
std::unique_ptr<InstrRefBasedLDV> LDV;
std::unique_ptr<MLocTracker> MTracker;
std::unique_ptr<VLocTracker> VTracker;
SmallString<256> MIRStr;
InstrRefLDVTest() : Ctx(), Mod(std::make_unique<Module>("beehives", Ctx)) {}
void SetUp() {
// Boilerplate that creates a MachineFunction and associated blocks.
Mod->setDataLayout("e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-"
"n8:16:32:64-S128");
Triple TargetTriple("x86_64--");
std::string Error;
const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
if (!T)
GTEST_SKIP();
TargetOptions Options;
Machine = std::unique_ptr<TargetMachine>(
T->createTargetMachine(Triple::normalize("x86_64--"), "", "", Options,
None, None, CodeGenOpt::Aggressive));
auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
auto F =
Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &*Mod);
unsigned FunctionNum = 42;
MMI = std::make_unique<MachineModuleInfo>((LLVMTargetMachine *)&*Machine);
const TargetSubtargetInfo &STI = *Machine->getSubtargetImpl(*F);
MF = std::make_unique<MachineFunction>(*F, (LLVMTargetMachine &)*Machine,
STI, FunctionNum, *MMI);
// Create metadata: CU, subprogram, some blocks and an inline function
// scope.
DIBuilder DIB(*Mod);
OurFile = DIB.createFile("xyzzy.c", "/cave");
OurCU =
DIB.createCompileUnit(dwarf::DW_LANG_C99, OurFile, "nou", false, "", 0);
auto OurSubT = DIB.createSubroutineType(DIB.getOrCreateTypeArray(None));
OurFunc =
DIB.createFunction(OurCU, "bees", "", OurFile, 1, OurSubT, 1,
DINode::FlagZero, DISubprogram::SPFlagDefinition);
F->setSubprogram(OurFunc);
OurBlock = DIB.createLexicalBlock(OurFunc, OurFile, 2, 3);
AnotherBlock = DIB.createLexicalBlock(OurFunc, OurFile, 2, 6);
ToInlineFunc =
DIB.createFunction(OurFile, "shoes", "", OurFile, 10, OurSubT, 10,
DINode::FlagZero, DISubprogram::SPFlagDefinition);
// Make some nested scopes.
OutermostLoc = DILocation::get(Ctx, 3, 1, OurFunc);
InBlockLoc = DILocation::get(Ctx, 4, 1, OurBlock);
InlinedLoc = DILocation::get(Ctx, 10, 1, ToInlineFunc, InBlockLoc.get());
// Make a scope that isn't nested within the others.
NotNestedBlockLoc = DILocation::get(Ctx, 4, 1, AnotherBlock);
LongInt = DIB.createBasicType("long", 64, llvm::dwarf::DW_ATE_unsigned);
FuncVariable = DIB.createAutoVariable(OurFunc, "lala", OurFile, 1, LongInt);
EmptyExpr = DIExpression::get(Ctx, {});
DIB.finalize();
}
Register getRegByName(const char *WantedName) {
auto *TRI = MF->getRegInfo().getTargetRegisterInfo();
// Slow, but works.
for (unsigned int I = 1; I < TRI->getNumRegs(); ++I) {
const char *Name = TRI->getName(I);
if (strcmp(WantedName, Name) == 0)
return I;
}
// If this ever fails, something is very wrong with this unit test.
llvm_unreachable("Can't find register by name");
}
InstrRefBasedLDV *setupLDVObj(MachineFunction *MF) {
// Create a new LDV object, and plug some relevant object ptrs into it.
LDV = std::make_unique<InstrRefBasedLDV>();
const TargetSubtargetInfo &STI = MF->getSubtarget();
LDV->TII = STI.getInstrInfo();
LDV->TRI = STI.getRegisterInfo();
LDV->TFI = STI.getFrameLowering();
LDV->MFI = &MF->getFrameInfo();
LDV->MRI = &MF->getRegInfo();
DomTree = std::make_unique<MachineDominatorTree>(*MF);
LDV->DomTree = &*DomTree;
// Future work: unit tests for mtracker / vtracker / ttracker.
// Setup things like the artifical block map, and BlockNo <=> RPO Order
// mappings.
LDV->initialSetup(*MF);
LDV->LS.initialize(*MF);
addMTracker(MF);
return &*LDV;
}
void addMTracker(MachineFunction *MF) {
ASSERT_TRUE(LDV);
// Add a machine-location-tracking object to LDV. Don't initialize any
// register locations within it though.
const TargetSubtargetInfo &STI = MF->getSubtarget();
MTracker = std::make_unique<MLocTracker>(
*MF, *LDV->TII, *LDV->TRI, *STI.getTargetLowering());
LDV->MTracker = &*MTracker;
}
void addVTracker() {
ASSERT_TRUE(LDV);
VTracker = std::make_unique<VLocTracker>(Overlaps, EmptyExpr);
LDV->VTracker = &*VTracker;
}
// Some routines for bouncing into LDV,
void buildMLocValueMap(ValueIDNum **MInLocs, ValueIDNum **MOutLocs,
SmallVectorImpl<MLocTransferMap> &MLocTransfer) {
LDV->buildMLocValueMap(*MF, MInLocs, MOutLocs, MLocTransfer);
}
void placeMLocPHIs(MachineFunction &MF,
SmallPtrSetImpl<MachineBasicBlock *> &AllBlocks,
ValueIDNum **MInLocs,
SmallVectorImpl<MLocTransferMap> &MLocTransfer) {
LDV->placeMLocPHIs(MF, AllBlocks, MInLocs, MLocTransfer);
}
Optional<ValueIDNum>
pickVPHILoc(const MachineBasicBlock &MBB, const DebugVariable &Var,
const InstrRefBasedLDV::LiveIdxT &LiveOuts, ValueIDNum **MOutLocs,
const SmallVectorImpl<const MachineBasicBlock *> &BlockOrders) {
return LDV->pickVPHILoc(MBB, Var, LiveOuts, MOutLocs, BlockOrders);
}
bool vlocJoin(MachineBasicBlock &MBB, InstrRefBasedLDV::LiveIdxT &VLOCOutLocs,
SmallPtrSet<const MachineBasicBlock *, 8> &BlocksToExplore,
DbgValue &InLoc) {
return LDV->vlocJoin(MBB, VLOCOutLocs, BlocksToExplore, InLoc);
}
void buildVLocValueMap(const DILocation *DILoc,
const SmallSet<DebugVariable, 4> &VarsWeCareAbout,
SmallPtrSetImpl<MachineBasicBlock *> &AssignBlocks,
InstrRefBasedLDV::LiveInsT &Output, ValueIDNum **MOutLocs,
ValueIDNum **MInLocs,
SmallVectorImpl<VLocTracker> &AllTheVLocs) {
LDV->buildVLocValueMap(DILoc, VarsWeCareAbout, AssignBlocks, Output,
MOutLocs, MInLocs, AllTheVLocs);
}
void initValueArray(ValueIDNum **Nums, unsigned Blks, unsigned Locs) {
for (unsigned int I = 0; I < Blks; ++I)
for (unsigned int J = 0; J < Locs; ++J)
Nums[I][J] = ValueIDNum::EmptyValue;
}
void setupSingleBlock() {
// Add an entry block with nothing but 'ret void' in it.
Function &F = const_cast<llvm::Function &>(MF->getFunction());
auto *BB0 = BasicBlock::Create(Ctx, "entry", &F);
IRBuilder<> IRB(BB0);
IRB.CreateRetVoid();
MBB0 = MF->CreateMachineBasicBlock(BB0);
MF->insert(MF->end(), MBB0);
MF->RenumberBlocks();
setupLDVObj(&*MF);
}
void setupDiamondBlocks() {
// entry
// / \
// br1 br2
// \ /
// ret
llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction());
auto *BB0 = BasicBlock::Create(Ctx, "a", &F);
auto *BB1 = BasicBlock::Create(Ctx, "b", &F);
auto *BB2 = BasicBlock::Create(Ctx, "c", &F);
auto *BB3 = BasicBlock::Create(Ctx, "d", &F);
IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3);
IRB0.CreateBr(BB1);
IRB1.CreateBr(BB2);
IRB2.CreateBr(BB3);
IRB3.CreateRetVoid();
MBB0 = MF->CreateMachineBasicBlock(BB0);
MF->insert(MF->end(), MBB0);
MBB1 = MF->CreateMachineBasicBlock(BB1);
MF->insert(MF->end(), MBB1);
MBB2 = MF->CreateMachineBasicBlock(BB2);
MF->insert(MF->end(), MBB2);
MBB3 = MF->CreateMachineBasicBlock(BB3);
MF->insert(MF->end(), MBB3);
MBB0->addSuccessor(MBB1);
MBB0->addSuccessor(MBB2);
MBB1->addSuccessor(MBB3);
MBB2->addSuccessor(MBB3);
MF->RenumberBlocks();
setupLDVObj(&*MF);
}
void setupSimpleLoop() {
// entry
// |
// |/-----\
// loopblk |
// |\-----/
// |
// ret
llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction());
auto *BB0 = BasicBlock::Create(Ctx, "entry", &F);
auto *BB1 = BasicBlock::Create(Ctx, "loop", &F);
auto *BB2 = BasicBlock::Create(Ctx, "ret", &F);
IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2);
IRB0.CreateBr(BB1);
IRB1.CreateBr(BB2);
IRB2.CreateRetVoid();
MBB0 = MF->CreateMachineBasicBlock(BB0);
MF->insert(MF->end(), MBB0);
MBB1 = MF->CreateMachineBasicBlock(BB1);
MF->insert(MF->end(), MBB1);
MBB2 = MF->CreateMachineBasicBlock(BB2);
MF->insert(MF->end(), MBB2);
MBB0->addSuccessor(MBB1);
MBB1->addSuccessor(MBB2);
MBB1->addSuccessor(MBB1);
MF->RenumberBlocks();
setupLDVObj(&*MF);
}
void setupNestedLoops() {
// entry
// |
// loop1
// ^\
// | \ /-\
// | loop2 |
// | / \-/
// ^ /
// join
// |
// ret
llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction());
auto *BB0 = BasicBlock::Create(Ctx, "entry", &F);
auto *BB1 = BasicBlock::Create(Ctx, "loop1", &F);
auto *BB2 = BasicBlock::Create(Ctx, "loop2", &F);
auto *BB3 = BasicBlock::Create(Ctx, "join", &F);
auto *BB4 = BasicBlock::Create(Ctx, "ret", &F);
IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4);
IRB0.CreateBr(BB1);
IRB1.CreateBr(BB2);
IRB2.CreateBr(BB3);
IRB3.CreateBr(BB4);
IRB4.CreateRetVoid();
MBB0 = MF->CreateMachineBasicBlock(BB0);
MF->insert(MF->end(), MBB0);
MBB1 = MF->CreateMachineBasicBlock(BB1);
MF->insert(MF->end(), MBB1);
MBB2 = MF->CreateMachineBasicBlock(BB2);
MF->insert(MF->end(), MBB2);
MBB3 = MF->CreateMachineBasicBlock(BB3);
MF->insert(MF->end(), MBB3);
MBB4 = MF->CreateMachineBasicBlock(BB4);
MF->insert(MF->end(), MBB4);
MBB0->addSuccessor(MBB1);
MBB1->addSuccessor(MBB2);
MBB2->addSuccessor(MBB2);
MBB2->addSuccessor(MBB3);
MBB3->addSuccessor(MBB1);
MBB3->addSuccessor(MBB4);
MF->RenumberBlocks();
setupLDVObj(&*MF);
}
void setupNoDominatingLoop() {
// entry
// / \
// / \
// / \
// head1 head2
// ^ \ / ^
// ^ \ / ^
// \-joinblk -/
// |
// ret
llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction());
auto *BB0 = BasicBlock::Create(Ctx, "entry", &F);
auto *BB1 = BasicBlock::Create(Ctx, "head1", &F);
auto *BB2 = BasicBlock::Create(Ctx, "head2", &F);
auto *BB3 = BasicBlock::Create(Ctx, "joinblk", &F);
auto *BB4 = BasicBlock::Create(Ctx, "ret", &F);
IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4);
IRB0.CreateBr(BB1);
IRB1.CreateBr(BB2);
IRB2.CreateBr(BB3);
IRB3.CreateBr(BB4);
IRB4.CreateRetVoid();
MBB0 = MF->CreateMachineBasicBlock(BB0);
MF->insert(MF->end(), MBB0);
MBB1 = MF->CreateMachineBasicBlock(BB1);
MF->insert(MF->end(), MBB1);
MBB2 = MF->CreateMachineBasicBlock(BB2);
MF->insert(MF->end(), MBB2);
MBB3 = MF->CreateMachineBasicBlock(BB3);
MF->insert(MF->end(), MBB3);
MBB4 = MF->CreateMachineBasicBlock(BB4);
MF->insert(MF->end(), MBB4);
MBB0->addSuccessor(MBB1);
MBB0->addSuccessor(MBB2);
MBB1->addSuccessor(MBB3);
MBB2->addSuccessor(MBB3);
MBB3->addSuccessor(MBB1);
MBB3->addSuccessor(MBB2);
MBB3->addSuccessor(MBB4);
MF->RenumberBlocks();
setupLDVObj(&*MF);
}
void setupBadlyNestedLoops() {
// entry
// |
// loop1 -o
// | ^
// | ^
// loop2 -o
// | ^
// | ^
// loop3 -o
// |
// ret
//
// NB: the loop blocks self-loop, which is a bit too fiddly to draw on
// accurately.
llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction());
auto *BB0 = BasicBlock::Create(Ctx, "entry", &F);
auto *BB1 = BasicBlock::Create(Ctx, "loop1", &F);
auto *BB2 = BasicBlock::Create(Ctx, "loop2", &F);
auto *BB3 = BasicBlock::Create(Ctx, "loop3", &F);
auto *BB4 = BasicBlock::Create(Ctx, "ret", &F);
IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4);
IRB0.CreateBr(BB1);
IRB1.CreateBr(BB2);
IRB2.CreateBr(BB3);
IRB3.CreateBr(BB4);
IRB4.CreateRetVoid();
MBB0 = MF->CreateMachineBasicBlock(BB0);
MF->insert(MF->end(), MBB0);
MBB1 = MF->CreateMachineBasicBlock(BB1);
MF->insert(MF->end(), MBB1);
MBB2 = MF->CreateMachineBasicBlock(BB2);
MF->insert(MF->end(), MBB2);
MBB3 = MF->CreateMachineBasicBlock(BB3);
MF->insert(MF->end(), MBB3);
MBB4 = MF->CreateMachineBasicBlock(BB4);
MF->insert(MF->end(), MBB4);
MBB0->addSuccessor(MBB1);
MBB1->addSuccessor(MBB1);
MBB1->addSuccessor(MBB2);
MBB2->addSuccessor(MBB1);
MBB2->addSuccessor(MBB2);
MBB2->addSuccessor(MBB3);
MBB3->addSuccessor(MBB2);
MBB3->addSuccessor(MBB3);
MBB3->addSuccessor(MBB4);
MF->RenumberBlocks();
setupLDVObj(&*MF);
}
MachineFunction *readMIRBlock(const char *Input) {
MIRStr.clear();
StringRef S = Twine(Twine(R"MIR(
--- |
target triple = "x86_64-unknown-linux-gnu"
define void @test() { ret void }
...
---
name: test
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
bb.0:
liveins: $rdi, $rsi
)MIR") + Twine(Input) + Twine("...\n"))
.toNullTerminatedStringRef(MIRStr);
;
// Clear the "test" function from MMI if it's still present.
if (Function *Fn = Mod->getFunction("test"))
MMI->deleteMachineFunctionFor(*Fn);
auto MemBuf = MemoryBuffer::getMemBuffer(S, "<input>");
auto MIRParse = createMIRParser(std::move(MemBuf), Ctx);
Mod = MIRParse->parseIRModule();
assert(Mod);
Mod->setDataLayout("e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-"
"n8:16:32:64-S128");
bool Result = MIRParse->parseMachineFunctions(*Mod, *MMI);
assert(!Result && "Failed to parse unit test machine function?");
(void)Result;
Function *Fn = Mod->getFunction("test");
assert(Fn && "Failed to parse a unit test module string?");
Fn->setSubprogram(OurFunc);
return MMI->getMachineFunction(*Fn);
}
void
produceMLocTransferFunction(MachineFunction &MF,
SmallVectorImpl<MLocTransferMap> &MLocTransfer,
unsigned MaxNumBlocks) {
LDV->produceMLocTransferFunction(MF, MLocTransfer, MaxNumBlocks);
}
};
TEST_F(InstrRefLDVTest, MTransferDefs) {
MachineFunction *MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" RET64 $rax\n");
setupLDVObj(MF);
// We should start with only SP tracked.
EXPECT_TRUE(MTracker->getNumLocs() == 1);
SmallVector<MLocTransferMap, 1> TransferMap;
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
// Code contains only one register write: that should assign to each of the
// aliasing registers. Test that all of them get locations, and have a
// corresponding def at the first instr in the function.
const char *RegNames[] = {"RAX", "HAX", "EAX", "AX", "AH", "AL"};
EXPECT_TRUE(MTracker->getNumLocs() == 7);
for (const char *RegName : RegNames) {
Register R = getRegByName(RegName);
ASSERT_TRUE(MTracker->isRegisterTracked(R));
LocIdx L = MTracker->getRegMLoc(R);
ValueIDNum V = MTracker->readReg(R);
// Value of this register should be: block zero, instruction 1, and the
// location it's defined in is itself.
ValueIDNum ToCmp(0, 1, L);
EXPECT_EQ(V, ToCmp);
}
// Do the same again, but with an aliasing write. This should write to all
// the same registers again, except $ah and $hax (the upper 8 bits of $ax
// and 32 bits of $rax resp.).
MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" $al = MOV8ri 0\n"
" RET64 $rax\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
auto TestRegSetSite = [&](const char *Name, unsigned InstrNum) {
Register R = getRegByName(Name);
ASSERT_TRUE(MTracker->isRegisterTracked(R));
LocIdx L = MTracker->getRegMLoc(R);
ValueIDNum V = MTracker->readMLoc(L);
ValueIDNum ToCmp(0, InstrNum, L);
EXPECT_EQ(V, ToCmp);
};
TestRegSetSite("AL", 2);
TestRegSetSite("AH", 1);
TestRegSetSite("AX", 2);
TestRegSetSite("EAX", 2);
TestRegSetSite("HAX", 1);
TestRegSetSite("RAX", 2);
// This call should:
// * Def rax via the implicit-def,
// * Clobber rsi/rdi and all their subregs, via the register mask
// * Same for rcx, despite it not being a use in the instr, it's in the mask
// * NOT clobber $rsp / $esp $ sp, LiveDebugValues deliberately ignores
// these.
// * NOT clobber $rbx, because it's non-volatile
// * Not track every other register in the machine, only those needed.
MF = readMIRBlock(
" $rax = MOV64ri 0\n" // instr 1
" $rbx = MOV64ri 0\n" // instr 2
" $rcx = MOV64ri 0\n" // instr 3
" $rdi = MOV64ri 0\n" // instr 4
" $rsi = MOV64ri 0\n" // instr 5
" CALL64r $rax, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, implicit-def $esp, implicit-def $sp\n\n\n\n" // instr 6
" RET64 $rax\n"); // instr 7
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
const char *RegsSetInCall[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX",
"DIL", "DIH", "DI", "EDI", "HDI", "RDI",
"SIL", "SIH", "SI", "ESI", "HSI", "RSI",
"CL", "CH", "CX", "ECX", "HCX", "RCX"};
for (const char *RegSetInCall : RegsSetInCall)
TestRegSetSite(RegSetInCall, 6);
const char *RegsLeftAlone[] = {"BL", "BH", "BX", "EBX", "HBX", "RBX"};
for (const char *RegLeftAlone : RegsLeftAlone)
TestRegSetSite(RegLeftAlone, 2);
// Stack pointer should be the live-in to the function, instruction zero.
TestRegSetSite("RSP", 0);
// These stack regs should not be tracked either. Nor the (fake) subregs.
EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("ESP")));
EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("SP")));
EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("SPL")));
EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("SPH")));
EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("HSP")));
// Should only be tracking: 6 x {A, B, C, DI, SI} registers = 30,
// Plus RSP, SSP = 32.
EXPECT_EQ(32u, MTracker->getNumLocs());
// When we DBG_PHI something, we should track all its subregs.
MF = readMIRBlock(
" DBG_PHI $rdi, 0\n"
" RET64\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
// All DI regs and RSP tracked.
EXPECT_EQ(7u, MTracker->getNumLocs());
// All the DI registers should have block live-in values, i.e. the argument
// to the function.
const char *DIRegs[] = {"DIL", "DIH", "DI", "EDI", "HDI", "RDI"};
for (const char *DIReg : DIRegs)
TestRegSetSite(DIReg, 0);
}
TEST_F(InstrRefLDVTest, MTransferMeta) {
// Meta instructions should not have any effect on register values.
SmallVector<MLocTransferMap, 1> TransferMap;
MachineFunction *MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" $rax = IMPLICIT_DEF\n"
" $rax = KILL killed $rax\n"
" RET64 $rax\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
LocIdx RaxLoc = MTracker->getRegMLoc(getRegByName("RAX"));
ValueIDNum V = MTracker->readMLoc(RaxLoc);
// Def of rax should be from instruction 1, i.e., unmodified.
ValueIDNum Cmp(0, 1, RaxLoc);
EXPECT_EQ(Cmp, V);
}
TEST_F(InstrRefLDVTest, MTransferCopies) {
SmallVector<MLocTransferMap, 1> TransferMap;
// This memory spill should be recognised, and a spill slot created.
MachineFunction *MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" RET64 $rax\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
// Check that the spill location contains the value defined in rax by
// instruction 1. The MIR header says -16 offset, but it's stored as -8;
// it's not completely clear why, but here we only care about correctly
// identifying the slot, not that all the surrounding data is correct.
SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)};
SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L);
unsigned SpillLocID = MTracker->getLocID(SpillNo, {64, 0});
LocIdx SpillLoc = MTracker->getSpillMLoc(SpillLocID);
ValueIDNum V = MTracker->readMLoc(SpillLoc);
Register RAX = getRegByName("RAX");
LocIdx RaxLoc = MTracker->getRegMLoc(RAX);
ValueIDNum Cmp(0, 1, RaxLoc);
EXPECT_EQ(V, Cmp);
// A spill and restore should be recognised.
MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
" RET64\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
// Test that rbx contains rax from instruction 1.
RAX = getRegByName("RAX");
RaxLoc = MTracker->getRegMLoc(RAX);
Register RBX = getRegByName("RBX");
LocIdx RbxLoc = MTracker->getRegMLoc(RBX);
Cmp = ValueIDNum(0, 1, RaxLoc);
ValueIDNum RbxVal = MTracker->readMLoc(RbxLoc);
EXPECT_EQ(RbxVal, Cmp);
// Testing that all the subregisters are transferred happens in
// MTransferSubregSpills.
// Copies and x86 movs should be recognised and honoured. In addition, all
// of the subregisters should be copied across too.
MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" $rcx = COPY $rax\n"
" $rbx = MOV64rr $rcx\n"
" RET64\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
const char *ARegs[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX"};
const char *BRegs[] = {"BL", "BH", "BX", "EBX", "HBX", "RBX"};
const char *CRegs[] = {"CL", "CH", "CX", "ECX", "HCX", "RCX"};
auto CheckReg = [&](unsigned int I) {
LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I]));
LocIdx B = MTracker->getRegMLoc(getRegByName(BRegs[I]));
LocIdx C = MTracker->getRegMLoc(getRegByName(CRegs[I]));
ValueIDNum ARefVal(0, 1, A);
ValueIDNum AVal = MTracker->readMLoc(A);
ValueIDNum BVal = MTracker->readMLoc(B);
ValueIDNum CVal = MTracker->readMLoc(C);
EXPECT_EQ(ARefVal, AVal);
EXPECT_EQ(ARefVal, BVal);
EXPECT_EQ(ARefVal, CVal);
};
for (unsigned int I = 0; I < 6; ++I)
CheckReg(I);
// When we copy to a subregister, the super-register should be def'd too: it's
// value will have changed.
MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" $ecx = COPY $eax\n"
" RET64\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
// First four regs [al, ah, ax, eax] should be copied to *cx.
for (unsigned int I = 0; I < 4; ++I) {
LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I]));
LocIdx C = MTracker->getRegMLoc(getRegByName(CRegs[I]));
ValueIDNum ARefVal(0, 1, A);
ValueIDNum AVal = MTracker->readMLoc(A);
ValueIDNum CVal = MTracker->readMLoc(C);
EXPECT_EQ(ARefVal, AVal);
EXPECT_EQ(ARefVal, CVal);
}
// But rcx should contain a value defined by the COPY.
LocIdx RcxLoc = MTracker->getRegMLoc(getRegByName("RCX"));
ValueIDNum RcxVal = MTracker->readMLoc(RcxLoc);
ValueIDNum RcxDefVal(0, 2, RcxLoc); // instr 2 -> the copy
EXPECT_EQ(RcxVal, RcxDefVal);
}
TEST_F(InstrRefLDVTest, MTransferSubregSpills) {
SmallVector<MLocTransferMap, 1> TransferMap;
MachineFunction *MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
" RET64\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
// Check that all the subregs of rax and rbx contain the same values. One
// should completely transfer to the other.
const char *ARegs[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX"};
const char *BRegs[] = {"BL", "BH", "BX", "EBX", "HBX", "RBX"};
for (unsigned int I = 0; I < 6; ++I) {
LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I]));
LocIdx B = MTracker->getRegMLoc(getRegByName(BRegs[I]));
EXPECT_EQ(MTracker->readMLoc(A), MTracker->readMLoc(B));
}
// Explicitly check what's in the different subreg slots, on the stack.
// Pair up subreg idx fields with the corresponding subregister in $rax.
MLocTracker::StackSlotPos SubRegIdxes[] = {{8, 0}, {8, 8}, {16, 0}, {32, 0}, {64, 0}};
const char *SubRegNames[] = {"AL", "AH", "AX", "EAX", "RAX"};
for (unsigned int I = 0; I < 5; ++I) {
// Value number where it's defined,
LocIdx RegLoc = MTracker->getRegMLoc(getRegByName(SubRegNames[I]));
ValueIDNum DefNum(0, 1, RegLoc);
// Read the corresponding subreg field from the stack.
SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)};
SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L);
unsigned SpillID = MTracker->getLocID(SpillNo, SubRegIdxes[I]);
LocIdx SpillLoc = MTracker->getSpillMLoc(SpillID);
ValueIDNum SpillValue = MTracker->readMLoc(SpillLoc);
EXPECT_EQ(DefNum, SpillValue);
}
// If we have exactly the same code, but we write $eax to the stack slot after
// $rax, then we should still have exactly the same output in the lower five
// subregisters. Storing $eax to the start of the slot will overwrite with the
// same values. $rax, as an aliasing register, should be reset to something
// else by that write.
// In theory, we could try and recognise that we're writing the _same_ values
// to the stack again, and so $rax doesn't need to be reset to something else.
// It seems vanishingly unlikely that LLVM would generate such code though,
// so the benefits would be small.
MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" MOV32mr $rsp, 1, $noreg, 16, $noreg, $eax :: (store 4 into %stack.0)\n"
" $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
" RET64\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
// Check lower five registers up to and include $eax == $ebx,
for (unsigned int I = 0; I < 5; ++I) {
LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I]));
LocIdx B = MTracker->getRegMLoc(getRegByName(BRegs[I]));
EXPECT_EQ(MTracker->readMLoc(A), MTracker->readMLoc(B));
}
// $rbx should contain something else; today it's a def at the spill point
// of the 4 byte value.
SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)};
SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L);
unsigned SpillID = MTracker->getLocID(SpillNo, {64, 0});
LocIdx Spill64Loc = MTracker->getSpillMLoc(SpillID);
ValueIDNum DefAtSpill64(0, 3, Spill64Loc);
LocIdx RbxLoc = MTracker->getRegMLoc(getRegByName("RBX"));
EXPECT_EQ(MTracker->readMLoc(RbxLoc), DefAtSpill64);
// Same again, test that the lower four subreg slots on the stack are the
// value defined by $rax in instruction 1.
for (unsigned int I = 0; I < 4; ++I) {
// Value number where it's defined,
LocIdx RegLoc = MTracker->getRegMLoc(getRegByName(SubRegNames[I]));
ValueIDNum DefNum(0, 1, RegLoc);
// Read the corresponding subreg field from the stack.
SpillNo = *MTracker->getOrTrackSpillLoc(L);
SpillID = MTracker->getLocID(SpillNo, SubRegIdxes[I]);
LocIdx SpillLoc = MTracker->getSpillMLoc(SpillID);
ValueIDNum SpillValue = MTracker->readMLoc(SpillLoc);
EXPECT_EQ(DefNum, SpillValue);
}
// Stack slot for $rax should be a different value, today it's EmptyValue.
ValueIDNum SpillValue = MTracker->readMLoc(Spill64Loc);
EXPECT_EQ(SpillValue, DefAtSpill64);
// If we write something to the stack, then over-write with some register
// from a completely different hierarchy, none of the "old" values should be
// readable.
// NB: slight hack, store 16 in to a 8 byte stack slot.
MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" $xmm0 = IMPLICIT_DEF\n"
" MOVUPDmr $rsp, 1, $noreg, 16, $noreg, killed $xmm0 :: (store (s128) into %stack.0)\n"
" $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
" RET64\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
for (unsigned int I = 0; I < 5; ++I) {
// Read subreg fields from the stack.
SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L);
unsigned SpillID = MTracker->getLocID(SpillNo, SubRegIdxes[I]);
LocIdx SpillLoc = MTracker->getSpillMLoc(SpillID);
ValueIDNum SpillValue = MTracker->readMLoc(SpillLoc);
// Value should be defined by the spill-to-xmm0 instr, get value of a def
// at the point of the spill.
ValueIDNum SpillDef(0, 4, SpillLoc);
EXPECT_EQ(SpillValue, SpillDef);
}
// Read xmm0's position and ensure it has a value. Should be the live-in
// value to the block, as IMPLICIT_DEF isn't a real def.
SpillNo = *MTracker->getOrTrackSpillLoc(L);
SpillID = MTracker->getLocID(SpillNo, {128, 0});
LocIdx Spill128Loc = MTracker->getSpillMLoc(SpillID);
SpillValue = MTracker->readMLoc(Spill128Loc);
Register XMM0 = getRegByName("XMM0");
LocIdx Xmm0Loc = MTracker->getRegMLoc(XMM0);
EXPECT_EQ(ValueIDNum(0, 0, Xmm0Loc), SpillValue);
// What happens if we spill ah to the stack, then load al? It should find
// the same value.
MF = readMIRBlock(
" $rax = MOV64ri 0\n"
" MOV8mr $rsp, 1, $noreg, 16, $noreg, $ah :: (store 1 into %stack.0)\n"
" $al = MOV8rm $rsp, 1, $noreg, 0, $noreg :: (load 1 from %stack.0)\n"
" RET64\n");
setupLDVObj(MF);
TransferMap.clear();
TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1);
Register AL = getRegByName("AL");
Register AH = getRegByName("AH");
LocIdx AlLoc = MTracker->getRegMLoc(AL);
LocIdx AhLoc = MTracker->getRegMLoc(AH);
ValueIDNum AHDef(0, 1, AhLoc);
ValueIDNum ALValue = MTracker->readMLoc(AlLoc);
EXPECT_EQ(ALValue, AHDef);
}
TEST_F(InstrRefLDVTest, MLocSingleBlock) {
// Test some very simple properties about interpreting the transfer function.
setupSingleBlock();
// We should start with a single location, the stack pointer.
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
// Set up live-in and live-out tables for this function: two locations (we
// add one later) in a single block.
ValueIDNum InLocs[2], OutLocs[2];
ValueIDNum *InLocsPtr[1] = {&InLocs[0]};
ValueIDNum *OutLocsPtr[1] = {&OutLocs[0]};
// Transfer function: nothing.
SmallVector<MLocTransferMap, 1> TransferFunc;
TransferFunc.resize(1);
// Try and build value maps...
buildMLocValueMap(InLocsPtr, OutLocsPtr, TransferFunc);
// The result should be that RSP is marked as a live-in-PHI -- this represents
// an argument. And as there's no transfer function, the block live-out should
// be the same.
EXPECT_EQ(InLocs[0], ValueIDNum(0, 0, RspLoc));
EXPECT_EQ(OutLocs[0], ValueIDNum(0, 0, RspLoc));
// Try again, this time initialising the in-locs to be defined by an
// instruction. The entry block should always be re-assigned to be the
// arguments.
initValueArray(InLocsPtr, 1, 2);
initValueArray(OutLocsPtr, 1, 2);
InLocs[0] = ValueIDNum(0, 1, RspLoc);
buildMLocValueMap(InLocsPtr, OutLocsPtr, TransferFunc);
EXPECT_EQ(InLocs[0], ValueIDNum(0, 0, RspLoc));
EXPECT_EQ(OutLocs[0], ValueIDNum(0, 0, RspLoc));
// Now insert something into the transfer function to assign to the single
// machine location.
TransferFunc[0].insert({RspLoc, ValueIDNum(0, 1, RspLoc)});
initValueArray(InLocsPtr, 1, 2);
initValueArray(OutLocsPtr, 1, 2);
buildMLocValueMap(InLocsPtr, OutLocsPtr, TransferFunc);
EXPECT_EQ(InLocs[0], ValueIDNum(0, 0, RspLoc));
EXPECT_EQ(OutLocs[0], ValueIDNum(0, 1, RspLoc));
TransferFunc[0].clear();
// Add a new register to be tracked, and insert it into the transfer function
// as a copy. The output of $rax should be the live-in value of $rsp.
Register RAX = getRegByName("RAX");
LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
TransferFunc[0].insert({RspLoc, ValueIDNum(0, 1, RspLoc)});
TransferFunc[0].insert({RaxLoc, ValueIDNum(0, 0, RspLoc)});
initValueArray(InLocsPtr, 1, 2);
initValueArray(OutLocsPtr, 1, 2);
buildMLocValueMap(InLocsPtr, OutLocsPtr, TransferFunc);
EXPECT_EQ(InLocs[0], ValueIDNum(0, 0, RspLoc));
EXPECT_EQ(InLocs[1], ValueIDNum(0, 0, RaxLoc));
EXPECT_EQ(OutLocs[0], ValueIDNum(0, 1, RspLoc));
EXPECT_EQ(OutLocs[1], ValueIDNum(0, 0, RspLoc)); // Rax contains RspLoc.
TransferFunc[0].clear();
}
TEST_F(InstrRefLDVTest, MLocDiamondBlocks) {
// Test that information flows from the entry block to two successors.
// entry
// / \
// br1 br2
// \ /
// ret
setupDiamondBlocks();
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
ValueIDNum InLocs[4][2], OutLocs[4][2];
ValueIDNum *InLocsPtr[4] = {InLocs[0], InLocs[1], InLocs[2], InLocs[3]};
ValueIDNum *OutLocsPtr[4] = {OutLocs[0], OutLocs[1], OutLocs[2], OutLocs[3]};
// Transfer function: start with nothing.
SmallVector<MLocTransferMap, 1> TransferFunc;
TransferFunc.resize(4);
// Name some values.
unsigned EntryBlk = 0, BrBlk1 = 1, BrBlk2 = 2, RetBlk = 3;
ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc);
ValueIDNum RspDefInBlk0(EntryBlk, 1, RspLoc);
ValueIDNum RspDefInBlk1(BrBlk1, 1, RspLoc);
ValueIDNum RspDefInBlk2(BrBlk2, 1, RspLoc);
ValueIDNum RspPHIInBlk3(RetBlk, 0, RspLoc);
ValueIDNum RaxLiveInBlk1(BrBlk1, 0, RaxLoc);
ValueIDNum RaxLiveInBlk2(BrBlk2, 0, RaxLoc);
// With no transfer function, the live-in values to the entry block should
// propagate to all live-outs and the live-ins to the two successor blocks.
// IN ADDITION: this checks that the exit block doesn't get a PHI put in it.
initValueArray(InLocsPtr, 4, 2);
initValueArray(OutLocsPtr, 4, 2);
buildMLocValueMap(InLocsPtr, OutLocsPtr, TransferFunc);
EXPECT_EQ(InLocs[0][0], LiveInRsp);
EXPECT_EQ(InLocs[1][0], LiveInRsp);
EXPECT_EQ(InLocs[2][0], LiveInRsp);
EXPECT_EQ(InLocs[3][0], LiveInRsp);
EXPECT_EQ(OutLocs[0][0], LiveInRsp);
EXPECT_EQ(OutLocs[1][0], LiveInRsp);
EXPECT_EQ(OutLocs[2][0], LiveInRsp);
EXPECT_EQ(OutLocs[3][0], LiveInRsp);