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Copy pathSystemZScheduleZ14.td
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SystemZScheduleZ14.td
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//-- SystemZScheduleZ14.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines the machine model for Z14 to support instruction
// scheduling and other instruction cost heuristics.
//
// Pseudos expanded right after isel do not need to be modelled here.
//
//===----------------------------------------------------------------------===//
def Z14Model : SchedMachineModel {
let UnsupportedFeatures = Arch12UnsupportedFeatures.List;
let IssueWidth = 6; // Number of instructions decoded per cycle.
let MicroOpBufferSize = 60; // Issue queues
let LoadLatency = 1; // Optimistic load latency.
let PostRAScheduler = 1;
// Extra cycles for a mispredicted branch.
let MispredictPenalty = 20;
}
let SchedModel = Z14Model in {
// These definitions need the SchedModel value. They could be put in a
// subtarget common include file, but it seems the include system in Tablegen
// currently (2016) rejects multiple includes of same file.
// Decoder grouping rules
let NumMicroOps = 1 in {
def : WriteRes<NormalGr, []>;
def : WriteRes<BeginGroup, []> { let BeginGroup = 1; }
def : WriteRes<EndGroup, []> { let EndGroup = 1; }
}
def : WriteRes<Cracked, []> {
let NumMicroOps = 2;
let BeginGroup = 1;
}
def : WriteRes<GroupAlone, []> {
let NumMicroOps = 3;
let BeginGroup = 1;
let EndGroup = 1;
}
def : WriteRes<GroupAlone2, []> {
let NumMicroOps = 6;
let BeginGroup = 1;
let EndGroup = 1;
}
def : WriteRes<GroupAlone3, []> {
let NumMicroOps = 9;
let BeginGroup = 1;
let EndGroup = 1;
}
// Incoming latency removed from the register operand which is used together
// with a memory operand by the instruction.
def : ReadAdvance<RegReadAdv, 4>;
// LoadLatency (above) is not used for instructions in this file. This is
// instead the role of LSULatency, which is the latency value added to the
// result of loads and instructions with folded memory operands.
def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
let NumMicroOps = 0 in {
foreach L = 1-30 in
def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
}
// Execution units.
def Z14_FXaUnit : ProcResource<2>;
def Z14_FXbUnit : ProcResource<2>;
def Z14_LSUnit : ProcResource<2>;
def Z14_VecUnit : ProcResource<2>;
def Z14_VecFPdUnit : ProcResource<2> { let BufferSize = 1; /* blocking */ }
def Z14_VBUnit : ProcResource<2>;
def Z14_MCD : ProcResource<1>;
// Subtarget specific definitions of scheduling resources.
let NumMicroOps = 0 in {
def : WriteRes<FXa, [Z14_FXaUnit]>;
def : WriteRes<FXb, [Z14_FXbUnit]>;
def : WriteRes<LSU, [Z14_LSUnit]>;
def : WriteRes<VecBF, [Z14_VecUnit]>;
def : WriteRes<VecDF, [Z14_VecUnit]>;
def : WriteRes<VecDFX, [Z14_VecUnit]>;
def : WriteRes<VecMul, [Z14_VecUnit]>;
def : WriteRes<VecStr, [Z14_VecUnit]>;
def : WriteRes<VecXsPm, [Z14_VecUnit]>;
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z14_VecUnit]>;
def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z14_VecUnit]>;
def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z14_VecUnit]>;
def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z14_VecUnit]>;
def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z14_VecUnit]>;
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
}}
def : WriteRes<VecFPd, [Z14_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VBU, [Z14_VBUnit]>; // Virtual Branching Unit
}
def : WriteRes<MCD, [Z14_MCD]> { let NumMicroOps = 3;
let BeginGroup = 1;
let EndGroup = 1; }
// -------------------------- INSTRUCTIONS ---------------------------------- //
// InstRW constructs have been used in order to preserve the
// readability of the InstrInfo files.
// For each instruction, as matched by a regexp, provide a list of
// resources that it needs. These will be combined into a SchedClass.
//===----------------------------------------------------------------------===//
// Stack allocation
//===----------------------------------------------------------------------===//
// Pseudo -> LA / LAY
def : InstRW<[WLat1, FXa, NormalGr], (instregex "ADJDYNALLOC$")>;
//===----------------------------------------------------------------------===//
// Branch instructions
//===----------------------------------------------------------------------===//
// Branch
def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?J(G)?(Asm.*)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
def : InstRW<[WLat1, FXa, FXb, GroupAlone], (instregex "BRCTH$")>;
def : InstRW<[WLat1, FXa, FXb, GroupAlone], (instregex "BCT(G)?(R)?$")>;
def : InstRW<[WLat1, FXa2, FXb2, GroupAlone2],
(instregex "B(R)?X(H|L).*$")>;
// Compare and branch
def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
def : InstRW<[WLat1, FXb2, GroupAlone],
(instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
//===----------------------------------------------------------------------===//
// Trap instructions
//===----------------------------------------------------------------------===//
// Trap
def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Cond)?Trap$")>;
// Compare and trap
def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CL(G)?RT(Asm.*)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CL(F|G)IT(Asm.*)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
//===----------------------------------------------------------------------===//
// Call and return instructions
//===----------------------------------------------------------------------===//
// Call
def : InstRW<[WLat1, VBU, FXa2, GroupAlone], (instregex "(Call)?BRAS$")>;
def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "(Call)?BRASL(_XPLINK64)?$")>;
def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "(Call)?BAS(R)?(_XPLINK64)?$")>;
def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
// Return
def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CondReturn$")>;
//===----------------------------------------------------------------------===//
// Move instructions
//===----------------------------------------------------------------------===//
// Moves
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
// Move character
def : InstRW<[WLat1, FXb, LSU3, GroupAlone], (instregex "MVC$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVCL(E|U)?$")>;
// Pseudo -> reg move
def : InstRW<[WLat1, FXa, NormalGr], (instregex "COPY(_TO_REGCLASS)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "EXTRACT_SUBREG$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "INSERT_SUBREG$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "REG_SEQUENCE$")>;
// Loads
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIH(F|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIL(F|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>;
// Load and zero rightmost byte
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;
// Load and trap
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "L(FH|G)?AT$")>;
// Load and test
def : InstRW<[WLat1LSU, WLat1LSU, LSU, FXa, NormalGr], (instregex "LT(G)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LT(G)?R$")>;
// Stores
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST128$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
// String moves.
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVST$")>;
//===----------------------------------------------------------------------===//
// Conditional move instructions
//===----------------------------------------------------------------------===//
def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOCRMux$")>;
def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|FH)?R(Asm.*)?$")>;
def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|H)?HI(Mux|(Asm.*))?$")>;
def : InstRW<[WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "LOC(G|FH|Mux)?(Asm.*)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr],
(instregex "STOC(G|FH|Mux)?(Asm.*)?$")>;
//===----------------------------------------------------------------------===//
// Sign extensions
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, FXa, NormalGr], (instregex "L(B|H|G)R$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(B|H|F)R$")>;
def : InstRW<[WLat1LSU, WLat1LSU, FXa, LSU, NormalGr], (instregex "LTGF$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LTGFR$")>;
def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(Y)?$")>;
def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(B|H|F)$")>;
def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
//===----------------------------------------------------------------------===//
// Zero extensions
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLHR(Mux)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLG(C|H|F|T)R$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLC(Mux)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLH(Mux)?$")>;
def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LL(C|H)H$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLHRL$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
// Load and zero rightmost byte
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLZRGF$")>;
// Load and trap
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "LLG(F|T)?AT$")>;
//===----------------------------------------------------------------------===//
// Truncations
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STC(H|Y|Mux)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STCM(H|Y)?$")>;
//===----------------------------------------------------------------------===//
// Multi-register moves
//===----------------------------------------------------------------------===//
// Load multiple (estimated average of 5 ops)
def : InstRW<[WLat10, WLat10, LSU5, GroupAlone], (instregex "LM(H|Y|G)?$")>;
// Load multiple disjoint
def : InstRW<[WLat30, WLat30, MCD], (instregex "LMD$")>;
// Store multiple
def : InstRW<[WLat1, LSU2, FXb3, GroupAlone], (instregex "STM(G|H|Y)?$")>;
//===----------------------------------------------------------------------===//
// Byte swaps
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LRV(G)?R$")>;
def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LRV(G|H)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STRV(G|H)?$")>;
def : InstRW<[WLat30, MCD], (instregex "MVCIN$")>;
//===----------------------------------------------------------------------===//
// Load address instructions
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LA(Y|RL)?$")>;
// Load the Global Offset Table address ( -> larl )
def : InstRW<[WLat1, FXa, NormalGr], (instregex "GOT$")>;
//===----------------------------------------------------------------------===//
// Absolute and Negation
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, WLat1, FXa, NormalGr], (instregex "LP(G)?R$")>;
def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "L(N|P)GFR$")>;
def : InstRW<[WLat1, WLat1, FXa, NormalGr], (instregex "LN(R|GR)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LC(R|GR)$")>;
def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "LCGFR$")>;
//===----------------------------------------------------------------------===//
// Insertion
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr], (instregex "IC(Y)?$")>;
def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "IC32(Y)?$")>;
def : InstRW<[WLat1LSU, RegReadAdv, WLat1LSU, FXa, LSU, NormalGr],
(instregex "ICM(H|Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "II(F|H|L)Mux$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "IIHF(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "IIHH(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "IIHL(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "IILF(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "IILH(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "IILL(64)?$")>;
//===----------------------------------------------------------------------===//
// Addition
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "A(Y)?$")>;
def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "AH(Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "AIH$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "AFI(Mux)?$")>;
def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "AG$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "AGFI$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "AGHI(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "AGR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "AHI(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "AHIMux(K)?$")>;
def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "AL(Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "AL(FI|HSIK)$")>;
def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "ALG(F)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALGHSIK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALGF(I|R)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALGR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "AR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "A(L)?HHHR$")>;
def : InstRW<[WLat2, WLat2, FXa, NormalGr], (instregex "A(L)?HHLR$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALSIH(N)?$")>;
def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "A(L)?(G)?SI$")>;
// Logical addition with carry
def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, GroupAlone],
(instregex "ALC(G)?$")>;
def : InstRW<[WLat2, WLat2, FXa, GroupAlone], (instregex "ALC(G)?R$")>;
// Add with sign extension (16/32 -> 64)
def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "AG(F|H)$")>;
def : InstRW<[WLat2, WLat2, FXa, NormalGr], (instregex "AGFR$")>;
//===----------------------------------------------------------------------===//
// Subtraction
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "S(G|Y)?$")>;
def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "SH(Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SGR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLFI$")>;
def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "SL(G|GF|Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLGF(I|R)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLGR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "S(L)?HHHR$")>;
def : InstRW<[WLat2, WLat2, FXa, NormalGr], (instregex "S(L)?HHLR$")>;
// Subtraction with borrow
def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, GroupAlone],
(instregex "SLB(G)?$")>;
def : InstRW<[WLat2, WLat2, FXa, GroupAlone], (instregex "SLB(G)?R$")>;
// Subtraction with sign extension (16/32 -> 64)
def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "SG(F|H)$")>;
def : InstRW<[WLat2, WLat2, FXa, NormalGr], (instregex "SGFR$")>;
//===----------------------------------------------------------------------===//
// AND
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "N(G|Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NGR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NI(FMux|HMux|LMux)$")>;
def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "NI(Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NIHF(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NIHH(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NIHL(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NILF(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NILH(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NILL(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NR(K)?$")>;
def : InstRW<[WLat3LSU, LSU2, FXb, Cracked], (instregex "NC$")>;
//===----------------------------------------------------------------------===//
// OR
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "O(G|Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OGR(K)?$")>;
def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "OI(Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OI(FMux|HMux|LMux)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OIHF(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OIHH(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OIHL(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OILF(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OILH(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OILL(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OR(K)?$")>;
def : InstRW<[WLat3LSU, LSU2, FXb, Cracked], (instregex "OC$")>;
//===----------------------------------------------------------------------===//
// XOR
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "X(G|Y)?$")>;
def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "XI(Y)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "XIFMux$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "XGR(K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "XIHF(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "XILF(64)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "XR(K)?$")>;
def : InstRW<[WLat3LSU, LSU2, FXb, Cracked], (instregex "XC$")>;
//===----------------------------------------------------------------------===//
// Multiplication
//===----------------------------------------------------------------------===//
def : InstRW<[WLat5LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "MS(GF|Y)?$")>;
def : InstRW<[WLat5, FXa, NormalGr], (instregex "MS(R|FI)$")>;
def : InstRW<[WLat7LSU, RegReadAdv, FXa, LSU, NormalGr], (instregex "MSG$")>;
def : InstRW<[WLat7, FXa, NormalGr], (instregex "MSGR$")>;
def : InstRW<[WLat5, FXa, NormalGr], (instregex "MSGF(I|R)$")>;
def : InstRW<[WLat8LSU, RegReadAdv, FXa2, LSU, GroupAlone], (instregex "MLG$")>;
def : InstRW<[WLat8, FXa2, GroupAlone], (instregex "MLGR$")>;
def : InstRW<[WLat4, FXa, NormalGr], (instregex "MGHI$")>;
def : InstRW<[WLat4, FXa, NormalGr], (instregex "MHI$")>;
def : InstRW<[WLat4LSU, RegReadAdv, FXa, LSU, NormalGr], (instregex "MH(Y)?$")>;
def : InstRW<[WLat6, FXa2, GroupAlone], (instregex "M(L)?R$")>;
def : InstRW<[WLat6LSU, RegReadAdv, FXa2, LSU, GroupAlone],
(instregex "M(FY|L)?$")>;
def : InstRW<[WLat8, RegReadAdv, FXa, LSU, NormalGr], (instregex "MGH$")>;
def : InstRW<[WLat12, RegReadAdv, FXa2, LSU, GroupAlone], (instregex "MG$")>;
def : InstRW<[WLat8, FXa2, GroupAlone], (instregex "MGRK$")>;
def : InstRW<[WLat6LSU, WLat6LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "MSC$")>;
def : InstRW<[WLat8LSU, WLat8LSU, RegReadAdv, FXa, LSU, NormalGr],
(instregex "MSGC$")>;
def : InstRW<[WLat6, WLat6, FXa, NormalGr], (instregex "MSRKC$")>;
def : InstRW<[WLat8, WLat8, FXa, NormalGr], (instregex "MSGRKC$")>;
//===----------------------------------------------------------------------===//
// Division and remainder
//===----------------------------------------------------------------------===//
def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DR$")>;
def : InstRW<[WLat30, RegReadAdv, FXa4, LSU, GroupAlone2], (instregex "D$")>;
def : InstRW<[WLat30, FXa2, GroupAlone], (instregex "DSG(F)?R$")>;
def : InstRW<[WLat30, RegReadAdv, FXa2, LSU, GroupAlone2],
(instregex "DSG(F)?$")>;
def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DLR$")>;
def : InstRW<[WLat30, FXa4, GroupAlone], (instregex "DLGR$")>;
def : InstRW<[WLat30, RegReadAdv, FXa4, LSU, GroupAlone2],
(instregex "DL(G)?$")>;
//===----------------------------------------------------------------------===//
// Shifts
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLL(G|K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SRL(G|K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SRA(G|K)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLA(G|K)?$")>;
def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
(instregex "S(L|R)D(A|L)$")>;
// Rotate
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
//===----------------------------------------------------------------------===//
// Comparison
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
(instregex "C(G|Y|Mux)?$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CRL$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(F|H)I(Mux)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CG(F|H)I$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(G)?R$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CIH$")>;
def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CHF$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CHSI$")>;
def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
(instregex "CL(Y|Mux)?$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLFHSI$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLFI(Mux)?$")>;
def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CLG$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLG(HRL|HSI)$")>;
def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CLGF$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLGFRL$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLGF(I|R)$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLGR$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLGRL$")>;
def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CLHF$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLIH$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLI(Y)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLR$")>;
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLRL$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(L)?HHR$")>;
def : InstRW<[WLat2, FXb, NormalGr], (instregex "C(L)?HLR$")>;
// Compare halfword
def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CH(Y)?$")>;
def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "CHRL$")>;
def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CGH$")>;
def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "CGHRL$")>;
def : InstRW<[WLat2LSU, FXa, FXb, LSU, Cracked], (instregex "CHHSI$")>;
// Compare with sign extension (32 -> 64)
def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CGF$")>;
def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "CGFRL$")>;
def : InstRW<[WLat2, FXb, NormalGr], (instregex "CGFR$")>;
// Compare logical character
def : InstRW<[WLat6, FXb, LSU2, Cracked], (instregex "CLC$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLCL(E|U)?$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLST$")>;
// Test under mask
def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "TM(Y)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "TM(H|L)Mux$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "TMHH(64)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "TMHL(64)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "TMLH(64)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "TMLL(64)?$")>;
// Compare logical characters under mask
def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr],
(instregex "CLM(H|Y)?$")>;
//===----------------------------------------------------------------------===//
// Prefetch and execution hint
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, LSU, NormalGr], (instregex "PFD(RL)?$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "BPP$")>;
def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "NIAI$")>;
//===----------------------------------------------------------------------===//
// Atomic operations
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, FXb, EndGroup], (instregex "Serialize$")>;
def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAA(G)?$")>;
def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAAL(G)?$")>;
def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAN(G)?$")>;
def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAO(G)?$")>;
def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAX(G)?$")>;
// Test and set
def : InstRW<[WLat2LSU, FXb, LSU, EndGroup], (instregex "TS$")>;
// Compare and swap
def : InstRW<[WLat3LSU, WLat3LSU, FXa, FXb, LSU, GroupAlone],
(instregex "CS(G|Y)?$")>;
// Compare double and swap
def : InstRW<[WLat6LSU, WLat6LSU, FXa3, FXb2, LSU, GroupAlone2],
(instregex "CDS(Y)?$")>;
def : InstRW<[WLat15, WLat15, FXa2, FXb4, LSU3,
GroupAlone3], (instregex "CDSG$")>;
// Compare and swap and store
def : InstRW<[WLat30, MCD], (instregex "CSST$")>;
// Perform locked operation
def : InstRW<[WLat30, MCD], (instregex "PLO$")>;
// Load/store pair from/to quadword
def : InstRW<[WLat4LSU, LSU2, GroupAlone], (instregex "LPQ$")>;
def : InstRW<[WLat1, FXb2, LSU, GroupAlone], (instregex "STPQ$")>;
// Load pair disjoint
def : InstRW<[WLat1LSU, WLat1LSU, LSU2, GroupAlone], (instregex "LPD(G)?$")>;
//===----------------------------------------------------------------------===//
// Translate and convert
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "TR$")>;
def : InstRW<[WLat30, WLat30, WLat30, FXa3, LSU2, GroupAlone2],
(instregex "TRT$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRTR$")>;
def : InstRW<[WLat30, WLat30, MCD], (instregex "TRE$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRT(R)?E(Opt)?$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TR(T|O)(T|O)(Opt)?$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD],
(instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
//===----------------------------------------------------------------------===//
// Message-security assist
//===----------------------------------------------------------------------===//
def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD],
(instregex "KM(C|F|O|CTR|A)?$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD],
(instregex "(KIMD|KLMD|KMAC)$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD],
(instregex "(PCC|PPNO|PRNO)$")>;
//===----------------------------------------------------------------------===//
// Guarded storage
//===----------------------------------------------------------------------===//
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LGG$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLGFSG$")>;
def : InstRW<[WLat30, MCD], (instregex "(L|ST)GSC$")>;
//===----------------------------------------------------------------------===//
// Decimal arithmetic
//===----------------------------------------------------------------------===//
def : InstRW<[WLat30, RegReadAdv, FXb, VecDF2, LSU2, GroupAlone2],
(instregex "CVBG$")>;
def : InstRW<[WLat30, RegReadAdv, FXb, VecDF, LSU, GroupAlone2],
(instregex "CVB(Y)?$")>;
def : InstRW<[WLat1, FXb3, VecDF4, LSU, GroupAlone3], (instregex "CVDG$")>;
def : InstRW<[WLat1, FXb2, VecDF, LSU, GroupAlone2], (instregex "CVD(Y)?$")>;
def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "MV(N|O|Z)$")>;
def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "(PACK|PKA|PKU)$")>;
def : InstRW<[WLat12, LSU5, GroupAlone], (instregex "UNPK(A|U)$")>;
def : InstRW<[WLat1, FXb, LSU2, Cracked], (instregex "UNPK$")>;
def : InstRW<[WLat5LSU, FXb, VecDFX, LSU3, GroupAlone2],
(instregex "(A|S|ZA)P$")>;
def : InstRW<[WLat1, FXb, VecDFX4, LSU3, GroupAlone2], (instregex "(M|D)P$")>;
def : InstRW<[WLat15, FXb, VecDFX2, LSU2, GroupAlone3], (instregex "SRP$")>;
def : InstRW<[WLat8, VecDFX, LSU, LSU, GroupAlone], (instregex "CP$")>;
def : InstRW<[WLat3LSU, VecDFX, LSU, Cracked], (instregex "TP$")>;
def : InstRW<[WLat30, MCD], (instregex "ED(MK)?$")>;
//===----------------------------------------------------------------------===//
// Access registers
//===----------------------------------------------------------------------===//
// Extract/set/copy access register
def : InstRW<[WLat3, LSU, NormalGr], (instregex "(EAR|SAR|CPYA)$")>;
// Load address extended
def : InstRW<[WLat5, LSU, FXa, Cracked], (instregex "LAE(Y)?$")>;
// Load/store access multiple (not modeled precisely)
def : InstRW<[WLat20, WLat20, LSU5, GroupAlone], (instregex "LAM(Y)?$")>;
def : InstRW<[WLat1, LSU5, FXb, GroupAlone2], (instregex "STAM(Y)?$")>;
//===----------------------------------------------------------------------===//
// Program mask and addressing mode
//===----------------------------------------------------------------------===//
// Insert Program Mask
def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
// Set Program Mask
def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
// Branch and link
def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "BAL(R)?$")>;
// Test addressing mode
def : InstRW<[WLat1, FXb, NormalGr], (instregex "TAM$")>;
// Set addressing mode
def : InstRW<[WLat1, FXb, EndGroup], (instregex "SAM(24|31|64)$")>;
// Branch (and save) and set mode.
def : InstRW<[WLat1, FXa, FXb, GroupAlone], (instregex "BSM$")>;
def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "BASSM$")>;
//===----------------------------------------------------------------------===//
// Transactional execution
//===----------------------------------------------------------------------===//
// Transaction begin
def : InstRW<[WLat9, LSU2, FXb5, GroupAlone2], (instregex "TBEGIN(C)?$")>;
// Transaction end
def : InstRW<[WLat1, FXb, GroupAlone], (instregex "TEND$")>;
// Transaction abort
def : InstRW<[WLat30, MCD], (instregex "TABORT$")>;
// Extract Transaction Nesting Depth
def : InstRW<[WLat1, FXa, NormalGr], (instregex "ETND$")>;
// Nontransactional store
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "NTSTG$")>;
//===----------------------------------------------------------------------===//
// Processor assist
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, FXb, GroupAlone], (instregex "PPA$")>;
//===----------------------------------------------------------------------===//
// Miscellaneous Instructions.
//===----------------------------------------------------------------------===//
// Find leftmost one
def : InstRW<[WLat5, WLat5, FXa2, GroupAlone], (instregex "FLOGR$")>;
// Population count
def : InstRW<[WLat3, WLat3, FXa, NormalGr], (instregex "POPCNT$")>;
// String instructions
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "SRST(U)?$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CUSE$")>;
// Various complex instructions
def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CFC$")>;
def : InstRW<[WLat30, WLat30, WLat30, WLat30, WLat30, WLat30, MCD],
(instregex "UPT$")>;
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CKSM$")>;
def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CMPSC$")>;
// Execute
def : InstRW<[WLat1, FXb, GroupAlone], (instregex "EX(RL)?$")>;
//===----------------------------------------------------------------------===//
// .insn directive instructions
//===----------------------------------------------------------------------===//
// An "empty" sched-class will be assigned instead of the "invalid sched-class".
// getNumDecoderSlots() will then return 1 instead of 0.
def : InstRW<[], (instregex "Insn.*")>;
// ----------------------------- Floating point ----------------------------- //
//===----------------------------------------------------------------------===//
// FP: Move instructions
//===----------------------------------------------------------------------===//
// Load zero
def : InstRW<[WLat1, FXb, NormalGr], (instregex "LZ(DR|ER)$")>;
def : InstRW<[WLat2, FXb2, Cracked], (instregex "LZXR$")>;
// Load
def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "LER$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "LD(R|R32|GR)$")>;
def : InstRW<[WLat3, FXb, NormalGr], (instregex "LGDR$")>;
def : InstRW<[WLat2, FXb2, GroupAlone], (instregex "LXR$")>;
// Load and Test
def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BR$")>;
def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BRCompare$")>;
def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone],
(instregex "LTXBR(Compare)?$")>;
// Copy sign
def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>;
//===----------------------------------------------------------------------===//
// FP: Load instructions
//===----------------------------------------------------------------------===//
def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "LE(Y)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LD(Y|E32)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;
//===----------------------------------------------------------------------===//
// FP: Store instructions
//===----------------------------------------------------------------------===//
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STX$")>;
//===----------------------------------------------------------------------===//
// FP: Conversion instructions
//===----------------------------------------------------------------------===//
// Load rounded
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "LEDBR(A)?$")>;
def : InstRW<[WLat9, VecDF2, NormalGr], (instregex "L(E|D)XBR(A)?$")>;
// Load lengthened
def : InstRW<[WLat7LSU, VecBF, LSU, NormalGr], (instregex "LDEB$")>;
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "LDEBR$")>;
def : InstRW<[WLat8LSU, VecBF4, LSU, GroupAlone], (instregex "LX(E|D)B$")>;
def : InstRW<[WLat8, VecBF4, GroupAlone], (instregex "LX(E|D)BR$")>;
// Convert from fixed / logical
def : InstRW<[WLat8, FXb, VecBF, Cracked], (instregex "C(E|D)(F|G)BR(A)?$")>;
def : InstRW<[WLat11, FXb, VecDF4, GroupAlone2], (instregex "CX(F|G)BR(A)?$")>;
def : InstRW<[WLat8, FXb, VecBF, Cracked], (instregex "C(E|D)L(F|G)BR$")>;
def : InstRW<[WLat11, FXb, VecDF4, GroupAlone2], (instregex "CXL(F|G)BR$")>;
// Convert to fixed / logical
def : InstRW<[WLat10, WLat10, FXb, VecBF, Cracked],
(instregex "C(F|G)(E|D)BR(A)?$")>;
def : InstRW<[WLat12, WLat12, FXb, VecDF2, Cracked],
(instregex "C(F|G)XBR(A)?$")>;
def : InstRW<[WLat10, WLat10, FXb, VecBF, GroupAlone], (instregex "CLFEBR$")>;
def : InstRW<[WLat10, WLat10, FXb, VecBF, Cracked], (instregex "CLFDBR$")>;
def : InstRW<[WLat10, WLat10, FXb, VecBF, Cracked], (instregex "CLG(E|D)BR$")>;
def : InstRW<[WLat12, WLat12, FXb, VecDF2, Cracked], (instregex "CL(F|G)XBR$")>;
//===----------------------------------------------------------------------===//
// FP: Unary arithmetic
//===----------------------------------------------------------------------===//
// Load Complement / Negative / Positive
def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "L(C|N|P)(E|D)BR$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "L(C|N|P)DFR(_32)?$")>;
def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "L(C|N|P)XBR$")>;
// Square root
def : InstRW<[WLat30, VecFPd, LSU, NormalGr], (instregex "SQ(E|D)B$")>;
def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "SQ(E|D)BR$")>;
def : InstRW<[WLat30, VecFPd, GroupAlone], (instregex "SQXBR$")>;
// Load FP integer
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "FI(E|D)BR(A)?$")>;
def : InstRW<[WLat10, VecDF4, GroupAlone], (instregex "FIXBR(A)?$")>;
//===----------------------------------------------------------------------===//
// FP: Binary arithmetic
//===----------------------------------------------------------------------===//
// Addition
def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, VecBF, LSU, NormalGr],
(instregex "A(E|D)B$")>;
def : InstRW<[WLat7, WLat7, VecBF, NormalGr], (instregex "A(E|D)BR$")>;
def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "AXBR$")>;
// Subtraction
def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, VecBF, LSU, NormalGr],
(instregex "S(E|D)B$")>;
def : InstRW<[WLat7, WLat7, VecBF, NormalGr], (instregex "S(E|D)BR$")>;
def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "SXBR$")>;
// Multiply
def : InstRW<[WLat7LSU, RegReadAdv, VecBF, LSU, NormalGr],
(instregex "M(D|DE|EE)B$")>;
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "M(D|DE|EE)BR$")>;
def : InstRW<[WLat8LSU, RegReadAdv, VecBF4, LSU, GroupAlone],
(instregex "MXDB$")>;
def : InstRW<[WLat8, VecBF4, GroupAlone], (instregex "MXDBR$")>;
def : InstRW<[WLat20, VecDF4, GroupAlone], (instregex "MXBR$")>;
// Multiply and add / subtract
def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, VecBF2, LSU, GroupAlone],
(instregex "M(A|S)EB$")>;
def : InstRW<[WLat7, VecBF, GroupAlone], (instregex "M(A|S)EBR$")>;
def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, VecBF2, LSU, GroupAlone],
(instregex "M(A|S)DB$")>;
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "M(A|S)DBR$")>;
// Division
def : InstRW<[WLat30, RegReadAdv, VecFPd, LSU, NormalGr],
(instregex "D(E|D)B$")>;
def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "D(E|D)BR$")>;
def : InstRW<[WLat30, VecFPd, GroupAlone], (instregex "DXBR$")>;
// Divide to integer
def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "DI(E|D)BR$")>;
//===----------------------------------------------------------------------===//
// FP: Comparisons
//===----------------------------------------------------------------------===//
// Compare
def : InstRW<[WLat3LSU, RegReadAdv, VecXsPm, LSU, NormalGr],
(instregex "(K|C)(E|D)B$")>;
def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "(K|C)(E|D)BR$")>;
def : InstRW<[WLat9, VecDF2, GroupAlone], (instregex "(K|C)XBR$")>;
// Test Data Class
def : InstRW<[WLat5, LSU, VecXsPm, NormalGr], (instregex "TC(E|D)B$")>;
def : InstRW<[WLat10, LSU, VecDF4, GroupAlone], (instregex "TCXB$")>;
//===----------------------------------------------------------------------===//
// FP: Floating-point control register instructions
//===----------------------------------------------------------------------===//
def : InstRW<[WLat4, FXa, LSU, GroupAlone], (instregex "EFPC$")>;
def : InstRW<[WLat1, FXb, LSU, GroupAlone], (instregex "STFPC$")>;
def : InstRW<[WLat3, LSU, GroupAlone], (instregex "SFPC$")>;
def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LFPC$")>;
def : InstRW<[WLat30, MCD], (instregex "SFASR$")>;
def : InstRW<[WLat30, MCD], (instregex "LFAS$")>;
def : InstRW<[WLat3, FXb, GroupAlone], (instregex "SRNM(B|T)?$")>;
// --------------------- Hexadecimal floating point ------------------------- //
//===----------------------------------------------------------------------===//
// HFP: Move instructions
//===----------------------------------------------------------------------===//
// Load and Test
def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)R$")>;
def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "LTXR$")>;
//===----------------------------------------------------------------------===//
// HFP: Conversion instructions
//===----------------------------------------------------------------------===//
// Load rounded
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "(LEDR|LRER)$")>;
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "LEXR$")>;
def : InstRW<[WLat9, VecDF2, NormalGr], (instregex "(LDXR|LRDR)$")>;
// Load lengthened
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LDE$")>;
def : InstRW<[WLat1, FXb, NormalGr], (instregex "LDER$")>;
def : InstRW<[WLat8LSU, VecBF4, LSU, GroupAlone], (instregex "LX(E|D)$")>;
def : InstRW<[WLat8, VecBF4, GroupAlone], (instregex "LX(E|D)R$")>;
// Convert from fixed
def : InstRW<[WLat8, FXb, VecBF, Cracked], (instregex "C(E|D)(F|G)R$")>;
def : InstRW<[WLat11, FXb, VecDF4, GroupAlone2], (instregex "CX(F|G)R$")>;
// Convert to fixed
def : InstRW<[WLat10, WLat10, FXb, VecBF, Cracked], (instregex "C(F|G)(E|D)R$")>;
def : InstRW<[WLat12, WLat12, FXb, VecDF2, Cracked], (instregex "C(F|G)XR$")>;
// Convert BFP to HFP / HFP to BFP.
def : InstRW<[WLat7, WLat7, VecBF, NormalGr], (instregex "THD(E)?R$")>;
def : InstRW<[WLat7, WLat7, VecBF, NormalGr], (instregex "TB(E)?DR$")>;
//===----------------------------------------------------------------------===//
// HFP: Unary arithmetic
//===----------------------------------------------------------------------===//
// Load Complement / Negative / Positive
def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "L(C|N|P)(E|D)R$")>;
def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "L(C|N|P)XR$")>;
// Halve
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "H(E|D)R$")>;
// Square root
def : InstRW<[WLat30, VecFPd, LSU, NormalGr], (instregex "SQ(E|D)$")>;
def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "SQ(E|D)R$")>;
def : InstRW<[WLat30, VecFPd, GroupAlone], (instregex "SQXR$")>;
// Load FP integer
def : InstRW<[WLat7, VecBF, NormalGr], (instregex "FI(E|D)R$")>;