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SystemZInstrInfo.td
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//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">;
def IsTargetELF : Predicate<"Subtarget->isTargetELF()">;
//===----------------------------------------------------------------------===//
// Stack allocation
//===----------------------------------------------------------------------===//
// The callseq_start node requires the hasSideEffects flag, even though these
// instructions are noops on SystemZ.
let hasNoSchedulingInfo = 1, hasSideEffects = 1 in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
[(callseq_start timm:$amt1, timm:$amt2)]>;
def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
[(callseq_end timm:$amt1, timm:$amt2)]>;
}
// Takes as input the value of the stack pointer after a dynamic allocation
// has been made. Sets the output to the address of the dynamically-
// allocated area itself, skipping the outgoing arguments.
//
// This expands to an LA or LAY instruction. We restrict the offset
// to the range of LA and keep the LAY range in reserve for when
// the size of the outgoing arguments is added.
def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
[(set GR64:$dst, dynalloc12only:$src)]>;
let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,
usesCustomInserter = 1 in
def PROBED_ALLOCA : Pseudo<(outs GR64:$dst),
(ins GR64:$oldSP, GR64:$space),
[(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>;
let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,
hasSideEffects = 1 in
def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>;
//===----------------------------------------------------------------------===//
// Branch instructions
//===----------------------------------------------------------------------===//
// Conditional branches.
let isBranch = 1, isTerminator = 1, Uses = [CC] in {
// It's easier for LLVM to handle these branches in their raw BRC/BRCL form
// with the condition-code mask being the first operand. It seems friendlier
// to use mnemonic forms like JE and JLH when writing out the assembly though.
let isCodeGenOnly = 1 in {
// An assembler extended mnemonic for BRC.
def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>;
// An assembler extended mnemonic for BRCL. (The extension is "G"
// rather than "L" because "JL" is "Jump if Less".)
def BRCL : CondBranchRIL<"jg#", 0xC04>;
let isIndirectBranch = 1 in {
def BC : CondBranchRX<"b#", 0x47>;
def BCR : CondBranchRR<"b#r", 0x07>;
def BIC : CondBranchRXY<"bi#", 0xe347>,
Requires<[FeatureMiscellaneousExtensions2]>;
}
}
// Allow using the raw forms directly from the assembler (and occasional
// special code generation needs) as well.
def BRCAsm : AsmCondBranchRI <"brc", 0xA74>;
def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>;
let isIndirectBranch = 1 in {
def BCAsm : AsmCondBranchRX<"bc", 0x47>;
def BCRAsm : AsmCondBranchRR<"bcr", 0x07>;
def BICAsm : AsmCondBranchRXY<"bic", 0xe347>,
Requires<[FeatureMiscellaneousExtensions2]>;
}
// Define AsmParser extended mnemonics for each general condition-code mask
// (integer or floating-point)
foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
"Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>;
def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>;
let isIndirectBranch = 1 in {
def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>;
def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>;
def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>,
Requires<[FeatureMiscellaneousExtensions2]>;
}
}
}
// Unconditional branches. These are in fact simply variants of the
// conditional branches with the condition mask set to "always".
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>;
def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>;
let isIndirectBranch = 1 in {
def B : FixedCondBranchRX<CondAlways, "b", 0x47>;
def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>;
def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>,
Requires<[FeatureMiscellaneousExtensions2]>;
}
}
// NOPs. These are again variants of the conditional branches, with the
// condition mask set to "never". NOP_bare can't be an InstAlias since it
// would need R0D hard coded which is not part of ADDR64BitRegClass.
def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in
def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
// An alias of BRC 0, label
def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>;
// An alias of BRCL 0, label
// jgnop on att ; jlnop on hlasm
def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>;
// Fused compare-and-branch instructions.
//
// These instructions do not use or clobber the condition codes.
// We nevertheless pretend that the relative compare-and-branch
// instructions clobber CC, so that we can lower them to separate
// comparisons and BRCLs if the branch ends up being out of range.
let isBranch = 1, isTerminator = 1 in {
// As for normal branches, we handle these instructions internally in
// their raw CRJ-like form, but use assembly macros like CRJE when writing
// them out. Using the *Pair multiclasses, we also create the raw forms.
let Defs = [CC] in {
defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>;
defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>;
defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>;
defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>;
defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>;
defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>;
defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>;
defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>;
}
let isIndirectBranch = 1 in {
defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>;
defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>;
defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>;
defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>;
defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>;
defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>;
defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>;
defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>;
}
// Define AsmParser mnemonics for each integer condition-code mask.
foreach V = [ "E", "H", "L", "HE", "LE", "LH",
"NE", "NH", "NL", "NHE", "NLE", "NLH" ] in {
let Defs = [CC] in {
def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>;
def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>;
def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32,
imm32sx8>;
def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64,
imm64sx8>;
def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>;
def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>;
def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32,
imm32zx8>;
def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64,
imm64zx8>;
}
let isIndirectBranch = 1 in {
def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>;
def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>;
def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32,
imm32sx8>;
def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64,
imm64sx8>;
def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>;
def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>;
def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32,
imm32zx8>;
def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64,
imm64zx8>;
}
}
}
// Decrement a register and branch if it is nonzero. These don't clobber CC,
// but we might need to split long relative branches into sequences that do.
let isBranch = 1, isTerminator = 1 in {
let Defs = [CC] in {
def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>;
def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
}
// This doesn't need to clobber CC since we never need to split it.
def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>,
Requires<[FeatureHighWord]>;
def BCT : BranchUnaryRX<"bct", 0x46,GR32>;
def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>;
def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>;
def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>;
}
let isBranch = 1, isTerminator = 1 in {
let Defs = [CC] in {
def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>;
def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>;
def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>;
def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>;
}
def BXH : BranchBinaryRS<"bxh", 0x86, GR32>;
def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>;
def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>;
def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>;
}
//===----------------------------------------------------------------------===//
// Trap instructions
//===----------------------------------------------------------------------===//
// Unconditional trap.
let hasCtrlDep = 1, hasSideEffects = 1 in
def Trap : Alias<4, (outs), (ins), [(trap)]>;
// Conditional trap.
let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in
def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>;
// Fused compare-and-trap instructions.
let hasCtrlDep = 1, hasSideEffects = 1 in {
// These patterns work the same way as for compare-and-branch.
defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>;
defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>;
defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>;
defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>;
defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>;
defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>;
defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>;
defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>;
let Predicates = [FeatureMiscellaneousExtensions] in {
defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>;
defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>;
}
foreach V = [ "E", "H", "L", "HE", "LE", "LH",
"NE", "NH", "NL", "NHE", "NLE", "NLH" ] in {
def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>;
def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>;
def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>;
def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>;
def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32,
imm32sx16>;
def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64,
imm64sx16>;
def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32,
imm32zx16>;
def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64,
imm64zx16>;
let Predicates = [FeatureMiscellaneousExtensions] in {
def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>;
def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>;
}
}
}
//===----------------------------------------------------------------------===//
// Call and return instructions
//===----------------------------------------------------------------------===//
// Define the general form of the call instructions for the asm parser.
// These instructions don't hard-code %r14 as the return address register.
let isCall = 1, Defs = [CC] in {
def BRAS : CallRI <"bras", 0xA75>;
def BRASL : CallRIL<"brasl", 0xC05>;
def BAS : CallRX <"bas", 0x4D>;
def BASR : CallRR <"basr", 0x0D>;
}
// z/OS XPLINK
let Predicates = [IsTargetXPLINK64] in {
let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in {
def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops),
[(z_call pcrel32:$I2)]>;
def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops),
[(z_call ADDR64:$R2)]>;
}
}
// Regular calls.
// z/Linux ELF
let Predicates = [IsTargetELF] in {
let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in {
def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
[(z_call pcrel32:$I2)]>;
def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
[(z_call ADDR64:$R2)]>;
}
// TLS calls. These will be lowered into a call to __tls_get_offset,
// with an extra relocation specifying the TLS symbol.
let isCall = 1, Defs = [R14D, CC] in {
def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
[(z_tls_gdcall tglobaltlsaddr:$I2)]>;
def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
[(z_tls_ldcall tglobaltlsaddr:$I2)]>;
}
}
// Sibling calls. Indirect sibling calls must be via R6 for XPLink,
// R1 used for ELF
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
[(z_sibcall pcrel32:$I2)]>;
def CallBR : Alias<2, (outs), (ins ADDR64:$R2),
[(z_sibcall ADDR64:$R2)]>;
}
// Conditional sibling calls.
let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in {
def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1,
pcrel32:$I2), []>;
def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1,
ADDR64:$R2), []>;
}
// Fused compare and conditional sibling calls.
let isCall = 1, isTerminator = 1, isReturn = 1 in {
def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;
def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;
def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>;
def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>;
def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;
def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;
def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>;
def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>;
}
// A return instruction (br %r14) for ELF and (b 2 %r7) for XPLink.
let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
// A conditional return instruction (bcr <cond>, %r14).
let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in
def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
// Fused compare and conditional returns.
let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in {
def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
}
//===----------------------------------------------------------------------===//
// Select instructions
//===----------------------------------------------------------------------===//
def Select32 : SelectWrapper<i32, GR32>,
Requires<[FeatureNoLoadStoreOnCond]>;
def Select64 : SelectWrapper<i64, GR64>,
Requires<[FeatureNoLoadStoreOnCond]>;
// We don't define 32-bit Mux stores if we don't have STOCFH, because the
// low-only STOC should then always be used if possible.
defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8,
nonvolatile_anyextloadi8, bdxaddr20only>,
Requires<[FeatureHighWord]>;
defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,
nonvolatile_anyextloadi16, bdxaddr20only>,
Requires<[FeatureHighWord]>;
defm CondStore32Mux : CondStores<GRX32, simple_store,
simple_load, bdxaddr20only>,
Requires<[FeatureLoadStoreOnCond2]>;
defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8,
nonvolatile_anyextloadi8, bdxaddr20only>;
defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16,
nonvolatile_anyextloadi16, bdxaddr20only>;
defm CondStore32 : CondStores<GR32, simple_store,
simple_load, bdxaddr20only>;
defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
nonvolatile_anyextloadi8, bdxaddr20only>;
defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
nonvolatile_anyextloadi16, bdxaddr20only>;
defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
nonvolatile_anyextloadi32, bdxaddr20only>;
defm CondStore64 : CondStores<GR64, simple_store,
simple_load, bdxaddr20only>;
//===----------------------------------------------------------------------===//
// Move instructions
//===----------------------------------------------------------------------===//
// Register moves.
def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;
def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>;
def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>;
}
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>;
// Immediate moves.
let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
// 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
// deopending on the choice of register.
def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
Requires<[FeatureHighWord]>;
def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
// Other 16-bit immediates.
def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
// 32-bit immediates.
def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
}
// Register loads.
let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
// Expands to L, LY or LFH, depending on the choice of register.
def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
Requires<[FeatureHighWord]>;
defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
Requires<[FeatureHighWord]>;
def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
// These instructions are split after register allocation, so we don't
// want a custom inserter.
let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
[(set GR128:$dst, (load bdxaddr20only128:$src))]>;
}
}
let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>;
def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
}
let canFoldAsLoad = 1 in {
def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
}
// Load and zero rightmost byte.
let Predicates = [FeatureLoadAndZeroRightmostByte] in {
def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>;
def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>;
def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00),
(LZRF bdxaddr20only:$src)>;
def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00),
(LZRG bdxaddr20only:$src)>;
}
// Load and trap.
let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {
def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>;
def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>;
def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>;
}
// Register stores.
let SimpleBDXStore = 1, mayStore = 1 in {
// Expands to ST, STY or STFH, depending on the choice of register.
def STMux : StoreRXYPseudo<store, GRX32, 4>,
Requires<[FeatureHighWord]>;
defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
Requires<[FeatureHighWord]>;
def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
// These instructions are split after register allocation, so we don't
// want a custom inserter.
let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
[(store GR128:$src, bdxaddr20only128:$dst)]>;
}
}
def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
// 8-bit immediate stores to 8-bit fields.
defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
// 16-bit immediate stores to 16-, 32- or 64-bit fields.
def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
// Memory-to-memory moves.
let mayLoad = 1, mayStore = 1 in
defm MVC : MemorySS<"mvc", 0xD2, z_mvc>;
let mayLoad = 1, mayStore = 1, Defs = [CC] in {
def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>;
def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>;
def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>;
}
// Memset[Length][Byte] pseudos.
def MemsetImmImm : MemsetPseudo<imm64, imm32zx8trunc>;
def MemsetImmReg : MemsetPseudo<imm64, GR32>;
def MemsetRegImm : MemsetPseudo<ADDR64, imm32zx8trunc>;
def MemsetRegReg : MemsetPseudo<ADDR64, GR32>;
// Move right.
let Predicates = [FeatureMiscellaneousExtensions3],
mayLoad = 1, mayStore = 1, Uses = [R0L] in
def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>;
// String moves.
let mayLoad = 1, mayStore = 1, Defs = [CC] in
defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
//===----------------------------------------------------------------------===//
// Conditional move instructions
//===----------------------------------------------------------------------===//
let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in {
// Select.
let isCommutable = 1 in {
// Expands to SELR or SELFHR or a branch-and-move sequence,
// depending on the choice of registers.
def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>;
defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>;
defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>;
defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>;
}
// Define AsmParser extended mnemonics for each general condition-code mask.
foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
"Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0,
GR32, GR32, GR32>;
def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0,
GRH32, GRH32, GRH32>;
def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3,
GR64, GR64, GR64>;
}
}
let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in {
// Load immediate on condition. Matched via DAG pattern and created
// by the PeepholeOptimizer via FoldImmediate.
// Expands to LOCHI or LOCHHI, depending on the choice of register.
def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>;
defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>;
defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>;
defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>;
// Move register on condition. Matched via DAG pattern and
// created by early if-conversion.
let isCommutable = 1 in {
// Expands to LOCR or LOCFHR or a branch-and-move sequence,
// depending on the choice of registers.
def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>;
defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>;
}
// Load on condition. Matched via DAG pattern.
// Expands to LOC or LOCFH, depending on the choice of register.
defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>;
defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>;
// Store on condition. Expanded from CondStore* pseudos.
// Expands to STOC or STOCFH, depending on the choice of register.
def STOCMux : CondStoreRSYPseudo<GRX32, 4>;
defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>;
// Define AsmParser extended mnemonics for each general condition-code mask.
foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
"Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32,
imm32sx16>;
def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64,
imm64sx16>;
def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32,
imm32sx16>;
def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>;
def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>;
def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>;
}
}
let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in {
// Move register on condition. Matched via DAG pattern and
// created by early if-conversion.
let isCommutable = 1 in {
defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>;
defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>;
}
// Load on condition. Matched via DAG pattern.
defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>;
defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>;
// Store on condition. Expanded from CondStore* pseudos.
defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>;
defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>;
// Define AsmParser extended mnemonics for each general condition-code mask.
foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
"Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>;
def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>;
def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>;
def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>;
def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>;
def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>;
}
}
//===----------------------------------------------------------------------===//
// Sign extensions
//===----------------------------------------------------------------------===//
//
// Note that putting these before zero extensions mean that we will prefer
// them for anyextload*. There's not really much to choose between the two
// either way, but signed-extending loads have a short LH and a long LHY,
// while zero-extending loads have only the long LLH.
//
//===----------------------------------------------------------------------===//
// 32-bit extensions from registers.
def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>;
def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;
// 64-bit extensions from registers.
def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>;
def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;
def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;
let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>;
// Match 32-to-64-bit sign extensions in which the source is already
// in a 64-bit register.
def : Pat<(sext_inreg GR64:$src, i32),
(LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH,
// depending on the choice of register.
def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
Requires<[FeatureHighWord]>;
def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
Requires<[FeatureHighWord]>;
// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH,
// depending on the choice of register.
def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
Requires<[FeatureHighWord]>;
defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
Requires<[FeatureHighWord]>;
def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
// 64-bit extensions from memory.
def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>;
def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
//===----------------------------------------------------------------------===//
// Zero extensions
//===----------------------------------------------------------------------===//
// 32-bit extensions from registers.
// Expands to LLCR or RISB[LH]G, depending on the choice of registers.
def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>,
Requires<[FeatureHighWord]>;
def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>;
// Expands to LLHR or RISB[LH]G, depending on the choice of registers.
def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>,
Requires<[FeatureHighWord]>;
def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
// 64-bit extensions from registers.
def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>;
def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;
def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;
// Match 32-to-64-bit zero extensions in which the source is already
// in a 64-bit register.
def : Pat<(and GR64:$src, 0xffffffff),
(LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH,
// depending on the choice of register.
def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
Requires<[FeatureHighWord]>;
def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>,
Requires<[FeatureHighWord]>;
// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH,
// depending on the choice of register.
def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
Requires<[FeatureHighWord]>;
def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>,
Requires<[FeatureHighWord]>;
def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
// 64-bit extensions from memory.
def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>;
def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
// 31-to-64-bit zero extensions.
def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>;
def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>;
def : Pat<(and GR64:$src, 0x7fffffff),
(LLGTR GR64:$src)>;
def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff),
(LLGT bdxaddr20only:$src)>;
// Load and zero rightmost byte.
let Predicates = [FeatureLoadAndZeroRightmostByte] in {
def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>;
def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00),
(LLZRGF bdxaddr20only:$src)>;
}
// Load and trap.
let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {
def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>;
def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>;
}
// Extend GR64s to GR128s.
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
//===----------------------------------------------------------------------===//
// "Any" extensions
//===----------------------------------------------------------------------===//
// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
def : Pat<(i64 (anyext GR32:$src)),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
// Extend GR64s to GR128s.
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
//===----------------------------------------------------------------------===//
// Truncations
//===----------------------------------------------------------------------===//
// Truncations of 64-bit registers to 32-bit registers.
def : Pat<(i32 (trunc GR64:$src)),
(EXTRACT_SUBREG GR64:$src, subreg_l32)>;
// Truncations of 32-bit registers to 8-bit memory. STCMux expands to
// STC, STCY or STCH, depending on the choice of register.
def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
Requires<[FeatureHighWord]>;
defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
Requires<[FeatureHighWord]>;
// Truncations of 32-bit registers to 16-bit memory. STHMux expands to
// STH, STHY or STHH, depending on the choice of register.
def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
Requires<[FeatureHighWord]>;
defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
Requires<[FeatureHighWord]>;
def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
// Truncations of 64-bit registers to memory.
defm : StoreGR64Pair<STC, STCY, truncstorei8>;
defm : StoreGR64Pair<STH, STHY, truncstorei16>;
def : StoreGR64PC<STHRL, aligned_truncstorei16>;
defm : StoreGR64Pair<ST, STY, truncstorei32>;
def : StoreGR64PC<STRL, aligned_truncstorei32>;
// Store characters under mask -- not (yet) used for codegen.
defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>;
def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>;
//===----------------------------------------------------------------------===//
// Multi-register moves
//===----------------------------------------------------------------------===//
// Multi-register loads.
defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>;
def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>;
def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>;
// Multi-register stores.
defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>;
def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>;
//===----------------------------------------------------------------------===//
// Byte swaps
//===----------------------------------------------------------------------===//
// Byte-swapping register moves.
def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>;
def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;
// Byte-swapping loads.
def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>;
def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>;
def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>;
// Byte-swapping stores.
def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>;
def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>;
def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>;
// Byte-swapping memory-to-memory moves.
let mayLoad = 1, mayStore = 1 in
def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>;
//===----------------------------------------------------------------------===//
// Load address instructions
//===----------------------------------------------------------------------===//
// Load BDX-style addresses.
let isAsCheapAsAMove = 1, isReMaterializable = 1 in
defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>;
// Load a PC-relative address. There's no version of this instruction
// with a 16-bit offset, so there's no relaxation.
let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in
def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>;
// Load the Global Offset Table address. This will be lowered into a
// larl $R1, _GLOBAL_OFFSET_TABLE_
// instruction.
def GOT : Alias<6, (outs GR64:$R1), (ins),
[(set GR64:$R1, (global_offset_table))]>;
//===----------------------------------------------------------------------===//
// Absolute and Negation
//===----------------------------------------------------------------------===//
let Defs = [CC] in {
let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>;
def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>;
}
let CCValues = 0xE, CompareZeroCCMask = 0xE in
def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>;
}
defm : SXU<abs, LPGFR>;
let Defs = [CC] in {
let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>;
def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>;
}
let CCValues = 0xE, CompareZeroCCMask = 0xE in
def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>;
}
defm : SXU<z_inegabs, LNGFR>;
let Defs = [CC] in {
let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>;
def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>;
}
let CCValues = 0xE, CompareZeroCCMask = 0xE in
def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;
}
defm : SXU<ineg, LCGFR>;
//===----------------------------------------------------------------------===//
// Insertion
//===----------------------------------------------------------------------===//
let isCodeGenOnly = 1 in
defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>;
defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>;
defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
// Insert characters under mask -- not (yet) used for codegen.
let Defs = [CC] in {
defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>;
def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>;
}
// Insertions of a 16-bit immediate, leaving other bits unaffected.
// We don't have or_as_insert equivalents of these operations because
// OI is available instead.
//
// IIxMux expands to II[LH]x, depending on the choice of register.
def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
Requires<[FeatureHighWord]>;
def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
Requires<[FeatureHighWord]>;
def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;
def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;
def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>;
def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>;
// ...likewise for 32-bit immediates. For GR32s this is a general
// full-width move. (We use IILF rather than something like LLILF
// for 32-bit moves because IILF leaves the upper 32 bits of the
// GR64 unchanged.)
let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,
Requires<[FeatureHighWord]>;
def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
}
def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
// An alternative model of inserthf, with the first operand being
// a zero-extended value.
def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
(IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
imm64hf32:$imm)>;
//===----------------------------------------------------------------------===//
// Addition
//===----------------------------------------------------------------------===//
// Addition producing a signed overflow flag.
let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in {
// Addition of a register.
let isCommutable = 1 in {
defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>;
defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>;
}
def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;
// Addition to a high register.
def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>,
Requires<[FeatureHighWord]>;
def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>,
Requires<[FeatureHighWord]>;
// Addition of signed 16-bit immediates.
defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>;
defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>;
defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>;
// Addition of signed 32-bit immediates.
def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>,
Requires<[FeatureHighWord]>;
def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>;
def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>,
Requires<[FeatureHighWord]>;
def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>;
// Addition of memory.
defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>;
defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>;
def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>,
Requires<[FeatureMiscellaneousExtensions2]>;
def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>;
defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>;
// Addition to memory.
def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
}
defm : SXB<z_sadd, GR64, AGFR>;
// Addition producing a carry.
let Defs = [CC], CCValues = 0xF, IsLogical = 1 in {
// Addition of a register.
let isCommutable = 1 in {
defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>;
defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>;