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Copy pathNVPTXReplaceImageHandles.cpp
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NVPTXReplaceImageHandles.cpp
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//===-- NVPTXReplaceImageHandles.cpp - Replace image handles for Fermi ----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// On Fermi, image handles are not supported. To work around this, we traverse
// the machine code and replace image handles with concrete symbols. For this
// to work reliably, inlining of all function call must be performed.
//
//===----------------------------------------------------------------------===//
#include "NVPTX.h"
#include "NVPTXMachineFunctionInfo.h"
#include "NVPTXSubtarget.h"
#include "NVPTXTargetMachine.h"
#include "MCTargetDesc/NVPTXBaseInfo.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
class NVPTXReplaceImageHandles : public MachineFunctionPass {
private:
static char ID;
DenseSet<MachineInstr *> InstrsToRemove;
public:
NVPTXReplaceImageHandles();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
return "NVPTX Replace Image Handles";
}
private:
bool processInstr(MachineInstr &MI);
bool replaceImageHandle(MachineOperand &Op, MachineFunction &MF);
bool findIndexForHandle(MachineOperand &Op, MachineFunction &MF,
unsigned &Idx);
};
}
char NVPTXReplaceImageHandles::ID = 0;
NVPTXReplaceImageHandles::NVPTXReplaceImageHandles()
: MachineFunctionPass(ID) {}
bool NVPTXReplaceImageHandles::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
InstrsToRemove.clear();
for (MachineBasicBlock &MBB : MF)
for (MachineInstr &MI : MBB)
Changed |= processInstr(MI);
// Now clean up any handle-access instructions
// This is needed in debug mode when code cleanup passes are not executed,
// but we need the handle access to be eliminated because they are not
// valid instructions when image handles are disabled.
for (MachineInstr *MI : InstrsToRemove)
MI->eraseFromParent();
return Changed;
}
static unsigned suldRegisterToIndexOpcode(unsigned RegOC) {
switch (RegOC) {
case NVPTX::SULD_1D_I8_CLAMP_R:
return NVPTX::SULD_1D_I8_CLAMP_I;
case NVPTX::SULD_1D_I16_CLAMP_R:
return NVPTX::SULD_1D_I16_CLAMP_I;
case NVPTX::SULD_1D_I32_CLAMP_R:
return NVPTX::SULD_1D_I32_CLAMP_I;
case NVPTX::SULD_1D_I64_CLAMP_R:
return NVPTX::SULD_1D_I64_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_I8_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_I8_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_I16_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_I16_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_I32_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_I32_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_I64_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_I64_CLAMP_I;
case NVPTX::SULD_2D_I8_CLAMP_R:
return NVPTX::SULD_2D_I8_CLAMP_I;
case NVPTX::SULD_2D_I16_CLAMP_R:
return NVPTX::SULD_2D_I16_CLAMP_I;
case NVPTX::SULD_2D_I32_CLAMP_R:
return NVPTX::SULD_2D_I32_CLAMP_I;
case NVPTX::SULD_2D_I64_CLAMP_R:
return NVPTX::SULD_2D_I64_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_I8_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_I8_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_I16_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_I16_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_I32_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_I32_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_I64_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_I64_CLAMP_I;
case NVPTX::SULD_3D_I8_CLAMP_R:
return NVPTX::SULD_3D_I8_CLAMP_I;
case NVPTX::SULD_3D_I16_CLAMP_R:
return NVPTX::SULD_3D_I16_CLAMP_I;
case NVPTX::SULD_3D_I32_CLAMP_R:
return NVPTX::SULD_3D_I32_CLAMP_I;
case NVPTX::SULD_3D_I64_CLAMP_R:
return NVPTX::SULD_3D_I64_CLAMP_I;
case NVPTX::SULD_1D_V2I8_CLAMP_R:
return NVPTX::SULD_1D_V2I8_CLAMP_I;
case NVPTX::SULD_1D_V2I16_CLAMP_R:
return NVPTX::SULD_1D_V2I16_CLAMP_I;
case NVPTX::SULD_1D_V2I32_CLAMP_R:
return NVPTX::SULD_1D_V2I32_CLAMP_I;
case NVPTX::SULD_1D_V2I64_CLAMP_R:
return NVPTX::SULD_1D_V2I64_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_V2I8_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_V2I8_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_V2I16_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_V2I16_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_V2I32_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_V2I32_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_V2I64_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_V2I64_CLAMP_I;
case NVPTX::SULD_2D_V2I8_CLAMP_R:
return NVPTX::SULD_2D_V2I8_CLAMP_I;
case NVPTX::SULD_2D_V2I16_CLAMP_R:
return NVPTX::SULD_2D_V2I16_CLAMP_I;
case NVPTX::SULD_2D_V2I32_CLAMP_R:
return NVPTX::SULD_2D_V2I32_CLAMP_I;
case NVPTX::SULD_2D_V2I64_CLAMP_R:
return NVPTX::SULD_2D_V2I64_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_V2I8_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_V2I8_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_V2I16_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_V2I16_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_V2I32_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_V2I32_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_V2I64_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_V2I64_CLAMP_I;
case NVPTX::SULD_3D_V2I8_CLAMP_R:
return NVPTX::SULD_3D_V2I8_CLAMP_I;
case NVPTX::SULD_3D_V2I16_CLAMP_R:
return NVPTX::SULD_3D_V2I16_CLAMP_I;
case NVPTX::SULD_3D_V2I32_CLAMP_R:
return NVPTX::SULD_3D_V2I32_CLAMP_I;
case NVPTX::SULD_3D_V2I64_CLAMP_R:
return NVPTX::SULD_3D_V2I64_CLAMP_I;
case NVPTX::SULD_1D_V4I8_CLAMP_R:
return NVPTX::SULD_1D_V4I8_CLAMP_I;
case NVPTX::SULD_1D_V4I16_CLAMP_R:
return NVPTX::SULD_1D_V4I16_CLAMP_I;
case NVPTX::SULD_1D_V4I32_CLAMP_R:
return NVPTX::SULD_1D_V4I32_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_V4I8_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_V4I8_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_V4I16_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_V4I16_CLAMP_I;
case NVPTX::SULD_1D_ARRAY_V4I32_CLAMP_R:
return NVPTX::SULD_1D_ARRAY_V4I32_CLAMP_I;
case NVPTX::SULD_2D_V4I8_CLAMP_R:
return NVPTX::SULD_2D_V4I8_CLAMP_I;
case NVPTX::SULD_2D_V4I16_CLAMP_R:
return NVPTX::SULD_2D_V4I16_CLAMP_I;
case NVPTX::SULD_2D_V4I32_CLAMP_R:
return NVPTX::SULD_2D_V4I32_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_V4I8_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_V4I8_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_V4I16_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_V4I16_CLAMP_I;
case NVPTX::SULD_2D_ARRAY_V4I32_CLAMP_R:
return NVPTX::SULD_2D_ARRAY_V4I32_CLAMP_I;
case NVPTX::SULD_3D_V4I8_CLAMP_R:
return NVPTX::SULD_3D_V4I8_CLAMP_I;
case NVPTX::SULD_3D_V4I16_CLAMP_R:
return NVPTX::SULD_3D_V4I16_CLAMP_I;
case NVPTX::SULD_3D_V4I32_CLAMP_R:
return NVPTX::SULD_3D_V4I32_CLAMP_I;
case NVPTX::SULD_1D_I8_TRAP_R:
return NVPTX::SULD_1D_I8_TRAP_I;
case NVPTX::SULD_1D_I16_TRAP_R:
return NVPTX::SULD_1D_I16_TRAP_I;
case NVPTX::SULD_1D_I32_TRAP_R:
return NVPTX::SULD_1D_I32_TRAP_I;
case NVPTX::SULD_1D_I64_TRAP_R:
return NVPTX::SULD_1D_I64_TRAP_I;
case NVPTX::SULD_1D_ARRAY_I8_TRAP_R:
return NVPTX::SULD_1D_ARRAY_I8_TRAP_I;
case NVPTX::SULD_1D_ARRAY_I16_TRAP_R:
return NVPTX::SULD_1D_ARRAY_I16_TRAP_I;
case NVPTX::SULD_1D_ARRAY_I32_TRAP_R:
return NVPTX::SULD_1D_ARRAY_I32_TRAP_I;
case NVPTX::SULD_1D_ARRAY_I64_TRAP_R:
return NVPTX::SULD_1D_ARRAY_I64_TRAP_I;
case NVPTX::SULD_2D_I8_TRAP_R:
return NVPTX::SULD_2D_I8_TRAP_I;
case NVPTX::SULD_2D_I16_TRAP_R:
return NVPTX::SULD_2D_I16_TRAP_I;
case NVPTX::SULD_2D_I32_TRAP_R:
return NVPTX::SULD_2D_I32_TRAP_I;
case NVPTX::SULD_2D_I64_TRAP_R:
return NVPTX::SULD_2D_I64_TRAP_I;
case NVPTX::SULD_2D_ARRAY_I8_TRAP_R:
return NVPTX::SULD_2D_ARRAY_I8_TRAP_I;
case NVPTX::SULD_2D_ARRAY_I16_TRAP_R:
return NVPTX::SULD_2D_ARRAY_I16_TRAP_I;
case NVPTX::SULD_2D_ARRAY_I32_TRAP_R:
return NVPTX::SULD_2D_ARRAY_I32_TRAP_I;
case NVPTX::SULD_2D_ARRAY_I64_TRAP_R:
return NVPTX::SULD_2D_ARRAY_I64_TRAP_I;
case NVPTX::SULD_3D_I8_TRAP_R:
return NVPTX::SULD_3D_I8_TRAP_I;
case NVPTX::SULD_3D_I16_TRAP_R:
return NVPTX::SULD_3D_I16_TRAP_I;
case NVPTX::SULD_3D_I32_TRAP_R:
return NVPTX::SULD_3D_I32_TRAP_I;
case NVPTX::SULD_3D_I64_TRAP_R:
return NVPTX::SULD_3D_I64_TRAP_I;
case NVPTX::SULD_1D_V2I8_TRAP_R:
return NVPTX::SULD_1D_V2I8_TRAP_I;
case NVPTX::SULD_1D_V2I16_TRAP_R:
return NVPTX::SULD_1D_V2I16_TRAP_I;
case NVPTX::SULD_1D_V2I32_TRAP_R:
return NVPTX::SULD_1D_V2I32_TRAP_I;
case NVPTX::SULD_1D_V2I64_TRAP_R:
return NVPTX::SULD_1D_V2I64_TRAP_I;
case NVPTX::SULD_1D_ARRAY_V2I8_TRAP_R:
return NVPTX::SULD_1D_ARRAY_V2I8_TRAP_I;
case NVPTX::SULD_1D_ARRAY_V2I16_TRAP_R:
return NVPTX::SULD_1D_ARRAY_V2I16_TRAP_I;
case NVPTX::SULD_1D_ARRAY_V2I32_TRAP_R:
return NVPTX::SULD_1D_ARRAY_V2I32_TRAP_I;
case NVPTX::SULD_1D_ARRAY_V2I64_TRAP_R:
return NVPTX::SULD_1D_ARRAY_V2I64_TRAP_I;
case NVPTX::SULD_2D_V2I8_TRAP_R:
return NVPTX::SULD_2D_V2I8_TRAP_I;
case NVPTX::SULD_2D_V2I16_TRAP_R:
return NVPTX::SULD_2D_V2I16_TRAP_I;
case NVPTX::SULD_2D_V2I32_TRAP_R:
return NVPTX::SULD_2D_V2I32_TRAP_I;
case NVPTX::SULD_2D_V2I64_TRAP_R:
return NVPTX::SULD_2D_V2I64_TRAP_I;
case NVPTX::SULD_2D_ARRAY_V2I8_TRAP_R:
return NVPTX::SULD_2D_ARRAY_V2I8_TRAP_I;
case NVPTX::SULD_2D_ARRAY_V2I16_TRAP_R:
return NVPTX::SULD_2D_ARRAY_V2I16_TRAP_I;
case NVPTX::SULD_2D_ARRAY_V2I32_TRAP_R:
return NVPTX::SULD_2D_ARRAY_V2I32_TRAP_I;
case NVPTX::SULD_2D_ARRAY_V2I64_TRAP_R:
return NVPTX::SULD_2D_ARRAY_V2I64_TRAP_I;
case NVPTX::SULD_3D_V2I8_TRAP_R:
return NVPTX::SULD_3D_V2I8_TRAP_I;
case NVPTX::SULD_3D_V2I16_TRAP_R:
return NVPTX::SULD_3D_V2I16_TRAP_I;
case NVPTX::SULD_3D_V2I32_TRAP_R:
return NVPTX::SULD_3D_V2I32_TRAP_I;
case NVPTX::SULD_3D_V2I64_TRAP_R:
return NVPTX::SULD_3D_V2I64_TRAP_I;
case NVPTX::SULD_1D_V4I8_TRAP_R:
return NVPTX::SULD_1D_V4I8_TRAP_I;
case NVPTX::SULD_1D_V4I16_TRAP_R:
return NVPTX::SULD_1D_V4I16_TRAP_I;
case NVPTX::SULD_1D_V4I32_TRAP_R:
return NVPTX::SULD_1D_V4I32_TRAP_I;
case NVPTX::SULD_1D_ARRAY_V4I8_TRAP_R:
return NVPTX::SULD_1D_ARRAY_V4I8_TRAP_I;
case NVPTX::SULD_1D_ARRAY_V4I16_TRAP_R:
return NVPTX::SULD_1D_ARRAY_V4I16_TRAP_I;
case NVPTX::SULD_1D_ARRAY_V4I32_TRAP_R:
return NVPTX::SULD_1D_ARRAY_V4I32_TRAP_I;
case NVPTX::SULD_2D_V4I8_TRAP_R:
return NVPTX::SULD_2D_V4I8_TRAP_I;
case NVPTX::SULD_2D_V4I16_TRAP_R:
return NVPTX::SULD_2D_V4I16_TRAP_I;
case NVPTX::SULD_2D_V4I32_TRAP_R:
return NVPTX::SULD_2D_V4I32_TRAP_I;
case NVPTX::SULD_2D_ARRAY_V4I8_TRAP_R:
return NVPTX::SULD_2D_ARRAY_V4I8_TRAP_I;
case NVPTX::SULD_2D_ARRAY_V4I16_TRAP_R:
return NVPTX::SULD_2D_ARRAY_V4I16_TRAP_I;
case NVPTX::SULD_2D_ARRAY_V4I32_TRAP_R:
return NVPTX::SULD_2D_ARRAY_V4I32_TRAP_I;
case NVPTX::SULD_3D_V4I8_TRAP_R:
return NVPTX::SULD_3D_V4I8_TRAP_I;
case NVPTX::SULD_3D_V4I16_TRAP_R:
return NVPTX::SULD_3D_V4I16_TRAP_I;
case NVPTX::SULD_3D_V4I32_TRAP_R:
return NVPTX::SULD_3D_V4I32_TRAP_I;
case NVPTX::SULD_1D_I8_ZERO_R:
return NVPTX::SULD_1D_I8_ZERO_I;
case NVPTX::SULD_1D_I16_ZERO_R:
return NVPTX::SULD_1D_I16_ZERO_I;
case NVPTX::SULD_1D_I32_ZERO_R:
return NVPTX::SULD_1D_I32_ZERO_I;
case NVPTX::SULD_1D_I64_ZERO_R:
return NVPTX::SULD_1D_I64_ZERO_I;
case NVPTX::SULD_1D_ARRAY_I8_ZERO_R:
return NVPTX::SULD_1D_ARRAY_I8_ZERO_I;
case NVPTX::SULD_1D_ARRAY_I16_ZERO_R:
return NVPTX::SULD_1D_ARRAY_I16_ZERO_I;
case NVPTX::SULD_1D_ARRAY_I32_ZERO_R:
return NVPTX::SULD_1D_ARRAY_I32_ZERO_I;
case NVPTX::SULD_1D_ARRAY_I64_ZERO_R:
return NVPTX::SULD_1D_ARRAY_I64_ZERO_I;
case NVPTX::SULD_2D_I8_ZERO_R:
return NVPTX::SULD_2D_I8_ZERO_I;
case NVPTX::SULD_2D_I16_ZERO_R:
return NVPTX::SULD_2D_I16_ZERO_I;
case NVPTX::SULD_2D_I32_ZERO_R:
return NVPTX::SULD_2D_I32_ZERO_I;
case NVPTX::SULD_2D_I64_ZERO_R:
return NVPTX::SULD_2D_I64_ZERO_I;
case NVPTX::SULD_2D_ARRAY_I8_ZERO_R:
return NVPTX::SULD_2D_ARRAY_I8_ZERO_I;
case NVPTX::SULD_2D_ARRAY_I16_ZERO_R:
return NVPTX::SULD_2D_ARRAY_I16_ZERO_I;
case NVPTX::SULD_2D_ARRAY_I32_ZERO_R:
return NVPTX::SULD_2D_ARRAY_I32_ZERO_I;
case NVPTX::SULD_2D_ARRAY_I64_ZERO_R:
return NVPTX::SULD_2D_ARRAY_I64_ZERO_I;
case NVPTX::SULD_3D_I8_ZERO_R:
return NVPTX::SULD_3D_I8_ZERO_I;
case NVPTX::SULD_3D_I16_ZERO_R:
return NVPTX::SULD_3D_I16_ZERO_I;
case NVPTX::SULD_3D_I32_ZERO_R:
return NVPTX::SULD_3D_I32_ZERO_I;
case NVPTX::SULD_3D_I64_ZERO_R:
return NVPTX::SULD_3D_I64_ZERO_I;
case NVPTX::SULD_1D_V2I8_ZERO_R:
return NVPTX::SULD_1D_V2I8_ZERO_I;
case NVPTX::SULD_1D_V2I16_ZERO_R:
return NVPTX::SULD_1D_V2I16_ZERO_I;
case NVPTX::SULD_1D_V2I32_ZERO_R:
return NVPTX::SULD_1D_V2I32_ZERO_I;
case NVPTX::SULD_1D_V2I64_ZERO_R:
return NVPTX::SULD_1D_V2I64_ZERO_I;
case NVPTX::SULD_1D_ARRAY_V2I8_ZERO_R:
return NVPTX::SULD_1D_ARRAY_V2I8_ZERO_I;
case NVPTX::SULD_1D_ARRAY_V2I16_ZERO_R:
return NVPTX::SULD_1D_ARRAY_V2I16_ZERO_I;
case NVPTX::SULD_1D_ARRAY_V2I32_ZERO_R:
return NVPTX::SULD_1D_ARRAY_V2I32_ZERO_I;
case NVPTX::SULD_1D_ARRAY_V2I64_ZERO_R:
return NVPTX::SULD_1D_ARRAY_V2I64_ZERO_I;
case NVPTX::SULD_2D_V2I8_ZERO_R:
return NVPTX::SULD_2D_V2I8_ZERO_I;
case NVPTX::SULD_2D_V2I16_ZERO_R:
return NVPTX::SULD_2D_V2I16_ZERO_I;
case NVPTX::SULD_2D_V2I32_ZERO_R:
return NVPTX::SULD_2D_V2I32_ZERO_I;
case NVPTX::SULD_2D_V2I64_ZERO_R:
return NVPTX::SULD_2D_V2I64_ZERO_I;
case NVPTX::SULD_2D_ARRAY_V2I8_ZERO_R:
return NVPTX::SULD_2D_ARRAY_V2I8_ZERO_I;
case NVPTX::SULD_2D_ARRAY_V2I16_ZERO_R:
return NVPTX::SULD_2D_ARRAY_V2I16_ZERO_I;
case NVPTX::SULD_2D_ARRAY_V2I32_ZERO_R:
return NVPTX::SULD_2D_ARRAY_V2I32_ZERO_I;
case NVPTX::SULD_2D_ARRAY_V2I64_ZERO_R:
return NVPTX::SULD_2D_ARRAY_V2I64_ZERO_I;
case NVPTX::SULD_3D_V2I8_ZERO_R:
return NVPTX::SULD_3D_V2I8_ZERO_I;
case NVPTX::SULD_3D_V2I16_ZERO_R:
return NVPTX::SULD_3D_V2I16_ZERO_I;
case NVPTX::SULD_3D_V2I32_ZERO_R:
return NVPTX::SULD_3D_V2I32_ZERO_I;
case NVPTX::SULD_3D_V2I64_ZERO_R:
return NVPTX::SULD_3D_V2I64_ZERO_I;
case NVPTX::SULD_1D_V4I8_ZERO_R:
return NVPTX::SULD_1D_V4I8_ZERO_I;
case NVPTX::SULD_1D_V4I16_ZERO_R:
return NVPTX::SULD_1D_V4I16_ZERO_I;
case NVPTX::SULD_1D_V4I32_ZERO_R:
return NVPTX::SULD_1D_V4I32_ZERO_I;
case NVPTX::SULD_1D_ARRAY_V4I8_ZERO_R:
return NVPTX::SULD_1D_ARRAY_V4I8_ZERO_I;
case NVPTX::SULD_1D_ARRAY_V4I16_ZERO_R:
return NVPTX::SULD_1D_ARRAY_V4I16_ZERO_I;
case NVPTX::SULD_1D_ARRAY_V4I32_ZERO_R:
return NVPTX::SULD_1D_ARRAY_V4I32_ZERO_I;
case NVPTX::SULD_2D_V4I8_ZERO_R:
return NVPTX::SULD_2D_V4I8_ZERO_I;
case NVPTX::SULD_2D_V4I16_ZERO_R:
return NVPTX::SULD_2D_V4I16_ZERO_I;
case NVPTX::SULD_2D_V4I32_ZERO_R:
return NVPTX::SULD_2D_V4I32_ZERO_I;
case NVPTX::SULD_2D_ARRAY_V4I8_ZERO_R:
return NVPTX::SULD_2D_ARRAY_V4I8_ZERO_I;
case NVPTX::SULD_2D_ARRAY_V4I16_ZERO_R:
return NVPTX::SULD_2D_ARRAY_V4I16_ZERO_I;
case NVPTX::SULD_2D_ARRAY_V4I32_ZERO_R:
return NVPTX::SULD_2D_ARRAY_V4I32_ZERO_I;
case NVPTX::SULD_3D_V4I8_ZERO_R:
return NVPTX::SULD_3D_V4I8_ZERO_I;
case NVPTX::SULD_3D_V4I16_ZERO_R:
return NVPTX::SULD_3D_V4I16_ZERO_I;
case NVPTX::SULD_3D_V4I32_ZERO_R:
return NVPTX::SULD_3D_V4I32_ZERO_I;
default:
llvm_unreachable("Unhandled SULD opcode");
}
}
static unsigned sustRegisterToIndexOpcode(unsigned RegOC) {
switch (RegOC) {
case NVPTX::SUST_B_1D_B8_CLAMP_R:
return NVPTX::SUST_B_1D_B8_CLAMP_I;
case NVPTX::SUST_B_1D_B16_CLAMP_R:
return NVPTX::SUST_B_1D_B16_CLAMP_I;
case NVPTX::SUST_B_1D_B32_CLAMP_R:
return NVPTX::SUST_B_1D_B32_CLAMP_I;
case NVPTX::SUST_B_1D_B64_CLAMP_R:
return NVPTX::SUST_B_1D_B64_CLAMP_I;
case NVPTX::SUST_B_1D_V2B8_CLAMP_R:
return NVPTX::SUST_B_1D_V2B8_CLAMP_I;
case NVPTX::SUST_B_1D_V2B16_CLAMP_R:
return NVPTX::SUST_B_1D_V2B16_CLAMP_I;
case NVPTX::SUST_B_1D_V2B32_CLAMP_R:
return NVPTX::SUST_B_1D_V2B32_CLAMP_I;
case NVPTX::SUST_B_1D_V2B64_CLAMP_R:
return NVPTX::SUST_B_1D_V2B64_CLAMP_I;
case NVPTX::SUST_B_1D_V4B8_CLAMP_R:
return NVPTX::SUST_B_1D_V4B8_CLAMP_I;
case NVPTX::SUST_B_1D_V4B16_CLAMP_R:
return NVPTX::SUST_B_1D_V4B16_CLAMP_I;
case NVPTX::SUST_B_1D_V4B32_CLAMP_R:
return NVPTX::SUST_B_1D_V4B32_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_B8_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_B8_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_B16_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_B16_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_B32_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_B32_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_B64_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_B64_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_V2B8_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_V2B8_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_V2B16_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_V2B16_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_V2B32_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_V2B32_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_V2B64_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_V2B64_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_V4B8_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_V4B8_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_V4B16_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_V4B16_CLAMP_I;
case NVPTX::SUST_B_1D_ARRAY_V4B32_CLAMP_R:
return NVPTX::SUST_B_1D_ARRAY_V4B32_CLAMP_I;
case NVPTX::SUST_B_2D_B8_CLAMP_R:
return NVPTX::SUST_B_2D_B8_CLAMP_I;
case NVPTX::SUST_B_2D_B16_CLAMP_R:
return NVPTX::SUST_B_2D_B16_CLAMP_I;
case NVPTX::SUST_B_2D_B32_CLAMP_R:
return NVPTX::SUST_B_2D_B32_CLAMP_I;
case NVPTX::SUST_B_2D_B64_CLAMP_R:
return NVPTX::SUST_B_2D_B64_CLAMP_I;
case NVPTX::SUST_B_2D_V2B8_CLAMP_R:
return NVPTX::SUST_B_2D_V2B8_CLAMP_I;
case NVPTX::SUST_B_2D_V2B16_CLAMP_R:
return NVPTX::SUST_B_2D_V2B16_CLAMP_I;
case NVPTX::SUST_B_2D_V2B32_CLAMP_R:
return NVPTX::SUST_B_2D_V2B32_CLAMP_I;
case NVPTX::SUST_B_2D_V2B64_CLAMP_R:
return NVPTX::SUST_B_2D_V2B64_CLAMP_I;
case NVPTX::SUST_B_2D_V4B8_CLAMP_R:
return NVPTX::SUST_B_2D_V4B8_CLAMP_I;
case NVPTX::SUST_B_2D_V4B16_CLAMP_R:
return NVPTX::SUST_B_2D_V4B16_CLAMP_I;
case NVPTX::SUST_B_2D_V4B32_CLAMP_R:
return NVPTX::SUST_B_2D_V4B32_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_B8_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_B8_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_B16_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_B16_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_B32_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_B32_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_B64_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_B64_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_V2B8_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_V2B8_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_V2B16_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_V2B16_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_V2B32_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_V2B32_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_V2B64_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_V2B64_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_V4B8_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_V4B8_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_V4B16_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_V4B16_CLAMP_I;
case NVPTX::SUST_B_2D_ARRAY_V4B32_CLAMP_R:
return NVPTX::SUST_B_2D_ARRAY_V4B32_CLAMP_I;
case NVPTX::SUST_B_3D_B8_CLAMP_R:
return NVPTX::SUST_B_3D_B8_CLAMP_I;
case NVPTX::SUST_B_3D_B16_CLAMP_R:
return NVPTX::SUST_B_3D_B16_CLAMP_I;
case NVPTX::SUST_B_3D_B32_CLAMP_R:
return NVPTX::SUST_B_3D_B32_CLAMP_I;
case NVPTX::SUST_B_3D_B64_CLAMP_R:
return NVPTX::SUST_B_3D_B64_CLAMP_I;
case NVPTX::SUST_B_3D_V2B8_CLAMP_R:
return NVPTX::SUST_B_3D_V2B8_CLAMP_I;
case NVPTX::SUST_B_3D_V2B16_CLAMP_R:
return NVPTX::SUST_B_3D_V2B16_CLAMP_I;
case NVPTX::SUST_B_3D_V2B32_CLAMP_R:
return NVPTX::SUST_B_3D_V2B32_CLAMP_I;
case NVPTX::SUST_B_3D_V2B64_CLAMP_R:
return NVPTX::SUST_B_3D_V2B64_CLAMP_I;
case NVPTX::SUST_B_3D_V4B8_CLAMP_R:
return NVPTX::SUST_B_3D_V4B8_CLAMP_I;
case NVPTX::SUST_B_3D_V4B16_CLAMP_R:
return NVPTX::SUST_B_3D_V4B16_CLAMP_I;
case NVPTX::SUST_B_3D_V4B32_CLAMP_R:
return NVPTX::SUST_B_3D_V4B32_CLAMP_I;
case NVPTX::SUST_B_1D_B8_TRAP_R:
return NVPTX::SUST_B_1D_B8_TRAP_I;
case NVPTX::SUST_B_1D_B16_TRAP_R:
return NVPTX::SUST_B_1D_B16_TRAP_I;
case NVPTX::SUST_B_1D_B32_TRAP_R:
return NVPTX::SUST_B_1D_B32_TRAP_I;
case NVPTX::SUST_B_1D_B64_TRAP_R:
return NVPTX::SUST_B_1D_B64_TRAP_I;
case NVPTX::SUST_B_1D_V2B8_TRAP_R:
return NVPTX::SUST_B_1D_V2B8_TRAP_I;
case NVPTX::SUST_B_1D_V2B16_TRAP_R:
return NVPTX::SUST_B_1D_V2B16_TRAP_I;
case NVPTX::SUST_B_1D_V2B32_TRAP_R:
return NVPTX::SUST_B_1D_V2B32_TRAP_I;
case NVPTX::SUST_B_1D_V2B64_TRAP_R:
return NVPTX::SUST_B_1D_V2B64_TRAP_I;
case NVPTX::SUST_B_1D_V4B8_TRAP_R:
return NVPTX::SUST_B_1D_V4B8_TRAP_I;
case NVPTX::SUST_B_1D_V4B16_TRAP_R:
return NVPTX::SUST_B_1D_V4B16_TRAP_I;
case NVPTX::SUST_B_1D_V4B32_TRAP_R:
return NVPTX::SUST_B_1D_V4B32_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_B8_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_B8_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_B16_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_B16_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_B32_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_B32_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_B64_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_B64_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_V2B8_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_V2B8_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_V2B16_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_V2B16_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_V2B32_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_V2B32_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_V2B64_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_V2B64_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_V4B8_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_V4B8_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_V4B16_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_V4B16_TRAP_I;
case NVPTX::SUST_B_1D_ARRAY_V4B32_TRAP_R:
return NVPTX::SUST_B_1D_ARRAY_V4B32_TRAP_I;
case NVPTX::SUST_B_2D_B8_TRAP_R:
return NVPTX::SUST_B_2D_B8_TRAP_I;
case NVPTX::SUST_B_2D_B16_TRAP_R:
return NVPTX::SUST_B_2D_B16_TRAP_I;
case NVPTX::SUST_B_2D_B32_TRAP_R:
return NVPTX::SUST_B_2D_B32_TRAP_I;
case NVPTX::SUST_B_2D_B64_TRAP_R:
return NVPTX::SUST_B_2D_B64_TRAP_I;
case NVPTX::SUST_B_2D_V2B8_TRAP_R:
return NVPTX::SUST_B_2D_V2B8_TRAP_I;
case NVPTX::SUST_B_2D_V2B16_TRAP_R:
return NVPTX::SUST_B_2D_V2B16_TRAP_I;
case NVPTX::SUST_B_2D_V2B32_TRAP_R:
return NVPTX::SUST_B_2D_V2B32_TRAP_I;
case NVPTX::SUST_B_2D_V2B64_TRAP_R:
return NVPTX::SUST_B_2D_V2B64_TRAP_I;
case NVPTX::SUST_B_2D_V4B8_TRAP_R:
return NVPTX::SUST_B_2D_V4B8_TRAP_I;
case NVPTX::SUST_B_2D_V4B16_TRAP_R:
return NVPTX::SUST_B_2D_V4B16_TRAP_I;
case NVPTX::SUST_B_2D_V4B32_TRAP_R:
return NVPTX::SUST_B_2D_V4B32_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_B8_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_B8_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_B16_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_B16_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_B32_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_B32_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_B64_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_B64_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_V2B8_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_V2B8_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_V2B16_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_V2B16_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_V2B32_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_V2B32_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_V2B64_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_V2B64_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_V4B8_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_V4B8_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_V4B16_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_V4B16_TRAP_I;
case NVPTX::SUST_B_2D_ARRAY_V4B32_TRAP_R:
return NVPTX::SUST_B_2D_ARRAY_V4B32_TRAP_I;
case NVPTX::SUST_B_3D_B8_TRAP_R:
return NVPTX::SUST_B_3D_B8_TRAP_I;
case NVPTX::SUST_B_3D_B16_TRAP_R:
return NVPTX::SUST_B_3D_B16_TRAP_I;
case NVPTX::SUST_B_3D_B32_TRAP_R:
return NVPTX::SUST_B_3D_B32_TRAP_I;
case NVPTX::SUST_B_3D_B64_TRAP_R:
return NVPTX::SUST_B_3D_B64_TRAP_I;
case NVPTX::SUST_B_3D_V2B8_TRAP_R:
return NVPTX::SUST_B_3D_V2B8_TRAP_I;
case NVPTX::SUST_B_3D_V2B16_TRAP_R:
return NVPTX::SUST_B_3D_V2B16_TRAP_I;
case NVPTX::SUST_B_3D_V2B32_TRAP_R:
return NVPTX::SUST_B_3D_V2B32_TRAP_I;
case NVPTX::SUST_B_3D_V2B64_TRAP_R:
return NVPTX::SUST_B_3D_V2B64_TRAP_I;
case NVPTX::SUST_B_3D_V4B8_TRAP_R:
return NVPTX::SUST_B_3D_V4B8_TRAP_I;
case NVPTX::SUST_B_3D_V4B16_TRAP_R:
return NVPTX::SUST_B_3D_V4B16_TRAP_I;
case NVPTX::SUST_B_3D_V4B32_TRAP_R:
return NVPTX::SUST_B_3D_V4B32_TRAP_I;
case NVPTX::SUST_B_1D_B8_ZERO_R:
return NVPTX::SUST_B_1D_B8_ZERO_I;
case NVPTX::SUST_B_1D_B16_ZERO_R:
return NVPTX::SUST_B_1D_B16_ZERO_I;
case NVPTX::SUST_B_1D_B32_ZERO_R:
return NVPTX::SUST_B_1D_B32_ZERO_I;
case NVPTX::SUST_B_1D_B64_ZERO_R:
return NVPTX::SUST_B_1D_B64_ZERO_I;
case NVPTX::SUST_B_1D_V2B8_ZERO_R:
return NVPTX::SUST_B_1D_V2B8_ZERO_I;
case NVPTX::SUST_B_1D_V2B16_ZERO_R:
return NVPTX::SUST_B_1D_V2B16_ZERO_I;
case NVPTX::SUST_B_1D_V2B32_ZERO_R:
return NVPTX::SUST_B_1D_V2B32_ZERO_I;
case NVPTX::SUST_B_1D_V2B64_ZERO_R:
return NVPTX::SUST_B_1D_V2B64_ZERO_I;
case NVPTX::SUST_B_1D_V4B8_ZERO_R:
return NVPTX::SUST_B_1D_V4B8_ZERO_I;
case NVPTX::SUST_B_1D_V4B16_ZERO_R:
return NVPTX::SUST_B_1D_V4B16_ZERO_I;
case NVPTX::SUST_B_1D_V4B32_ZERO_R:
return NVPTX::SUST_B_1D_V4B32_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_B8_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_B8_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_B16_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_B16_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_B32_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_B32_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_B64_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_B64_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_V2B8_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_V2B8_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_V2B16_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_V2B16_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_V2B32_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_V2B32_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_V2B64_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_V2B64_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_V4B8_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_V4B8_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_V4B16_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_V4B16_ZERO_I;
case NVPTX::SUST_B_1D_ARRAY_V4B32_ZERO_R:
return NVPTX::SUST_B_1D_ARRAY_V4B32_ZERO_I;
case NVPTX::SUST_B_2D_B8_ZERO_R:
return NVPTX::SUST_B_2D_B8_ZERO_I;
case NVPTX::SUST_B_2D_B16_ZERO_R:
return NVPTX::SUST_B_2D_B16_ZERO_I;
case NVPTX::SUST_B_2D_B32_ZERO_R:
return NVPTX::SUST_B_2D_B32_ZERO_I;
case NVPTX::SUST_B_2D_B64_ZERO_R:
return NVPTX::SUST_B_2D_B64_ZERO_I;
case NVPTX::SUST_B_2D_V2B8_ZERO_R:
return NVPTX::SUST_B_2D_V2B8_ZERO_I;
case NVPTX::SUST_B_2D_V2B16_ZERO_R:
return NVPTX::SUST_B_2D_V2B16_ZERO_I;
case NVPTX::SUST_B_2D_V2B32_ZERO_R:
return NVPTX::SUST_B_2D_V2B32_ZERO_I;
case NVPTX::SUST_B_2D_V2B64_ZERO_R:
return NVPTX::SUST_B_2D_V2B64_ZERO_I;
case NVPTX::SUST_B_2D_V4B8_ZERO_R:
return NVPTX::SUST_B_2D_V4B8_ZERO_I;
case NVPTX::SUST_B_2D_V4B16_ZERO_R:
return NVPTX::SUST_B_2D_V4B16_ZERO_I;
case NVPTX::SUST_B_2D_V4B32_ZERO_R:
return NVPTX::SUST_B_2D_V4B32_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_B8_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_B8_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_B16_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_B16_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_B32_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_B32_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_B64_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_B64_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_V2B8_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_V2B8_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_V2B16_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_V2B16_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_V2B32_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_V2B32_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_V2B64_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_V2B64_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_V4B8_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_V4B8_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_V4B16_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_V4B16_ZERO_I;
case NVPTX::SUST_B_2D_ARRAY_V4B32_ZERO_R:
return NVPTX::SUST_B_2D_ARRAY_V4B32_ZERO_I;
case NVPTX::SUST_B_3D_B8_ZERO_R:
return NVPTX::SUST_B_3D_B8_ZERO_I;
case NVPTX::SUST_B_3D_B16_ZERO_R:
return NVPTX::SUST_B_3D_B16_ZERO_I;
case NVPTX::SUST_B_3D_B32_ZERO_R:
return NVPTX::SUST_B_3D_B32_ZERO_I;
case NVPTX::SUST_B_3D_B64_ZERO_R:
return NVPTX::SUST_B_3D_B64_ZERO_I;
case NVPTX::SUST_B_3D_V2B8_ZERO_R:
return NVPTX::SUST_B_3D_V2B8_ZERO_I;
case NVPTX::SUST_B_3D_V2B16_ZERO_R:
return NVPTX::SUST_B_3D_V2B16_ZERO_I;
case NVPTX::SUST_B_3D_V2B32_ZERO_R:
return NVPTX::SUST_B_3D_V2B32_ZERO_I;
case NVPTX::SUST_B_3D_V2B64_ZERO_R:
return NVPTX::SUST_B_3D_V2B64_ZERO_I;
case NVPTX::SUST_B_3D_V4B8_ZERO_R:
return NVPTX::SUST_B_3D_V4B8_ZERO_I;
case NVPTX::SUST_B_3D_V4B16_ZERO_R:
return NVPTX::SUST_B_3D_V4B16_ZERO_I;
case NVPTX::SUST_B_3D_V4B32_ZERO_R:
return NVPTX::SUST_B_3D_V4B32_ZERO_I;
case NVPTX::SUST_P_1D_B8_TRAP_R:
return NVPTX::SUST_P_1D_B8_TRAP_I;
case NVPTX::SUST_P_1D_B16_TRAP_R:
return NVPTX::SUST_P_1D_B16_TRAP_I;
case NVPTX::SUST_P_1D_B32_TRAP_R:
return NVPTX::SUST_P_1D_B32_TRAP_I;
case NVPTX::SUST_P_1D_V2B8_TRAP_R:
return NVPTX::SUST_P_1D_V2B8_TRAP_I;
case NVPTX::SUST_P_1D_V2B16_TRAP_R:
return NVPTX::SUST_P_1D_V2B16_TRAP_I;
case NVPTX::SUST_P_1D_V2B32_TRAP_R:
return NVPTX::SUST_P_1D_V2B32_TRAP_I;
case NVPTX::SUST_P_1D_V4B8_TRAP_R:
return NVPTX::SUST_P_1D_V4B8_TRAP_I;
case NVPTX::SUST_P_1D_V4B16_TRAP_R:
return NVPTX::SUST_P_1D_V4B16_TRAP_I;
case NVPTX::SUST_P_1D_V4B32_TRAP_R:
return NVPTX::SUST_P_1D_V4B32_TRAP_I;
case NVPTX::SUST_P_1D_ARRAY_B8_TRAP_R:
return NVPTX::SUST_P_1D_ARRAY_B8_TRAP_I;
case NVPTX::SUST_P_1D_ARRAY_B16_TRAP_R:
return NVPTX::SUST_P_1D_ARRAY_B16_TRAP_I;
case NVPTX::SUST_P_1D_ARRAY_B32_TRAP_R:
return NVPTX::SUST_P_1D_ARRAY_B32_TRAP_I;
case NVPTX::SUST_P_1D_ARRAY_V2B8_TRAP_R:
return NVPTX::SUST_P_1D_ARRAY_V2B8_TRAP_I;
case NVPTX::SUST_P_1D_ARRAY_V2B16_TRAP_R:
return NVPTX::SUST_P_1D_ARRAY_V2B16_TRAP_I;
case NVPTX::SUST_P_1D_ARRAY_V2B32_TRAP_R:
return NVPTX::SUST_P_1D_ARRAY_V2B32_TRAP_I;
case NVPTX::SUST_P_1D_ARRAY_V4B8_TRAP_R:
return NVPTX::SUST_P_1D_ARRAY_V4B8_TRAP_I;
case NVPTX::SUST_P_1D_ARRAY_V4B16_TRAP_R:
return NVPTX::SUST_P_1D_ARRAY_V4B16_TRAP_I;
case NVPTX::SUST_P_1D_ARRAY_V4B32_TRAP_R:
return NVPTX::SUST_P_1D_ARRAY_V4B32_TRAP_I;
case NVPTX::SUST_P_2D_B8_TRAP_R:
return NVPTX::SUST_P_2D_B8_TRAP_I;
case NVPTX::SUST_P_2D_B16_TRAP_R:
return NVPTX::SUST_P_2D_B16_TRAP_I;
case NVPTX::SUST_P_2D_B32_TRAP_R:
return NVPTX::SUST_P_2D_B32_TRAP_I;
case NVPTX::SUST_P_2D_V2B8_TRAP_R:
return NVPTX::SUST_P_2D_V2B8_TRAP_I;
case NVPTX::SUST_P_2D_V2B16_TRAP_R:
return NVPTX::SUST_P_2D_V2B16_TRAP_I;
case NVPTX::SUST_P_2D_V2B32_TRAP_R:
return NVPTX::SUST_P_2D_V2B32_TRAP_I;
case NVPTX::SUST_P_2D_V4B8_TRAP_R:
return NVPTX::SUST_P_2D_V4B8_TRAP_I;
case NVPTX::SUST_P_2D_V4B16_TRAP_R:
return NVPTX::SUST_P_2D_V4B16_TRAP_I;
case NVPTX::SUST_P_2D_V4B32_TRAP_R:
return NVPTX::SUST_P_2D_V4B32_TRAP_I;
case NVPTX::SUST_P_2D_ARRAY_B8_TRAP_R:
return NVPTX::SUST_P_2D_ARRAY_B8_TRAP_I;
case NVPTX::SUST_P_2D_ARRAY_B16_TRAP_R:
return NVPTX::SUST_P_2D_ARRAY_B16_TRAP_I;
case NVPTX::SUST_P_2D_ARRAY_B32_TRAP_R:
return NVPTX::SUST_P_2D_ARRAY_B32_TRAP_I;
case NVPTX::SUST_P_2D_ARRAY_V2B8_TRAP_R:
return NVPTX::SUST_P_2D_ARRAY_V2B8_TRAP_I;
case NVPTX::SUST_P_2D_ARRAY_V2B16_TRAP_R:
return NVPTX::SUST_P_2D_ARRAY_V2B16_TRAP_I;
case NVPTX::SUST_P_2D_ARRAY_V2B32_TRAP_R:
return NVPTX::SUST_P_2D_ARRAY_V2B32_TRAP_I;
case NVPTX::SUST_P_2D_ARRAY_V4B8_TRAP_R:
return NVPTX::SUST_P_2D_ARRAY_V4B8_TRAP_I;
case NVPTX::SUST_P_2D_ARRAY_V4B16_TRAP_R:
return NVPTX::SUST_P_2D_ARRAY_V4B16_TRAP_I;
case NVPTX::SUST_P_2D_ARRAY_V4B32_TRAP_R:
return NVPTX::SUST_P_2D_ARRAY_V4B32_TRAP_I;
case NVPTX::SUST_P_3D_B8_TRAP_R:
return NVPTX::SUST_P_3D_B8_TRAP_I;
case NVPTX::SUST_P_3D_B16_TRAP_R:
return NVPTX::SUST_P_3D_B16_TRAP_I;
case NVPTX::SUST_P_3D_B32_TRAP_R:
return NVPTX::SUST_P_3D_B32_TRAP_I;
case NVPTX::SUST_P_3D_V2B8_TRAP_R:
return NVPTX::SUST_P_3D_V2B8_TRAP_I;
case NVPTX::SUST_P_3D_V2B16_TRAP_R:
return NVPTX::SUST_P_3D_V2B16_TRAP_I;
case NVPTX::SUST_P_3D_V2B32_TRAP_R:
return NVPTX::SUST_P_3D_V2B32_TRAP_I;
case NVPTX::SUST_P_3D_V4B8_TRAP_R:
return NVPTX::SUST_P_3D_V4B8_TRAP_I;
case NVPTX::SUST_P_3D_V4B16_TRAP_R:
return NVPTX::SUST_P_3D_V4B16_TRAP_I;
case NVPTX::SUST_P_3D_V4B32_TRAP_R:
return NVPTX::SUST_P_3D_V4B32_TRAP_I;
default:
llvm_unreachable("Unhandled SUST opcode");
}
}
static unsigned texRegisterToIndexOpcode(unsigned RegOC) {
switch (RegOC) {
case NVPTX::TEX_1D_F32_S32_RR:
return NVPTX::TEX_1D_F32_S32_IR;
case NVPTX::TEX_1D_F32_S32_RI:
return NVPTX::TEX_1D_F32_S32_II;
case NVPTX::TEX_1D_F32_F32_RR:
return NVPTX::TEX_1D_F32_F32_IR;
case NVPTX::TEX_1D_F32_F32_RI:
return NVPTX::TEX_1D_F32_F32_II;
case NVPTX::TEX_1D_F32_F32_LEVEL_RR:
return NVPTX::TEX_1D_F32_F32_LEVEL_IR;
case NVPTX::TEX_1D_F32_F32_LEVEL_RI:
return NVPTX::TEX_1D_F32_F32_LEVEL_II;
case NVPTX::TEX_1D_F32_F32_GRAD_RR:
return NVPTX::TEX_1D_F32_F32_GRAD_IR;
case NVPTX::TEX_1D_F32_F32_GRAD_RI:
return NVPTX::TEX_1D_F32_F32_GRAD_II;
case NVPTX::TEX_1D_S32_S32_RR:
return NVPTX::TEX_1D_S32_S32_IR;
case NVPTX::TEX_1D_S32_S32_RI:
return NVPTX::TEX_1D_S32_S32_II;
case NVPTX::TEX_1D_S32_F32_RR:
return NVPTX::TEX_1D_S32_F32_IR;
case NVPTX::TEX_1D_S32_F32_RI:
return NVPTX::TEX_1D_S32_F32_II;
case NVPTX::TEX_1D_S32_F32_LEVEL_RR:
return NVPTX::TEX_1D_S32_F32_LEVEL_IR;
case NVPTX::TEX_1D_S32_F32_LEVEL_RI:
return NVPTX::TEX_1D_S32_F32_LEVEL_II;
case NVPTX::TEX_1D_S32_F32_GRAD_RR:
return NVPTX::TEX_1D_S32_F32_GRAD_IR;
case NVPTX::TEX_1D_S32_F32_GRAD_RI:
return NVPTX::TEX_1D_S32_F32_GRAD_II;
case NVPTX::TEX_1D_U32_S32_RR:
return NVPTX::TEX_1D_U32_S32_IR;
case NVPTX::TEX_1D_U32_S32_RI:
return NVPTX::TEX_1D_U32_S32_II;
case NVPTX::TEX_1D_U32_F32_RR:
return NVPTX::TEX_1D_U32_F32_IR;
case NVPTX::TEX_1D_U32_F32_RI:
return NVPTX::TEX_1D_U32_F32_II;
case NVPTX::TEX_1D_U32_F32_LEVEL_RR:
return NVPTX::TEX_1D_U32_F32_LEVEL_IR;
case NVPTX::TEX_1D_U32_F32_LEVEL_RI:
return NVPTX::TEX_1D_U32_F32_LEVEL_II;
case NVPTX::TEX_1D_U32_F32_GRAD_RR:
return NVPTX::TEX_1D_U32_F32_GRAD_IR;
case NVPTX::TEX_1D_U32_F32_GRAD_RI:
return NVPTX::TEX_1D_U32_F32_GRAD_II;
case NVPTX::TEX_1D_ARRAY_F32_S32_RR:
return NVPTX::TEX_1D_ARRAY_F32_S32_IR;
case NVPTX::TEX_1D_ARRAY_F32_S32_RI:
return NVPTX::TEX_1D_ARRAY_F32_S32_II;
case NVPTX::TEX_1D_ARRAY_F32_F32_RR:
return NVPTX::TEX_1D_ARRAY_F32_F32_IR;
case NVPTX::TEX_1D_ARRAY_F32_F32_RI:
return NVPTX::TEX_1D_ARRAY_F32_F32_II;
case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RR:
return NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_IR;
case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RI:
return NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_II;
case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RR:
return NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_IR;
case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RI:
return NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_II;
case NVPTX::TEX_1D_ARRAY_S32_S32_RR:
return NVPTX::TEX_1D_ARRAY_S32_S32_IR;
case NVPTX::TEX_1D_ARRAY_S32_S32_RI:
return NVPTX::TEX_1D_ARRAY_S32_S32_II;
case NVPTX::TEX_1D_ARRAY_S32_F32_RR:
return NVPTX::TEX_1D_ARRAY_S32_F32_IR;
case NVPTX::TEX_1D_ARRAY_S32_F32_RI:
return NVPTX::TEX_1D_ARRAY_S32_F32_II;
case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RR:
return NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_IR;
case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RI:
return NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_II;
case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RR:
return NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_IR;
case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RI:
return NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_II;
case NVPTX::TEX_1D_ARRAY_U32_S32_RR:
return NVPTX::TEX_1D_ARRAY_U32_S32_IR;
case NVPTX::TEX_1D_ARRAY_U32_S32_RI:
return NVPTX::TEX_1D_ARRAY_U32_S32_II;
case NVPTX::TEX_1D_ARRAY_U32_F32_RR:
return NVPTX::TEX_1D_ARRAY_U32_F32_IR;
case NVPTX::TEX_1D_ARRAY_U32_F32_RI:
return NVPTX::TEX_1D_ARRAY_U32_F32_II;
case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RR:
return NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_IR;
case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RI:
return NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_II;
case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RR:
return NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_IR;
case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RI:
return NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_II;
case NVPTX::TEX_2D_F32_S32_RR:
return NVPTX::TEX_2D_F32_S32_IR;
case NVPTX::TEX_2D_F32_S32_RI:
return NVPTX::TEX_2D_F32_S32_II;
case NVPTX::TEX_2D_F32_F32_RR:
return NVPTX::TEX_2D_F32_F32_IR;
case NVPTX::TEX_2D_F32_F32_RI:
return NVPTX::TEX_2D_F32_F32_II;
case NVPTX::TEX_2D_F32_F32_LEVEL_RR:
return NVPTX::TEX_2D_F32_F32_LEVEL_IR;
case NVPTX::TEX_2D_F32_F32_LEVEL_RI:
return NVPTX::TEX_2D_F32_F32_LEVEL_II;
case NVPTX::TEX_2D_F32_F32_GRAD_RR:
return NVPTX::TEX_2D_F32_F32_GRAD_IR;
case NVPTX::TEX_2D_F32_F32_GRAD_RI:
return NVPTX::TEX_2D_F32_F32_GRAD_II;
case NVPTX::TEX_2D_S32_S32_RR:
return NVPTX::TEX_2D_S32_S32_IR;
case NVPTX::TEX_2D_S32_S32_RI:
return NVPTX::TEX_2D_S32_S32_II;
case NVPTX::TEX_2D_S32_F32_RR:
return NVPTX::TEX_2D_S32_F32_IR;
case NVPTX::TEX_2D_S32_F32_RI:
return NVPTX::TEX_2D_S32_F32_II;
case NVPTX::TEX_2D_S32_F32_LEVEL_RR:
return NVPTX::TEX_2D_S32_F32_LEVEL_IR;
case NVPTX::TEX_2D_S32_F32_LEVEL_RI:
return NVPTX::TEX_2D_S32_F32_LEVEL_II;
case NVPTX::TEX_2D_S32_F32_GRAD_RR:
return NVPTX::TEX_2D_S32_F32_GRAD_IR;
case NVPTX::TEX_2D_S32_F32_GRAD_RI:
return NVPTX::TEX_2D_S32_F32_GRAD_II;
case NVPTX::TEX_2D_U32_S32_RR:
return NVPTX::TEX_2D_U32_S32_IR;
case NVPTX::TEX_2D_U32_S32_RI:
return NVPTX::TEX_2D_U32_S32_II;
case NVPTX::TEX_2D_U32_F32_RR:
return NVPTX::TEX_2D_U32_F32_IR;
case NVPTX::TEX_2D_U32_F32_RI:
return NVPTX::TEX_2D_U32_F32_II;
case NVPTX::TEX_2D_U32_F32_LEVEL_RR:
return NVPTX::TEX_2D_U32_F32_LEVEL_IR;
case NVPTX::TEX_2D_U32_F32_LEVEL_RI:
return NVPTX::TEX_2D_U32_F32_LEVEL_II;
case NVPTX::TEX_2D_U32_F32_GRAD_RR:
return NVPTX::TEX_2D_U32_F32_GRAD_IR;
case NVPTX::TEX_2D_U32_F32_GRAD_RI:
return NVPTX::TEX_2D_U32_F32_GRAD_II;
case NVPTX::TEX_2D_ARRAY_F32_S32_RR:
return NVPTX::TEX_2D_ARRAY_F32_S32_IR;
case NVPTX::TEX_2D_ARRAY_F32_S32_RI:
return NVPTX::TEX_2D_ARRAY_F32_S32_II;
case NVPTX::TEX_2D_ARRAY_F32_F32_RR:
return NVPTX::TEX_2D_ARRAY_F32_F32_IR;
case NVPTX::TEX_2D_ARRAY_F32_F32_RI:
return NVPTX::TEX_2D_ARRAY_F32_F32_II;
case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RR:
return NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_IR;
case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RI:
return NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_II;
case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RR:
return NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_IR;
case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RI:
return NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_II;
case NVPTX::TEX_2D_ARRAY_S32_S32_RR:
return NVPTX::TEX_2D_ARRAY_S32_S32_IR;
case NVPTX::TEX_2D_ARRAY_S32_S32_RI: