forked from llvm/llvm-project
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathHexagonMCCodeEmitter.cpp
798 lines (747 loc) · 36 KB
/
HexagonMCCodeEmitter.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
//===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/HexagonMCCodeEmitter.h"
#include "MCTargetDesc/HexagonBaseInfo.h"
#include "MCTargetDesc/HexagonFixupKinds.h"
#include "MCTargetDesc/HexagonMCExpr.h"
#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "MCTargetDesc/HexagonMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Endian.h"
#include "llvm/Support/EndianStream.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
#include <map>
#include <string>
#include <vector>
#define DEBUG_TYPE "mccodeemitter"
using namespace llvm;
using namespace Hexagon;
STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
static const unsigned fixup_Invalid = ~0u;
#define _ fixup_Invalid
#define P(x) Hexagon::fixup_Hexagon##x
static const std::map<unsigned, std::vector<unsigned>> ExtFixups = {
{ MCSymbolRefExpr::VK_DTPREL,
{ _, _, _, _,
_, _, P(_DTPREL_16_X), P(_DTPREL_11_X),
P(_DTPREL_11_X), P(_9_X), _, P(_DTPREL_11_X),
P(_DTPREL_16_X), _, _, _,
P(_DTPREL_16_X), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_DTPREL_32_6_X) }},
{ MCSymbolRefExpr::VK_GOT,
{ _, _, _, _,
_, _, P(_GOT_11_X), _ /* [1] */,
_ /* [1] */, P(_9_X), _, P(_GOT_11_X),
P(_GOT_16_X), _, _, _,
P(_GOT_16_X), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_GOT_32_6_X) }},
{ MCSymbolRefExpr::VK_GOTREL,
{ _, _, _, _,
_, _, P(_GOTREL_11_X), P(_GOTREL_11_X),
P(_GOTREL_11_X), P(_9_X), _, P(_GOTREL_11_X),
P(_GOTREL_16_X), _, _, _,
P(_GOTREL_16_X), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_GOTREL_32_6_X) }},
{ MCSymbolRefExpr::VK_TPREL,
{ _, _, _, _,
_, _, P(_TPREL_16_X), P(_TPREL_11_X),
P(_TPREL_11_X), P(_9_X), _, P(_TPREL_11_X),
P(_TPREL_16_X), _, _, _,
P(_TPREL_16_X), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_TPREL_32_6_X) }},
{ MCSymbolRefExpr::VK_Hexagon_GD_GOT,
{ _, _, _, _,
_, _, P(_GD_GOT_16_X), P(_GD_GOT_11_X),
P(_GD_GOT_11_X), P(_9_X), _, P(_GD_GOT_11_X),
P(_GD_GOT_16_X), _, _, _,
P(_GD_GOT_16_X), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_GD_GOT_32_6_X) }},
{ MCSymbolRefExpr::VK_Hexagon_GD_PLT,
{ _, _, _, _,
_, _, _, _,
_, P(_9_X), _, P(_GD_PLT_B22_PCREL_X),
_, _, _, _,
_, _, _, _,
_, _, P(_GD_PLT_B22_PCREL_X), _,
_, _, _, _,
_, _, _, _,
_ }},
{ MCSymbolRefExpr::VK_Hexagon_IE,
{ _, _, _, _,
_, _, P(_IE_16_X), _,
_, P(_9_X), _, _,
P(_IE_16_X), _, _, _,
P(_IE_16_X), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_IE_32_6_X) }},
{ MCSymbolRefExpr::VK_Hexagon_IE_GOT,
{ _, _, _, _,
_, _, P(_IE_GOT_11_X), P(_IE_GOT_11_X),
P(_IE_GOT_11_X), P(_9_X), _, P(_IE_GOT_11_X),
P(_IE_GOT_16_X), _, _, _,
P(_IE_GOT_16_X), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_IE_GOT_32_6_X) }},
{ MCSymbolRefExpr::VK_Hexagon_LD_GOT,
{ _, _, _, _,
_, _, P(_LD_GOT_11_X), P(_LD_GOT_11_X),
P(_LD_GOT_11_X), P(_9_X), _, P(_LD_GOT_11_X),
P(_LD_GOT_16_X), _, _, _,
P(_LD_GOT_16_X), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_LD_GOT_32_6_X) }},
{ MCSymbolRefExpr::VK_Hexagon_LD_PLT,
{ _, _, _, _,
_, _, _, _,
_, P(_9_X), _, P(_LD_PLT_B22_PCREL_X),
_, _, _, _,
_, _, _, _,
_, _, P(_LD_PLT_B22_PCREL_X), _,
_, _, _, _,
_, _, _, _,
_ }},
{ MCSymbolRefExpr::VK_PCREL,
{ _, _, _, _,
_, _, P(_6_PCREL_X), _,
_, P(_9_X), _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_32_PCREL) }},
{ MCSymbolRefExpr::VK_None,
{ _, _, _, _,
_, _, P(_6_X), P(_8_X),
P(_8_X), P(_9_X), P(_10_X), P(_11_X),
P(_12_X), P(_B13_PCREL), _, P(_B15_PCREL_X),
P(_16_X), _, _, _,
_, _, P(_B22_PCREL_X), _,
_, _, _, _,
_, _, _, _,
P(_32_6_X) }},
};
// [1] The fixup is GOT_16_X for signed values and GOT_11_X for unsigned.
static const std::map<unsigned, std::vector<unsigned>> StdFixups = {
{ MCSymbolRefExpr::VK_DTPREL,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_DTPREL_16), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_DTPREL_32) }},
{ MCSymbolRefExpr::VK_GOT,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_GOT_32) }},
{ MCSymbolRefExpr::VK_GOTREL,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_ /* [2] */, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_GOTREL_32) }},
{ MCSymbolRefExpr::VK_PLT,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, P(_PLT_B22_PCREL), _,
_, _, _, _,
_, _, _, _,
_ }},
{ MCSymbolRefExpr::VK_TPREL,
{ _, _, _, _,
_, _, _, _,
_, _, _, P(_TPREL_11_X),
_, _, _, _,
P(_TPREL_16), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_TPREL_32) }},
{ MCSymbolRefExpr::VK_Hexagon_GD_GOT,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_GD_GOT_16), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_GD_GOT_32) }},
{ MCSymbolRefExpr::VK_Hexagon_GD_PLT,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, P(_GD_PLT_B22_PCREL), _,
_, _, _, _,
_, _, _, _,
_ }},
{ MCSymbolRefExpr::VK_Hexagon_GPREL,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_GPREL16_0), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_ }},
{ MCSymbolRefExpr::VK_Hexagon_HI16,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_HI16), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_ }},
{ MCSymbolRefExpr::VK_Hexagon_IE,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_IE_32) }},
{ MCSymbolRefExpr::VK_Hexagon_IE_GOT,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_IE_GOT_16), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_IE_GOT_32) }},
{ MCSymbolRefExpr::VK_Hexagon_LD_GOT,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_LD_GOT_16), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_LD_GOT_32) }},
{ MCSymbolRefExpr::VK_Hexagon_LD_PLT,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, P(_LD_PLT_B22_PCREL), _,
_, _, _, _,
_, _, _, _,
_ }},
{ MCSymbolRefExpr::VK_Hexagon_LO16,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_LO16), _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_ }},
{ MCSymbolRefExpr::VK_PCREL,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
_, _, _, _,
P(_32_PCREL) }},
{ MCSymbolRefExpr::VK_None,
{ _, _, _, _,
_, _, _, _,
_, _, _, _,
_, P(_B13_PCREL), _, P(_B15_PCREL),
_, _, _, _,
_, _, P(_B22_PCREL), _,
_, _, _, _,
_, _, _, _,
P(_32) }},
};
//
// [2] The actual fixup is LO16 or HI16, depending on the instruction.
#undef P
#undef _
uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
MCInst const &MCI) const {
bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
if (State.Index == 0) {
if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
assert(!Duplex);
assert(State.Index != Last);
return HexagonII::INST_PARSE_LOOP_END;
}
}
if (State.Index == 1) {
if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
assert(!Duplex);
assert(State.Index != Last);
return HexagonII::INST_PARSE_LOOP_END;
}
}
if (Duplex) {
assert(State.Index == Last);
return HexagonII::INST_PARSE_DUPLEX;
}
if (State.Index == Last)
return HexagonII::INST_PARSE_PACKET_END;
return HexagonII::INST_PARSE_NOT_END;
}
/// Emit the bundle.
void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
MCInst &HMB = const_cast<MCInst &>(MI);
assert(HexagonMCInstrInfo::isBundle(HMB));
LLVM_DEBUG(dbgs() << "Encoding bundle\n";);
State.Addend = 0;
State.Extended = false;
State.Bundle = &MI;
State.Index = 0;
size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
FeatureBitset Features = computeAvailableFeatures(STI.getFeatureBits());
for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
MCInst &HMI = const_cast<MCInst &>(*I.getInst());
verifyInstructionPredicates(HMI, Features);
EncodeSingleInstruction(HMI, OS, Fixups, STI, parseBits(Last, HMB, HMI));
State.Extended = HexagonMCInstrInfo::isImmext(HMI);
State.Addend += HEXAGON_INSTR_SIZE;
++State.Index;
}
}
static bool RegisterMatches(unsigned Consumer, unsigned Producer,
unsigned Producer2) {
return (Consumer == Producer) || (Consumer == Producer2) ||
HexagonMCInstrInfo::IsSingleConsumerRefPairProducer(Producer,
Consumer);
}
/// EncodeSingleInstruction - Emit a single
void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI,
raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI, uint32_t Parse) const {
assert(!HexagonMCInstrInfo::isBundle(MI));
uint64_t Binary;
// Pseudo instructions don't get encoded and shouldn't be here
// in the first place!
assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() &&
"pseudo-instruction found");
LLVM_DEBUG(dbgs() << "Encoding insn `"
<< HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
Binary = getBinaryCodeForInstr(MI, Fixups, STI);
unsigned Opc = MI.getOpcode();
// Check for unimplemented instructions. Immediate extenders
// are encoded as zero, so they need to be accounted for.
if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) {
LLVM_DEBUG(dbgs() << "Unimplemented inst `"
<< HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
llvm_unreachable("Unimplemented Instruction");
}
Binary |= Parse;
// if we need to emit a duplexed instruction
if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) {
assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
"Emitting duplex without duplex parse bits");
unsigned DupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
// 29 is the bit position.
// 0b1110 =0xE bits are masked off and down shifted by 1 bit.
// Last bit is moved to bit position 13
Binary = ((DupIClass & 0xE) << (29 - 1)) | ((DupIClass & 0x1) << 13);
const MCInst *Sub0 = MI.getOperand(0).getInst();
const MCInst *Sub1 = MI.getOperand(1).getInst();
// Get subinstruction slot 0.
unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI);
// Get subinstruction slot 1.
State.SubInst1 = true;
unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI);
State.SubInst1 = false;
Binary |= SubBits0 | (SubBits1 << 16);
}
support::endian::write<uint32_t>(OS, Binary, support::little);
++MCNumEmitted;
}
[[noreturn]] static void raise_relocation_error(unsigned Width, unsigned Kind) {
std::string Text;
raw_string_ostream Stream(Text);
Stream << "Unrecognized relocation combination: width=" << Width
<< " kind=" << Kind;
report_fatal_error(Twine(Stream.str()));
}
/// Some insns are not extended and thus have no bits. These cases require
/// a more brute force method for determining the correct relocation.
Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
const MCSymbolRefExpr::VariantKind VarKind) const {
const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI);
using namespace Hexagon;
if (InsnType == HexagonII::TypeEXTENDER) {
if (VarKind == MCSymbolRefExpr::VK_None) {
auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
for (auto I = Instrs.begin(), N = Instrs.end(); I != N; ++I) {
if (I->getInst() != &MI)
continue;
assert(I+1 != N && "Extender cannot be last in packet");
const MCInst &NextI = *(I+1)->getInst();
const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI);
if (NextD.isBranch() || NextD.isCall() ||
HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR)
return fixup_Hexagon_B32_PCREL_X;
return fixup_Hexagon_32_6_X;
}
}
static const std::map<unsigned,unsigned> Relocs = {
{ MCSymbolRefExpr::VK_GOTREL, fixup_Hexagon_GOTREL_32_6_X },
{ MCSymbolRefExpr::VK_GOT, fixup_Hexagon_GOT_32_6_X },
{ MCSymbolRefExpr::VK_TPREL, fixup_Hexagon_TPREL_32_6_X },
{ MCSymbolRefExpr::VK_DTPREL, fixup_Hexagon_DTPREL_32_6_X },
{ MCSymbolRefExpr::VK_Hexagon_GD_GOT, fixup_Hexagon_GD_GOT_32_6_X },
{ MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_32_6_X },
{ MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_32_6_X },
{ MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_32_6_X },
{ MCSymbolRefExpr::VK_PCREL, fixup_Hexagon_B32_PCREL_X },
{ MCSymbolRefExpr::VK_Hexagon_GD_PLT, fixup_Hexagon_GD_PLT_B32_PCREL_X },
{ MCSymbolRefExpr::VK_Hexagon_LD_PLT, fixup_Hexagon_LD_PLT_B32_PCREL_X },
};
auto F = Relocs.find(VarKind);
if (F != Relocs.end())
return Hexagon::Fixups(F->second);
raise_relocation_error(0, VarKind);
}
if (MCID.isBranch())
return fixup_Hexagon_B13_PCREL;
static const std::map<unsigned,unsigned> RelocsLo = {
{ MCSymbolRefExpr::VK_GOT, fixup_Hexagon_GOT_LO16 },
{ MCSymbolRefExpr::VK_GOTREL, fixup_Hexagon_GOTREL_LO16 },
{ MCSymbolRefExpr::VK_Hexagon_GD_GOT, fixup_Hexagon_GD_GOT_LO16 },
{ MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_LO16 },
{ MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_LO16 },
{ MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_LO16 },
{ MCSymbolRefExpr::VK_TPREL, fixup_Hexagon_TPREL_LO16 },
{ MCSymbolRefExpr::VK_DTPREL, fixup_Hexagon_DTPREL_LO16 },
{ MCSymbolRefExpr::VK_None, fixup_Hexagon_LO16 },
};
static const std::map<unsigned,unsigned> RelocsHi = {
{ MCSymbolRefExpr::VK_GOT, fixup_Hexagon_GOT_HI16 },
{ MCSymbolRefExpr::VK_GOTREL, fixup_Hexagon_GOTREL_HI16 },
{ MCSymbolRefExpr::VK_Hexagon_GD_GOT, fixup_Hexagon_GD_GOT_HI16 },
{ MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_HI16 },
{ MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_HI16 },
{ MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_HI16 },
{ MCSymbolRefExpr::VK_TPREL, fixup_Hexagon_TPREL_HI16 },
{ MCSymbolRefExpr::VK_DTPREL, fixup_Hexagon_DTPREL_HI16 },
{ MCSymbolRefExpr::VK_None, fixup_Hexagon_HI16 },
};
switch (MCID.getOpcode()) {
case Hexagon::LO:
case Hexagon::A2_tfril: {
auto F = RelocsLo.find(VarKind);
if (F != RelocsLo.end())
return Hexagon::Fixups(F->second);
break;
}
case Hexagon::HI:
case Hexagon::A2_tfrih: {
auto F = RelocsHi.find(VarKind);
if (F != RelocsHi.end())
return Hexagon::Fixups(F->second);
break;
}
}
raise_relocation_error(0, VarKind);
}
static bool isPCRel(unsigned Kind) {
switch (Kind){
case fixup_Hexagon_B22_PCREL:
case fixup_Hexagon_B15_PCREL:
case fixup_Hexagon_B7_PCREL:
case fixup_Hexagon_B13_PCREL:
case fixup_Hexagon_B9_PCREL:
case fixup_Hexagon_B32_PCREL_X:
case fixup_Hexagon_B22_PCREL_X:
case fixup_Hexagon_B15_PCREL_X:
case fixup_Hexagon_B13_PCREL_X:
case fixup_Hexagon_B9_PCREL_X:
case fixup_Hexagon_B7_PCREL_X:
case fixup_Hexagon_32_PCREL:
case fixup_Hexagon_PLT_B22_PCREL:
case fixup_Hexagon_GD_PLT_B22_PCREL:
case fixup_Hexagon_LD_PLT_B22_PCREL:
case fixup_Hexagon_GD_PLT_B22_PCREL_X:
case fixup_Hexagon_LD_PLT_B22_PCREL_X:
case fixup_Hexagon_6_PCREL_X:
return true;
default:
return false;
}
}
unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
const MCOperand &MO, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (isa<HexagonMCExpr>(ME))
ME = &HexagonMCInstrInfo::getExpr(*ME);
int64_t Value;
if (ME->evaluateAsAbsolute(Value)) {
bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) ||
HexagonMCInstrInfo::isExtended(MCII, MI);
// Only sub-instruction #1 can be extended in a duplex. If MI is a
// sub-instruction #0, it is not extended even if Extended is true
// (it can be true for the duplex as a whole).
bool IsSub0 = HexagonMCInstrInfo::isSubInstruction(MI) && !State.SubInst1;
if (State.Extended && InstExtendable && !IsSub0) {
unsigned OpIdx = ~0u;
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
if (&MO != &MI.getOperand(I))
continue;
OpIdx = I;
break;
}
assert(OpIdx != ~0u);
if (OpIdx == HexagonMCInstrInfo::getExtendableOp(MCII, MI)) {
unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
Value = (Value & 0x3f) << Shift;
}
}
return Value;
}
assert(ME->getKind() == MCExpr::SymbolRef ||
ME->getKind() == MCExpr::Binary);
if (ME->getKind() == MCExpr::Binary) {
MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
return 0;
}
unsigned FixupKind = fixup_Invalid;
const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
unsigned FixupWidth = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
MCSymbolRefExpr::VariantKind VarKind = MCSRE->getKind();
unsigned Opc = MCID.getOpcode();
unsigned IType = HexagonMCInstrInfo::getType(MCII, MI);
LLVM_DEBUG(dbgs() << "----------------------------------------\n"
<< "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
<< "\nOpcode: " << Opc << "\nRelocation bits: "
<< FixupWidth << "\nAddend: " << State.Addend
<< "\nVariant: " << unsigned(VarKind)
<< "\n----------------------------------------\n");
// Pick the applicable fixup kind for the symbol.
// Handle special cases first, the rest will be looked up in the tables.
if (FixupWidth == 16 && !State.Extended) {
if (VarKind == MCSymbolRefExpr::VK_None) {
if (HexagonMCInstrInfo::s27_2_reloc(*MO.getExpr())) {
// A2_iconst.
FixupKind = Hexagon::fixup_Hexagon_27_REG;
} else {
// Look for GP-relative fixups.
unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
static const Hexagon::Fixups GPRelFixups[] = {
Hexagon::fixup_Hexagon_GPREL16_0, Hexagon::fixup_Hexagon_GPREL16_1,
Hexagon::fixup_Hexagon_GPREL16_2, Hexagon::fixup_Hexagon_GPREL16_3
};
assert(Shift < array_lengthof(GPRelFixups));
auto UsesGP = [] (const MCInstrDesc &D) {
for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U)
if (*U == Hexagon::GP)
return true;
return false;
};
if (UsesGP(MCID))
FixupKind = GPRelFixups[Shift];
}
} else if (VarKind == MCSymbolRefExpr::VK_GOTREL) {
// Select between LO/HI.
if (Opc == Hexagon::LO)
FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
else if (Opc == Hexagon::HI)
FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
}
} else {
bool BranchOrCR = MCID.isBranch() || IType == HexagonII::TypeCR;
switch (FixupWidth) {
case 9:
if (BranchOrCR)
FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
: Hexagon::fixup_Hexagon_B9_PCREL;
break;
case 8:
case 7:
if (State.Extended && VarKind == MCSymbolRefExpr::VK_GOT)
FixupKind = HexagonMCInstrInfo::isExtentSigned(MCII, MI)
? Hexagon::fixup_Hexagon_GOT_16_X
: Hexagon::fixup_Hexagon_GOT_11_X;
else if (FixupWidth == 7 && BranchOrCR)
FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
: Hexagon::fixup_Hexagon_B7_PCREL;
break;
case 0:
FixupKind = getFixupNoBits(MCII, MI, MO, VarKind);
break;
}
}
if (FixupKind == fixup_Invalid) {
const auto &FixupTable = State.Extended ? ExtFixups : StdFixups;
auto FindVK = FixupTable.find(VarKind);
if (FindVK != FixupTable.end())
FixupKind = FindVK->second[FixupWidth];
}
if (FixupKind == fixup_Invalid)
raise_relocation_error(FixupWidth, VarKind);
const MCExpr *FixupExpr = MO.getExpr();
if (State.Addend != 0 && isPCRel(FixupKind)) {
const MCExpr *C = MCConstantExpr::create(State.Addend, MCT);
FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
}
MCFixup Fixup = MCFixup::create(State.Addend, FixupExpr,
MCFixupKind(FixupKind), MI.getLoc());
Fixups.push_back(Fixup);
// All of the information is in the fixup.
return 0;
}
unsigned
HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
SmallVectorImpl<MCFixup> &Fixups,
MCSubtargetInfo const &STI) const {
size_t OperandNumber = ~0U;
for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
if (&MI.getOperand(i) == &MO) {
OperandNumber = i;
break;
}
assert((OperandNumber != ~0U) && "Operand not found");
if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
&MO == &HexagonMCInstrInfo::getNewValueOperand(MCII, MI)) {
// Calculate the new value distance to the associated producer
unsigned SOffset = 0;
unsigned VOffset = 0;
unsigned UseReg = MO.getReg();
unsigned DefReg1 = Hexagon::NoRegister;
unsigned DefReg2 = Hexagon::NoRegister;
auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
const MCOperand *I = Instrs.begin() + State.Index - 1;
for (;; --I) {
assert(I != Instrs.begin() - 1 && "Couldn't find producer");
MCInst const &Inst = *I->getInst();
if (HexagonMCInstrInfo::isImmext(Inst))
continue;
DefReg1 = Hexagon::NoRegister;
DefReg2 = Hexagon::NoRegister;
++SOffset;
if (HexagonMCInstrInfo::isVector(MCII, Inst)) {
// Vector instructions don't count scalars.
++VOffset;
}
if (HexagonMCInstrInfo::hasNewValue(MCII, Inst))
DefReg1 = HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg();
if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst))
DefReg2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg();
if (!RegisterMatches(UseReg, DefReg1, DefReg2)) {
// This isn't the register we're looking for
continue;
}
if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) {
// Producer is unpredicated
break;
}
assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
"Unpredicated consumer depending on predicated producer");
if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
HexagonMCInstrInfo::isPredicatedTrue(MCII, MI))
// Producer predicate sense matched ours.
break;
}
// Hexagon PRM 10.11 Construct Nt from distance
unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset
: SOffset;
Offset <<= 1;
Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2);
return Offset;
}
assert(!MO.isImm());
if (MO.isReg()) {
unsigned Reg = MO.getReg();
switch (HexagonMCInstrInfo::getDesc(MCII, MI).OpInfo[OperandNumber].RegClass) {
case GeneralSubRegsRegClassID:
case GeneralDoubleLow8RegsRegClassID:
return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg);
default:
break;
}
return MCT.getRegisterInfo()->getEncodingValue(Reg);
}
return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
}
MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
MCRegisterInfo const &MRI,
MCContext &MCT) {
return new HexagonMCCodeEmitter(MII, MCT);
}
#define ENABLE_INSTR_PREDICATE_VERIFIER
#include "HexagonGenMCCodeEmitter.inc"