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Copy pathHexagonISelDAGToDAG.cpp
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HexagonISelDAGToDAG.cpp
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//===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines an instruction selector for the Hexagon target.
//
//===----------------------------------------------------------------------===//
#include "HexagonISelDAGToDAG.h"
#include "Hexagon.h"
#include "HexagonISelLowering.h"
#include "HexagonMachineFunctionInfo.h"
#include "HexagonTargetMachine.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsHexagon.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
using namespace llvm;
#define DEBUG_TYPE "hexagon-isel"
static
cl::opt<bool>
EnableAddressRebalancing("isel-rebalance-addr", cl::Hidden, cl::init(true),
cl::desc("Rebalance address calculation trees to improve "
"instruction selection"));
// Rebalance only if this allows e.g. combining a GA with an offset or
// factoring out a shift.
static
cl::opt<bool>
RebalanceOnlyForOptimizations("rebalance-only-opt", cl::Hidden, cl::init(false),
cl::desc("Rebalance address tree only if this allows optimizations"));
static
cl::opt<bool>
RebalanceOnlyImbalancedTrees("rebalance-only-imbal", cl::Hidden,
cl::init(false), cl::desc("Rebalance address tree only if it is imbalanced"));
static cl::opt<bool> CheckSingleUse("hexagon-isel-su", cl::Hidden,
cl::init(true), cl::desc("Enable checking of SDNode's single-use status"));
//===----------------------------------------------------------------------===//
// Instruction Selector Implementation
//===----------------------------------------------------------------------===//
#define GET_DAGISEL_BODY HexagonDAGToDAGISel
#include "HexagonGenDAGISel.inc"
namespace llvm {
/// createHexagonISelDag - This pass converts a legalized DAG into a
/// Hexagon-specific DAG, ready for instruction scheduling.
FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new HexagonDAGToDAGISel(TM, OptLevel);
}
}
void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Offset = LD->getOffset();
int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
EVT LoadedVT = LD->getMemoryVT();
unsigned Opcode = 0;
// Check for zero extended loads. Treat any-extend loads as zero extended
// loads.
ISD::LoadExtType ExtType = LD->getExtensionType();
bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc);
assert(LoadedVT.isSimple());
switch (LoadedVT.getSimpleVT().SimpleTy) {
case MVT::i8:
if (IsZeroExt)
Opcode = IsValidInc ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrub_io;
else
Opcode = IsValidInc ? Hexagon::L2_loadrb_pi : Hexagon::L2_loadrb_io;
break;
case MVT::i16:
if (IsZeroExt)
Opcode = IsValidInc ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadruh_io;
else
Opcode = IsValidInc ? Hexagon::L2_loadrh_pi : Hexagon::L2_loadrh_io;
break;
case MVT::i32:
case MVT::f32:
case MVT::v2i16:
case MVT::v4i8:
Opcode = IsValidInc ? Hexagon::L2_loadri_pi : Hexagon::L2_loadri_io;
break;
case MVT::i64:
case MVT::f64:
case MVT::v2i32:
case MVT::v4i16:
case MVT::v8i8:
Opcode = IsValidInc ? Hexagon::L2_loadrd_pi : Hexagon::L2_loadrd_io;
break;
case MVT::v64i8:
case MVT::v32i16:
case MVT::v16i32:
case MVT::v8i64:
case MVT::v128i8:
case MVT::v64i16:
case MVT::v32i32:
case MVT::v16i64:
if (isAlignedMemNode(LD)) {
if (LD->isNonTemporal())
Opcode = IsValidInc ? Hexagon::V6_vL32b_nt_pi : Hexagon::V6_vL32b_nt_ai;
else
Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai;
} else {
Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai;
}
break;
default:
llvm_unreachable("Unexpected memory type in indexed load");
}
SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
MachineMemOperand *MemOp = LD->getMemOperand();
auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl)
-> MachineSDNode* {
if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32);
return CurDAG->getMachineNode(Hexagon::A4_combineir, dl, MVT::i64,
Zero, SDValue(N, 0));
}
if (ExtType == ISD::SEXTLOAD)
return CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
SDValue(N, 0));
return N;
};
// Loaded value Next address Chain
SDValue From[3] = { SDValue(LD,0), SDValue(LD,1), SDValue(LD,2) };
SDValue To[3];
EVT ValueVT = LD->getValueType(0);
if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) {
// A load extending to i64 will actually produce i32, which will then
// need to be extended to i64.
assert(LoadedVT.getSizeInBits() <= 32);
ValueVT = MVT::i32;
}
if (IsValidInc) {
MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT,
MVT::i32, MVT::Other, Base,
IncV, Chain);
CurDAG->setNodeMemRefs(L, {MemOp});
To[1] = SDValue(L, 1); // Next address.
To[2] = SDValue(L, 2); // Chain.
// Handle special case for extension to i64.
if (LD->getValueType(0) == MVT::i64)
L = getExt64(L, dl);
To[0] = SDValue(L, 0); // Loaded (extended) value.
} else {
SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32);
MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other,
Base, Zero, Chain);
CurDAG->setNodeMemRefs(L, {MemOp});
To[2] = SDValue(L, 1); // Chain.
MachineSDNode *A = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
Base, IncV);
To[1] = SDValue(A, 0); // Next address.
// Handle special case for extension to i64.
if (LD->getValueType(0) == MVT::i64)
L = getExt64(L, dl);
To[0] = SDValue(L, 0); // Loaded (extended) value.
}
ReplaceUses(From, To, 3);
CurDAG->RemoveDeadNode(LD);
}
MachineSDNode *HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(SDNode *IntN) {
if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
return nullptr;
SDLoc dl(IntN);
unsigned IntNo = cast<ConstantSDNode>(IntN->getOperand(1))->getZExtValue();
static std::map<unsigned,unsigned> LoadPciMap = {
{ Intrinsic::hexagon_circ_ldb, Hexagon::L2_loadrb_pci },
{ Intrinsic::hexagon_circ_ldub, Hexagon::L2_loadrub_pci },
{ Intrinsic::hexagon_circ_ldh, Hexagon::L2_loadrh_pci },
{ Intrinsic::hexagon_circ_lduh, Hexagon::L2_loadruh_pci },
{ Intrinsic::hexagon_circ_ldw, Hexagon::L2_loadri_pci },
{ Intrinsic::hexagon_circ_ldd, Hexagon::L2_loadrd_pci },
};
auto FLC = LoadPciMap.find(IntNo);
if (FLC != LoadPciMap.end()) {
EVT ValTy = (IntNo == Intrinsic::hexagon_circ_ldd) ? MVT::i64 : MVT::i32;
EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
// Operands: { Base, Increment, Modifier, Chain }
auto Inc = cast<ConstantSDNode>(IntN->getOperand(5));
SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), dl, MVT::i32);
MachineSDNode *Res = CurDAG->getMachineNode(FLC->second, dl, RTys,
{ IntN->getOperand(2), I, IntN->getOperand(4),
IntN->getOperand(0) });
return Res;
}
return nullptr;
}
SDNode *HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(MachineSDNode *LoadN,
SDNode *IntN) {
// The "LoadN" is just a machine load instruction. The intrinsic also
// involves storing it. Generate an appropriate store to the location
// given in the intrinsic's operand(3).
uint64_t F = HII->get(LoadN->getMachineOpcode()).TSFlags;
unsigned SizeBits = (F >> HexagonII::MemAccessSizePos) &
HexagonII::MemAccesSizeMask;
unsigned Size = 1U << (SizeBits-1);
SDLoc dl(IntN);
MachinePointerInfo PI;
SDValue TS;
SDValue Loc = IntN->getOperand(3);
if (Size >= 4)
TS = CurDAG->getStore(SDValue(LoadN, 2), dl, SDValue(LoadN, 0), Loc, PI,
Align(Size));
else
TS = CurDAG->getTruncStore(SDValue(LoadN, 2), dl, SDValue(LoadN, 0), Loc,
PI, MVT::getIntegerVT(Size * 8), Align(Size));
SDNode *StoreN;
{
HandleSDNode Handle(TS);
SelectStore(TS.getNode());
StoreN = Handle.getValue().getNode();
}
// Load's results are { Loaded value, Updated pointer, Chain }
ReplaceUses(SDValue(IntN, 0), SDValue(LoadN, 1));
ReplaceUses(SDValue(IntN, 1), SDValue(StoreN, 0));
return StoreN;
}
bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) {
// The intrinsics for load circ/brev perform two operations:
// 1. Load a value V from the specified location, using the addressing
// mode corresponding to the intrinsic.
// 2. Store V into a specified location. This location is typically a
// local, temporary object.
// In many cases, the program using these intrinsics will immediately
// load V again from the local object. In those cases, when certain
// conditions are met, the last load can be removed.
// This function identifies and optimizes this pattern. If the pattern
// cannot be optimized, it returns nullptr, which will cause the load
// to be selected separately from the intrinsic (which will be handled
// in SelectIntrinsicWChain).
SDValue Ch = N->getOperand(0);
SDValue Loc = N->getOperand(1);
// Assume that the load and the intrinsic are connected directly with a
// chain:
// t1: i32,ch = int.load ..., ..., ..., Loc, ... // <-- C
// t2: i32,ch = load t1:1, Loc, ...
SDNode *C = Ch.getNode();
if (C->getOpcode() != ISD::INTRINSIC_W_CHAIN)
return false;
// The second load can only be eliminated if its extension type matches
// that of the load instruction corresponding to the intrinsic. The user
// can provide an address of an unsigned variable to store the result of
// a sign-extending intrinsic into (or the other way around).
ISD::LoadExtType IntExt;
switch (cast<ConstantSDNode>(C->getOperand(1))->getZExtValue()) {
case Intrinsic::hexagon_circ_ldub:
case Intrinsic::hexagon_circ_lduh:
IntExt = ISD::ZEXTLOAD;
break;
case Intrinsic::hexagon_circ_ldw:
case Intrinsic::hexagon_circ_ldd:
IntExt = ISD::NON_EXTLOAD;
break;
default:
IntExt = ISD::SEXTLOAD;
break;
}
if (N->getExtensionType() != IntExt)
return false;
// Make sure the target location for the loaded value in the load intrinsic
// is the location from which LD (or N) is loading.
if (C->getNumOperands() < 4 || Loc.getNode() != C->getOperand(3).getNode())
return false;
if (MachineSDNode *L = LoadInstrForLoadIntrinsic(C)) {
SDNode *S = StoreInstrForLoadIntrinsic(L, C);
SDValue F[] = { SDValue(N,0), SDValue(N,1), SDValue(C,0), SDValue(C,1) };
SDValue T[] = { SDValue(L,0), SDValue(S,0), SDValue(L,1), SDValue(S,0) };
ReplaceUses(F, T, array_lengthof(T));
// This transformation will leave the intrinsic dead. If it remains in
// the DAG, the selection code will see it again, but without the load,
// and it will generate a store that is normally required for it.
CurDAG->RemoveDeadNode(C);
return true;
}
return false;
}
// Convert the bit-reverse load intrinsic to appropriate target instruction.
bool HexagonDAGToDAGISel::SelectBrevLdIntrinsic(SDNode *IntN) {
if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
return false;
const SDLoc &dl(IntN);
unsigned IntNo = cast<ConstantSDNode>(IntN->getOperand(1))->getZExtValue();
static const std::map<unsigned, unsigned> LoadBrevMap = {
{ Intrinsic::hexagon_L2_loadrb_pbr, Hexagon::L2_loadrb_pbr },
{ Intrinsic::hexagon_L2_loadrub_pbr, Hexagon::L2_loadrub_pbr },
{ Intrinsic::hexagon_L2_loadrh_pbr, Hexagon::L2_loadrh_pbr },
{ Intrinsic::hexagon_L2_loadruh_pbr, Hexagon::L2_loadruh_pbr },
{ Intrinsic::hexagon_L2_loadri_pbr, Hexagon::L2_loadri_pbr },
{ Intrinsic::hexagon_L2_loadrd_pbr, Hexagon::L2_loadrd_pbr }
};
auto FLI = LoadBrevMap.find(IntNo);
if (FLI != LoadBrevMap.end()) {
EVT ValTy =
(IntNo == Intrinsic::hexagon_L2_loadrd_pbr) ? MVT::i64 : MVT::i32;
EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
// Operands of Intrinsic: {chain, enum ID of intrinsic, baseptr,
// modifier}.
// Operands of target instruction: { Base, Modifier, Chain }.
MachineSDNode *Res = CurDAG->getMachineNode(
FLI->second, dl, RTys,
{IntN->getOperand(2), IntN->getOperand(3), IntN->getOperand(0)});
MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(IntN)->getMemOperand();
CurDAG->setNodeMemRefs(Res, {MemOp});
ReplaceUses(SDValue(IntN, 0), SDValue(Res, 0));
ReplaceUses(SDValue(IntN, 1), SDValue(Res, 1));
ReplaceUses(SDValue(IntN, 2), SDValue(Res, 2));
CurDAG->RemoveDeadNode(IntN);
return true;
}
return false;
}
/// Generate a machine instruction node for the new circlar buffer intrinsics.
/// The new versions use a CSx register instead of the K field.
bool HexagonDAGToDAGISel::SelectNewCircIntrinsic(SDNode *IntN) {
if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
return false;
SDLoc DL(IntN);
unsigned IntNo = cast<ConstantSDNode>(IntN->getOperand(1))->getZExtValue();
SmallVector<SDValue, 7> Ops;
static std::map<unsigned,unsigned> LoadNPcMap = {
{ Intrinsic::hexagon_L2_loadrub_pci, Hexagon::PS_loadrub_pci },
{ Intrinsic::hexagon_L2_loadrb_pci, Hexagon::PS_loadrb_pci },
{ Intrinsic::hexagon_L2_loadruh_pci, Hexagon::PS_loadruh_pci },
{ Intrinsic::hexagon_L2_loadrh_pci, Hexagon::PS_loadrh_pci },
{ Intrinsic::hexagon_L2_loadri_pci, Hexagon::PS_loadri_pci },
{ Intrinsic::hexagon_L2_loadrd_pci, Hexagon::PS_loadrd_pci },
{ Intrinsic::hexagon_L2_loadrub_pcr, Hexagon::PS_loadrub_pcr },
{ Intrinsic::hexagon_L2_loadrb_pcr, Hexagon::PS_loadrb_pcr },
{ Intrinsic::hexagon_L2_loadruh_pcr, Hexagon::PS_loadruh_pcr },
{ Intrinsic::hexagon_L2_loadrh_pcr, Hexagon::PS_loadrh_pcr },
{ Intrinsic::hexagon_L2_loadri_pcr, Hexagon::PS_loadri_pcr },
{ Intrinsic::hexagon_L2_loadrd_pcr, Hexagon::PS_loadrd_pcr }
};
auto FLI = LoadNPcMap.find (IntNo);
if (FLI != LoadNPcMap.end()) {
EVT ValTy = MVT::i32;
if (IntNo == Intrinsic::hexagon_L2_loadrd_pci ||
IntNo == Intrinsic::hexagon_L2_loadrd_pcr)
ValTy = MVT::i64;
EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
// Handle load.*_pci case which has 6 operands.
if (IntN->getNumOperands() == 6) {
auto Inc = cast<ConstantSDNode>(IntN->getOperand(3));
SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), DL, MVT::i32);
// Operands: { Base, Increment, Modifier, Start, Chain }.
Ops = { IntN->getOperand(2), I, IntN->getOperand(4), IntN->getOperand(5),
IntN->getOperand(0) };
} else
// Handle load.*_pcr case which has 5 operands.
// Operands: { Base, Modifier, Start, Chain }.
Ops = { IntN->getOperand(2), IntN->getOperand(3), IntN->getOperand(4),
IntN->getOperand(0) };
MachineSDNode *Res = CurDAG->getMachineNode(FLI->second, DL, RTys, Ops);
ReplaceUses(SDValue(IntN, 0), SDValue(Res, 0));
ReplaceUses(SDValue(IntN, 1), SDValue(Res, 1));
ReplaceUses(SDValue(IntN, 2), SDValue(Res, 2));
CurDAG->RemoveDeadNode(IntN);
return true;
}
static std::map<unsigned,unsigned> StoreNPcMap = {
{ Intrinsic::hexagon_S2_storerb_pci, Hexagon::PS_storerb_pci },
{ Intrinsic::hexagon_S2_storerh_pci, Hexagon::PS_storerh_pci },
{ Intrinsic::hexagon_S2_storerf_pci, Hexagon::PS_storerf_pci },
{ Intrinsic::hexagon_S2_storeri_pci, Hexagon::PS_storeri_pci },
{ Intrinsic::hexagon_S2_storerd_pci, Hexagon::PS_storerd_pci },
{ Intrinsic::hexagon_S2_storerb_pcr, Hexagon::PS_storerb_pcr },
{ Intrinsic::hexagon_S2_storerh_pcr, Hexagon::PS_storerh_pcr },
{ Intrinsic::hexagon_S2_storerf_pcr, Hexagon::PS_storerf_pcr },
{ Intrinsic::hexagon_S2_storeri_pcr, Hexagon::PS_storeri_pcr },
{ Intrinsic::hexagon_S2_storerd_pcr, Hexagon::PS_storerd_pcr }
};
auto FSI = StoreNPcMap.find (IntNo);
if (FSI != StoreNPcMap.end()) {
EVT RTys[] = { MVT::i32, MVT::Other };
// Handle store.*_pci case which has 7 operands.
if (IntN->getNumOperands() == 7) {
auto Inc = cast<ConstantSDNode>(IntN->getOperand(3));
SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), DL, MVT::i32);
// Operands: { Base, Increment, Modifier, Value, Start, Chain }.
Ops = { IntN->getOperand(2), I, IntN->getOperand(4), IntN->getOperand(5),
IntN->getOperand(6), IntN->getOperand(0) };
} else
// Handle store.*_pcr case which has 6 operands.
// Operands: { Base, Modifier, Value, Start, Chain }.
Ops = { IntN->getOperand(2), IntN->getOperand(3), IntN->getOperand(4),
IntN->getOperand(5), IntN->getOperand(0) };
MachineSDNode *Res = CurDAG->getMachineNode(FSI->second, DL, RTys, Ops);
ReplaceUses(SDValue(IntN, 0), SDValue(Res, 0));
ReplaceUses(SDValue(IntN, 1), SDValue(Res, 1));
CurDAG->RemoveDeadNode(IntN);
return true;
}
return false;
}
void HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
SDLoc dl(N);
LoadSDNode *LD = cast<LoadSDNode>(N);
// Handle indexed loads.
ISD::MemIndexedMode AM = LD->getAddressingMode();
if (AM != ISD::UNINDEXED) {
SelectIndexedLoad(LD, dl);
return;
}
// Handle patterns using circ/brev load intrinsics.
if (tryLoadOfLoadIntrinsic(LD))
return;
SelectCode(LD);
}
void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) {
SDValue Chain = ST->getChain();
SDValue Base = ST->getBasePtr();
SDValue Offset = ST->getOffset();
SDValue Value = ST->getValue();
// Get the constant value.
int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
EVT StoredVT = ST->getMemoryVT();
EVT ValueVT = Value.getValueType();
bool IsValidInc = HII->isValidAutoIncImm(StoredVT, Inc);
unsigned Opcode = 0;
assert(StoredVT.isSimple());
switch (StoredVT.getSimpleVT().SimpleTy) {
case MVT::i8:
Opcode = IsValidInc ? Hexagon::S2_storerb_pi : Hexagon::S2_storerb_io;
break;
case MVT::i16:
Opcode = IsValidInc ? Hexagon::S2_storerh_pi : Hexagon::S2_storerh_io;
break;
case MVT::i32:
case MVT::f32:
case MVT::v2i16:
case MVT::v4i8:
Opcode = IsValidInc ? Hexagon::S2_storeri_pi : Hexagon::S2_storeri_io;
break;
case MVT::i64:
case MVT::f64:
case MVT::v2i32:
case MVT::v4i16:
case MVT::v8i8:
Opcode = IsValidInc ? Hexagon::S2_storerd_pi : Hexagon::S2_storerd_io;
break;
case MVT::v64i8:
case MVT::v32i16:
case MVT::v16i32:
case MVT::v8i64:
case MVT::v128i8:
case MVT::v64i16:
case MVT::v32i32:
case MVT::v16i64:
if (isAlignedMemNode(ST)) {
if (ST->isNonTemporal())
Opcode = IsValidInc ? Hexagon::V6_vS32b_nt_pi : Hexagon::V6_vS32b_nt_ai;
else
Opcode = IsValidInc ? Hexagon::V6_vS32b_pi : Hexagon::V6_vS32b_ai;
} else {
Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi : Hexagon::V6_vS32Ub_ai;
}
break;
default:
llvm_unreachable("Unexpected memory type in indexed store");
}
if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
Value = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo,
dl, MVT::i32, Value);
}
SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
MachineMemOperand *MemOp = ST->getMemOperand();
// Next address Chain
SDValue From[2] = { SDValue(ST,0), SDValue(ST,1) };
SDValue To[2];
if (IsValidInc) {
// Build post increment store.
SDValue Ops[] = { Base, IncV, Value, Chain };
MachineSDNode *S = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
Ops);
CurDAG->setNodeMemRefs(S, {MemOp});
To[0] = SDValue(S, 0);
To[1] = SDValue(S, 1);
} else {
SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32);
SDValue Ops[] = { Base, Zero, Value, Chain };
MachineSDNode *S = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
CurDAG->setNodeMemRefs(S, {MemOp});
To[1] = SDValue(S, 0);
MachineSDNode *A = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
Base, IncV);
To[0] = SDValue(A, 0);
}
ReplaceUses(From, To, 2);
CurDAG->RemoveDeadNode(ST);
}
void HexagonDAGToDAGISel::SelectStore(SDNode *N) {
SDLoc dl(N);
StoreSDNode *ST = cast<StoreSDNode>(N);
// Handle indexed stores.
ISD::MemIndexedMode AM = ST->getAddressingMode();
if (AM != ISD::UNINDEXED) {
SelectIndexedStore(ST, dl);
return;
}
SelectCode(ST);
}
void HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
SDLoc dl(N);
SDValue Shl_0 = N->getOperand(0);
SDValue Shl_1 = N->getOperand(1);
auto Default = [this,N] () -> void { SelectCode(N); };
if (N->getValueType(0) != MVT::i32 || Shl_1.getOpcode() != ISD::Constant)
return Default();
// RHS is const.
int32_t ShlConst = cast<ConstantSDNode>(Shl_1)->getSExtValue();
if (Shl_0.getOpcode() == ISD::MUL) {
SDValue Mul_0 = Shl_0.getOperand(0); // Val
SDValue Mul_1 = Shl_0.getOperand(1); // Const
// RHS of mul is const.
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mul_1)) {
int32_t ValConst = C->getSExtValue() << ShlConst;
if (isInt<9>(ValConst)) {
SDValue Val = CurDAG->getTargetConstant(ValConst, dl, MVT::i32);
SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
MVT::i32, Mul_0, Val);
ReplaceNode(N, Result);
return;
}
}
return Default();
}
if (Shl_0.getOpcode() == ISD::SUB) {
SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
SDValue Sub_1 = Shl_0.getOperand(1); // Val
if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Sub_0)) {
if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL)
return Default();
SDValue Shl2_0 = Sub_1.getOperand(0); // Val
SDValue Shl2_1 = Sub_1.getOperand(1); // Const
if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(Shl2_1)) {
int32_t ValConst = 1 << (ShlConst + C2->getSExtValue());
if (isInt<9>(-ValConst)) {
SDValue Val = CurDAG->getTargetConstant(-ValConst, dl, MVT::i32);
SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
MVT::i32, Shl2_0, Val);
ReplaceNode(N, Result);
return;
}
}
}
}
return Default();
}
//
// Handling intrinsics for circular load and bitreverse load.
//
void HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
if (MachineSDNode *L = LoadInstrForLoadIntrinsic(N)) {
StoreInstrForLoadIntrinsic(L, N);
CurDAG->RemoveDeadNode(N);
return;
}
// Handle bit-reverse load intrinsics.
if (SelectBrevLdIntrinsic(N))
return;
if (SelectNewCircIntrinsic(N))
return;
unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
if (IntNo == Intrinsic::hexagon_V6_vgathermw ||
IntNo == Intrinsic::hexagon_V6_vgathermw_128B ||
IntNo == Intrinsic::hexagon_V6_vgathermh ||
IntNo == Intrinsic::hexagon_V6_vgathermh_128B ||
IntNo == Intrinsic::hexagon_V6_vgathermhw ||
IntNo == Intrinsic::hexagon_V6_vgathermhw_128B) {
SelectV65Gather(N);
return;
}
if (IntNo == Intrinsic::hexagon_V6_vgathermwq ||
IntNo == Intrinsic::hexagon_V6_vgathermwq_128B ||
IntNo == Intrinsic::hexagon_V6_vgathermhq ||
IntNo == Intrinsic::hexagon_V6_vgathermhq_128B ||
IntNo == Intrinsic::hexagon_V6_vgathermhwq ||
IntNo == Intrinsic::hexagon_V6_vgathermhwq_128B) {
SelectV65GatherPred(N);
return;
}
SelectCode(N);
}
void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
unsigned Bits;
switch (IID) {
case Intrinsic::hexagon_S2_vsplatrb:
Bits = 8;
break;
case Intrinsic::hexagon_S2_vsplatrh:
Bits = 16;
break;
case Intrinsic::hexagon_V6_vaddcarry:
case Intrinsic::hexagon_V6_vaddcarry_128B:
case Intrinsic::hexagon_V6_vsubcarry:
case Intrinsic::hexagon_V6_vsubcarry_128B:
SelectHVXDualOutput(N);
return;
default:
SelectCode(N);
return;
}
SDValue V = N->getOperand(1);
SDValue U;
if (keepsLowBits(V, Bits, U)) {
SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
N->getOperand(0), U);
ReplaceNode(N, R.getNode());
SelectCode(R.getNode());
return;
}
SelectCode(N);
}
//
// Map floating point constant values.
//
void HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
SDLoc dl(N);
auto *CN = cast<ConstantFPSDNode>(N);
APInt A = CN->getValueAPF().bitcastToAPInt();
if (N->getValueType(0) == MVT::f32) {
SDValue V = CurDAG->getTargetConstant(A.getZExtValue(), dl, MVT::i32);
ReplaceNode(N, CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::f32, V));
return;
}
if (N->getValueType(0) == MVT::f64) {
SDValue V = CurDAG->getTargetConstant(A.getZExtValue(), dl, MVT::i64);
ReplaceNode(N, CurDAG->getMachineNode(Hexagon::CONST64, dl, MVT::f64, V));
return;
}
SelectCode(N);
}
//
// Map boolean values.
//
void HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
if (N->getValueType(0) == MVT::i1) {
assert(!(cast<ConstantSDNode>(N)->getZExtValue() >> 1));
unsigned Opc = (cast<ConstantSDNode>(N)->getSExtValue() != 0)
? Hexagon::PS_true
: Hexagon::PS_false;
ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), MVT::i1));
return;
}
SelectCode(N);
}
void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
MachineFrameInfo &MFI = MF->getFrameInfo();
const HexagonFrameLowering *HFI = HST->getFrameLowering();
int FX = cast<FrameIndexSDNode>(N)->getIndex();
Align StkA = HFI->getStackAlign();
Align MaxA = MFI.getMaxAlign();
SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
SDLoc DL(N);
SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
SDNode *R = nullptr;
// Use PS_fi when:
// - the object is fixed, or
// - there are no objects with higher-than-default alignment, or
// - there are no dynamically allocated objects.
// Otherwise, use PS_fia.
if (FX < 0 || MaxA <= StkA || !MFI.hasVarSizedObjects()) {
R = CurDAG->getMachineNode(Hexagon::PS_fi, DL, MVT::i32, FI, Zero);
} else {
auto &HMFI = *MF->getInfo<HexagonMachineFunctionInfo>();
unsigned AR = HMFI.getStackAlignBaseVReg();
SDValue CH = CurDAG->getEntryNode();
SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR, MVT::i32), FI, Zero };
R = CurDAG->getMachineNode(Hexagon::PS_fia, DL, MVT::i32, Ops);
}
ReplaceNode(N, R);
}
void HexagonDAGToDAGISel::SelectAddSubCarry(SDNode *N) {
unsigned OpcCarry = N->getOpcode() == HexagonISD::ADDC ? Hexagon::A4_addp_c
: Hexagon::A4_subp_c;
SDNode *C = CurDAG->getMachineNode(OpcCarry, SDLoc(N), N->getVTList(),
{ N->getOperand(0), N->getOperand(1),
N->getOperand(2) });
ReplaceNode(N, C);
}
void HexagonDAGToDAGISel::SelectVAlign(SDNode *N) {
MVT ResTy = N->getValueType(0).getSimpleVT();
if (HST->isHVXVectorType(ResTy, true))
return SelectHvxVAlign(N);
const SDLoc &dl(N);
unsigned VecLen = ResTy.getSizeInBits();
if (VecLen == 32) {
SDValue Ops[] = {
CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID, dl, MVT::i32),
N->getOperand(0),
CurDAG->getTargetConstant(Hexagon::isub_hi, dl, MVT::i32),
N->getOperand(1),
CurDAG->getTargetConstant(Hexagon::isub_lo, dl, MVT::i32)
};
SDNode *R = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl,
MVT::i64, Ops);
// Shift right by "(Addr & 0x3) * 8" bytes.
SDNode *C;
SDValue M0 = CurDAG->getTargetConstant(0x18, dl, MVT::i32);
SDValue M1 = CurDAG->getTargetConstant(0x03, dl, MVT::i32);
if (HST->useCompound()) {
C = CurDAG->getMachineNode(Hexagon::S4_andi_asl_ri, dl, MVT::i32,
M0, N->getOperand(2), M1);
} else {
SDNode *T = CurDAG->getMachineNode(Hexagon::S2_asl_i_r, dl, MVT::i32,
N->getOperand(2), M1);
C = CurDAG->getMachineNode(Hexagon::A2_andir, dl, MVT::i32,
SDValue(T, 0), M0);
}
SDNode *S = CurDAG->getMachineNode(Hexagon::S2_lsr_r_p, dl, MVT::i64,
SDValue(R, 0), SDValue(C, 0));
SDValue E = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo, dl, ResTy,
SDValue(S, 0));
ReplaceNode(N, E.getNode());
} else {
assert(VecLen == 64);
SDNode *Pu = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::v8i1,
N->getOperand(2));
SDNode *VA = CurDAG->getMachineNode(Hexagon::S2_valignrb, dl, ResTy,
N->getOperand(0), N->getOperand(1),
SDValue(Pu,0));
ReplaceNode(N, VA);
}
}
void HexagonDAGToDAGISel::SelectVAlignAddr(SDNode *N) {
const SDLoc &dl(N);
SDValue A = N->getOperand(1);
int Mask = -cast<ConstantSDNode>(A.getNode())->getSExtValue();
assert(isPowerOf2_32(-Mask));
SDValue M = CurDAG->getTargetConstant(Mask, dl, MVT::i32);
SDNode *AA = CurDAG->getMachineNode(Hexagon::A2_andir, dl, MVT::i32,
N->getOperand(0), M);
ReplaceNode(N, AA);
}
// Handle these nodes here to avoid having to write patterns for all
// combinations of input/output types. In all cases, the resulting
// instruction is the same.
void HexagonDAGToDAGISel::SelectTypecast(SDNode *N) {
SDValue Op = N->getOperand(0);
MVT OpTy = Op.getValueType().getSimpleVT();
SDNode *T = CurDAG->MorphNodeTo(N, N->getOpcode(),
CurDAG->getVTList(OpTy), {Op});
ReplaceNode(T, Op.getNode());
}
void HexagonDAGToDAGISel::SelectP2D(SDNode *N) {
MVT ResTy = N->getValueType(0).getSimpleVT();
SDNode *T = CurDAG->getMachineNode(Hexagon::C2_mask, SDLoc(N), ResTy,
N->getOperand(0));
ReplaceNode(N, T);
}
void HexagonDAGToDAGISel::SelectD2P(SDNode *N) {
const SDLoc &dl(N);
MVT ResTy = N->getValueType(0).getSimpleVT();
SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32);
SDNode *T = CurDAG->getMachineNode(Hexagon::A4_vcmpbgtui, dl, ResTy,
N->getOperand(0), Zero);
ReplaceNode(N, T);
}
void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) {
const SDLoc &dl(N);
MVT ResTy = N->getValueType(0).getSimpleVT();
// The argument to V2Q should be a single vector.
MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy;
assert(HST->getVectorLength() * 8 == OpTy.getSizeInBits());
SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);
SDNode *T = CurDAG->getMachineNode(Hexagon::V6_vandvrt, dl, ResTy,
N->getOperand(0), SDValue(R,0));
ReplaceNode(N, T);
}
void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) {
const SDLoc &dl(N);
MVT ResTy = N->getValueType(0).getSimpleVT();
// The result of V2Q should be a single vector.
assert(HST->getVectorLength() * 8 == ResTy.getSizeInBits());
SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);
SDNode *T = CurDAG->getMachineNode(Hexagon::V6_vandqrt, dl, ResTy,
N->getOperand(0), SDValue(R,0));
ReplaceNode(N, T);
}
void HexagonDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode())
return N->setNodeId(-1); // Already selected.
switch (N->getOpcode()) {
case ISD::Constant: return SelectConstant(N);
case ISD::ConstantFP: return SelectConstantFP(N);
case ISD::FrameIndex: return SelectFrameIndex(N);
case ISD::SHL: return SelectSHL(N);
case ISD::LOAD: return SelectLoad(N);
case ISD::STORE: return SelectStore(N);
case ISD::INTRINSIC_W_CHAIN: return SelectIntrinsicWChain(N);
case ISD::INTRINSIC_WO_CHAIN: return SelectIntrinsicWOChain(N);
case HexagonISD::ADDC:
case HexagonISD::SUBC: return SelectAddSubCarry(N);
case HexagonISD::VALIGN: return SelectVAlign(N);
case HexagonISD::VALIGNADDR: return SelectVAlignAddr(N);
case HexagonISD::TYPECAST: return SelectTypecast(N);
case HexagonISD::P2D: return SelectP2D(N);
case HexagonISD::D2P: return SelectD2P(N);
case HexagonISD::Q2V: return SelectQ2V(N);
case HexagonISD::V2Q: return SelectV2Q(N);
}
if (HST->useHVXOps()) {
switch (N->getOpcode()) {
case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N);
case HexagonISD::VROR: return SelectHvxRor(N);
}
}
SelectCode(N);
}
bool HexagonDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
std::vector<SDValue> &OutOps) {
SDValue Inp = Op, Res;
switch (ConstraintID) {
default:
return true;
case InlineAsm::Constraint_o: // Offsetable.
case InlineAsm::Constraint_v: // Not offsetable.
case InlineAsm::Constraint_m: // Memory.
if (SelectAddrFI(Inp, Res))
OutOps.push_back(Res);
else
OutOps.push_back(Inp);
break;
}
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
return false;
}
static bool isMemOPCandidate(SDNode *I, SDNode *U) {
// I is an operand of U. Check if U is an arithmetic (binary) operation
// usable in a memop, where the other operand is a loaded value, and the
// result of U is stored in the same location.
if (!U->hasOneUse())
return false;
unsigned Opc = U->getOpcode();
switch (Opc) {
case ISD::ADD:
case ISD::SUB:
case ISD::AND:
case ISD::OR:
break;
default:
return false;
}
SDValue S0 = U->getOperand(0);
SDValue S1 = U->getOperand(1);
SDValue SY = (S0.getNode() == I) ? S1 : S0;
SDNode *UUse = *U->use_begin();
if (UUse->getNumValues() != 1)
return false;
// Check if one of the inputs to U is a load instruction and the output
// is used by a store instruction. If so and they also have the same
// base pointer, then don't preoprocess this node sequence as it
// can be matched to a memop.
SDNode *SYNode = SY.getNode();
if (UUse->getOpcode() == ISD::STORE && SYNode->getOpcode() == ISD::LOAD) {
SDValue LDBasePtr = cast<MemSDNode>(SYNode)->getBasePtr();
SDValue STBasePtr = cast<MemSDNode>(UUse)->getBasePtr();
if (LDBasePtr == STBasePtr)
return true;
}
return false;
}
// Transform: (or (select c x 0) z) -> (select c (or x z) z)
// (or (select c 0 y) z) -> (select c z (or y z))
void HexagonDAGToDAGISel::ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes) {
SelectionDAG &DAG = *CurDAG;
for (auto I : Nodes) {
if (I->getOpcode() != ISD::OR)
continue;
auto IsZero = [] (const SDValue &V) -> bool {
if (ConstantSDNode *SC = dyn_cast<ConstantSDNode>(V.getNode()))
return SC->isZero();
return false;
};
auto IsSelect0 = [IsZero] (const SDValue &Op) -> bool {
if (Op.getOpcode() != ISD::SELECT)
return false;
return IsZero(Op.getOperand(1)) || IsZero(Op.getOperand(2));
};