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HexagonPatterns.td
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//===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Table of contents:
// (0) Definitions
// (1) Immediates
// (2) Type casts
// (3) Extend/truncate
// (4) Logical
// (5) Compare
// (6) Select
// (7) Insert/extract
// (8) Shift/permute
// (9) Arithmetic/bitwise
// (10) Bit
// (11) PIC
// (12) Load
// (13) Store
// (14) Memop
// (15) Call
// (16) Branch
// (17) Misc
// Guidelines (in no particular order):
// 1. Avoid relying on pattern ordering to give preference to one pattern
// over another, prefer using AddedComplexity instead. The reason for
// this is to avoid unintended conseqeuences (caused by altering the
// order) when making changes. The current order of patterns in this
// file obviously does play some role, but none of the ordering was
// deliberately chosen (other than to create a logical structure of
// this file). When making changes, adding AddedComplexity to existing
// patterns may be needed.
// 2. Maintain the logical structure of the file, try to put new patterns
// in designated sections.
// 3. Do not use A2_combinew instruction directly, use Combinew fragment
// instead. It uses REG_SEQUENCE, which is more amenable to optimizations.
// 4. Most selection macros are based on PatFrags. For DAGs that involve
// SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags
// whenever possible (see the Definitions section). When adding new
// macro, try to make is general to enable reuse across sections.
// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
// that the nested operation has only one use. Having it separated in case
// of multiple uses avoids duplication of (processor) work.
// 6. The v4 vector instructions (64-bit) are treated as core instructions,
// for example, A2_vaddh is in the "arithmetic" section with A2_add.
// 7. When adding a pattern for an instruction with a constant-extendable
// operand, allow all possible kinds of inputs for the immediate value
// (see AnyImm/anyimm and their variants in the Definitions section).
// --(0) Definitions -----------------------------------------------------
//
// This complex pattern exists only to create a machine instruction operand
// of type "frame index". There doesn't seem to be a way to do that directly
// in the patterns.
def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
// These complex patterns are not strictly necessary, since global address
// folding will happen during DAG combining. For distinguishing between GA
// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used.
def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>;
def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>;
// Global address or a constant being a multiple of 2^n.
def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>;
def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>;
def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>;
def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>;
// Type helper frags.
def V2I1: PatLeaf<(v2i1 PredRegs:$R)>;
def V4I1: PatLeaf<(v4i1 PredRegs:$R)>;
def V8I1: PatLeaf<(v8i1 PredRegs:$R)>;
def V4I8: PatLeaf<(v4i8 IntRegs:$R)>;
def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>;
def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>;
def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
def HQ8: PatLeaf<(VecQ8 HvxQR:$R)>;
def HQ16: PatLeaf<(VecQ16 HvxQR:$R)>;
def HQ32: PatLeaf<(VecQ32 HvxQR:$R)>;
def HVI8: PatLeaf<(VecI8 HvxVR:$R)>;
def HVI16: PatLeaf<(VecI16 HvxVR:$R)>;
def HVI32: PatLeaf<(VecI32 HvxVR:$R)>;
def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>;
def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>;
def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>;
def SDTVecLeaf:
SDTypeProfile<1, 0, [SDTCisVec<0>]>;
def SDTVecVecIntOp:
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>,
SDTCisVT<3,i32>]>;
def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>;
def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>;
def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>;
def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>;
def ptrue: PatFrag<(ops), (HexagonPTRUE)>;
def pfalse: PatFrag<(ops), (HexagonPFALSE)>;
def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>;
def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru),
(HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>;
def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>;
// Pattern fragments to extract the low and high subregisters from a
// 64-bit value.
def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
return isOrEquivalentToAdd(N);
}]>;
def IsPow2_32: PatLeaf<(i32 imm), [{
uint32_t V = N->getZExtValue();
return isPowerOf2_32(V);
}]>;
def IsPow2_64: PatLeaf<(i64 imm), [{
uint64_t V = N->getZExtValue();
return isPowerOf2_64(V);
}]>;
def IsNPow2_32: PatLeaf<(i32 imm), [{
uint32_t NV = ~N->getZExtValue();
return isPowerOf2_32(NV);
}]>;
def IsPow2_64L: PatLeaf<(i64 imm), [{
uint64_t V = N->getZExtValue();
return isPowerOf2_64(V) && Log2_64(V) < 32;
}]>;
def IsPow2_64H: PatLeaf<(i64 imm), [{
uint64_t V = N->getZExtValue();
return isPowerOf2_64(V) && Log2_64(V) >= 32;
}]>;
def IsNPow2_64L: PatLeaf<(i64 imm), [{
uint64_t NV = ~N->getZExtValue();
return isPowerOf2_64(NV) && Log2_64(NV) < 32;
}]>;
def IsNPow2_64H: PatLeaf<(i64 imm), [{
uint64_t NV = ~N->getZExtValue();
return isPowerOf2_64(NV) && Log2_64(NV) >= 32;
}]>;
class IsULE<int Width, int Arg>: PatLeaf<(i32 imm),
"uint64_t V = N->getZExtValue();" #
"return isUInt<" # Width # ">(V) && V <= " # Arg # ";"
>;
class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm),
"uint64_t V = N->getZExtValue();" #
"return isUInt<" # Width # ">(V) && V > " # Arg # ";"
>;
def SDEC1: SDNodeXForm<imm, [{
int32_t V = N->getSExtValue();
return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
}]>;
def UDEC1: SDNodeXForm<imm, [{
uint32_t V = N->getZExtValue();
assert(V >= 1);
return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
}]>;
def UDEC32: SDNodeXForm<imm, [{
uint32_t V = N->getZExtValue();
assert(V >= 32);
return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32);
}]>;
class Subi<int From>: SDNodeXForm<imm,
"int32_t V = " # From # " - N->getSExtValue();" #
"return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);"
>;
def Log2_32: SDNodeXForm<imm, [{
uint32_t V = N->getZExtValue();
return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32);
}]>;
def Log2_64: SDNodeXForm<imm, [{
uint64_t V = N->getZExtValue();
return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32);
}]>;
def LogN2_32: SDNodeXForm<imm, [{
uint32_t NV = ~N->getZExtValue();
return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
}]>;
def LogN2_64: SDNodeXForm<imm, [{
uint64_t NV = ~N->getZExtValue();
return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32);
}]>;
def NegImm8: SDNodeXForm<imm, [{
int8_t NV = -N->getSExtValue();
return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
}]>;
def NegImm16: SDNodeXForm<imm, [{
int16_t NV = -N->getSExtValue();
return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
}]>;
def NegImm32: SDNodeXForm<imm, [{
int32_t NV = -N->getSExtValue();
return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
}]>;
def SplatB: SDNodeXForm<imm, [{
uint32_t V = N->getZExtValue();
assert(isUInt<8>(V) || V >> 8 == 0xFFFFFF);
V &= 0xFF;
uint32_t S = V << 24 | V << 16 | V << 8 | V;
return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32);
}]>;
def SplatH: SDNodeXForm<imm, [{
uint32_t V = N->getZExtValue();
assert(isUInt<16>(V) || V >> 16 == 0xFFFF);
V &= 0xFFFF;
return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32);
}]>;
// Helpers for type promotions/contractions.
def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>;
def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
def ToAext64: OutPatFrag<(ops node:$Rs),
(REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>;
def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
(REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
def anyimm: PatLeaf<(i32 AnyImm:$Imm)>;
def anyint: PatLeaf<(i32 AnyInt:$Imm)>;
// Global address or an aligned constant.
def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>;
def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>;
def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>;
def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>;
def f32ImmPred : PatLeaf<(f32 fpimm:$F)>;
def f64ImmPred : PatLeaf<(f64 fpimm:$F)>;
// This complex pattern is really only to detect various forms of
// sign-extension i32->i64. The selected value will be of type i64
// whose low word is the value being extended. The high word is
// unspecified.
def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>;
def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>;
def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>;
def Sext64: PatLeaf<(i64 Usxtw:$Rs)>;
def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>;
def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>;
def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off),
(PS_fi (i32 AddrFI:$Rs), imm:$off)>;
// Converters from unary/binary SDNode to PatFrag.
class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>;
class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>;
class Not2<PatFrag P>
: PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>;
class VNot2<PatFrag P, PatFrag Not>
: PatFrag<(ops node:$A, node:$B), (P node:$A, (Not node:$B))>;
// If there is a constant operand that feeds the and/or instruction,
// do not generate the compound instructions.
// It is not always profitable, as some times we end up with a transfer.
// Check the below example.
// ra = #65820; rb = lsr(rb, #8); rc ^= and (rb, ra)
// Instead this is preferable.
// ra = and (#65820, lsr(ra, #8)); rb = xor(rb, ra)
class Su_ni1<PatFrag Op>
: PatFrag<Op.Operands, !head(Op.Fragments), [{
if (hasOneUse(N)){
// Check if Op1 is an immediate operand.
SDValue Op1 = N->getOperand(1);
return !isa<ConstantSDNode>(Op1);
}
return false;}],
Op.OperandTransform>;
class Su<PatFrag Op>
: PatFrag<Op.Operands, !head(Op.Fragments), [{ return hasOneUse(N); }],
Op.OperandTransform>;
// Main selection macros.
class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred>
: Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;
class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType,
PatFrag RegPred, PatFrag ImmPred>
: Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)),
(MI RegPred:$Rs, imm:$I)>;
class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType,
PatFrag RsPred, PatFrag RtPred = RsPred>
: Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
(MI RsPred:$Rs, RtPred:$Rt)>;
class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
PatFrag RegPred, PatFrag ImmPred>
: Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)),
(MI RegPred:$Rx, RegPred:$Rs, imm:$I)>;
class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
PatFrag RxPred, PatFrag RsPred, PatFrag RtPred>
: Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
(MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val,
InstHexagon InstA, InstHexagon InstB> {
def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B),
(InstA Val:$A, Val:$B)>;
def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A),
(InstB Val:$A, Val:$B)>;
}
multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS,
SDPatternOperator Sel, SDPatternOperator CmpOp,
ValueType CmpType, PatFrag CmpPred> {
def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)),
CmpPred:$Vt, CmpPred:$Vs),
(PickT CmpPred:$Vs, CmpPred:$Vt)>;
def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)),
CmpPred:$Vs, CmpPred:$Vt),
(PickS CmpPred:$Vs, CmpPred:$Vt)>;
}
// Bitcasts between same-size vector types are no-ops, except for the
// actual type change.
multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> {
def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>;
def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>;
}
// Frags for commonly used SDNodes.
def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>;
def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>;
def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>;
def Smin: pf2<smin>; def Smax: pf2<smax>;
def Umin: pf2<umin>; def Umax: pf2<umax>;
def Rol: pf2<rotl>;
// --(1) Immediate -------------------------------------------------------
//
def Imm64Lo: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(int32_t (N->getSExtValue()),
SDLoc(N), MVT::i32);
}]>;
def Imm64Hi: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32),
SDLoc(N), MVT::i32);
}]>;
def SDTHexagonCONST32
: SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>;
def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>;
def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
def TruncI64ToI32: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
}]>;
def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>;
def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>;
def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>;
def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>;
def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>;
def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>;
def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>;
def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>;
def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>;
// The HVX load patterns also match CP directly. Make sure that if
// the selection of this opcode changes, it's updated in all places.
def: Pat<(i1 0), (PS_false)>;
def: Pat<(i1 1), (PS_true)>;
def: Pat<(i64 imm:$v), (CONST64 imm:$v)>,
Requires<[UseSmallData,NotOptTinyCore]>;
def: Pat<(i64 imm:$v),
(Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>;
def ftoi : SDNodeXForm<fpimm, [{
APInt I = N->getValueAPF().bitcastToAPInt();
return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N),
MVT::getIntegerVT(I.getBitWidth()));
}]>;
def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>;
def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>;
def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>;
// --(2) Type cast -------------------------------------------------------
//
def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>;
def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>;
def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>;
def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>;
def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>;
def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>;
def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>;
def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>;
def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>;
def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>;
def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>;
def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>;
def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>;
def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>;
def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>;
def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>;
def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>;
def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>;
// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>;
def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>;
def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>;
def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>;
// Bit convert 32- and 64-bit types.
// All of these are bitcastable to one another: i32, v2i16, v4i8.
defm: NopCast_pat<i32, v2i16, IntRegs>;
defm: NopCast_pat<i32, v4i8, IntRegs>;
defm: NopCast_pat<v2i16, v4i8, IntRegs>;
// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8.
defm: NopCast_pat<i64, v2i32, DoubleRegs>;
defm: NopCast_pat<i64, v4i16, DoubleRegs>;
defm: NopCast_pat<i64, v8i8, DoubleRegs>;
defm: NopCast_pat<v2i32, v4i16, DoubleRegs>;
defm: NopCast_pat<v2i32, v8i8, DoubleRegs>;
defm: NopCast_pat<v4i16, v8i8, DoubleRegs>;
// --(3) Extend/truncate -------------------------------------------------
//
def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>;
def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>;
def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>;
def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>;
def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>;
def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>;
def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>;
def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>;
def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>;
def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>;
def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>;
let AddedComplexity = 20 in {
def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>;
def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>;
}
// Extensions from i1 or vectors of i1.
def: Pat<(i32 (azext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>;
def: Pat<(i64 (azext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>;
def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>;
def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0),
(C2_muxii PredRegs:$Pu, -1, 0))>;
def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>;
def: Pat<(v2i32 (sext V2I1:$Pu)), (C2_mask V2I1:$Pu)>;
def: Pat<(v4i8 (sext V4I1:$Pu)), (S2_vtrunehb (C2_mask V4I1:$Pu))>;
def: Pat<(v4i16 (sext V4I1:$Pu)), (C2_mask V4I1:$Pu)>;
def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>;
def Vsplatpi: OutPatFrag<(ops node:$V),
(Combinew (A2_tfrsi $V), (A2_tfrsi $V))>;
def: Pat<(v2i16 (azext V2I1:$Pu)),
(A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>;
def: Pat<(v2i32 (azext V2I1:$Pu)),
(A2_andp (C2_mask V2I1:$Pu), (A2_combineii (i32 1), (i32 1)))>;
def: Pat<(v4i8 (azext V4I1:$Pu)),
(A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>;
def: Pat<(v4i16 (azext V4I1:$Pu)),
(A2_andp (C2_mask V4I1:$Pu), (Vsplatpi (i32 0x00010001)))>;
def: Pat<(v8i8 (azext V8I1:$Pu)),
(A2_andp (C2_mask V8I1:$Pu), (Vsplatpi (i32 0x01010101)))>;
def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>;
def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>;
def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>;
def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
(Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
(Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
// Truncate: from vector B copy all 'E'ven 'B'yte elements:
// A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6];
def: Pat<(v4i8 (trunc V4I16:$Rs)),
(S2_vtrunehb V4I16:$Rs)>;
// Truncate: from vector B copy all 'O'dd 'B'yte elements:
// A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7];
// S2_vtrunohb
// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements:
// A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2];
// S2_vtruneh
def: Pat<(v2i16 (trunc V2I32:$Rs)),
(A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
// --(4) Logical ---------------------------------------------------------
//
def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>;
def: Pat<(pnot V2I1:$Ps), (C2_not V2I1:$Ps)>;
def: Pat<(pnot V4I1:$Ps), (C2_not V4I1:$Ps)>;
def: Pat<(pnot V8I1:$Ps), (C2_not V8I1:$Ps)>;
def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>;
def: OpR_RR_pat<C2_and, And, i1, I1>;
def: OpR_RR_pat<C2_or, Or, i1, I1>;
def: OpR_RR_pat<C2_xor, Xor, i1, I1>;
def: OpR_RR_pat<C2_andn, Not2<And>, i1, I1>;
def: OpR_RR_pat<C2_orn, Not2<Or>, i1, I1>;
def: AccRRR_pat<C4_and_and, And, Su<And>, I1, I1, I1>;
def: AccRRR_pat<C4_and_or, And, Su< Or>, I1, I1, I1>;
def: AccRRR_pat<C4_or_and, Or, Su<And>, I1, I1, I1>;
def: AccRRR_pat<C4_or_or, Or, Su< Or>, I1, I1, I1>;
def: AccRRR_pat<C4_and_andn, And, Su<Not2<And>>, I1, I1, I1>;
def: AccRRR_pat<C4_and_orn, And, Su<Not2< Or>>, I1, I1, I1>;
def: AccRRR_pat<C4_or_andn, Or, Su<Not2<And>>, I1, I1, I1>;
def: AccRRR_pat<C4_or_orn, Or, Su<Not2< Or>>, I1, I1, I1>;
multiclass BoolvOpR_RR_pat<InstHexagon MI, PatFrag VOp> {
def: OpR_RR_pat<MI, VOp, v2i1, V2I1>;
def: OpR_RR_pat<MI, VOp, v4i1, V4I1>;
def: OpR_RR_pat<MI, VOp, v8i1, V8I1>;
}
multiclass BoolvAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag VOp> {
def: AccRRR_pat<MI, AccOp, VOp, V2I1, V2I1, V2I1>;
def: AccRRR_pat<MI, AccOp, VOp, V4I1, V4I1, V4I1>;
def: AccRRR_pat<MI, AccOp, VOp, V8I1, V8I1, V8I1>;
}
defm: BoolvOpR_RR_pat<C2_and, And>;
defm: BoolvOpR_RR_pat<C2_or, Or>;
defm: BoolvOpR_RR_pat<C2_xor, Xor>;
defm: BoolvOpR_RR_pat<C2_andn, VNot2<And, pnot>>;
defm: BoolvOpR_RR_pat<C2_orn, VNot2< Or, pnot>>;
// op(Ps, op(Pt, Pu))
defm: BoolvAccRRR_pat<C4_and_and, And, Su<And>>;
defm: BoolvAccRRR_pat<C4_and_or, And, Su<Or>>;
defm: BoolvAccRRR_pat<C4_or_and, Or, Su<And>>;
defm: BoolvAccRRR_pat<C4_or_or, Or, Su<Or>>;
// op(Ps, op(Pt, !Pu))
defm: BoolvAccRRR_pat<C4_and_andn, And, Su<VNot2<And, pnot>>>;
defm: BoolvAccRRR_pat<C4_and_orn, And, Su<VNot2< Or, pnot>>>;
defm: BoolvAccRRR_pat<C4_or_andn, Or, Su<VNot2<And, pnot>>>;
defm: BoolvAccRRR_pat<C4_or_orn, Or, Su<VNot2< Or, pnot>>>;
// --(5) Compare ---------------------------------------------------------
//
// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)".
// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt).
def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>;
def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>;
def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>;
def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)),
(C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>;
def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)),
(C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>;
def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)),
(C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>;
def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)),
(C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>;
// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
// that reverse the order of the operands.
class RevCmp<PatFrag F>
: PatFrag<(ops node:$rhs, node:$lhs), !head(F.Fragments), F.PredicateCode,
F.OperandTransform>;
def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>;
def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>;
def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>;
def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>;
def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>;
def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>;
def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>;
def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>;
def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>;
def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>;
def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>;
def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>;
def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>;
def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>;
def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>;
def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>;
def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>;
def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>;
def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>;
def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>;
def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>;
def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>;
def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>;
def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>;
def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>;
def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>;
def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>;
def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>;
def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>;
def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>;
def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>;
def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>;
def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>;
def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>;
def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>;
def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>;
def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>;
def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>;
def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>;
def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>;
def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>;
def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>;
def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>;
def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>;
def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>;
def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>;
def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>;
def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>;
def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>;
def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>;
def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>;
def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>;
def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>;
def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>;
def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>;
def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>;
def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>;
def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>;
def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>;
def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>;
def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>;
def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>;
// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds.
def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)),
(C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>;
def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)),
(C2_not (C2_cmpgti I32:$Rs, imm:$u5))>;
def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)),
(C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>;
class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType,
PatFrag RsPred, PatFrag RtPred = RsPred>
: Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
(Output RsPred:$Rs, RtPred:$Rt)>;
class Outn<InstHexagon MI>
: OutPatFrag<(ops node:$Rs, node:$Rt),
(C2_not (MI $Rs, $Rt))>;
def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>;
def: OpmR_RR_pat<Outn<C2_cmpgt>, setle, i1, I32>;
def: OpmR_RR_pat<Outn<C2_cmpgtu>, setule, i1, I32>;
def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>;
def: OpmR_RR_pat<Outn<C2_cmpgtu>, RevCmp<setuge>, i1, I32>;
def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>;
def: OpmR_RR_pat<Outn<C2_cmpgtp>, setle, i1, I64>;
def: OpmR_RR_pat<Outn<C2_cmpgtup>, setule, i1, I64>;
def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>;
def: OpmR_RR_pat<Outn<C2_cmpgtup>, RevCmp<setuge>, i1, I64>;
def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>;
def: OpmR_RR_pat<Outn<A4_vcmpbgt>, setle, v8i1, V8I8>;
def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, setule, v8i1, V8I8>;
def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>;
def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, RevCmp<setuge>, v8i1, V8I8>;
def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>;
def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>;
def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>;
def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>;
def: OpmR_RR_pat<Outn<A2_vcmphgtu>, RevCmp<setuge>, v4i1, V4I16>;
def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>;
def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>;
def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>;
def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>;
def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, RevCmp<setuge>, v2i1, V2I32>;
let AddedComplexity = 100 in {
def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)),
(A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)),
(C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)),
(A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)),
(C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
}
// PatFrag for AsserZext which takes the original type as a parameter.
def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>;
def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
PatLeaf ImmPred, int Mask> {
def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
(MI I32:$Rs, imm:$I)>;
def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
(MI I32:$Rs, imm:$I)>;
}
multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
PatLeaf ImmPred, int Mask> {
def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
(C2_not (MI I32:$Rs, imm:$I))>;
def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
(C2_not (MI I32:$Rs, imm:$I))>;
}
multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
PatLeaf ImmPred, int Mask> {
def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
(C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
(C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
}
let AddedComplexity = 200 in {
defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>;
defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>;
defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>;
defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>;
defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
}
def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))),
(A4_rcmpeq I32:$Rs, I32:$Rt)>;
def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))),
(A4_rcmpneq I32:$Rs, I32:$Rt)>;
def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))),
(A4_rcmpeqi I32:$Rs, imm:$s8)>;
def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))),
(A4_rcmpneqi I32:$Rs, imm:$s8)>;
def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>;
def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>;
def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, (C2_not I1:$Pt))>;
def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
// Floating-point comparisons with checks for ordered/unordered status.
class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
: OutPatFrag<(ops node:$Rs, node:$Rt),
(MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>;
class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>;
class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>;
class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>;
def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>;
def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>;
def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>;
def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>;
def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>;
def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>;
def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>;
def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>;
def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>;
def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>;
def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>;
def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>;
def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>;
def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>;
def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>;
def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>;
def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>;
def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>;
// --(6) Select ----------------------------------------------------------
//
def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt),
(C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>;
def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs),
(C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8),
(C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8),
(C2_muxii I1:$Pu, imm:$s8, imm:$S8)>;
def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt),
(C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>;
def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8),
(C2_muxii I1:$Pu, imm:$s8, imm:$S8)>;
def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs),
(C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8),
(C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
// Map from a 64-bit select to an emulated 64-bit mux.
// Hexagon does not support 64-bit MUXes; so emulate with combines.
def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt),
(Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
(C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I),
(C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>;
def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt),
(C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>;
def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt),
(C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>;
def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt),
(Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
(C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt),
(C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>;
def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt),
(C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs),
(C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>;
def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I),
(C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>;
def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt),
(C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>;
def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt),
(C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>;
def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt),
(C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>;
def: Pat<(vselect (pnot V8I1:$Pu), V8I8:$Rs, V8I8:$Rt),
(C2_vmux V8I1:$Pu, V8I8:$Rt, V8I8:$Rs)>;
def: Pat<(vselect (pnot V4I1:$Pu), V4I16:$Rs, V4I16:$Rt),
(C2_vmux V4I1:$Pu, V4I16:$Rt, V4I16:$Rs)>;
def: Pat<(vselect (pnot V2I1:$Pu), V2I32:$Rs, V2I32:$Rt),
(C2_vmux V2I1:$Pu, V2I32:$Rt, V2I32:$Rs)>;
// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw).
def: Pat<(select I1:$Pu, I1:$Pv, I1:$Pw),
(C2_or (C2_and I1:$Pu, I1:$Pv),
(C2_andn I1:$Pw, I1:$Pu))>;
def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{
return isPositiveHalfWord(N);
}]>;
multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA,
InstHexagon InstB> {
def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
IsPosHalf:$Rs, IsPosHalf:$Rt), i16),
(InstA IntRegs:$Rs, IntRegs:$Rt)>;
def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
IsPosHalf:$Rt, IsPosHalf:$Rs), i16),
(InstB IntRegs:$Rs, IntRegs:$Rt)>;
}
let AddedComplexity = 200 in {
defm: SelMinMax16_pats<setge, A2_max, A2_min>;
defm: SelMinMax16_pats<setgt, A2_max, A2_min>;
defm: SelMinMax16_pats<setle, A2_min, A2_max>;
defm: SelMinMax16_pats<setlt, A2_min, A2_max>;
defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>;
defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>;
defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>;
defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>;
}
def: OpR_RR_pat<A2_min, Smin, i32, I32, I32>;
def: OpR_RR_pat<A2_max, Smax, i32, I32, I32>;
def: OpR_RR_pat<A2_minu, Umin, i32, I32, I32>;
def: OpR_RR_pat<A2_maxu, Umax, i32, I32, I32>;
def: OpR_RR_pat<A2_minp, Smin, i64, I64, I64>;
def: OpR_RR_pat<A2_maxp, Smax, i64, I64, I64>;
def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>;
def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>;
let AddedComplexity = 100 in {
defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>;
defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setoge, i1, F32>;
defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setolt, i1, F32>;
defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>;
}
let AddedComplexity = 100, Predicates = [HasV67] in {
defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>;
defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>;
defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>;
defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>;
}
def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>;
def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>;
def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>;
def: OpR_RR_pat<A2_vmaxub, Umax, v8i8, V8I8>;
def: OpR_RR_pat<A2_vminh, Smin, v4i16, V4I16>;
def: OpR_RR_pat<A2_vmaxh, Smax, v4i16, V4I16>;
def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>;
def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>;
def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>;
def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>;
def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>;
def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>;
// --(7) Insert/extract --------------------------------------------------
//
def SDTHexagonINSERT:
SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>;
let AddedComplexity = 10 in {
def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2),
(S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>;
def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2),
(S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>;
}
def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off),
(S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>;
def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off),
(S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>;