diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp index b06e0735a71..0719417f87d 100644 --- a/cores/esp32/HardwareSerial.cpp +++ b/cores/esp32/HardwareSerial.cpp @@ -30,7 +30,7 @@ HardwareSerial Serial2(2); HardwareSerial::HardwareSerial(int uart_nr) : _uart_nr(uart_nr), _uart(NULL) {} -void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, int8_t txPin, bool invert, unsigned long timeout_ms) +void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, int8_t txPin, bool invert, unsigned long timeout_ms, uint8_t rxfifo_full_thrhd) { if(0 > _uart_nr || _uart_nr > 2) { log_e("Serial number is invalid, please use 0, 1 or 2"); @@ -52,7 +52,7 @@ void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, in txPin = TX2; } - _uart = uartBegin(_uart_nr, baud ? baud : 9600, config, rxPin, txPin, 256, invert); + _uart = uartBegin(_uart_nr, baud ? baud : 9600, config, rxPin, txPin, 256, invert, rxfifo_full_thrhd); _tx_pin = txPin; _rx_pin = rxPin; @@ -68,7 +68,7 @@ void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, in if(detectedBaudRate) { delay(100); // Give some time... - _uart = uartBegin(_uart_nr, detectedBaudRate, config, rxPin, txPin, 256, invert); + _uart = uartBegin(_uart_nr, detectedBaudRate, config, rxPin, txPin, 256, invert, rxfifo_full_thrhd); } else { log_e("Could not detect baudrate. Serial data at the port must be present within the timeout for detection to be possible"); _uart = NULL; diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h index e776e939d0b..7a36653a0f0 100644 --- a/cores/esp32/HardwareSerial.h +++ b/cores/esp32/HardwareSerial.h @@ -55,7 +55,7 @@ class HardwareSerial: public Stream public: HardwareSerial(int uart_nr); - void begin(unsigned long baud, uint32_t config=SERIAL_8N1, int8_t rxPin=-1, int8_t txPin=-1, bool invert=false, unsigned long timeout_ms = 20000UL); + void begin(unsigned long baud, uint32_t config=SERIAL_8N1, int8_t rxPin=-1, int8_t txPin=-1, bool invert=false, unsigned long timeout_ms = 20000UL, uint8_t rxfifo_full_thrhd = 112); void end(); void updateBaudRate(unsigned long baud); int available(void); diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c index 7ee23b95c95..244beaa3f7d 100644 --- a/cores/esp32/esp32-hal-uart.c +++ b/cores/esp32/esp32-hal-uart.c @@ -96,10 +96,10 @@ static void IRAM_ATTR _uart_isr(void *arg) } } -void uartEnableInterrupt(uart_t* uart) +static void uartEnableInterrupt(uart_t* uart, uint8_t rxfifo_full_thrhd) { UART_MUTEX_LOCK(); - uart->dev->conf1.rxfifo_full_thrhd = 112; + uart->dev->conf1.rxfifo_full_thrhd = rxfifo_full_thrhd; uart->dev->conf1.rx_tout_thrhd = 2; uart->dev->conf1.rx_tout_en = 1; uart->dev->int_ena.rxfifo_full = 1; @@ -111,7 +111,7 @@ void uartEnableInterrupt(uart_t* uart) UART_MUTEX_UNLOCK(); } -void uartDisableInterrupt(uart_t* uart) +static void uartDisableInterrupt(uart_t* uart) { UART_MUTEX_LOCK(); uart->dev->conf1.val = 0; @@ -124,7 +124,7 @@ void uartDisableInterrupt(uart_t* uart) UART_MUTEX_UNLOCK(); } -void uartDetachRx(uart_t* uart, uint8_t rxPin) +static void uartDetachRx(uart_t* uart, uint8_t rxPin) { if(uart == NULL) { return; @@ -133,7 +133,7 @@ void uartDetachRx(uart_t* uart, uint8_t rxPin) uartDisableInterrupt(uart); } -void uartDetachTx(uart_t* uart, uint8_t txPin) +static void uartDetachTx(uart_t* uart, uint8_t txPin) { if(uart == NULL) { return; @@ -141,17 +141,17 @@ void uartDetachTx(uart_t* uart, uint8_t txPin) pinMatrixOutDetach(txPin, false, false); } -void uartAttachRx(uart_t* uart, uint8_t rxPin, bool inverted) +static void uartAttachRx(uart_t* uart, uint8_t rxPin, bool inverted, uint8_t rxfifo_full_thrhd) { if(uart == NULL || rxPin > 39) { return; } pinMode(rxPin, INPUT); + uartEnableInterrupt(uart, rxfifo_full_thrhd); pinMatrixInAttach(rxPin, UART_RXD_IDX(uart->num), inverted); - uartEnableInterrupt(uart); } -void uartAttachTx(uart_t* uart, uint8_t txPin, bool inverted) +static void uartAttachTx(uart_t* uart, uint8_t txPin, bool inverted) { if(uart == NULL || txPin > 39) { return; @@ -160,7 +160,7 @@ void uartAttachTx(uart_t* uart, uint8_t txPin, bool inverted) pinMatrixOutAttach(txPin, UART_TXD_IDX(uart->num), inverted, false); } -uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint16_t queueLen, bool inverted) +uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint16_t queueLen, bool inverted, uint8_t rxfifo_full_thrhd) { if(uart_nr > 2) { return NULL; @@ -216,7 +216,7 @@ uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rx UART_MUTEX_UNLOCK(); if(rxPin != -1) { - uartAttachRx(uart, rxPin, inverted); + uartAttachRx(uart, rxPin, inverted, rxfifo_full_thrhd); } if(txPin != -1) { @@ -282,7 +282,11 @@ uint32_t uartAvailable(uart_t* uart) if(uart == NULL || uart->queue == NULL) { return 0; } +#ifdef UART_READ_RX_FIFO return (uxQueueMessagesWaiting(uart->queue) + uart->dev->status.rxfifo_cnt) ; +#else + return uxQueueMessagesWaiting(uart->queue); +#endif } uint32_t uartAvailableForWrite(uart_t* uart) @@ -293,6 +297,7 @@ uint32_t uartAvailableForWrite(uart_t* uart) return 0x7f - uart->dev->status.txfifo_cnt; } +#ifdef UART_READ_RX_FIFO void uartRxFifoToQueue(uart_t* uart) { uint8_t c; @@ -311,6 +316,7 @@ void uartRxFifoToQueue(uart_t* uart) uart->dev->int_clr.val = 0xffffffff; UART_MUTEX_UNLOCK(); } +#endif uint8_t uartRead(uart_t* uart) { @@ -318,10 +324,12 @@ uint8_t uartRead(uart_t* uart) return 0; } uint8_t c; +#ifdef UART_READ_RX_FIFO if ((uxQueueMessagesWaiting(uart->queue) == 0) && (uart->dev->status.rxfifo_cnt > 0)) { uartRxFifoToQueue(uart); } +#endif if(xQueueReceive(uart->queue, &c, 0)) { return c; } @@ -334,10 +342,12 @@ uint8_t uartPeek(uart_t* uart) return 0; } uint8_t c; +#ifdef UART_READ_RX_FIFO if ((uxQueueMessagesWaiting(uart->queue) == 0) && (uart->dev->status.rxfifo_cnt > 0)) { uartRxFifoToQueue(uart); } +#endif if(xQueuePeek(uart->queue, &c, 0)) { return c; } diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h index e35f05d4cff..9e8e7ad0d36 100644 --- a/cores/esp32/esp32-hal-uart.h +++ b/cores/esp32/esp32-hal-uart.h @@ -51,7 +51,7 @@ extern "C" { struct uart_struct_t; typedef struct uart_struct_t uart_t; -uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint16_t queueLen, bool inverted); +uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint16_t queueLen, bool inverted, uint8_t rxfifo_full_thrhd); void uartEnd(uart_t* uart, uint8_t rxPin, uint8_t txPin); uint32_t uartAvailable(uart_t* uart); diff --git a/platform.txt b/platform.txt index 7db3908f1ed..6047ef132ee 100644 --- a/platform.txt +++ b/platform.txt @@ -35,7 +35,7 @@ compiler.S.flags=-c -g3 -x assembler-with-cpp -MMD -mlongcalls compiler.c.elf.cmd=xtensa-esp32-elf-gcc compiler.c.elf.flags=-nostdlib "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" -T esp32_out.ld -T esp32.project.ld -T esp32.rom.ld -T esp32.peripherals.ld -T esp32.rom.libgcc.ld -T esp32.rom.spiram_incompatible_fns.ld -u esp_app_desc -u ld_include_panic_highint_hdl -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static -Wl,--undefined=uxTopUsedPriority -u __cxa_guard_dummy -u __cxx_fatal_exception -compiler.c.elf.libs=-lgcc -lesp_websocket_client -lwpa2 -ldetection -lesp_https_server -lwps -lhal -lconsole -lpe -lsoc -lsdmmc -lpthread -llog -lesp_http_client -ljson -lmesh -lesp32-camera -lnet80211 -lwpa_supplicant -lc -lmqtt -lcxx -lesp_https_ota -lulp -lefuse -lpp -lmdns -lbt -lwpa -lspiffs -lheap -limage_util -lunity -lrtc -lmbedtls -lface_recognition -lnghttp -ljsmn -lopenssl -lcore -lfatfs -lm -lprotocomm -lsmartconfig -lxtensa-debug-module -ldl -lesp_event -lesp-tls -lfd -lespcoredump -lesp_http_server -lfr -lsmartconfig_ack -lwear_levelling -ltcp_transport -llwip -lphy -lvfs -lcoap -lesp32 -llibsodium -lbootloader_support -ldriver -lcoexist -lasio -lod -lmicro-ecc -lesp_ringbuf -ldetection_cat_face -lapp_update -lespnow -lface_detection -lapp_trace -lnewlib -lbtdm_app -lwifi_provisioning -lfreertos -lfreemodbus -lethernet -lnvs_flash -lspi_flash -lc_nano -lexpat -lfb_gfx -lprotobuf-c -lesp_adc_cal -ltcpip_adapter -lstdc++ +compiler.c.elf.libs=-lgcc -lcore -lsmartconfig_ack -lwear_levelling -limage_util -lmesh -lface_detection -lsoc -lbtdm_app -lesp-tls -lesp_https_ota -lcoap -ldl -lefuse -lspiffs -lspi_flash -lpp -lethernet -lhal -lm -ltcpip_adapter -lfatfs -lwpa2 -lprotobuf-c -lmqtt -ltcp_transport -lfreemodbus -lheap -lrtc -lc_nano -llibsodium -lnewlib -lbootloader_support -ljsmn -lmbedtls -lsdmmc -lesp_websocket_client -lprotocomm -lwps -lconsole -lphy -lespcoredump -lesp_http_client -ldetection -lnghttp -lvfs -lunity -lpe -ldetection_cat_face -lwpa_supplicant -lfreertos -lespnow -lwpa -lnvs_flash -lpthread -lmicro-ecc -ljson -llog -lesp_event -lesp_http_server -lcoexist -lnet80211 -lfd -lxtensa-debug-module -lesp32-camera -lwifi_provisioning -lexpat -lapp_update -lmdns -lsmartconfig -lc -lesp32 -lface_recognition -lopenssl -lulp -lesp_ringbuf -lfr -lasio -ldriver -llwip -lfb_gfx -lbt -lesp_https_server -lcxx -lesp_adc_cal -lod -lapp_trace -lstdc++ compiler.as.cmd=xtensa-esp32-elf-as diff --git a/tools/platformio-build.py b/tools/platformio-build.py index eaca5a23085..8f28ed24a7d 100644 --- a/tools/platformio-build.py +++ b/tools/platformio-build.py @@ -170,7 +170,7 @@ ], LIBS=[ - "-lgcc", "-lesp_websocket_client", "-lwpa2", "-ldetection", "-lesp_https_server", "-lwps", "-lhal", "-lconsole", "-lpe", "-lsoc", "-lsdmmc", "-lpthread", "-llog", "-lesp_http_client", "-ljson", "-lmesh", "-lesp32-camera", "-lnet80211", "-lwpa_supplicant", "-lc", "-lmqtt", "-lcxx", "-lesp_https_ota", "-lulp", "-lefuse", "-lpp", "-lmdns", "-lbt", "-lwpa", "-lspiffs", "-lheap", "-limage_util", "-lunity", "-lrtc", "-lmbedtls", "-lface_recognition", "-lnghttp", "-ljsmn", "-lopenssl", "-lcore", "-lfatfs", "-lm", "-lprotocomm", "-lsmartconfig", "-lxtensa-debug-module", "-ldl", "-lesp_event", "-lesp-tls", "-lfd", "-lespcoredump", "-lesp_http_server", "-lfr", "-lsmartconfig_ack", "-lwear_levelling", "-ltcp_transport", "-llwip", "-lphy", "-lvfs", "-lcoap", "-lesp32", "-llibsodium", "-lbootloader_support", "-ldriver", "-lcoexist", "-lasio", "-lod", "-lmicro-ecc", "-lesp_ringbuf", "-ldetection_cat_face", "-lapp_update", "-lespnow", "-lface_detection", "-lapp_trace", "-lnewlib", "-lbtdm_app", "-lwifi_provisioning", "-lfreertos", "-lfreemodbus", "-lethernet", "-lnvs_flash", "-lspi_flash", "-lc_nano", "-lexpat", "-lfb_gfx", "-lprotobuf-c", "-lesp_adc_cal", "-ltcpip_adapter", "-lstdc++" + "-lgcc", "-lcore", "-lsmartconfig_ack", "-lwear_levelling", "-limage_util", "-lmesh", "-lface_detection", "-lsoc", "-lbtdm_app", "-lesp-tls", "-lesp_https_ota", "-lcoap", "-ldl", "-lefuse", "-lspiffs", "-lspi_flash", "-lpp", "-lethernet", "-lhal", "-lm", "-ltcpip_adapter", "-lfatfs", "-lwpa2", "-lprotobuf-c", "-lmqtt", "-ltcp_transport", "-lfreemodbus", "-lheap", "-lrtc", "-lc_nano", "-llibsodium", "-lnewlib", "-lbootloader_support", "-ljsmn", "-lmbedtls", "-lsdmmc", "-lesp_websocket_client", "-lprotocomm", "-lwps", "-lconsole", "-lphy", "-lespcoredump", "-lesp_http_client", "-ldetection", "-lnghttp", "-lvfs", "-lunity", "-lpe", "-ldetection_cat_face", "-lwpa_supplicant", "-lfreertos", "-lespnow", "-lwpa", "-lnvs_flash", "-lpthread", "-lmicro-ecc", "-ljson", "-llog", "-lesp_event", "-lesp_http_server", "-lcoexist", "-lnet80211", "-lfd", "-lxtensa-debug-module", "-lesp32-camera", "-lwifi_provisioning", "-lexpat", "-lapp_update", "-lmdns", "-lsmartconfig", "-lc", "-lesp32", "-lface_recognition", "-lopenssl", "-lulp", "-lesp_ringbuf", "-lfr", "-lasio", "-ldriver", "-llwip", "-lfb_gfx", "-lbt", "-lesp_https_server", "-lcxx", "-lesp_adc_cal", "-lod", "-lapp_trace", "-lstdc++" ], LIBSOURCE_DIRS=[ diff --git a/tools/sdk/bin/bootloader_dio_40m.bin b/tools/sdk/bin/bootloader_dio_40m.bin index 3314163fc62..8757994435d 100644 Binary files a/tools/sdk/bin/bootloader_dio_40m.bin and b/tools/sdk/bin/bootloader_dio_40m.bin differ diff --git a/tools/sdk/bin/bootloader_dio_80m.bin b/tools/sdk/bin/bootloader_dio_80m.bin index 3f8528b0f0d..df14755741b 100644 Binary files a/tools/sdk/bin/bootloader_dio_80m.bin and b/tools/sdk/bin/bootloader_dio_80m.bin differ diff --git a/tools/sdk/bin/bootloader_dout_40m.bin b/tools/sdk/bin/bootloader_dout_40m.bin index 642afd79219..7a487af4eb9 100644 Binary files a/tools/sdk/bin/bootloader_dout_40m.bin and b/tools/sdk/bin/bootloader_dout_40m.bin differ diff --git a/tools/sdk/bin/bootloader_dout_80m.bin b/tools/sdk/bin/bootloader_dout_80m.bin index d563d4a7ea3..6361d3b5df2 100644 Binary files a/tools/sdk/bin/bootloader_dout_80m.bin and b/tools/sdk/bin/bootloader_dout_80m.bin differ diff --git a/tools/sdk/bin/bootloader_qio_40m.bin b/tools/sdk/bin/bootloader_qio_40m.bin index 7a2976e4115..52b3558f855 100644 Binary files a/tools/sdk/bin/bootloader_qio_40m.bin and b/tools/sdk/bin/bootloader_qio_40m.bin differ diff --git a/tools/sdk/bin/bootloader_qio_80m.bin b/tools/sdk/bin/bootloader_qio_80m.bin index 63c05c18a07..969a3a4181e 100644 Binary files a/tools/sdk/bin/bootloader_qio_80m.bin and b/tools/sdk/bin/bootloader_qio_80m.bin differ diff --git a/tools/sdk/bin/bootloader_qout_40m.bin b/tools/sdk/bin/bootloader_qout_40m.bin index 2c6acf7452d..d229a0f2cd3 100644 Binary files a/tools/sdk/bin/bootloader_qout_40m.bin and b/tools/sdk/bin/bootloader_qout_40m.bin differ diff --git a/tools/sdk/bin/bootloader_qout_80m.bin b/tools/sdk/bin/bootloader_qout_80m.bin index 03a453db4bb..f476a2487c1 100644 Binary files a/tools/sdk/bin/bootloader_qout_80m.bin and b/tools/sdk/bin/bootloader_qout_80m.bin differ diff --git a/tools/sdk/include/bootloader_support/esp_secure_boot.h b/tools/sdk/include/bootloader_support/esp_secure_boot.h index 17b405e4fab..5914baac86e 100644 --- a/tools/sdk/include/bootloader_support/esp_secure_boot.h +++ b/tools/sdk/include/bootloader_support/esp_secure_boot.h @@ -123,6 +123,19 @@ typedef struct { esp_err_t esp_secure_boot_verify_signature_block(const esp_secure_boot_sig_block_t *sig_block, const uint8_t *image_digest); +/** @brief Verify the ECDSA secure boot signature block for Secure Boot. + * + * Calculates Deterministic ECDSA w/ SHA256 based on the SHA256 hash of the image. ECDSA signature + * verification must be enabled in project configuration to use this function. + * + * Similar to esp_secure_boot_verify_signature(), but can be used when the digest is precalculated. + * @param sig_block Pointer to ECDSA signature block data + * @param image_digest Pointer to 32 byte buffer holding SHA-256 hash. + * @param verified_digest Pointer to 32 byte buffer that will receive verified digest if verification completes. (Used during bootloader implementation only, result is invalid otherwise.) + * + */ +esp_err_t esp_secure_boot_verify_ecdsa_signature_block(const esp_secure_boot_sig_block_t *sig_block, const uint8_t *image_digest, uint8_t *verified_digest); + #define FLASH_OFFS_SECURE_BOOT_IV_DIGEST 0 /** @brief Secure boot IV+digest header */ diff --git a/tools/sdk/include/bt/esp_a2dp_api.h b/tools/sdk/include/bt/esp_a2dp_api.h index 96aad492b59..c0c4395c34c 100644 --- a/tools/sdk/include/bt/esp_a2dp_api.h +++ b/tools/sdk/include/bt/esp_a2dp_api.h @@ -46,6 +46,12 @@ typedef struct { } cie; /*!< A2DP codec information element */ } __attribute__((packed)) esp_a2d_mcc_t; +/// Bluetooth A2DP Initiation states +typedef enum { + ESP_A2D_DEINIT_SUCCESS = 0, /*!< A2DP profile deinit successful event */ + ESP_A2D_INIT_SUCCESS /*!< A2DP profile init successful event */ +} esp_a2d_init_state_t; + /// Bluetooth A2DP connection states typedef enum { ESP_A2D_CONNECTION_STATE_DISCONNECTED = 0, /*!< connection released */ @@ -89,6 +95,7 @@ typedef enum { ESP_A2D_AUDIO_STATE_EVT, /*!< audio stream transmission state changed event */ ESP_A2D_AUDIO_CFG_EVT, /*!< audio codec is configured, only used for A2DP SINK */ ESP_A2D_MEDIA_CTRL_ACK_EVT, /*!< acknowledge event in response to media control commands */ + ESP_A2D_PROF_STATE_EVT, /*!< indicate a2dp deinit complete */ } esp_a2d_cb_event_t; /// A2DP state callback parameters @@ -125,6 +132,13 @@ typedef union { esp_a2d_media_ctrl_t cmd; /*!< media control commands to acknowledge */ esp_a2d_media_ctrl_ack_t status; /*!< acknowledgement to media control commands */ } media_ctrl_stat; /*!< status in acknowledgement to media control commands */ + + /** + * @brief ESP_A2D_PROF_STATE_EVT + */ + struct a2d_prof_stat_param { + esp_a2d_init_state_t init_state; /*!< a2dp profile state param */ + } a2d_prof_stat; /*!< status to indicate a2d prof init or deinit */ } esp_a2d_cb_param_t; /** @@ -193,7 +207,8 @@ esp_err_t esp_a2d_sink_register_data_callback(esp_a2d_sink_data_cb_t callback); /** * * @brief Initialize the bluetooth A2DP sink module. This function should be called - * after esp_bluedroid_enable() completes successfully + * after esp_bluedroid_enable() completes successfully, and ESP_A2D_PROF_STATE_EVT + * with ESP_A2D_INIT_SUCCESS will reported to the APP layer * * @return * - ESP_OK: if the initialization request is sent successfully @@ -207,7 +222,8 @@ esp_err_t esp_a2d_sink_init(void); /** * * @brief De-initialize for A2DP sink module. This function - * should be called only after esp_bluedroid_enable() completes successfully + * should be called only after esp_bluedroid_enable() completes successfully, + * and ESP_A2D_PROF_STATE_EVT with ESP_A2D_DEINIT_SUCCESS will reported to APP layer. * * @return * - ESP_OK: success @@ -264,7 +280,8 @@ esp_err_t esp_a2d_media_ctrl(esp_a2d_media_ctrl_t ctrl); /** * * @brief Initialize the bluetooth A2DP source module. This function should be called - * after esp_bluedroid_enable() completes successfully + * after esp_bluedroid_enable() completes successfully, and ESP_A2D_PROF_STATE_EVT + * with ESP_A2D_INIT_SUCCESS will reported to the APP layer * * @return * - ESP_OK: if the initialization request is sent successfully @@ -278,7 +295,8 @@ esp_err_t esp_a2d_source_init(void); /** * * @brief De-initialize for A2DP source module. This function - * should be called only after esp_bluedroid_enable() completes successfully + * should be called only after esp_bluedroid_enable() completes successfully, + * and ESP_A2D_PROF_STATE_EVT with ESP_A2D_DEINIT_SUCCESS will reported to APP layer. * * @return * - ESP_OK: success diff --git a/tools/sdk/include/bt/esp_blufi_api.h b/tools/sdk/include/bt/esp_blufi_api.h index f17fcbc2282..0d4b8662f09 100644 --- a/tools/sdk/include/bt/esp_blufi_api.h +++ b/tools/sdk/include/bt/esp_blufi_api.h @@ -301,6 +301,7 @@ typedef void (* esp_blufi_event_cb_t)(esp_blufi_cb_event_t event, esp_blufi_cb_p * @param len : length of data from phone * @param output_data : data want to send to phone * @param output_len : length of data want to send to phone + * @param need_free : output reporting if memory needs to be freed or not * */ typedef void (*esp_blufi_negotiate_data_handler_t)(uint8_t *data, int len, uint8_t **output_data, int *output_len, bool *need_free); @@ -311,7 +312,7 @@ typedef void (*esp_blufi_negotiate_data_handler_t)(uint8_t *data, int len, uint8 * @param crypt_len : length of plain text * @return Nonnegative number is encrypted length, if error, return negative number; */ -typedef int (* esp_blufi_encrypt_func_t)(uint8_t iv8, uint8_t *crypt_data, int cyprt_len); +typedef int (* esp_blufi_encrypt_func_t)(uint8_t iv8, uint8_t *crypt_data, int crypt_len); /** * @brief BLUFI decrypt the data after negotiate a share key diff --git a/tools/sdk/include/bt/esp_bt_defs.h b/tools/sdk/include/bt/esp_bt_defs.h index da93b87bcad..18d0391e8bd 100644 --- a/tools/sdk/include/bt/esp_bt_defs.h +++ b/tools/sdk/include/bt/esp_bt_defs.h @@ -69,7 +69,7 @@ typedef uint8_t esp_link_key[ESP_BT_OCTET16_LEN]; /* Link Key */ #define ESP_BLE_CONN_INT_MIN 0x0006 /*!< relate to BTM_BLE_CONN_INT_MIN in stack/btm_ble_api.h */ #define ESP_BLE_CONN_INT_MAX 0x0C80 /*!< relate to BTM_BLE_CONN_INT_MAX in stack/btm_ble_api.h */ -#define ESP_BLE_CONN_LATENCY_MAX 500 /*!< relate to ESP_BLE_CONN_LATENCY_MAX in stack/btm_ble_api.h */ +#define ESP_BLE_CONN_LATENCY_MAX 499 /*!< relate to ESP_BLE_CONN_LATENCY_MAX in stack/btm_ble_api.h */ #define ESP_BLE_CONN_SUP_TOUT_MIN 0x000A /*!< relate to BTM_BLE_CONN_SUP_TOUT_MIN in stack/btm_ble_api.h */ #define ESP_BLE_CONN_SUP_TOUT_MAX 0x0C80 /*!< relate to ESP_BLE_CONN_SUP_TOUT_MAX in stack/btm_ble_api.h */ #define ESP_BLE_CONN_PARAM_UNDEF 0xffff /* use this value when a specific value not to be overwritten */ /* relate to ESP_BLE_CONN_PARAM_UNDEF in stack/btm_ble_api.h */ diff --git a/tools/sdk/include/bt/esp_gattc_api.h b/tools/sdk/include/bt/esp_gattc_api.h index c7465253ad6..96e9af4cbf5 100644 --- a/tools/sdk/include/bt/esp_gattc_api.h +++ b/tools/sdk/include/bt/esp_gattc_api.h @@ -248,7 +248,7 @@ typedef union { /** * @brief GATT Client callback function type * @param event : Event type - * @param gatts_if : GATT client access interface, normally + * @param gattc_if : GATT client access interface, normally * different gattc_if correspond to different profile * @param param : Point to callback parameter, currently is union type */ diff --git a/tools/sdk/include/bt/esp_hf_client_api.h b/tools/sdk/include/bt/esp_hf_client_api.h index dfc06ed5d1c..e215ea32519 100644 --- a/tools/sdk/include/bt/esp_hf_client_api.h +++ b/tools/sdk/include/bt/esp_hf_client_api.h @@ -271,7 +271,7 @@ typedef void (* esp_hf_client_incoming_data_cb_t)(const uint8_t *buf, uint32_t l * buffer is allocated inside bluetooth protocol stack and will be released after * invoke of the callback is finished. * @param[in] len : size(in bytes) in buf - * @param[out] length of data successfully read + * @return length of data successfully read */ typedef uint32_t (* esp_hf_client_outgoing_data_cb_t)(uint8_t *buf, uint32_t len); diff --git a/tools/sdk/include/bt/esp_spp_api.h b/tools/sdk/include/bt/esp_spp_api.h index 385f3bff310..25a4d1ed1a1 100644 --- a/tools/sdk/include/bt/esp_spp_api.h +++ b/tools/sdk/include/bt/esp_spp_api.h @@ -26,11 +26,12 @@ typedef enum { ESP_SPP_SUCCESS = 0, /*!< Successful operation. */ ESP_SPP_FAILURE, /*!< Generic failure. */ ESP_SPP_BUSY, /*!< Temporarily can not handle this request. */ - ESP_SPP_NO_DATA, /*!< no data. */ + ESP_SPP_NO_DATA, /*!< No data. */ ESP_SPP_NO_RESOURCE, /*!< No more resource */ ESP_SPP_NEED_INIT, /*!< SPP module shall init first */ ESP_SPP_NEED_DEINIT, /*!< SPP module shall deinit first */ - ESP_SPP_NO_CONNECTION, /*!< connection may have been closed */ + ESP_SPP_NO_CONNECTION, /*!< Connection may have been closed */ + ESP_SPP_NO_SERVER, /*!< No SPP server */ } esp_spp_status_t; /* Security Setting Mask, Suggest to use ESP_SPP_SEC_NONE, ESP_SPP_SEC_AUTHORIZE or ESP_SPP_SEC_AUTHENTICATE only.*/ @@ -96,9 +97,11 @@ typedef union { * @brief SPP_DISCOVERY_COMP_EVT */ struct spp_discovery_comp_evt_param { - esp_spp_status_t status; /*!< status */ - uint8_t scn_num; /*!< The num of scn_num */ - uint8_t scn[ESP_SPP_MAX_SCN]; /*!< channel # */ + + esp_spp_status_t status; /*!< status */ + uint8_t scn_num; /*!< The num of scn_num */ + uint8_t scn[ESP_SPP_MAX_SCN]; /*!< channel # */ + const char *service_name[ESP_SPP_MAX_SCN]; /*!< service_name */ } disc_comp; /*!< SPP callback param of SPP_DISCOVERY_COMP_EVT */ /** @@ -138,6 +141,7 @@ typedef union { esp_spp_status_t status; /*!< status */ uint32_t handle; /*!< The connection handle */ uint8_t sec_id; /*!< security ID used by this server */ + uint8_t scn; /*!< Server channel number */ bool use_co; /*!< TRUE to use co_rfc_data */ } start; /*!< SPP callback param of ESP_SPP_START_EVT */ @@ -146,6 +150,7 @@ typedef union { */ struct spp_srv_stop_evt_param { esp_spp_status_t status; /*!< status */ + uint8_t scn; /*!< Server channel number */ } srv_stop; /*!< SPP callback param of ESP_SPP_SRV_STOP_EVT */ /** @@ -294,9 +299,12 @@ esp_err_t esp_spp_start_srv(esp_spp_sec_t sec_mask, esp_spp_role_t role, uint8_t local_scn, const char *name); /** - * @brief This function stops a SPP server - * When the server is stopped successfully, the callback is called - * with ESP_SPP_SRV_STOP_EVT. + + * @brief This function stops all SPP servers. + * The operation will close all active SPP connection first, then the callback function will be called + * with ESP_SPP_CLOSE_EVT, and the number of ESP_SPP_CLOSE_EVT is equal to the number of connection. + * When the operation is completed, the callback is called with ESP_SPP_SRV_STOP_EVT. + * This funciton must be called after esp_spp_init() successful and before esp_spp_deinit(). * * @return * - ESP_OK: success @@ -304,6 +312,21 @@ esp_err_t esp_spp_start_srv(esp_spp_sec_t sec_mask, */ esp_err_t esp_spp_stop_srv(void); +/** + * @brief This function stops a specific SPP server. + * The operation will close all active SPP connection first on the specific SPP server, then the callback function will be called + * with ESP_SPP_CLOSE_EVT, and the number of ESP_SPP_CLOSE_EVT is equal to the number of connection. + * When the operation is completed, the callback is called with ESP_SPP_SRV_STOP_EVT. + * This funciton must be called after esp_spp_init() successful and before esp_spp_deinit(). + * + * @param[in] scn: Server channel number. + * + * @return + * - ESP_OK: success + * - other: failed + */ +esp_err_t esp_spp_stop_srv_scn(uint8_t scn); + /** * @brief This function is used to write data, only for ESP_SPP_MODE_CB. * diff --git a/tools/sdk/include/config/sdkconfig.h b/tools/sdk/include/config/sdkconfig.h index abc464c16ee..cd6eb69ffd9 100644 --- a/tools/sdk/include/config/sdkconfig.h +++ b/tools/sdk/include/config/sdkconfig.h @@ -18,6 +18,7 @@ #define CONFIG_LWIP_ETHARP_TRUST_IP_MAC 1 #define CONFIG_BLE_SCAN_DUPLICATE 1 #define CONFIG_STACK_CHECK_NORM 1 +#define CONFIG_GC032A_SUPPORT 1 #define CONFIG_TCP_WND_DEFAULT 5744 #define CONFIG_PARTITION_TABLE_OFFSET 0x8000 #define CONFIG_SW_COEXIST_ENABLE 1 @@ -33,6 +34,7 @@ #define CONFIG_SCCB_HARDWARE_I2C_PORT1 1 #define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1 #define CONFIG_UDP_RECVMBOX_SIZE 6 +#define CONFIG_GC0308_SUPPORT 1 #define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 16 #define CONFIG_ARDUHAL_PARTITION_SCHEME_DEFAULT 1 #define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0 @@ -128,8 +130,10 @@ #define CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS 4 #define CONFIG_ESPTOOLPY_FLASHSIZE_DETECT 1 #define CONFIG_AUTOSTART_ARDUINO 1 +#define CONFIG_GC_SENSOR_SUBSAMPLE_MODE 1 #define CONFIG_ARDUINO_RUNNING_CORE 1 #define CONFIG_ESP32_ECO3_CACHE_LOCK_FIX 1 +#define CONFIG_CAMERA_DMA_BUFFER_SIZE_MAX 32768 #define CONFIG_PPP_CHAP_SUPPORT 1 #define CONFIG_LOG_DEFAULT_LEVEL_ERROR 1 #define CONFIG_TIMER_TASK_STACK_SIZE 4096 @@ -276,6 +280,7 @@ #define CONFIG_ARDUINO_UDP_TASK_PRIORITY 3 #define CONFIG_MBEDTLS_SSL_SESSION_TICKETS 1 #define CONFIG_SPIFFS_MAX_PARTITIONS 3 +#define CONFIG_GC2145_SUPPORT 1 #define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1 #define CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_0 1 #define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1 @@ -397,5 +402,5 @@ #define CONFIG_BTDM_MODEM_SLEEP_MODE_ORIG 1 #define CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_ERROR 1 #define CONFIG_FATFS_API_ENCODING_ANSI_OEM 1 -#define CONFIG_ARDUINO_IDF_COMMIT "85c43024c" +#define CONFIG_ARDUINO_IDF_COMMIT "e173e47322" #define CONFIG_ARDUINO_IDF_BRANCH "release/v3.3" diff --git a/tools/sdk/include/driver/driver/dac.h b/tools/sdk/include/driver/driver/dac.h index f921d98f146..c58bc5aeedd 100644 --- a/tools/sdk/include/driver/driver/dac.h +++ b/tools/sdk/include/driver/driver/dac.h @@ -21,6 +21,7 @@ extern "C" { #include #include "esp_err.h" +#include "driver/gpio.h" #include "soc/dac_channel.h" typedef enum { diff --git a/tools/sdk/include/driver/driver/spi_common.h b/tools/sdk/include/driver/driver/spi_common.h index c2d645566e9..1e86541cb2a 100644 --- a/tools/sdk/include/driver/driver/spi_common.h +++ b/tools/sdk/include/driver/driver/spi_common.h @@ -85,7 +85,7 @@ typedef struct { int sclk_io_num; ///< GPIO pin for Spi CLocK signal, or -1 if not used. int quadwp_io_num; ///< GPIO pin for WP (Write Protect) signal which is used as D2 in 4-bit communication modes, or -1 if not used. int quadhd_io_num; ///< GPIO pin for HD (HolD) signal which is used as D3 in 4-bit communication modes, or -1 if not used. - int max_transfer_sz; ///< Maximum transfer size, in bytes. Defaults to 4094 if 0. + int max_transfer_sz; ///< Maximum transfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to 64 if DMA is disabled. uint32_t flags; ///< Abilities of bus to be checked by the driver. Or-ed value of ``SPICOMMON_BUSFLAG_*`` flags. int intr_flags; /**< Interrupt flag for the bus to set the priority, and IRAM attribute, see * ``esp_intr_alloc.h``. Note that the EDGE, INTRDISABLED attribute are ignored diff --git a/tools/sdk/include/esp-tls/esp_tls.h b/tools/sdk/include/esp-tls/esp_tls.h index b48c1e42d11..499e06679ad 100644 --- a/tools/sdk/include/esp-tls/esp_tls.h +++ b/tools/sdk/include/esp-tls/esp_tls.h @@ -43,6 +43,16 @@ typedef enum esp_tls_conn_state { ESP_TLS_DONE, } esp_tls_conn_state_t; +/** + * @brief Keep alive parameters structure + */ +typedef struct tls_keep_alive_cfg { + bool keep_alive_enable; /*!< Enable keep-alive timeout */ + int keep_alive_idle; /*!< Keep-alive idle time (second) */ + int keep_alive_interval; /*!< Keep-alive interval time (second) */ + int keep_alive_count; /*!< Keep-alive packet retry send count */ +} tls_keep_alive_cfg_t; + /** * @brief ESP-TLS configuration parameters */ @@ -93,6 +103,8 @@ typedef struct esp_tls_cfg { If NULL, server certificate CN must match hostname. */ bool skip_common_name; /*!< Skip any validation of server certificate CN field */ + + tls_keep_alive_cfg_t *keep_alive_cfg; /*!< Enable TCP keep-alive timeout for SSL connection */ } esp_tls_cfg_t; /** diff --git a/tools/sdk/include/esp32-camera/esp_camera.h b/tools/sdk/include/esp32-camera/esp_camera.h index dadd0c0983f..b6047d312ae 100755 --- a/tools/sdk/include/esp32-camera/esp_camera.h +++ b/tools/sdk/include/esp32-camera/esp_camera.h @@ -38,7 +38,8 @@ .pixel_format = PIXFORMAT_JPEG, .frame_size = FRAMESIZE_SVGA, .jpeg_quality = 10, - .fb_count = 2 + .fb_count = 2, + .grab_mode = CAMERA_GRAB_WHEN_EMPTY }; esp_err_t camera_example_init(){ @@ -74,6 +75,22 @@ extern "C" { #endif +/** + * @brief Configuration structure for camera initialization + */ +typedef enum { + CAMERA_GRAB_WHEN_EMPTY, /*!< Fills buffers when they are empty. Less resources but first 'fb_count' frames might be old */ + CAMERA_GRAB_LATEST /*!< Except when 1 frame buffer is used, queue will always contain the last 'fb_count' frames */ +} camera_grab_mode_t; + +/** + * @brief Camera frame buffer location + */ +typedef enum { + CAMERA_FB_IN_PSRAM, /*!< Frame buffer is placed in external PSRAM */ + CAMERA_FB_IN_DRAM /*!< Frame buffer is placed in internal DRAM */ +} camera_fb_location_t; + /** * @brief Configuration structure for camera initialization */ @@ -95,7 +112,7 @@ typedef struct { int pin_href; /*!< GPIO pin for camera HREF line */ int pin_pclk; /*!< GPIO pin for camera PCLK line */ - int xclk_freq_hz; /*!< Frequency of XCLK signal, in Hz. Either 20KHz or 10KHz for OV2640 double FPS (Experimental) */ + int xclk_freq_hz; /*!< Frequency of XCLK signal, in Hz. EXPERIMENTAL: Set to 16MHz on ESP32-S2 or ESP32-S3 to enable EDMA mode */ ledc_timer_t ledc_timer; /*!< LEDC timer to be used for generating XCLK */ ledc_channel_t ledc_channel; /*!< LEDC channel to be used for generating XCLK */ @@ -105,6 +122,8 @@ typedef struct { int jpeg_quality; /*!< Quality of JPEG output. 0-63 lower means higher quality */ size_t fb_count; /*!< Number of frame buffers to be allocated. If more than one, then each frame will be acquired (double speed) */ + camera_fb_location_t fb_location; /*!< The location where the frame buffer will be allocated */ + camera_grab_mode_t grab_mode; /*!< When buffers should be filled */ } camera_config_t; /** diff --git a/tools/sdk/include/esp32-camera/img_converters.h b/tools/sdk/include/esp32-camera/img_converters.h index 330f8db8b90..f736200a9b2 100644 --- a/tools/sdk/include/esp32-camera/img_converters.h +++ b/tools/sdk/include/esp32-camera/img_converters.h @@ -22,6 +22,7 @@ extern "C" { #include #include #include "esp_camera.h" +#include "esp_jpg_decode.h" typedef size_t (* jpg_out_cb)(void * arg, size_t index, const void* data, size_t len); @@ -120,6 +121,8 @@ bool frame2bmp(camera_fb_t * fb, uint8_t ** out, size_t * out_len); */ bool fmt2rgb888(const uint8_t *src_buf, size_t src_len, pixformat_t format, uint8_t * rgb_buf); +bool jpg2rgb565(const uint8_t *src, size_t src_len, uint8_t * out, jpg_scale_t scale); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/include/esp32-camera/sensor.h b/tools/sdk/include/esp32-camera/sensor.h index ad6cd890d19..1f99c154185 100755 --- a/tools/sdk/include/esp32-camera/sensor.h +++ b/tools/sdk/include/esp32-camera/sensor.h @@ -11,13 +11,48 @@ #include #include -#define NT99141_PID (0x14) -#define OV9650_PID (0x96) -#define OV7725_PID (0x77) -#define OV2640_PID (0x26) -#define OV3660_PID (0x36) -#define OV5640_PID (0x56) -#define OV7670_PID (0x76) +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OV9650_PID = 0x96, + OV7725_PID = 0x77, + OV2640_PID = 0x26, + OV3660_PID = 0x3660, + OV5640_PID = 0x5640, + OV7670_PID = 0x76, + NT99141_PID = 0x1410, + GC2145_PID = 0x2145, + GC032A_PID = 0x232a, + GC0308_PID = 0x9b, +} camera_pid_t; + +typedef enum { + CAMERA_OV7725, + CAMERA_OV2640, + CAMERA_OV3660, + CAMERA_OV5640, + CAMERA_OV7670, + CAMERA_NT99141, + CAMERA_GC2145, + CAMERA_GC032A, + CAMERA_GC0308, + CAMERA_MODEL_MAX, + CAMERA_NONE, +} camera_model_t; + +typedef enum { + OV2640_SCCB_ADDR = 0x30,// 0x60 >> 1 + OV5640_SCCB_ADDR = 0x3C,// 0x78 >> 1 + OV3660_SCCB_ADDR = 0x3C,// 0x78 >> 1 + OV7725_SCCB_ADDR = 0x21,// 0x42 >> 1 + OV7670_SCCB_ADDR = 0x21,// 0x42 >> 1 + NT99141_SCCB_ADDR = 0x2A,// 0x54 >> 1 + GC2145_SCCB_ADDR = 0x3C,// 0x78 >> 1 + GC032A_SCCB_ADDR = 0x21,// 0x42 >> 1 + GC0308_SCCB_ADDR = 0x21,// 0x42 >> 1 +} camera_sccb_addr_t; typedef enum { PIXFORMAT_RGB565, // 2BPP/RGB565 @@ -58,6 +93,15 @@ typedef enum { FRAMESIZE_INVALID } framesize_t; +typedef struct { + const camera_model_t model; + const char *name; + const camera_sccb_addr_t sccb_addr; + const camera_pid_t pid; + const framesize_t max_size; + const bool support_jpeg; +} camera_sensor_info_t; + typedef enum { ASPECT_RATIO_4X3, ASPECT_RATIO_3X2, @@ -101,11 +145,13 @@ typedef struct { // Resolution table (in sensor.c) extern const resolution_info_t resolution[]; +// camera sensor table (in sensor.c) +extern const camera_sensor_info_t camera_sensor[]; typedef struct { uint8_t MIDH; uint8_t MIDL; - uint8_t PID; + uint16_t PID; uint8_t VER; } sensor_id_t; @@ -190,4 +236,10 @@ typedef struct _sensor { int (*set_xclk) (sensor_t *sensor, int timer, int xclk); } sensor_t; +camera_sensor_info_t *esp_camera_sensor_get_info(sensor_id_t *id); + +#ifdef __cplusplus +} +#endif + #endif /* __SENSOR_H__ */ diff --git a/tools/sdk/include/esp32/esp_crosscore_int.h b/tools/sdk/include/esp32/esp_crosscore_int.h index 2f1c5b3becf..41ddd7a7070 100644 --- a/tools/sdk/include/esp32/esp_crosscore_int.h +++ b/tools/sdk/include/esp32/esp_crosscore_int.h @@ -51,4 +51,14 @@ void esp_crosscore_int_send_yield(int core_id); */ void esp_crosscore_int_send_freq_switch(int core_id); +/** + * Send an interrupt to a CPU indicating it should print its current backtrace + * + * This is use internally by the Task Watchdog to dump the backtrace of the + * opposite core and should not be called from application code. + * + * @param core_id Core that should print its backtrace + */ +void esp_crosscore_int_send_print_backtrace(int core_id); + #endif diff --git a/tools/sdk/include/esp32/esp_fault.h b/tools/sdk/include/esp32/esp_fault.h new file mode 100644 index 00000000000..84700b8abb2 --- /dev/null +++ b/tools/sdk/include/esp32/esp_fault.h @@ -0,0 +1,94 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "sdkconfig.h" +#include "soc/rtc_cntl_reg.h" + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Assert a condition is true, in a way that should be resistant to fault injection for + * single fault attacks. + * + * - Expands CONDITION multiple times (condition must have no side effects) + * - Compiler is told all registers are invalid before evaluating CONDITION each time, to avoid a fault + * causing a misread of a register used in all three evaluations of CONDITION. + * - If CONDITION is ever false, a system reset is triggered. + * + * @note Place this macro after a "normal" check of CONDITION that will fail with a normal error + * message. This is the fallback in case a fault injection attack skips or corrupts the result of + * that check. (Although ensure that an attacker can't use fault injection to skip past the "normal" + * error message, to avoid this check entirely.) + * + * @note This macro increases binary size and is slow and should be used sparingly. +* + * @note This macro does not guarantee fault injection resistance. In particular CONDITION must be + * chosen carefully - a fault injection attack which sets CONDITION to true will not be detected by + * this macro. Care must also be taken that an attacker can't use a fault to completely bypass calling + * whatever function tests ESP_FAULT_ASSERT. + * + * @note This is difficult to debug as a failure triggers an instant software reset, and UART output + * is often truncated (as FIFO is not flushed). Define the ESP_FAULT_ASSERT_DEBUG macro to debug any + * failures of this macro due to software bugs. + * + * @param CONDITION A condition which will evaluate true unless an attacker used fault injection to skip or corrupt some other critical system + calculation. + * + */ +#define ESP_FAULT_ASSERT(CONDITION) do { \ + asm volatile ("" ::: "memory"); \ + if(!(CONDITION)) _ESP_FAULT_RESET(); \ + asm volatile ("" ::: "memory"); \ + if(!(CONDITION)) _ESP_FAULT_RESET(); \ + asm volatile ("" ::: "memory"); \ + if(!(CONDITION)) _ESP_FAULT_RESET(); \ +} while(0) + + +// Uncomment this macro to get debug output if ESP_FAULT_ASSERT() fails +// +// Note that uncommenting this macro reduces the anti-FI effectiveness +// +//#define ESP_FAULT_ASSERT_DEBUG + +/* Internal macro, purpose is to trigger a system reset if an inconsistency due to fault injection + is detected. + + Illegal instruction opcodes are there as a fallback to crash the CPU in case it doesn't + reset as expected. +*/ +#ifndef ESP_FAULT_ASSERT_DEBUG + +#define _ESP_FAULT_RESET() do { \ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); \ + asm volatile("ill; ill; ill;"); \ + } while(0) + +#else // ESP_FAULT_ASSERT_DEBUG + +#warning "Enabling ESP_FAULT_ASSERT_DEBUG makes ESP_FAULT_ASSERT() less effective" + +#define _ESP_FAULT_RESET() do { \ + ets_printf("ESP_FAULT_ASSERT %s:%d\n", __FILE__, __LINE__); \ + asm volatile("ill;"); \ + } while(0) + +#endif // ESP_FAULT_ASSERT_DEBUG + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/include/esp32/esp_panic.h b/tools/sdk/include/esp32/esp_panic.h index 8db2836ee37..1ee6341cdd9 100644 --- a/tools/sdk/include/esp32/esp_panic.h +++ b/tools/sdk/include/esp32/esp_panic.h @@ -1,5 +1,18 @@ -#ifndef PANIC_H -#define PANIC_H +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once #ifdef __cplusplus extern "C" @@ -21,8 +34,27 @@ extern "C" #include "esp_err.h" #include "soc/soc.h" +#include "soc/soc_memory_layout.h" +/* + * @brief Structure used for backtracing + * + * This structure stores the backtrace information of a particular stack frame + * (i.e. the PC and SP). This structure is used iteratively with the + * esp_cpu_get_next_backtrace_frame() function to traverse each frame within a + * single stack. The next_pc represents the PC of the current frame's caller, thus + * a next_pc of 0 indicates that the current frame is the last frame on the stack. + * + * @note Call esp_backtrace_get_start() to obtain initialization values for + * this structure + */ +typedef struct { + uint32_t pc; /* PC of the current frame */ + uint32_t sp; /* SP of the current frame */ + uint32_t next_pc; /* PC of the current frame's caller */ +} esp_backtrace_frame_t; + /** * @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function * address. Do nothing otherwise. @@ -53,7 +85,6 @@ void esp_set_breakpoint_if_jtag(void *fn); */ esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags); - /** * @brief Clear a watchpoint * @@ -82,21 +113,56 @@ inline static bool esp_stack_ptr_in_extram(uint32_t sp) } #endif +/* + * Get the first frame of the current stack's backtrace + * + * Given the following function call flow (B -> A -> X -> esp_backtrace_get_start), + * this function will do the following. + * - Flush CPU registers and window frames onto the current stack + * - Return PC and SP of function A (i.e. start of the stack's backtrace) + * - Return PC of function B (i.e. next_pc) + * + * @note This function is implemented in assembly + * + * @param[out] pc PC of the first frame in the backtrace + * @param[out] sp SP of the first frame in the backtrace + * @param[out] next_pc PC of the first frame's caller + */ +extern void esp_backtrace_get_start(uint32_t *pc, uint32_t *sp, uint32_t *next_pc); + +/** + * Get the next frame on a stack for backtracing + * + * Given a stack frame(i), this function will obtain the next stack frame(i-1) + * on the same call stack (i.e. the caller of frame(i)). This function is meant to be + * called iteratively when doing a backtrace. + * + * Entry Conditions: Frame structure containing valid SP and next_pc + * Exit Conditions: + * - Frame structure updated with SP and PC of frame(i-1). next_pc now points to frame(i-2). + * - If a next_pc of 0 is returned, it indicates that frame(i-1) is last frame on the stack + * + * @param[inout] frame Pointer to frame structure + * + * @return + * - True if the SP and PC of the next frame(i-1) are sane + * - False otherwise + */ +bool esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame); + /** - * @brief Checks stack pointer + * @brief Print the backtrace of the current stack + * + * @param depth The maximum number of stack frames to print (should be > 0) + * + * @return + * - ESP_OK Backtrace successfully printed to completion or to depth limit + * - ESP_FAIL Backtrace is corrupted */ -static inline bool esp_stack_ptr_is_sane(uint32_t sp) -{ -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - return (esp_stack_ptr_in_dram(sp) || esp_stack_ptr_in_extram(sp)); -#else - return esp_stack_ptr_in_dram(sp); -#endif -} +esp_err_t esp_backtrace_print(int depth); + #endif #ifdef __cplusplus } #endif - -#endif diff --git a/tools/sdk/include/esp_event/esp_event.h b/tools/sdk/include/esp_event/esp_event.h index 48918398cf4..7c6a78c1106 100644 --- a/tools/sdk/include/esp_event/esp_event.h +++ b/tools/sdk/include/esp_event/esp_event.h @@ -49,6 +49,7 @@ typedef struct { * * @return * - ESP_OK: Success + * - ESP_ERR_INVALID_ARG: event_loop_args or event_loop was NULL * - ESP_ERR_NO_MEM: Cannot allocate memory for event loops list * - ESP_FAIL: Failed to create task loop * - Others: Fail @@ -58,7 +59,7 @@ esp_err_t esp_event_loop_create(const esp_event_loop_args_t* event_loop_args, es /** * @brief Delete an existing event loop. * - * @param[in] event_loop event loop to delete + * @param[in] event_loop event loop to delete, must not be NULL * * @return * - ESP_OK: Success @@ -103,7 +104,7 @@ esp_err_t esp_event_loop_delete_default(); * In cases where waiting on the queue times out, ESP_OK is returned and not ESP_ERR_TIMEOUT, since it is * normal behavior. * - * @param[in] event_loop event loop to dispatch posted events from + * @param[in] event_loop event loop to dispatch posted events from, must not be NULL * @param[in] ticks_to_run number of ticks to run the loop * * @note encountering an unknown event that has been posted to the loop will only generate a warning, not an error. @@ -153,7 +154,7 @@ esp_err_t esp_event_handler_register(esp_event_base_t event_base, * This function behaves in the same manner as esp_event_handler_register, except the additional * specification of the event loop to register the handler to. * - * @param[in] event_loop the event loop to register this handler function to + * @param[in] event_loop the event loop to register this handler function to, must not be NULL * @param[in] event_base the base id of the event to register the handler for * @param[in] event_id the id of the event to register the handler for * @param[in] event_handler the handler function which gets called when the event is dispatched @@ -169,23 +170,23 @@ esp_err_t esp_event_handler_register(esp_event_base_t event_base, * - Others: Fail */ esp_err_t esp_event_handler_register_with(esp_event_loop_handle_t event_loop, - esp_event_base_t event_base, - int32_t event_id, - esp_event_handler_t event_handler, - void* event_handler_arg); + esp_event_base_t event_base, + int32_t event_id, + esp_event_handler_t event_handler, + void *event_handler_arg); /** * @brief Unregister a handler with the system event loop. * - * This function can be used to unregister a handler so that it no longer gets called during dispatch. - * Handlers can be unregistered for either: (1) specific events, (2) all events of a certain event base, - * or (3) all events known by the system event loop - * - * - specific events: specify exact event_base and event_id - * - all events of a certain base: specify exact event_base and use ESP_EVENT_ANY_ID as the event_id - * - all events known by the loop: use ESP_EVENT_ANY_BASE for event_base and ESP_EVENT_ANY_ID as the event_id + * Unregisters a handler so it will no longer be called during dispatch. + * Handlers can be unregistered for any combination of event_base and event_id which were previously registered. + * To unregister a handler, the event_base and event_id arguments must match exactly the arguments passed to + * esp_event_handler_register() when that handler was registered. Passing ESP_EVENT_ANY_BASE and/or ESP_EVENT_ANY_ID + * will only unregister handlers that were registered with the same wildcard arguments. * - * This function ignores unregistration of handlers that has not been previously registered. + * @note When using ESP_EVENT_ANY_ID, handlers registered to specific event IDs using the same base will not be + * unregistered. When using ESP_EVENT_ANY_BASE, events registered to specific bases will also not be + * unregistered. This avoids accidental unregistration of handlers registered by other users or components. * * @param[in] event_base the base of the event with which to unregister the handler * @param[in] event_id the id of the event with which to unregister the handler @@ -203,7 +204,7 @@ esp_err_t esp_event_handler_unregister(esp_event_base_t event_base, int32_t even * This function behaves in the same manner as esp_event_handler_unregister, except the additional specification of * the event loop to unregister the handler with. * - * @param[in] event_loop the event loop with which to unregister this handler function + * @param[in] event_loop the event loop with which to unregister this handler function, must not be NULL * @param[in] event_base the base of the event with which to unregister the handler * @param[in] event_id the id of the event with which to unregister the handler * @param[in] event_handler the handler to unregister @@ -251,7 +252,7 @@ esp_err_t esp_event_post(esp_event_base_t event_base, * This function behaves in the same manner as esp_event_post_to, except the additional specification of the event loop * to post the event to. * - * @param[in] event_loop the event loop to post to + * @param[in] event_loop the event loop to post to, must not be NULL * @param[in] event_base the event base that identifies the event * @param[in] event_id the the event id that identifies the event * @param[in] event_data the data, specific to the event occurence, that gets passed to the handler @@ -323,4 +324,4 @@ esp_err_t esp_event_dump(FILE* file); } // extern "C" #endif -#endif // #ifndef ESP_EVENT_H_ \ No newline at end of file +#endif // #ifndef ESP_EVENT_H_ diff --git a/tools/sdk/include/esp_http_client/esp_http_client.h b/tools/sdk/include/esp_http_client/esp_http_client.h index 881fcd4b442..fddbf58a52f 100644 --- a/tools/sdk/include/esp_http_client/esp_http_client.h +++ b/tools/sdk/include/esp_http_client/esp_http_client.h @@ -120,6 +120,10 @@ typedef struct { bool is_async; /*!< Set asynchronous mode, only supported with HTTPS for now */ bool use_global_ca_store; /*!< Use a global ca_store for all the connections in which this bool is set. */ bool skip_cert_common_name_check; /*!< Skip any validation of server certificate CN field */ + bool keep_alive_enable; /*!< Enable keep-alive timeout */ + int keep_alive_idle; /*!< Keep-alive idle time. Default is 5 (second) */ + int keep_alive_interval; /*!< Keep-alive interval time. Default is 5 (second) */ + int keep_alive_count; /*!< Keep-alive packet retry send count. Default is 3 counts */ } esp_http_client_config_t; /** diff --git a/tools/sdk/include/esp_websocket_client/esp_websocket_client.h b/tools/sdk/include/esp_websocket_client/esp_websocket_client.h index 6a8bca2b97b..43857f552b2 100644 --- a/tools/sdk/include/esp_websocket_client/esp_websocket_client.h +++ b/tools/sdk/include/esp_websocket_client/esp_websocket_client.h @@ -86,6 +86,10 @@ typedef struct { char *user_agent; /*!< Websocket user-agent */ char *headers; /*!< Websocket additional headers */ int pingpong_timeout_sec; /*!< Period before connection is aborted due to no PONGs received, disabled if value is 0 */ + bool keep_alive_enable; /*!< Enable keep-alive timeout */ + int keep_alive_idle; /*!< Keep-alive idle time. Default is 5 (second) */ + int keep_alive_interval; /*!< Keep-alive interval time. Default is 5 (second) */ + int keep_alive_count; /*!< Keep-alive packet retry send count. Default is 3 counts */ } esp_websocket_client_config_t; /** diff --git a/tools/sdk/include/mbedtls/mbedtls/aes.h b/tools/sdk/include/mbedtls/mbedtls/aes.h index d20cdbd6da8..4468b6623ac 100644 --- a/tools/sdk/include/mbedtls/mbedtls/aes.h +++ b/tools/sdk/include/mbedtls/mbedtls/aes.h @@ -21,7 +21,7 @@ */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -62,8 +62,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_AES_H diff --git a/tools/sdk/include/mbedtls/mbedtls/aesni.h b/tools/sdk/include/mbedtls/mbedtls/aesni.h index 91a4e0f1160..9b63a0010a0 100644 --- a/tools/sdk/include/mbedtls/mbedtls/aesni.h +++ b/tools/sdk/include/mbedtls/mbedtls/aesni.h @@ -7,7 +7,7 @@ * functions; you must not call them directly. */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -48,8 +48,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_AESNI_H #define MBEDTLS_AESNI_H diff --git a/tools/sdk/include/mbedtls/mbedtls/arc4.h b/tools/sdk/include/mbedtls/mbedtls/arc4.h index ecaf3101221..6334a9cc1e2 100644 --- a/tools/sdk/include/mbedtls/mbedtls/arc4.h +++ b/tools/sdk/include/mbedtls/mbedtls/arc4.h @@ -7,7 +7,7 @@ * security risk. We recommend considering stronger ciphers instead. */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -49,8 +49,6 @@ * * ********** * - * This file is part of mbed TLS (https://tls.mbed.org) - * */ #ifndef MBEDTLS_ARC4_H #define MBEDTLS_ARC4_H diff --git a/tools/sdk/include/mbedtls/mbedtls/aria.h b/tools/sdk/include/mbedtls/mbedtls/aria.h index 66f2668bf37..20f43f2256d 100644 --- a/tools/sdk/include/mbedtls/mbedtls/aria.h +++ b/tools/sdk/include/mbedtls/mbedtls/aria.h @@ -10,7 +10,7 @@ * and also described by the IETF in RFC 5794. */ /* - * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -51,8 +51,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ARIA_H @@ -90,14 +88,14 @@ /* MBEDTLS_ERR_ARIA_HW_ACCEL_FAILED is deprecated and should not be used. */ #define MBEDTLS_ERR_ARIA_HW_ACCEL_FAILED -0x0058 /**< ARIA hardware accelerator failed. */ -#if !defined(MBEDTLS_ARIA_ALT) -// Regular implementation -// - #ifdef __cplusplus extern "C" { #endif +#if !defined(MBEDTLS_ARIA_ALT) +// Regular implementation +// + /** * \brief The ARIA context-type definition. */ diff --git a/tools/sdk/include/mbedtls/mbedtls/asn1.h b/tools/sdk/include/mbedtls/mbedtls/asn1.h index c64038cdb5c..0e596bca2cd 100644 --- a/tools/sdk/include/mbedtls/mbedtls/asn1.h +++ b/tools/sdk/include/mbedtls/mbedtls/asn1.h @@ -4,7 +4,7 @@ * \brief Generic ASN.1 parsing */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ASN1_H #define MBEDTLS_ASN1_H diff --git a/tools/sdk/include/mbedtls/mbedtls/asn1write.h b/tools/sdk/include/mbedtls/mbedtls/asn1write.h index 4fed59371ca..3c7cdd6b469 100644 --- a/tools/sdk/include/mbedtls/mbedtls/asn1write.h +++ b/tools/sdk/include/mbedtls/mbedtls/asn1write.h @@ -4,7 +4,7 @@ * \brief ASN.1 buffer writing functionality */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ASN1_WRITE_H #define MBEDTLS_ASN1_WRITE_H diff --git a/tools/sdk/include/mbedtls/mbedtls/base64.h b/tools/sdk/include/mbedtls/mbedtls/base64.h index 215255e628e..cbed6887ee6 100644 --- a/tools/sdk/include/mbedtls/mbedtls/base64.h +++ b/tools/sdk/include/mbedtls/mbedtls/base64.h @@ -4,7 +4,7 @@ * \brief RFC 1521 base64 encoding/decoding */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_BASE64_H #define MBEDTLS_BASE64_H diff --git a/tools/sdk/include/mbedtls/mbedtls/bignum.h b/tools/sdk/include/mbedtls/mbedtls/bignum.h index 1e41d702456..3deedfedd9c 100644 --- a/tools/sdk/include/mbedtls/mbedtls/bignum.h +++ b/tools/sdk/include/mbedtls/mbedtls/bignum.h @@ -4,7 +4,7 @@ * \brief Multi-precision integer library */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_BIGNUM_H #define MBEDTLS_BIGNUM_H @@ -90,12 +88,12 @@ * Maximum window size used for modular exponentiation. Default: 6 * Minimum value: 1. Maximum value: 6. * - * Result is an array of ( 2 << MBEDTLS_MPI_WINDOW_SIZE ) MPIs used + * Result is an array of ( 2 ** MBEDTLS_MPI_WINDOW_SIZE ) MPIs used * for the sliding window calculation. (So 64 by default) * * Reduction in size, reduces speed. */ -#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */ +#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum window size used. */ #endif /* !MBEDTLS_MPI_WINDOW_SIZE */ #if !defined(MBEDTLS_MPI_MAX_SIZE) diff --git a/tools/sdk/include/mbedtls/mbedtls/blowfish.h b/tools/sdk/include/mbedtls/mbedtls/blowfish.h index d2a1ebdbf41..945bd426a9f 100644 --- a/tools/sdk/include/mbedtls/mbedtls/blowfish.h +++ b/tools/sdk/include/mbedtls/mbedtls/blowfish.h @@ -4,7 +4,7 @@ * \brief Blowfish block cipher */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_BLOWFISH_H #define MBEDTLS_BLOWFISH_H diff --git a/tools/sdk/include/mbedtls/mbedtls/bn_mul.h b/tools/sdk/include/mbedtls/mbedtls/bn_mul.h index 42339b7b718..6f1201bf50a 100644 --- a/tools/sdk/include/mbedtls/mbedtls/bn_mul.h +++ b/tools/sdk/include/mbedtls/mbedtls/bn_mul.h @@ -4,7 +4,7 @@ * \brief Multi-precision integer library */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ /* * Multiply source vector [s] with b, add result @@ -73,6 +71,46 @@ #include "bignum.h" + +/* + * Conversion macros for embedded constants: + * build lists of mbedtls_mpi_uint's from lists of unsigned char's grouped by 8, 4 or 2 + */ +#if defined(MBEDTLS_HAVE_INT32) + +#define MBEDTLS_BYTES_TO_T_UINT_4( a, b, c, d ) \ + ( (mbedtls_mpi_uint) (a) << 0 ) | \ + ( (mbedtls_mpi_uint) (b) << 8 ) | \ + ( (mbedtls_mpi_uint) (c) << 16 ) | \ + ( (mbedtls_mpi_uint) (d) << 24 ) + +#define MBEDTLS_BYTES_TO_T_UINT_2( a, b ) \ + MBEDTLS_BYTES_TO_T_UINT_4( a, b, 0, 0 ) + +#define MBEDTLS_BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + MBEDTLS_BYTES_TO_T_UINT_4( a, b, c, d ), \ + MBEDTLS_BYTES_TO_T_UINT_4( e, f, g, h ) + +#else /* 64-bits */ + +#define MBEDTLS_BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + ( (mbedtls_mpi_uint) (a) << 0 ) | \ + ( (mbedtls_mpi_uint) (b) << 8 ) | \ + ( (mbedtls_mpi_uint) (c) << 16 ) | \ + ( (mbedtls_mpi_uint) (d) << 24 ) | \ + ( (mbedtls_mpi_uint) (e) << 32 ) | \ + ( (mbedtls_mpi_uint) (f) << 40 ) | \ + ( (mbedtls_mpi_uint) (g) << 48 ) | \ + ( (mbedtls_mpi_uint) (h) << 56 ) + +#define MBEDTLS_BYTES_TO_T_UINT_4( a, b, c, d ) \ + MBEDTLS_BYTES_TO_T_UINT_8( a, b, c, d, 0, 0, 0, 0 ) + +#define MBEDTLS_BYTES_TO_T_UINT_2( a, b ) \ + MBEDTLS_BYTES_TO_T_UINT_8( a, b, 0, 0, 0, 0, 0, 0 ) + +#endif /* bits in mbedtls_mpi_uint */ + #if defined(MBEDTLS_HAVE_ASM) #ifndef asm diff --git a/tools/sdk/include/mbedtls/mbedtls/camellia.h b/tools/sdk/include/mbedtls/mbedtls/camellia.h index 41d6f955bae..38871288e4b 100644 --- a/tools/sdk/include/mbedtls/mbedtls/camellia.h +++ b/tools/sdk/include/mbedtls/mbedtls/camellia.h @@ -4,7 +4,7 @@ * \brief Camellia block cipher */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CAMELLIA_H #define MBEDTLS_CAMELLIA_H diff --git a/tools/sdk/include/mbedtls/mbedtls/ccm.h b/tools/sdk/include/mbedtls/mbedtls/ccm.h index 3647d5094f5..d50c6ec9939 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ccm.h +++ b/tools/sdk/include/mbedtls/mbedtls/ccm.h @@ -28,7 +28,7 @@ * consistent with RFC 3610. */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -69,8 +69,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CCM_H @@ -177,7 +175,7 @@ void mbedtls_ccm_free( mbedtls_ccm_context *ctx ); * than zero, \p output must be a writable buffer of at least * that length. * \param tag The buffer holding the authentication field. This must be a - * readable buffer of at least \p tag_len Bytes. + * writable buffer of at least \p tag_len Bytes. * \param tag_len The length of the authentication field to generate in Bytes: * 4, 6, 8, 10, 12, 14 or 16. * @@ -222,7 +220,7 @@ int mbedtls_ccm_encrypt_and_tag( mbedtls_ccm_context *ctx, size_t length, * than zero, \p output must be a writable buffer of at least * that length. * \param tag The buffer holding the authentication field. This must be a - * readable buffer of at least \p tag_len Bytes. + * writable buffer of at least \p tag_len Bytes. * \param tag_len The length of the authentication field to generate in Bytes: * 0, 4, 6, 8, 10, 12, 14 or 16. * diff --git a/tools/sdk/include/mbedtls/mbedtls/certs.h b/tools/sdk/include/mbedtls/mbedtls/certs.h index 2a645ad0d04..8472a6f38ce 100644 --- a/tools/sdk/include/mbedtls/mbedtls/certs.h +++ b/tools/sdk/include/mbedtls/mbedtls/certs.h @@ -4,7 +4,7 @@ * \brief Sample certificates and DHM parameters for testing */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CERTS_H #define MBEDTLS_CERTS_H diff --git a/tools/sdk/include/mbedtls/mbedtls/chacha20.h b/tools/sdk/include/mbedtls/mbedtls/chacha20.h index e2950e1a015..8c9c2af6ffb 100644 --- a/tools/sdk/include/mbedtls/mbedtls/chacha20.h +++ b/tools/sdk/include/mbedtls/mbedtls/chacha20.h @@ -13,7 +13,7 @@ */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -54,8 +54,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CHACHA20_H diff --git a/tools/sdk/include/mbedtls/mbedtls/chachapoly.h b/tools/sdk/include/mbedtls/mbedtls/chachapoly.h index bee5a3ab036..5f6cb6e0306 100644 --- a/tools/sdk/include/mbedtls/mbedtls/chachapoly.h +++ b/tools/sdk/include/mbedtls/mbedtls/chachapoly.h @@ -13,7 +13,7 @@ */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -54,8 +54,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CHACHAPOLY_H diff --git a/tools/sdk/include/mbedtls/mbedtls/check_config.h b/tools/sdk/include/mbedtls/mbedtls/check_config.h index 8ce73ceff11..2bbd7a80ffe 100644 --- a/tools/sdk/include/mbedtls/mbedtls/check_config.h +++ b/tools/sdk/include/mbedtls/mbedtls/check_config.h @@ -4,7 +4,7 @@ * \brief Consistency checks for configuration options */ /* - * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ /* @@ -199,6 +197,16 @@ #error "MBEDTLS_ENTROPY_FORCE_SHA256 defined, but not all prerequisites" #endif +#if defined(__has_feature) +#if __has_feature(memory_sanitizer) +#define MBEDTLS_HAS_MEMSAN +#endif +#endif +#if defined(MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN) && !defined(MBEDTLS_HAS_MEMSAN) +#error "MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN requires building with MemorySanitizer" +#endif +#undef MBEDTLS_HAS_MEMSAN + #if defined(MBEDTLS_TEST_NULL_ENTROPY) && \ ( !defined(MBEDTLS_ENTROPY_C) || !defined(MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES) ) #error "MBEDTLS_TEST_NULL_ENTROPY defined, but not all prerequisites" diff --git a/tools/sdk/include/mbedtls/mbedtls/cipher.h b/tools/sdk/include/mbedtls/mbedtls/cipher.h index 8672dd2b98b..1f41b528c48 100644 --- a/tools/sdk/include/mbedtls/mbedtls/cipher.h +++ b/tools/sdk/include/mbedtls/mbedtls/cipher.h @@ -8,7 +8,7 @@ * \author Adriaan de Jong */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -49,8 +49,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CIPHER_H diff --git a/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h b/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h index 558be52a7e0..88282ec9d20 100644 --- a/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h +++ b/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h @@ -6,7 +6,7 @@ * \author Adriaan de Jong */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -47,8 +47,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CIPHER_WRAP_H #define MBEDTLS_CIPHER_WRAP_H diff --git a/tools/sdk/include/mbedtls/mbedtls/cmac.h b/tools/sdk/include/mbedtls/mbedtls/cmac.h index 20747475679..5a7c9b246f0 100644 --- a/tools/sdk/include/mbedtls/mbedtls/cmac.h +++ b/tools/sdk/include/mbedtls/mbedtls/cmac.h @@ -7,7 +7,7 @@ * Authentication is defined in RFC-4493: The AES-CMAC Algorithm. */ /* - * Copyright (C) 2015-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -48,8 +48,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CMAC_H diff --git a/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h b/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h index 71cc4f4d973..45e5a1cf77c 100644 --- a/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h +++ b/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h @@ -7,7 +7,7 @@ * \deprecated Use the new names directly instead */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -48,8 +48,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #if !defined(MBEDTLS_CONFIG_FILE) diff --git a/tools/sdk/include/mbedtls/mbedtls/config.h b/tools/sdk/include/mbedtls/mbedtls/config.h index f7e55aef5cf..b1d67f7a931 100644 --- a/tools/sdk/include/mbedtls/mbedtls/config.h +++ b/tools/sdk/include/mbedtls/mbedtls/config.h @@ -8,7 +8,7 @@ * memory footprint. */ /* - * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -49,8 +49,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CONFIG_H @@ -455,7 +453,7 @@ * be overridden, but the wrapper functions mbedtls_aes_decrypt and mbedtls_aes_encrypt * must stay untouched. * - * \note If you use the AES_xxx_ALT macros, then is is recommended to also set + * \note If you use the AES_xxx_ALT macros, then it is recommended to also set * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES * tables. * @@ -551,6 +549,42 @@ //#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT //#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + * + * Enable testing of the constant-flow nature of some sensitive functions with + * clang's MemorySanitizer. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires compiling with clang -fsanitize=memory. The test + * suites can then be run normally. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +//#define MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + * + * Enable testing of the constant-flow nature of some sensitive functions with + * valgrind's memcheck tool. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires valgrind headers for building, and is only useful for + * testing if the tests suites are run with valgrind's memcheck. This can be + * done for an individual test suite with 'valgrind ./test_suite_xxx', or when + * using CMake, this can be done for all test suites with 'make memcheck'. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +//#define MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + /** * \def MBEDTLS_TEST_NULL_ENTROPY * @@ -1712,6 +1746,23 @@ */ //#define MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT +/** + * \def MBEDTLS_TEST_HOOKS + * + * Enable features for invasive testing such as introspection functions and + * hooks for fault injection. This enables additional unit tests. + * + * Merely enabling this feature should not change the behavior of the product. + * It only adds new code, and new branching points where the default behavior + * is the same as when this feature is disabled. + * However, this feature increases the attack surface: there is an added + * risk of vulnerabilities, and more gadgets that can make exploits easier. + * Therefore this feature must never be enabled in production. + * + * Uncomment to enable invasive tests. + */ +//#define MBEDTLS_TEST_HOOKS + /** * \def MBEDTLS_THREADING_ALT * @@ -3092,7 +3143,7 @@ */ /* MPI / BIGNUM options */ -//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */ +//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum window size used. */ //#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ /* CTR_DRBG options */ diff --git a/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h b/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h index 894fa17130f..6c099adf4d3 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h +++ b/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h @@ -38,7 +38,7 @@ * - \c 32 if \c MBEDTLS_ENTROPY_FORCE_SHA256 is enabled at compile time. */ /* - * Copyright (C) 2006-2019, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -79,8 +79,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CTR_DRBG_H @@ -216,6 +214,13 @@ typedef struct mbedtls_ctr_drbg_context void *p_entropy; /*!< The context for the entropy function. */ #if defined(MBEDTLS_THREADING_C) + /* Invariant: the mutex is initialized if and only if f_entropy != NULL. + * This means that the mutex is initialized during the initial seeding + * in mbedtls_ctr_drbg_seed() and freed in mbedtls_ctr_drbg_free(). + * + * Note that this invariant may change without notice. Do not rely on it + * and do not access the mutex directly in application code. + */ mbedtls_threading_mutex_t mutex; #endif } @@ -226,6 +231,11 @@ mbedtls_ctr_drbg_context; * and prepares it for mbedtls_ctr_drbg_seed() * or mbedtls_ctr_drbg_free(). * + * \note The reseed interval is + * #MBEDTLS_CTR_DRBG_RESEED_INTERVAL by default. + * You can override it by calling + * mbedtls_ctr_drbg_set_reseed_interval(). + * * \param ctx The CTR_DRBG context to initialize. */ void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx ); @@ -274,6 +284,15 @@ void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx ); * device. */ #endif +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * after this function returns successfully, + * it is safe to call mbedtls_ctr_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ /** * \param ctx The CTR_DRBG context to seed. * It must have been initialized with @@ -283,6 +302,8 @@ void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx ); * the same context unless you call * mbedtls_ctr_drbg_free() and mbedtls_ctr_drbg_init() * again first. + * After a failed call to mbedtls_ctr_drbg_seed(), + * you must call mbedtls_ctr_drbg_free(). * \param f_entropy The entropy callback, taking as arguments the * \p p_entropy context, the buffer to fill, and the * length of the buffer. @@ -307,7 +328,8 @@ int mbedtls_ctr_drbg_seed( mbedtls_ctr_drbg_context *ctx, size_t len ); /** - * \brief This function clears CTR_CRBG context data. + * \brief This function resets CTR_DRBG context to the state immediately + * after initial call of mbedtls_ctr_drbg_init(). * * \param ctx The CTR_DRBG context to clear. */ @@ -373,6 +395,11 @@ void mbedtls_ctr_drbg_set_reseed_interval( mbedtls_ctr_drbg_context *ctx, * \brief This function reseeds the CTR_DRBG context, that is * extracts data from the entropy source. * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * * \param ctx The CTR_DRBG context. * \param additional Additional data to add to the state. Can be \c NULL. * \param len The length of the additional data. @@ -390,6 +417,11 @@ int mbedtls_ctr_drbg_reseed( mbedtls_ctr_drbg_context *ctx, /** * \brief This function updates the state of the CTR_DRBG context. * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * * \param ctx The CTR_DRBG context. * \param additional The data to update the state with. This must not be * \c NULL unless \p add_len is \c 0. @@ -413,6 +445,11 @@ int mbedtls_ctr_drbg_update_ret( mbedtls_ctr_drbg_context *ctx, * This function automatically reseeds if the reseed counter is exceeded * or prediction resistance is enabled. * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * * \param p_rng The CTR_DRBG context. This must be a pointer to a * #mbedtls_ctr_drbg_context structure. * \param output The buffer to fill. @@ -441,8 +478,16 @@ int mbedtls_ctr_drbg_random_with_add( void *p_rng, * * This function automatically reseeds if the reseed counter is exceeded * or prediction resistance is enabled. - * - * + */ +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * it is safe to call mbedtls_ctr_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** * \param p_rng The CTR_DRBG context. This must be a pointer to a * #mbedtls_ctr_drbg_context structure. * \param output The buffer to fill. diff --git a/tools/sdk/include/mbedtls/mbedtls/debug.h b/tools/sdk/include/mbedtls/mbedtls/debug.h index 11928e98183..abc2d4f07ca 100644 --- a/tools/sdk/include/mbedtls/mbedtls/debug.h +++ b/tools/sdk/include/mbedtls/mbedtls/debug.h @@ -4,7 +4,7 @@ * \brief Functions for controlling and providing debug output from the library. */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_DEBUG_H #define MBEDTLS_DEBUG_H diff --git a/tools/sdk/include/mbedtls/mbedtls/des.h b/tools/sdk/include/mbedtls/mbedtls/des.h index 4c6441d7d94..ee24f659459 100644 --- a/tools/sdk/include/mbedtls/mbedtls/des.h +++ b/tools/sdk/include/mbedtls/mbedtls/des.h @@ -8,7 +8,7 @@ * instead. */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -50,8 +50,6 @@ * * ********** * - * This file is part of mbed TLS (https://tls.mbed.org) - * */ #ifndef MBEDTLS_DES_H #define MBEDTLS_DES_H diff --git a/tools/sdk/include/mbedtls/mbedtls/dhm.h b/tools/sdk/include/mbedtls/mbedtls/dhm.h index 5c04ed19fb4..11042efb556 100644 --- a/tools/sdk/include/mbedtls/mbedtls/dhm.h +++ b/tools/sdk/include/mbedtls/mbedtls/dhm.h @@ -44,7 +44,7 @@ * */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -85,8 +85,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_DHM_H diff --git a/tools/sdk/include/mbedtls/mbedtls/ecdh.h b/tools/sdk/include/mbedtls/mbedtls/ecdh.h index a0052df4719..b9324bc4964 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ecdh.h +++ b/tools/sdk/include/mbedtls/mbedtls/ecdh.h @@ -13,7 +13,7 @@ * Cryptography. */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -54,8 +54,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ECDH_H diff --git a/tools/sdk/include/mbedtls/mbedtls/ecdsa.h b/tools/sdk/include/mbedtls/mbedtls/ecdsa.h index bc219dcad75..da02b278643 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ecdsa.h +++ b/tools/sdk/include/mbedtls/mbedtls/ecdsa.h @@ -11,7 +11,7 @@ * */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -52,8 +52,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ECDSA_H diff --git a/tools/sdk/include/mbedtls/mbedtls/ecjpake.h b/tools/sdk/include/mbedtls/mbedtls/ecjpake.h index 1b6c6ac244e..a9b68d00c61 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ecjpake.h +++ b/tools/sdk/include/mbedtls/mbedtls/ecjpake.h @@ -4,7 +4,7 @@ * \brief Elliptic curve J-PAKE */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ECJPAKE_H #define MBEDTLS_ECJPAKE_H diff --git a/tools/sdk/include/mbedtls/mbedtls/ecp.h b/tools/sdk/include/mbedtls/mbedtls/ecp.h index 8db206060b2..e4a1ed81cf0 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ecp.h +++ b/tools/sdk/include/mbedtls/mbedtls/ecp.h @@ -15,7 +15,7 @@ */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -56,8 +56,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ECP_H @@ -156,6 +154,40 @@ typedef struct mbedtls_ecp_point } mbedtls_ecp_point; +/* Determine the minimum safe value of MBEDTLS_ECP_MAX_BITS. */ +#if !defined(MBEDTLS_ECP_C) +#define MBEDTLS_ECP_MAX_BITS_MIN 0 +/* Note: the curves must be listed in DECREASING size! */ +#elif defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 521 +#elif defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 512 +#elif defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 448 +#elif defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 384 +#elif defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 384 +#elif defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 256 +#elif defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 256 +#elif defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 256 +#elif defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 255 +#elif defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 225 // n is slightly above 2^224 +#elif defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 224 +#elif defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 192 +#elif defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 192 +#else +#error "MBEDTLS_ECP_C enabled, but no curve?" +#endif + #if !defined(MBEDTLS_ECP_ALT) /* * default mbed TLS elliptic curve arithmetic implementation @@ -230,7 +262,13 @@ mbedtls_ecp_group; * \{ */ -#if !defined(MBEDTLS_ECP_MAX_BITS) +#if defined(MBEDTLS_ECP_MAX_BITS) + +#if MBEDTLS_ECP_MAX_BITS < MBEDTLS_ECP_MAX_BITS_MIN +#error "MBEDTLS_ECP_MAX_BITS is smaller than the largest supported curve" +#endif + +#else /** * The maximum size of the groups, that is, of \c N and \c P. */ diff --git a/tools/sdk/include/mbedtls/mbedtls/ecp_internal.h b/tools/sdk/include/mbedtls/mbedtls/ecp_internal.h index 4e9445ae444..0047bd4ef91 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ecp_internal.h +++ b/tools/sdk/include/mbedtls/mbedtls/ecp_internal.h @@ -5,7 +5,7 @@ * point arithmetic. */ /* - * Copyright (C) 2016, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -46,8 +46,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ /* diff --git a/tools/sdk/include/mbedtls/mbedtls/entropy.h b/tools/sdk/include/mbedtls/mbedtls/entropy.h index fd70cd7e9e0..1d6e9b821bf 100644 --- a/tools/sdk/include/mbedtls/mbedtls/entropy.h +++ b/tools/sdk/include/mbedtls/mbedtls/entropy.h @@ -4,7 +4,7 @@ * \brief Entropy accumulator implementation */ /* - * Copyright (C) 2006-2016, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ENTROPY_H #define MBEDTLS_ENTROPY_H @@ -149,13 +147,15 @@ mbedtls_entropy_source_state; */ typedef struct mbedtls_entropy_context { - int accumulator_started; + int accumulator_started; /* 0 after init. + * 1 after the first update. + * -1 after free. */ #if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR) mbedtls_sha512_context accumulator; #else mbedtls_sha256_context accumulator; #endif - int source_count; + int source_count; /* Number of entries used in source. */ mbedtls_entropy_source_state source[MBEDTLS_ENTROPY_MAX_SOURCES]; #if defined(MBEDTLS_HAVEGE_C) mbedtls_havege_state havege_data; diff --git a/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h b/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h index 9843a9e460b..c348fe52d42 100644 --- a/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h +++ b/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h @@ -4,7 +4,7 @@ * \brief Platform-specific and custom entropy polling functions */ /* - * Copyright (C) 2006-2016, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ENTROPY_POLL_H #define MBEDTLS_ENTROPY_POLL_H diff --git a/tools/sdk/include/mbedtls/mbedtls/error.h b/tools/sdk/include/mbedtls/mbedtls/error.h index 3ee7bbba892..fa8582a3914 100644 --- a/tools/sdk/include/mbedtls/mbedtls/error.h +++ b/tools/sdk/include/mbedtls/mbedtls/error.h @@ -4,7 +4,7 @@ * \brief Error to string translation */ /* - * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ERROR_H #define MBEDTLS_ERROR_H diff --git a/tools/sdk/include/mbedtls/mbedtls/gcm.h b/tools/sdk/include/mbedtls/mbedtls/gcm.h index 52d03b0ce89..1201fbd4f10 100644 --- a/tools/sdk/include/mbedtls/mbedtls/gcm.h +++ b/tools/sdk/include/mbedtls/mbedtls/gcm.h @@ -12,7 +12,7 @@ * */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -53,8 +53,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_GCM_H @@ -184,7 +182,7 @@ int mbedtls_gcm_setkey( mbedtls_gcm_context *ctx, * than zero, this must be a writable buffer of at least that * size in Bytes. * \param tag_len The length of the tag to generate. - * \param tag The buffer for holding the tag. This must be a readable + * \param tag The buffer for holding the tag. This must be a writable * buffer of at least \p tag_len Bytes. * * \return \c 0 if the encryption or decryption was performed @@ -312,7 +310,7 @@ int mbedtls_gcm_update( mbedtls_gcm_context *ctx, * tag. The tag can have a maximum length of 16 Bytes. * * \param ctx The GCM context. This must be initialized. - * \param tag The buffer for holding the tag. This must be a readable + * \param tag The buffer for holding the tag. This must be a writable * buffer of at least \p tag_len Bytes. * \param tag_len The length of the tag to generate. This must be at least * four. diff --git a/tools/sdk/include/mbedtls/mbedtls/havege.h b/tools/sdk/include/mbedtls/mbedtls/havege.h index 75ab3cb9637..e90839ddeb4 100644 --- a/tools/sdk/include/mbedtls/mbedtls/havege.h +++ b/tools/sdk/include/mbedtls/mbedtls/havege.h @@ -4,7 +4,7 @@ * \brief HAVEGE: HArdware Volatile Entropy Gathering and Expansion */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_HAVEGE_H #define MBEDTLS_HAVEGE_H diff --git a/tools/sdk/include/mbedtls/mbedtls/hkdf.h b/tools/sdk/include/mbedtls/mbedtls/hkdf.h index a8db554d9f4..07ffe83b23d 100644 --- a/tools/sdk/include/mbedtls/mbedtls/hkdf.h +++ b/tools/sdk/include/mbedtls/mbedtls/hkdf.h @@ -7,7 +7,7 @@ * specified by RFC 5869. */ /* - * Copyright (C) 2016-2019, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -48,8 +48,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_HKDF_H #define MBEDTLS_HKDF_H diff --git a/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h b/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h index 231fb459bcf..5718e187a9f 100644 --- a/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h +++ b/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h @@ -8,7 +8,7 @@ * Deterministic Random Bit Generators. */ /* - * Copyright (C) 2006-2019, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -49,8 +49,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_HMAC_DRBG_H #define MBEDTLS_HMAC_DRBG_H @@ -130,6 +128,14 @@ typedef struct mbedtls_hmac_drbg_context void *p_entropy; /*!< context for the entropy function */ #if defined(MBEDTLS_THREADING_C) + /* Invariant: the mutex is initialized if and only if + * md_ctx->md_info != NULL. This means that the mutex is initialized + * during the initial seeding in mbedtls_hmac_drbg_seed() or + * mbedtls_hmac_drbg_seed_buf() and freed in mbedtls_ctr_drbg_free(). + * + * Note that this invariant may change without notice. Do not rely on it + * and do not access the mutex directly in application code. + */ mbedtls_threading_mutex_t mutex; #endif } mbedtls_hmac_drbg_context; @@ -140,6 +146,10 @@ typedef struct mbedtls_hmac_drbg_context * This function makes the context ready for mbedtls_hmac_drbg_seed(), * mbedtls_hmac_drbg_seed_buf() or mbedtls_hmac_drbg_free(). * + * \note The reseed interval is #MBEDTLS_HMAC_DRBG_RESEED_INTERVAL + * by default. Override this value by calling + * mbedtls_hmac_drbg_set_reseed_interval(). + * * \param ctx HMAC_DRBG context to be initialized. */ void mbedtls_hmac_drbg_init( mbedtls_hmac_drbg_context *ctx ); @@ -175,7 +185,17 @@ void mbedtls_hmac_drbg_init( mbedtls_hmac_drbg_context *ctx ); * \note During the initial seeding, this function calls * the entropy source to obtain a nonce * whose length is half the entropy length. - * + */ +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * after this function returns successfully, + * it is safe to call mbedtls_hmac_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** * \param ctx HMAC_DRBG context to be seeded. * \param md_info MD algorithm to use for HMAC_DRBG. * \param f_entropy The entropy callback, taking as arguments the @@ -214,7 +234,17 @@ int mbedtls_hmac_drbg_seed( mbedtls_hmac_drbg_context *ctx, * * This function is meant for use in algorithms that need a pseudorandom * input such as deterministic ECDSA. - * + */ +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * after this function returns successfully, + * it is safe to call mbedtls_hmac_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** * \param ctx HMAC_DRBG context to be initialised. * \param md_info MD algorithm to use for HMAC_DRBG. * \param data Concatenation of the initial entropy string and @@ -277,6 +307,11 @@ void mbedtls_hmac_drbg_set_reseed_interval( mbedtls_hmac_drbg_context *ctx, /** * \brief This function updates the state of the HMAC_DRBG context. * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * * \param ctx The HMAC_DRBG context. * \param additional The data to update the state with. * If this is \c NULL, there is no additional data. @@ -293,6 +328,11 @@ int mbedtls_hmac_drbg_update_ret( mbedtls_hmac_drbg_context *ctx, * \brief This function reseeds the HMAC_DRBG context, that is * extracts data from the entropy source. * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * * \param ctx The HMAC_DRBG context. * \param additional Additional data to add to the state. * If this is \c NULL, there is no additional data @@ -318,6 +358,11 @@ int mbedtls_hmac_drbg_reseed( mbedtls_hmac_drbg_context *ctx, * This function automatically reseeds if the reseed counter is exceeded * or prediction resistance is enabled. * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * * \param p_rng The HMAC_DRBG context. This must be a pointer to a * #mbedtls_hmac_drbg_context structure. * \param output The buffer to fill. @@ -347,7 +392,16 @@ int mbedtls_hmac_drbg_random_with_add( void *p_rng, * * This function automatically reseeds if the reseed counter is exceeded * or prediction resistance is enabled. - * + */ +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * it is safe to call mbedtls_ctr_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** * \param p_rng The HMAC_DRBG context. This must be a pointer to a * #mbedtls_hmac_drbg_context structure. * \param output The buffer to fill. @@ -363,7 +417,8 @@ int mbedtls_hmac_drbg_random_with_add( void *p_rng, int mbedtls_hmac_drbg_random( void *p_rng, unsigned char *output, size_t out_len ); /** - * \brief Free an HMAC_DRBG context + * \brief This function resets HMAC_DRBG context to the state immediately + * after initial call of mbedtls_hmac_drbg_init(). * * \param ctx The HMAC_DRBG context to free. */ diff --git a/tools/sdk/include/mbedtls/mbedtls/md.h b/tools/sdk/include/mbedtls/mbedtls/md.h index 6a21f059082..2ba8d9e7a91 100644 --- a/tools/sdk/include/mbedtls/mbedtls/md.h +++ b/tools/sdk/include/mbedtls/mbedtls/md.h @@ -6,7 +6,7 @@ * \author Adriaan de Jong */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -47,8 +47,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_MD_H diff --git a/tools/sdk/include/mbedtls/mbedtls/md2.h b/tools/sdk/include/mbedtls/mbedtls/md2.h index 6d563b41bec..9607df66baf 100644 --- a/tools/sdk/include/mbedtls/mbedtls/md2.h +++ b/tools/sdk/include/mbedtls/mbedtls/md2.h @@ -8,7 +8,7 @@ * instead. */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -50,8 +50,6 @@ * * ********** * - * This file is part of mbed TLS (https://tls.mbed.org) - * */ #ifndef MBEDTLS_MD2_H #define MBEDTLS_MD2_H diff --git a/tools/sdk/include/mbedtls/mbedtls/md4.h b/tools/sdk/include/mbedtls/mbedtls/md4.h index 3f4bcdc607b..6ceaf7a2f69 100644 --- a/tools/sdk/include/mbedtls/mbedtls/md4.h +++ b/tools/sdk/include/mbedtls/mbedtls/md4.h @@ -8,7 +8,7 @@ * instead. */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -50,8 +50,6 @@ * * ********** * - * This file is part of mbed TLS (https://tls.mbed.org) - * */ #ifndef MBEDTLS_MD4_H #define MBEDTLS_MD4_H diff --git a/tools/sdk/include/mbedtls/mbedtls/md5.h b/tools/sdk/include/mbedtls/mbedtls/md5.h index 34279c72121..b9d0ca929a0 100644 --- a/tools/sdk/include/mbedtls/mbedtls/md5.h +++ b/tools/sdk/include/mbedtls/mbedtls/md5.h @@ -8,7 +8,7 @@ * digests instead. */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -49,8 +49,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_MD5_H #define MBEDTLS_MD5_H diff --git a/tools/sdk/include/mbedtls/mbedtls/md_internal.h b/tools/sdk/include/mbedtls/mbedtls/md_internal.h index 154b8bbc270..847f50aa0a8 100644 --- a/tools/sdk/include/mbedtls/mbedtls/md_internal.h +++ b/tools/sdk/include/mbedtls/mbedtls/md_internal.h @@ -8,7 +8,7 @@ * \author Adriaan de Jong */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -49,8 +49,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_MD_WRAP_H #define MBEDTLS_MD_WRAP_H diff --git a/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h b/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h index c1e0926b13f..89c06174957 100644 --- a/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h +++ b/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h @@ -4,7 +4,7 @@ * \brief Buffer-based memory allocator */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_MEMORY_BUFFER_ALLOC_H #define MBEDTLS_MEMORY_BUFFER_ALLOC_H diff --git a/tools/sdk/include/mbedtls/mbedtls/net.h b/tools/sdk/include/mbedtls/mbedtls/net.h index bba4a359406..6c7a49d3bdf 100644 --- a/tools/sdk/include/mbedtls/mbedtls/net.h +++ b/tools/sdk/include/mbedtls/mbedtls/net.h @@ -6,7 +6,7 @@ * \deprecated Superseded by mbedtls/net_sockets.h */ /* - * Copyright (C) 2006-2016, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -47,8 +47,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #if !defined(MBEDTLS_CONFIG_FILE) #include "config.h" diff --git a/tools/sdk/include/mbedtls/mbedtls/net_sockets.h b/tools/sdk/include/mbedtls/mbedtls/net_sockets.h index d4d23fe9d89..c6e1a0270e8 100644 --- a/tools/sdk/include/mbedtls/mbedtls/net_sockets.h +++ b/tools/sdk/include/mbedtls/mbedtls/net_sockets.h @@ -20,7 +20,7 @@ * */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -61,8 +61,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_NET_SOCKETS_H #define MBEDTLS_NET_SOCKETS_H @@ -153,6 +151,7 @@ int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char * * \return 0 if successful, or one of: * MBEDTLS_ERR_NET_SOCKET_FAILED, + * MBEDTLS_ERR_NET_UNKNOWN_HOST, * MBEDTLS_ERR_NET_BIND_FAILED, * MBEDTLS_ERR_NET_LISTEN_FAILED * @@ -172,6 +171,8 @@ int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char * can be NULL if client_ip is null * * \return 0 if successful, or + * MBEDTLS_ERR_NET_SOCKET_FAILED, + * MBEDTLS_ERR_NET_BIND_FAILED, * MBEDTLS_ERR_NET_ACCEPT_FAILED, or * MBEDTLS_ERR_NET_BUFFER_TOO_SMALL if buf_size is too small, * MBEDTLS_ERR_SSL_WANT_READ if bind_fd was set to @@ -184,6 +185,10 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, /** * \brief Check and wait for the context to be ready for read/write * + * \note The current implementation of this function uses + * select() and returns an error if the file descriptor + * is \c FD_SETSIZE or greater. + * * \param ctx Socket to check * \param rw Bitflag composed of MBEDTLS_NET_POLL_READ and * MBEDTLS_NET_POLL_WRITE specifying the events @@ -265,16 +270,21 @@ int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ); * 'timeout' seconds. If no error occurs, the actual amount * read is returned. * + * \note The current implementation of this function uses + * select() and returns an error if the file descriptor + * is \c FD_SETSIZE or greater. + * * \param ctx Socket * \param buf The buffer to write to * \param len Maximum length of the buffer * \param timeout Maximum number of milliseconds to wait for data * 0 means no timeout (wait forever) * - * \return the number of bytes received, - * or a non-zero error code: - * MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out, + * \return The number of bytes received if successful. + * MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out. * MBEDTLS_ERR_SSL_WANT_READ if interrupted by a signal. + * Another negative error code (MBEDTLS_ERR_NET_xxx) + * for other failures. * * \note This function will block (until data becomes available or * timeout is reached) even if the socket is set to diff --git a/tools/sdk/include/mbedtls/mbedtls/nist_kw.h b/tools/sdk/include/mbedtls/mbedtls/nist_kw.h index f2b9cebf9ca..94356569942 100644 --- a/tools/sdk/include/mbedtls/mbedtls/nist_kw.h +++ b/tools/sdk/include/mbedtls/mbedtls/nist_kw.h @@ -16,7 +16,7 @@ * */ /* - * Copyright (C) 2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -57,8 +57,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_NIST_KW_H diff --git a/tools/sdk/include/mbedtls/mbedtls/oid.h b/tools/sdk/include/mbedtls/mbedtls/oid.h index 7fe4b386215..4a7e3b4b3fd 100644 --- a/tools/sdk/include/mbedtls/mbedtls/oid.h +++ b/tools/sdk/include/mbedtls/mbedtls/oid.h @@ -4,7 +4,7 @@ * \brief Object Identifier (OID) database */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_OID_H #define MBEDTLS_OID_H diff --git a/tools/sdk/include/mbedtls/mbedtls/padlock.h b/tools/sdk/include/mbedtls/mbedtls/padlock.h index bd476f5f385..0e4a6bbf69f 100644 --- a/tools/sdk/include/mbedtls/mbedtls/padlock.h +++ b/tools/sdk/include/mbedtls/mbedtls/padlock.h @@ -8,7 +8,7 @@ * functions; you must not call them directly. */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -49,8 +49,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PADLOCK_H #define MBEDTLS_PADLOCK_H @@ -100,7 +98,7 @@ extern "C" { * * \param feature The feature to detect * - * \return 1 if CPU has support for the feature, 0 otherwise + * \return non-zero if CPU has support for the feature, 0 otherwise */ int mbedtls_padlock_has_support( int feature ); diff --git a/tools/sdk/include/mbedtls/mbedtls/pem.h b/tools/sdk/include/mbedtls/mbedtls/pem.h index 16b6101415a..c9df7ca6e86 100644 --- a/tools/sdk/include/mbedtls/mbedtls/pem.h +++ b/tools/sdk/include/mbedtls/mbedtls/pem.h @@ -4,7 +4,7 @@ * \brief Privacy Enhanced Mail (PEM) decoding */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PEM_H #define MBEDTLS_PEM_H @@ -139,17 +137,27 @@ void mbedtls_pem_free( mbedtls_pem_context *ctx ); * \brief Write a buffer of PEM information from a DER encoded * buffer. * - * \param header header string to write - * \param footer footer string to write - * \param der_data DER data to write - * \param der_len length of the DER data - * \param buf buffer to write to - * \param buf_len length of output buffer - * \param olen total length written / required (if buf_len is not enough) - * - * \return 0 on success, or a specific PEM or BASE64 error code. On - * MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL olen is the required - * size. + * \param header The header string to write. + * \param footer The footer string to write. + * \param der_data The DER data to encode. + * \param der_len The length of the DER data \p der_data in Bytes. + * \param buf The buffer to write to. + * \param buf_len The length of the output buffer \p buf in Bytes. + * \param olen The address at which to store the total length written + * or required (if \p buf_len is not enough). + * + * \note You may pass \c NULL for \p buf and \c 0 for \p buf_len + * to request the length of the resulting PEM buffer in + * `*olen`. + * + * \note This function may be called with overlapping \p der_data + * and \p buf buffers. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL if \p buf isn't large + * enough to hold the PEM buffer. In this case, `*olen` holds + * the required minimum size of \p buf. + * \return Another PEM or BASE64 error code on other kinds of failure. */ int mbedtls_pem_write_buffer( const char *header, const char *footer, const unsigned char *der_data, size_t der_len, diff --git a/tools/sdk/include/mbedtls/mbedtls/pk.h b/tools/sdk/include/mbedtls/mbedtls/pk.h index 408f7baee7d..20d51d4f38c 100644 --- a/tools/sdk/include/mbedtls/mbedtls/pk.h +++ b/tools/sdk/include/mbedtls/mbedtls/pk.h @@ -4,7 +4,7 @@ * \brief Public Key abstraction layer */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PK_H diff --git a/tools/sdk/include/mbedtls/mbedtls/pk_internal.h b/tools/sdk/include/mbedtls/mbedtls/pk_internal.h index 1cd05943bac..3f84cdf7489 100644 --- a/tools/sdk/include/mbedtls/mbedtls/pk_internal.h +++ b/tools/sdk/include/mbedtls/mbedtls/pk_internal.h @@ -4,7 +4,7 @@ * \brief Public Key abstraction layer: wrapper functions */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PK_WRAP_H diff --git a/tools/sdk/include/mbedtls/mbedtls/pkcs11.h b/tools/sdk/include/mbedtls/mbedtls/pkcs11.h index e1446120c85..3874d4a05ee 100644 --- a/tools/sdk/include/mbedtls/mbedtls/pkcs11.h +++ b/tools/sdk/include/mbedtls/mbedtls/pkcs11.h @@ -6,7 +6,7 @@ * \author Adriaan de Jong */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -47,8 +47,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PKCS11_H #define MBEDTLS_PKCS11_H diff --git a/tools/sdk/include/mbedtls/mbedtls/pkcs12.h b/tools/sdk/include/mbedtls/mbedtls/pkcs12.h index c418e8f243d..9cbcb173055 100644 --- a/tools/sdk/include/mbedtls/mbedtls/pkcs12.h +++ b/tools/sdk/include/mbedtls/mbedtls/pkcs12.h @@ -4,7 +4,7 @@ * \brief PKCS#12 Personal Information Exchange Syntax */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PKCS12_H #define MBEDTLS_PKCS12_H diff --git a/tools/sdk/include/mbedtls/mbedtls/pkcs5.h b/tools/sdk/include/mbedtls/mbedtls/pkcs5.h index c3f645aff1b..328633c492d 100644 --- a/tools/sdk/include/mbedtls/mbedtls/pkcs5.h +++ b/tools/sdk/include/mbedtls/mbedtls/pkcs5.h @@ -6,7 +6,7 @@ * \author Mathias Olsson */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -47,8 +47,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PKCS5_H #define MBEDTLS_PKCS5_H diff --git a/tools/sdk/include/mbedtls/mbedtls/platform.h b/tools/sdk/include/mbedtls/mbedtls/platform.h index dcb5a88eebd..689cfc6ec79 100644 --- a/tools/sdk/include/mbedtls/mbedtls/platform.h +++ b/tools/sdk/include/mbedtls/mbedtls/platform.h @@ -13,7 +13,7 @@ * dynamically configured at runtime. */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -54,8 +54,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PLATFORM_H #define MBEDTLS_PLATFORM_H diff --git a/tools/sdk/include/mbedtls/mbedtls/platform_time.h b/tools/sdk/include/mbedtls/mbedtls/platform_time.h index a45870c3a65..e132f6a688c 100644 --- a/tools/sdk/include/mbedtls/mbedtls/platform_time.h +++ b/tools/sdk/include/mbedtls/mbedtls/platform_time.h @@ -4,7 +4,7 @@ * \brief mbed TLS Platform time abstraction */ /* - * Copyright (C) 2006-2016, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PLATFORM_TIME_H #define MBEDTLS_PLATFORM_TIME_H diff --git a/tools/sdk/include/mbedtls/mbedtls/platform_util.h b/tools/sdk/include/mbedtls/mbedtls/platform_util.h index f10574afe6f..426afaf0401 100644 --- a/tools/sdk/include/mbedtls/mbedtls/platform_util.h +++ b/tools/sdk/include/mbedtls/mbedtls/platform_util.h @@ -5,7 +5,7 @@ * library. */ /* - * Copyright (C) 2018, Arm Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -46,8 +46,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PLATFORM_UTIL_H #define MBEDTLS_PLATFORM_UTIL_H diff --git a/tools/sdk/include/mbedtls/mbedtls/poly1305.h b/tools/sdk/include/mbedtls/mbedtls/poly1305.h index 6e45b2c2ba0..b337aa841ca 100644 --- a/tools/sdk/include/mbedtls/mbedtls/poly1305.h +++ b/tools/sdk/include/mbedtls/mbedtls/poly1305.h @@ -13,7 +13,7 @@ */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -54,8 +54,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_POLY1305_H diff --git a/tools/sdk/include/mbedtls/mbedtls/ripemd160.h b/tools/sdk/include/mbedtls/mbedtls/ripemd160.h index 505c39252e5..31c6637d6dc 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ripemd160.h +++ b/tools/sdk/include/mbedtls/mbedtls/ripemd160.h @@ -4,7 +4,7 @@ * \brief RIPE MD-160 message digest */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_RIPEMD160_H #define MBEDTLS_RIPEMD160_H diff --git a/tools/sdk/include/mbedtls/mbedtls/rsa.h b/tools/sdk/include/mbedtls/mbedtls/rsa.h index cd22fc4c1fb..b2f65334fe7 100644 --- a/tools/sdk/include/mbedtls/mbedtls/rsa.h +++ b/tools/sdk/include/mbedtls/mbedtls/rsa.h @@ -10,7 +10,7 @@ * */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -51,8 +51,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_RSA_H #define MBEDTLS_RSA_H @@ -126,7 +124,10 @@ extern "C" { */ typedef struct mbedtls_rsa_context { - int ver; /*!< Always 0.*/ + int ver; /*!< Reserved for internal purposes. + * Do not set this field in application + * code. Its meaning might change without + * notice. */ size_t len; /*!< The size of \p N in Bytes. */ mbedtls_mpi N; /*!< The public modulus. */ @@ -156,6 +157,7 @@ typedef struct mbedtls_rsa_context mask generating function used in the EME-OAEP and EMSA-PSS encodings. */ #if defined(MBEDTLS_THREADING_C) + /* Invariant: the mutex is initialized iff ver != 0. */ mbedtls_threading_mutex_t mutex; /*!< Thread-safety mutex. */ #endif } diff --git a/tools/sdk/include/mbedtls/mbedtls/rsa_internal.h b/tools/sdk/include/mbedtls/mbedtls/rsa_internal.h index 2464e6b082b..953cb7b81d7 100644 --- a/tools/sdk/include/mbedtls/mbedtls/rsa_internal.h +++ b/tools/sdk/include/mbedtls/mbedtls/rsa_internal.h @@ -35,7 +35,7 @@ * */ /* - * Copyright (C) 2006-2017, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -77,8 +77,6 @@ * * ********** * - * This file is part of mbed TLS (https://tls.mbed.org) - * */ #ifndef MBEDTLS_RSA_INTERNAL_H diff --git a/tools/sdk/include/mbedtls/mbedtls/sha1.h b/tools/sdk/include/mbedtls/mbedtls/sha1.h index e69db8a15a0..60c514a49ec 100644 --- a/tools/sdk/include/mbedtls/mbedtls/sha1.h +++ b/tools/sdk/include/mbedtls/mbedtls/sha1.h @@ -11,7 +11,7 @@ * digests instead. */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -52,8 +52,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SHA1_H #define MBEDTLS_SHA1_H diff --git a/tools/sdk/include/mbedtls/mbedtls/sha256.h b/tools/sdk/include/mbedtls/mbedtls/sha256.h index 5b03bc31dc9..b1881e183c4 100644 --- a/tools/sdk/include/mbedtls/mbedtls/sha256.h +++ b/tools/sdk/include/mbedtls/mbedtls/sha256.h @@ -7,7 +7,7 @@ * hash functions are defined in FIPS 180-4: Secure Hash Standard (SHS). */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -48,8 +48,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SHA256_H #define MBEDTLS_SHA256_H diff --git a/tools/sdk/include/mbedtls/mbedtls/sha512.h b/tools/sdk/include/mbedtls/mbedtls/sha512.h index 2fbc69f80e6..5e5a15e0008 100644 --- a/tools/sdk/include/mbedtls/mbedtls/sha512.h +++ b/tools/sdk/include/mbedtls/mbedtls/sha512.h @@ -6,7 +6,7 @@ * hash functions are defined in FIPS 180-4: Secure Hash Standard (SHS). */ /* - * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -47,8 +47,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SHA512_H #define MBEDTLS_SHA512_H @@ -154,8 +152,7 @@ int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, /** * \brief This function finishes the SHA-512 operation, and writes - * the result to the output buffer. This function is for - * internal use only. + * the result to the output buffer. * * \param ctx The SHA-512 context. This must be initialized * and have a hash operation started. @@ -171,6 +168,7 @@ int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx, /** * \brief This function processes a single data block within * the ongoing SHA-512 computation. + * This function is for internal use only. * * \param ctx The SHA-512 context. This must be initialized. * \param data The buffer holding one block of data. This diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl.h b/tools/sdk/include/mbedtls/mbedtls/ssl.h index 6f56983562e..0abeb430e49 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ssl.h +++ b/tools/sdk/include/mbedtls/mbedtls/ssl.h @@ -4,7 +4,7 @@ * \brief SSL/TLS functions. */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_H #define MBEDTLS_SSL_H @@ -1411,7 +1409,7 @@ void mbedtls_ssl_conf_dbg( mbedtls_ssl_config *conf, * \note For DTLS, you need to provide either a non-NULL * f_recv_timeout callback, or a f_recv that doesn't block. * - * \note See the documentations of \c mbedtls_ssl_sent_t, + * \note See the documentations of \c mbedtls_ssl_send_t, * \c mbedtls_ssl_recv_t and \c mbedtls_ssl_recv_timeout_t for * the conventions those callbacks must follow. * @@ -2239,7 +2237,7 @@ void mbedtls_ssl_conf_dhm_min_bitlen( mbedtls_ssl_config *conf, #if defined(MBEDTLS_ECP_C) /** * \brief Set the allowed curves in order of preference. - * (Default: all defined curves.) + * (Default: all defined curves in order of decreasing size.) * * On server: this only affects selection of the ECDHE curve; * the curves used for ECDH and ECDSA are determined by the @@ -2271,7 +2269,9 @@ void mbedtls_ssl_conf_curves( mbedtls_ssl_config *conf, #if defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED) /** * \brief Set the allowed hashes for signatures during the handshake. - * (Default: all available hashes except MD5.) + * (Default: all SHA-2 hashes, largest first. Also SHA-1 if + * the compile-time option + * `MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE` is enabled.) * * \note This only affects which hashes are offered and can be used * for signatures during the handshake. Hashes for message diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h b/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h index e987c29e110..612d81776ef 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h +++ b/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h @@ -4,7 +4,7 @@ * \brief SSL session cache implementation */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_CACHE_H #define MBEDTLS_SSL_CACHE_H diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h b/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h index 8969141165e..ab8e601db71 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h +++ b/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h @@ -4,7 +4,7 @@ * \brief SSL Ciphersuites for mbed TLS */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_CIPHERSUITES_H #define MBEDTLS_SSL_CIPHERSUITES_H diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h b/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h index 71e056781c5..9c2d5b62a43 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h +++ b/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h @@ -4,7 +4,7 @@ * \brief DTLS cookie callbacks implementation */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_COOKIE_H #define MBEDTLS_SSL_COOKIE_H diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h b/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h index b371094f1e8..6ba6c2af09d 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h +++ b/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h @@ -4,7 +4,7 @@ * \brief Internal functions shared by the SSL modules */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_INTERNAL_H #define MBEDTLS_SSL_INTERNAL_H @@ -152,6 +150,24 @@ #define MBEDTLS_SSL_RETRANS_WAITING 2 #define MBEDTLS_SSL_RETRANS_FINISHED 3 +/* This macro determines whether CBC is supported. */ +#if defined(MBEDTLS_CIPHER_MODE_CBC) && \ + ( defined(MBEDTLS_AES_C) || \ + defined(MBEDTLS_CAMELLIA_C) || \ + defined(MBEDTLS_ARIA_C) || \ + defined(MBEDTLS_DES_C) ) +#define MBEDTLS_SSL_SOME_SUITES_USE_CBC +#endif + +/* This macro determines whether the CBC construct used in TLS 1.0-1.2 (as + * opposed to the very different CBC construct used in SSLv3) is supported. */ +#if defined(MBEDTLS_SSL_SOME_SUITES_USE_CBC) && \ + ( defined(MBEDTLS_SSL_PROTO_TLS1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) ) +#define MBEDTLS_SSL_SOME_SUITES_USE_TLS_CBC +#endif + /* * Allow extra bytes for record, authentication and encryption overhead: * counter (8) + header (5) + IV(16) + MAC (16-48) + padding (0-256) @@ -843,6 +859,73 @@ int mbedtls_ssl_get_key_exchange_md_tls1_2( mbedtls_ssl_context *ssl, #endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 || \ MBEDTLS_SSL_PROTO_TLS1_2 */ +#if defined(MBEDTLS_SSL_SOME_SUITES_USE_TLS_CBC) +/** \brief Compute the HMAC of variable-length data with constant flow. + * + * This function computes the HMAC of the concatenation of \p add_data and \p + * data, and does with a code flow and memory access pattern that does not + * depend on \p data_len_secret, but only on \p min_data_len and \p + * max_data_len. In particular, this function always reads exactly \p + * max_data_len bytes from \p data. + * + * \param ctx The HMAC context. It must have keys configured + * with mbedtls_md_hmac_starts() and use one of the + * following hashes: SHA-384, SHA-256, SHA-1 or MD-5. + * It is reset using mbedtls_md_hmac_reset() after + * the computation is complete to prepare for the + * next computation. + * \param add_data The additional data prepended to \p data. This + * must point to a readable buffer of \p add_data_len + * bytes. + * \param add_data_len The length of \p add_data in bytes. + * \param data The data appended to \p add_data. This must point + * to a readable buffer of \p max_data_len bytes. + * \param data_len_secret The length of the data to process in \p data. + * This must be no less than \p min_data_len and no + * greater than \p max_data_len. + * \param min_data_len The minimal length of \p data in bytes. + * \param max_data_len The maximal length of \p data in bytes. + * \param output The HMAC will be written here. This must point to + * a writable buffer of sufficient size to hold the + * HMAC value. + * + * \retval 0 + * Success. + * \retval MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED + * The hardware accelerator failed. + */ +int mbedtls_ssl_cf_hmac( + mbedtls_md_context_t *ctx, + const unsigned char *add_data, size_t add_data_len, + const unsigned char *data, size_t data_len_secret, + size_t min_data_len, size_t max_data_len, + unsigned char *output ); + +/** \brief Copy data from a secret position with constant flow. + * + * This function copies \p len bytes from \p src_base + \p offset_secret to \p + * dst, with a code flow and memory access pattern that does not depend on \p + * offset_secret, but only on \p offset_min, \p offset_max and \p len. + * + * \param dst The destination buffer. This must point to a writable + * buffer of at least \p len bytes. + * \param src_base The base of the source buffer. This must point to a + * readable buffer of at least \p offset_max + \p len + * bytes. + * \param offset_secret The offset in the source buffer from which to copy. + * This must be no less than \p offset_min and no greater + * than \p offset_max. + * \param offset_min The minimal value of \p offset_secret. + * \param offset_max The maximal value of \p offset_secret. + * \param len The number of bytes to copy. + */ +void mbedtls_ssl_cf_memcpy_offset( unsigned char *dst, + const unsigned char *src_base, + size_t offset_secret, + size_t offset_min, size_t offset_max, + size_t len ); +#endif /* MBEDTLS_SSL_SOME_SUITES_USE_TLS_CBC */ + #ifdef __cplusplus } #endif diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h b/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h index ac3be043374..a83f5e66623 100644 --- a/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h +++ b/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h @@ -4,7 +4,7 @@ * \brief TLS server ticket callbacks implementation */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_TICKET_H #define MBEDTLS_SSL_TICKET_H @@ -126,7 +124,7 @@ void mbedtls_ssl_ticket_init( mbedtls_ssl_ticket_context *ctx ); * Recommended value: 86400 (one day). * * \note It is highly recommended to select a cipher that is at - * least as strong as the the strongest ciphersuite + * least as strong as the strongest ciphersuite * supported. Usually that means a 256-bit key. * * \note The lifetime of the keys is twice the lifetime of tickets. diff --git a/tools/sdk/include/mbedtls/mbedtls/threading.h b/tools/sdk/include/mbedtls/mbedtls/threading.h index b6ec4df8e95..45161ce467c 100644 --- a/tools/sdk/include/mbedtls/mbedtls/threading.h +++ b/tools/sdk/include/mbedtls/mbedtls/threading.h @@ -4,7 +4,7 @@ * \brief Threading abstraction layer */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_THREADING_H #define MBEDTLS_THREADING_H @@ -75,6 +73,9 @@ extern "C" { typedef struct mbedtls_threading_mutex_t { pthread_mutex_t mutex; + /* is_valid is 0 after a failed init or a free, and nonzero after a + * successful init. This field is not considered part of the public + * API of Mbed TLS and may change without notice. */ char is_valid; } mbedtls_threading_mutex_t; #endif diff --git a/tools/sdk/include/mbedtls/mbedtls/timing.h b/tools/sdk/include/mbedtls/mbedtls/timing.h index 149ccfb6660..8611ba9a4e5 100644 --- a/tools/sdk/include/mbedtls/mbedtls/timing.h +++ b/tools/sdk/include/mbedtls/mbedtls/timing.h @@ -4,7 +4,7 @@ * \brief Portable interface to timeouts and to the CPU cycle counter */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_TIMING_H #define MBEDTLS_TIMING_H diff --git a/tools/sdk/include/mbedtls/mbedtls/version.h b/tools/sdk/include/mbedtls/mbedtls/version.h index 2bff31d51f1..49cbeb003a8 100644 --- a/tools/sdk/include/mbedtls/mbedtls/version.h +++ b/tools/sdk/include/mbedtls/mbedtls/version.h @@ -4,7 +4,7 @@ * \brief Run-time version information */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ /* * This set of compile-time defines and run-time variables can be used to @@ -67,16 +65,16 @@ */ #define MBEDTLS_VERSION_MAJOR 2 #define MBEDTLS_VERSION_MINOR 16 -#define MBEDTLS_VERSION_PATCH 7 +#define MBEDTLS_VERSION_PATCH 11 /** * The single version number has the following structure: * MMNNPP00 * Major version | Minor version | Patch version */ -#define MBEDTLS_VERSION_NUMBER 0x02100700 -#define MBEDTLS_VERSION_STRING "2.16.7" -#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.16.7" +#define MBEDTLS_VERSION_NUMBER 0x02100B00 +#define MBEDTLS_VERSION_STRING "2.16.11" +#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.16.11" #if defined(MBEDTLS_VERSION_C) diff --git a/tools/sdk/include/mbedtls/mbedtls/x509.h b/tools/sdk/include/mbedtls/mbedtls/x509.h index e9f2fc60245..5bb9b00292f 100644 --- a/tools/sdk/include/mbedtls/mbedtls/x509.h +++ b/tools/sdk/include/mbedtls/mbedtls/x509.h @@ -4,7 +4,7 @@ * \brief X.509 generic defines and structures */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_H #define MBEDTLS_X509_H diff --git a/tools/sdk/include/mbedtls/mbedtls/x509_crl.h b/tools/sdk/include/mbedtls/mbedtls/x509_crl.h index 0e37f65e8f0..2ade47c89db 100644 --- a/tools/sdk/include/mbedtls/mbedtls/x509_crl.h +++ b/tools/sdk/include/mbedtls/mbedtls/x509_crl.h @@ -4,7 +4,7 @@ * \brief X.509 certificate revocation list parsing */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_CRL_H #define MBEDTLS_X509_CRL_H diff --git a/tools/sdk/include/mbedtls/mbedtls/x509_crt.h b/tools/sdk/include/mbedtls/mbedtls/x509_crt.h index 4aae923ea02..30da1909b74 100644 --- a/tools/sdk/include/mbedtls/mbedtls/x509_crt.h +++ b/tools/sdk/include/mbedtls/mbedtls/x509_crt.h @@ -4,7 +4,7 @@ * \brief X.509 certificate parsing and writing */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_CRT_H #define MBEDTLS_X509_CRT_H @@ -231,12 +229,21 @@ typedef void mbedtls_x509_crt_restart_ctx; /** * Default security profile. Should provide a good balance between security * and compatibility with current deployments. + * + * This profile permits: + * - SHA2 hashes. + * - All supported elliptic curves. + * - RSA with 2048 bits and above. + * + * New minor versions of Mbed TLS may extend this profile, for example if + * new curves are added to the library. New minor versions of Mbed TLS will + * not reduce this profile unless serious security concerns require it. */ extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_default; /** * Expected next default profile. Recommended for new deployments. - * Currently targets a 128-bit security level, except for RSA-2048. + * Currently targets a 128-bit security level, except for allowing RSA-2048. */ extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_next; diff --git a/tools/sdk/include/mbedtls/mbedtls/x509_csr.h b/tools/sdk/include/mbedtls/mbedtls/x509_csr.h index 8ba2cda0dc5..5dfb4213e8d 100644 --- a/tools/sdk/include/mbedtls/mbedtls/x509_csr.h +++ b/tools/sdk/include/mbedtls/mbedtls/x509_csr.h @@ -4,7 +4,7 @@ * \brief X.509 certificate signing request parsing and writing */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_CSR_H #define MBEDTLS_X509_CSR_H diff --git a/tools/sdk/include/mbedtls/mbedtls/xtea.h b/tools/sdk/include/mbedtls/mbedtls/xtea.h index d372110215f..cd6d3753d13 100644 --- a/tools/sdk/include/mbedtls/mbedtls/xtea.h +++ b/tools/sdk/include/mbedtls/mbedtls/xtea.h @@ -4,7 +4,7 @@ * \brief XTEA block cipher (32-bit) */ /* - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright The Mbed TLS Contributors * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is provided under the Apache License 2.0, or the @@ -45,8 +45,6 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * ********** - * - * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_XTEA_H #define MBEDTLS_XTEA_H diff --git a/tools/sdk/include/micro-ecc/micro-ecc/types.h b/tools/sdk/include/micro-ecc/micro-ecc/types.h new file mode 100644 index 00000000000..9ee81438fac --- /dev/null +++ b/tools/sdk/include/micro-ecc/micro-ecc/types.h @@ -0,0 +1,108 @@ +/* Copyright 2015, Kenneth MacKay. Licensed under the BSD 2-clause license. */ + +#ifndef _UECC_TYPES_H_ +#define _UECC_TYPES_H_ + +#ifndef uECC_PLATFORM + #if __AVR__ + #define uECC_PLATFORM uECC_avr + #elif defined(__thumb2__) || defined(_M_ARMT) /* I think MSVC only supports Thumb-2 targets */ + #define uECC_PLATFORM uECC_arm_thumb2 + #elif defined(__thumb__) + #define uECC_PLATFORM uECC_arm_thumb + #elif defined(__arm__) || defined(_M_ARM) + #define uECC_PLATFORM uECC_arm + #elif defined(__aarch64__) + #define uECC_PLATFORM uECC_arm64 + #elif defined(__i386__) || defined(_M_IX86) || defined(_X86_) || defined(__I86__) + #define uECC_PLATFORM uECC_x86 + #elif defined(__amd64__) || defined(_M_X64) + #define uECC_PLATFORM uECC_x86_64 + #else + #define uECC_PLATFORM uECC_arch_other + #endif +#endif + +#ifndef uECC_ARM_USE_UMAAL + #if (uECC_PLATFORM == uECC_arm) && (__ARM_ARCH >= 6) + #define uECC_ARM_USE_UMAAL 1 + #elif (uECC_PLATFORM == uECC_arm_thumb2) && (__ARM_ARCH >= 6) && !__ARM_ARCH_7M__ + #define uECC_ARM_USE_UMAAL 1 + #else + #define uECC_ARM_USE_UMAAL 0 + #endif +#endif + +#ifndef uECC_WORD_SIZE + #if uECC_PLATFORM == uECC_avr + #define uECC_WORD_SIZE 1 + #elif (uECC_PLATFORM == uECC_x86_64 || uECC_PLATFORM == uECC_arm64) + #define uECC_WORD_SIZE 8 + #else + #define uECC_WORD_SIZE 4 + #endif +#endif + +#if (uECC_WORD_SIZE != 1) && (uECC_WORD_SIZE != 4) && (uECC_WORD_SIZE != 8) + #error "Unsupported value for uECC_WORD_SIZE" +#endif + +#if ((uECC_PLATFORM == uECC_avr) && (uECC_WORD_SIZE != 1)) + #pragma message ("uECC_WORD_SIZE must be 1 for AVR") + #undef uECC_WORD_SIZE + #define uECC_WORD_SIZE 1 +#endif + +#if ((uECC_PLATFORM == uECC_arm || uECC_PLATFORM == uECC_arm_thumb || \ + uECC_PLATFORM == uECC_arm_thumb2) && \ + (uECC_WORD_SIZE != 4)) + #pragma message ("uECC_WORD_SIZE must be 4 for ARM") + #undef uECC_WORD_SIZE + #define uECC_WORD_SIZE 4 +#endif + +#if defined(__SIZEOF_INT128__) || ((__clang_major__ * 100 + __clang_minor__) >= 302) + #define SUPPORTS_INT128 1 +#else + #define SUPPORTS_INT128 0 +#endif + +typedef int8_t wordcount_t; +typedef int16_t bitcount_t; +typedef int8_t cmpresult_t; + +#if (uECC_WORD_SIZE == 1) + +typedef uint8_t uECC_word_t; +typedef uint16_t uECC_dword_t; + +#define HIGH_BIT_SET 0x80 +#define uECC_WORD_BITS 8 +#define uECC_WORD_BITS_SHIFT 3 +#define uECC_WORD_BITS_MASK 0x07 + +#elif (uECC_WORD_SIZE == 4) + +typedef uint32_t uECC_word_t; +typedef uint64_t uECC_dword_t; + +#define HIGH_BIT_SET 0x80000000 +#define uECC_WORD_BITS 32 +#define uECC_WORD_BITS_SHIFT 5 +#define uECC_WORD_BITS_MASK 0x01F + +#elif (uECC_WORD_SIZE == 8) + +typedef uint64_t uECC_word_t; +#if SUPPORTS_INT128 +typedef unsigned __int128 uECC_dword_t; +#endif + +#define HIGH_BIT_SET 0x8000000000000000ull +#define uECC_WORD_BITS 64 +#define uECC_WORD_BITS_SHIFT 6 +#define uECC_WORD_BITS_MASK 0x03F + +#endif /* uECC_WORD_SIZE */ + +#endif /* _UECC_TYPES_H_ */ diff --git a/tools/sdk/include/micro-ecc/micro-ecc/uECC.h b/tools/sdk/include/micro-ecc/micro-ecc/uECC.h new file mode 100644 index 00000000000..43a19d63cb2 --- /dev/null +++ b/tools/sdk/include/micro-ecc/micro-ecc/uECC.h @@ -0,0 +1,365 @@ +/* Copyright 2014, Kenneth MacKay. Licensed under the BSD 2-clause license. */ + +#ifndef _UECC_H_ +#define _UECC_H_ + +#include + +/* Platform selection options. +If uECC_PLATFORM is not defined, the code will try to guess it based on compiler macros. +Possible values for uECC_PLATFORM are defined below: */ +#define uECC_arch_other 0 +#define uECC_x86 1 +#define uECC_x86_64 2 +#define uECC_arm 3 +#define uECC_arm_thumb 4 +#define uECC_arm_thumb2 5 +#define uECC_arm64 6 +#define uECC_avr 7 + +/* If desired, you can define uECC_WORD_SIZE as appropriate for your platform (1, 4, or 8 bytes). +If uECC_WORD_SIZE is not explicitly defined then it will be automatically set based on your +platform. */ + +/* Optimization level; trade speed for code size. + Larger values produce code that is faster but larger. + Currently supported values are 0 - 4; 0 is unusably slow for most applications. + Optimization level 4 currently only has an effect ARM platforms where more than one + curve is enabled. */ +#ifndef uECC_OPTIMIZATION_LEVEL + #define uECC_OPTIMIZATION_LEVEL 2 +#endif + +/* uECC_SQUARE_FUNC - If enabled (defined as nonzero), this will cause a specific function to be +used for (scalar) squaring instead of the generic multiplication function. This can make things +faster somewhat faster, but increases the code size. */ +#ifndef uECC_SQUARE_FUNC + #define uECC_SQUARE_FUNC 0 +#endif + +/* uECC_VLI_NATIVE_LITTLE_ENDIAN - If enabled (defined as nonzero), this will switch to native +little-endian format for *all* arrays passed in and out of the public API. This includes public +and private keys, shared secrets, signatures and message hashes. +Using this switch reduces the amount of call stack memory used by uECC, since less intermediate +translations are required. +Note that this will *only* work on native little-endian processors and it will treat the uint8_t +arrays passed into the public API as word arrays, therefore requiring the provided byte arrays +to be word aligned on architectures that do not support unaligned accesses. +IMPORTANT: Keys and signatures generated with uECC_VLI_NATIVE_LITTLE_ENDIAN=1 are incompatible +with keys and signatures generated with uECC_VLI_NATIVE_LITTLE_ENDIAN=0; all parties must use +the same endianness. */ +#ifndef uECC_VLI_NATIVE_LITTLE_ENDIAN + #define uECC_VLI_NATIVE_LITTLE_ENDIAN 0 +#endif + +/* Curve support selection. Set to 0 to remove that curve. */ +#ifndef uECC_SUPPORTS_secp160r1 + #define uECC_SUPPORTS_secp160r1 1 +#endif +#ifndef uECC_SUPPORTS_secp192r1 + #define uECC_SUPPORTS_secp192r1 1 +#endif +#ifndef uECC_SUPPORTS_secp224r1 + #define uECC_SUPPORTS_secp224r1 1 +#endif +#ifndef uECC_SUPPORTS_secp256r1 + #define uECC_SUPPORTS_secp256r1 1 +#endif +#ifndef uECC_SUPPORTS_secp256k1 + #define uECC_SUPPORTS_secp256k1 1 +#endif + +/* Specifies whether compressed point format is supported. + Set to 0 to disable point compression/decompression functions. */ +#ifndef uECC_SUPPORT_COMPRESSED_POINT + #define uECC_SUPPORT_COMPRESSED_POINT 1 +#endif + +struct uECC_Curve_t; +typedef const struct uECC_Curve_t * uECC_Curve; + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if uECC_SUPPORTS_secp160r1 +uECC_Curve uECC_secp160r1(void); +#endif +#if uECC_SUPPORTS_secp192r1 +uECC_Curve uECC_secp192r1(void); +#endif +#if uECC_SUPPORTS_secp224r1 +uECC_Curve uECC_secp224r1(void); +#endif +#if uECC_SUPPORTS_secp256r1 +uECC_Curve uECC_secp256r1(void); +#endif +#if uECC_SUPPORTS_secp256k1 +uECC_Curve uECC_secp256k1(void); +#endif + +/* uECC_RNG_Function type +The RNG function should fill 'size' random bytes into 'dest'. It should return 1 if +'dest' was filled with random data, or 0 if the random data could not be generated. +The filled-in values should be either truly random, or from a cryptographically-secure PRNG. + +A correctly functioning RNG function must be set (using uECC_set_rng()) before calling +uECC_make_key() or uECC_sign(). + +Setting a correctly functioning RNG function improves the resistance to side-channel attacks +for uECC_shared_secret() and uECC_sign_deterministic(). + +A correct RNG function is set by default when building for Windows, Linux, or OS X. +If you are building on another POSIX-compliant system that supports /dev/random or /dev/urandom, +you can define uECC_POSIX to use the predefined RNG. For embedded platforms there is no predefined +RNG function; you must provide your own. +*/ +typedef int (*uECC_RNG_Function)(uint8_t *dest, unsigned size); + +/* uECC_set_rng() function. +Set the function that will be used to generate random bytes. The RNG function should +return 1 if the random data was generated, or 0 if the random data could not be generated. + +On platforms where there is no predefined RNG function (eg embedded platforms), this must +be called before uECC_make_key() or uECC_sign() are used. + +Inputs: + rng_function - The function that will be used to generate random bytes. +*/ +void uECC_set_rng(uECC_RNG_Function rng_function); + +/* uECC_get_rng() function. + +Returns the function that will be used to generate random bytes. +*/ +uECC_RNG_Function uECC_get_rng(void); + +/* uECC_curve_private_key_size() function. + +Returns the size of a private key for the curve in bytes. +*/ +int uECC_curve_private_key_size(uECC_Curve curve); + +/* uECC_curve_public_key_size() function. + +Returns the size of a public key for the curve in bytes. +*/ +int uECC_curve_public_key_size(uECC_Curve curve); + +/* uECC_make_key() function. +Create a public/private key pair. + +Outputs: + public_key - Will be filled in with the public key. Must be at least 2 * the curve size + (in bytes) long. For example, if the curve is secp256r1, public_key must be 64 + bytes long. + private_key - Will be filled in with the private key. Must be as long as the curve order; this + is typically the same as the curve size, except for secp160r1. For example, if the + curve is secp256r1, private_key must be 32 bytes long. + + For secp160r1, private_key must be 21 bytes long! Note that the first byte will + almost always be 0 (there is about a 1 in 2^80 chance of it being non-zero). + +Returns 1 if the key pair was generated successfully, 0 if an error occurred. +*/ +int uECC_make_key(uint8_t *public_key, uint8_t *private_key, uECC_Curve curve); + +/* uECC_shared_secret() function. +Compute a shared secret given your secret key and someone else's public key. +Note: It is recommended that you hash the result of uECC_shared_secret() before using it for +symmetric encryption or HMAC. + +Inputs: + public_key - The public key of the remote party. + private_key - Your private key. + +Outputs: + secret - Will be filled in with the shared secret value. Must be the same size as the + curve size; for example, if the curve is secp256r1, secret must be 32 bytes long. + +Returns 1 if the shared secret was generated successfully, 0 if an error occurred. +*/ +int uECC_shared_secret(const uint8_t *public_key, + const uint8_t *private_key, + uint8_t *secret, + uECC_Curve curve); + +#if uECC_SUPPORT_COMPRESSED_POINT +/* uECC_compress() function. +Compress a public key. + +Inputs: + public_key - The public key to compress. + +Outputs: + compressed - Will be filled in with the compressed public key. Must be at least + (curve size + 1) bytes long; for example, if the curve is secp256r1, + compressed must be 33 bytes long. +*/ +void uECC_compress(const uint8_t *public_key, uint8_t *compressed, uECC_Curve curve); + +/* uECC_decompress() function. +Decompress a compressed public key. + +Inputs: + compressed - The compressed public key. + +Outputs: + public_key - Will be filled in with the decompressed public key. +*/ +void uECC_decompress(const uint8_t *compressed, uint8_t *public_key, uECC_Curve curve); +#endif /* uECC_SUPPORT_COMPRESSED_POINT */ + +/* uECC_valid_public_key() function. +Check to see if a public key is valid. + +Note that you are not required to check for a valid public key before using any other uECC +functions. However, you may wish to avoid spending CPU time computing a shared secret or +verifying a signature using an invalid public key. + +Inputs: + public_key - The public key to check. + +Returns 1 if the public key is valid, 0 if it is invalid. +*/ +int uECC_valid_public_key(const uint8_t *public_key, uECC_Curve curve); + +/* uECC_compute_public_key() function. +Compute the corresponding public key for a private key. + +Inputs: + private_key - The private key to compute the public key for + +Outputs: + public_key - Will be filled in with the corresponding public key + +Returns 1 if the key was computed successfully, 0 if an error occurred. +*/ +int uECC_compute_public_key(const uint8_t *private_key, uint8_t *public_key, uECC_Curve curve); + +/* uECC_sign() function. +Generate an ECDSA signature for a given hash value. + +Usage: Compute a hash of the data you wish to sign (SHA-2 is recommended) and pass it in to +this function along with your private key. + +Inputs: + private_key - Your private key. + message_hash - The hash of the message to sign. + hash_size - The size of message_hash in bytes. + +Outputs: + signature - Will be filled in with the signature value. Must be at least 2 * curve size long. + For example, if the curve is secp256r1, signature must be 64 bytes long. + +Returns 1 if the signature generated successfully, 0 if an error occurred. +*/ +int uECC_sign(const uint8_t *private_key, + const uint8_t *message_hash, + unsigned hash_size, + uint8_t *signature, + uECC_Curve curve); + +/* uECC_HashContext structure. +This is used to pass in an arbitrary hash function to uECC_sign_deterministic(). +The structure will be used for multiple hash computations; each time a new hash +is computed, init_hash() will be called, followed by one or more calls to +update_hash(), and finally a call to finish_hash() to produce the resulting hash. + +The intention is that you will create a structure that includes uECC_HashContext +followed by any hash-specific data. For example: + +typedef struct SHA256_HashContext { + uECC_HashContext uECC; + SHA256_CTX ctx; +} SHA256_HashContext; + +void init_SHA256(uECC_HashContext *base) { + SHA256_HashContext *context = (SHA256_HashContext *)base; + SHA256_Init(&context->ctx); +} + +void update_SHA256(uECC_HashContext *base, + const uint8_t *message, + unsigned message_size) { + SHA256_HashContext *context = (SHA256_HashContext *)base; + SHA256_Update(&context->ctx, message, message_size); +} + +void finish_SHA256(uECC_HashContext *base, uint8_t *hash_result) { + SHA256_HashContext *context = (SHA256_HashContext *)base; + SHA256_Final(hash_result, &context->ctx); +} + +... when signing ... +{ + uint8_t tmp[32 + 32 + 64]; + SHA256_HashContext ctx = {{&init_SHA256, &update_SHA256, &finish_SHA256, 64, 32, tmp}}; + uECC_sign_deterministic(key, message_hash, &ctx.uECC, signature); +} +*/ +typedef struct uECC_HashContext { + void (*init_hash)(const struct uECC_HashContext *context); + void (*update_hash)(const struct uECC_HashContext *context, + const uint8_t *message, + unsigned message_size); + void (*finish_hash)(const struct uECC_HashContext *context, uint8_t *hash_result); + unsigned block_size; /* Hash function block size in bytes, eg 64 for SHA-256. */ + unsigned result_size; /* Hash function result size in bytes, eg 32 for SHA-256. */ + uint8_t *tmp; /* Must point to a buffer of at least (2 * result_size + block_size) bytes. */ +} uECC_HashContext; + +/* uECC_sign_deterministic() function. +Generate an ECDSA signature for a given hash value, using a deterministic algorithm +(see RFC 6979). You do not need to set the RNG using uECC_set_rng() before calling +this function; however, if the RNG is defined it will improve resistance to side-channel +attacks. + +Usage: Compute a hash of the data you wish to sign (SHA-2 is recommended) and pass it to +this function along with your private key and a hash context. Note that the message_hash +does not need to be computed with the same hash function used by hash_context. + +Inputs: + private_key - Your private key. + message_hash - The hash of the message to sign. + hash_size - The size of message_hash in bytes. + hash_context - A hash context to use. + +Outputs: + signature - Will be filled in with the signature value. + +Returns 1 if the signature generated successfully, 0 if an error occurred. +*/ +int uECC_sign_deterministic(const uint8_t *private_key, + const uint8_t *message_hash, + unsigned hash_size, + const uECC_HashContext *hash_context, + uint8_t *signature, + uECC_Curve curve); + +/* uECC_verify() function. +Verify an ECDSA signature. + +Usage: Compute the hash of the signed data using the same hash as the signer and +pass it to this function along with the signer's public key and the signature values (r and s). + +Inputs: + public_key - The signer's public key. + message_hash - The hash of the signed data. + hash_size - The size of message_hash in bytes. + signature - The signature value. + +Returns 1 if the signature is valid, 0 if it is invalid. +*/ +int uECC_verify(const uint8_t *public_key, + const uint8_t *message_hash, + unsigned hash_size, + const uint8_t *signature, + uECC_Curve curve); + +#ifdef __cplusplus +} /* end of extern "C" */ +#endif + +#endif /* _UECC_H_ */ diff --git a/tools/sdk/include/micro-ecc/micro-ecc/uECC_vli.h b/tools/sdk/include/micro-ecc/micro-ecc/uECC_vli.h new file mode 100644 index 00000000000..864cc333569 --- /dev/null +++ b/tools/sdk/include/micro-ecc/micro-ecc/uECC_vli.h @@ -0,0 +1,172 @@ +/* Copyright 2015, Kenneth MacKay. Licensed under the BSD 2-clause license. */ + +#ifndef _UECC_VLI_H_ +#define _UECC_VLI_H_ + +#include "uECC.h" +#include "types.h" + +/* Functions for raw large-integer manipulation. These are only available + if uECC.c is compiled with uECC_ENABLE_VLI_API defined to 1. */ +#ifndef uECC_ENABLE_VLI_API + #define uECC_ENABLE_VLI_API 0 +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if uECC_ENABLE_VLI_API + +void uECC_vli_clear(uECC_word_t *vli, wordcount_t num_words); + +/* Constant-time comparison to zero - secure way to compare long integers */ +/* Returns 1 if vli == 0, 0 otherwise. */ +uECC_word_t uECC_vli_isZero(const uECC_word_t *vli, wordcount_t num_words); + +/* Returns nonzero if bit 'bit' of vli is set. */ +uECC_word_t uECC_vli_testBit(const uECC_word_t *vli, bitcount_t bit); + +/* Counts the number of bits required to represent vli. */ +bitcount_t uECC_vli_numBits(const uECC_word_t *vli, const wordcount_t max_words); + +/* Sets dest = src. */ +void uECC_vli_set(uECC_word_t *dest, const uECC_word_t *src, wordcount_t num_words); + +/* Constant-time comparison function - secure way to compare long integers */ +/* Returns one if left == right, zero otherwise */ +uECC_word_t uECC_vli_equal(const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +/* Constant-time comparison function - secure way to compare long integers */ +/* Returns sign of left - right, in constant time. */ +cmpresult_t uECC_vli_cmp(const uECC_word_t *left, const uECC_word_t *right, wordcount_t num_words); + +/* Computes vli = vli >> 1. */ +void uECC_vli_rshift1(uECC_word_t *vli, wordcount_t num_words); + +/* Computes result = left + right, returning carry. Can modify in place. */ +uECC_word_t uECC_vli_add(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +/* Computes result = left - right, returning borrow. Can modify in place. */ +uECC_word_t uECC_vli_sub(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +/* Computes result = left * right. Result must be 2 * num_words long. */ +void uECC_vli_mult(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +/* Computes result = left^2. Result must be 2 * num_words long. */ +void uECC_vli_square(uECC_word_t *result, const uECC_word_t *left, wordcount_t num_words); + +/* Computes result = (left + right) % mod. + Assumes that left < mod and right < mod, and that result does not overlap mod. */ +void uECC_vli_modAdd(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Computes result = (left - right) % mod. + Assumes that left < mod and right < mod, and that result does not overlap mod. */ +void uECC_vli_modSub(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Computes result = product % mod, where product is 2N words long. + Currently only designed to work for mod == curve->p or curve_n. */ +void uECC_vli_mmod(uECC_word_t *result, + uECC_word_t *product, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Calculates result = product (mod curve->p), where product is up to + 2 * curve->num_words long. */ +void uECC_vli_mmod_fast(uECC_word_t *result, uECC_word_t *product, uECC_Curve curve); + +/* Computes result = (left * right) % mod. + Currently only designed to work for mod == curve->p or curve_n. */ +void uECC_vli_modMult(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Computes result = (left * right) % curve->p. */ +void uECC_vli_modMult_fast(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + uECC_Curve curve); + +/* Computes result = left^2 % mod. + Currently only designed to work for mod == curve->p or curve_n. */ +void uECC_vli_modSquare(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Computes result = left^2 % curve->p. */ +void uECC_vli_modSquare_fast(uECC_word_t *result, const uECC_word_t *left, uECC_Curve curve); + +/* Computes result = (1 / input) % mod.*/ +void uECC_vli_modInv(uECC_word_t *result, + const uECC_word_t *input, + const uECC_word_t *mod, + wordcount_t num_words); + +#if uECC_SUPPORT_COMPRESSED_POINT +/* Calculates a = sqrt(a) (mod curve->p) */ +void uECC_vli_mod_sqrt(uECC_word_t *a, uECC_Curve curve); +#endif + +/* Converts an integer in uECC native format to big-endian bytes. */ +void uECC_vli_nativeToBytes(uint8_t *bytes, int num_bytes, const uECC_word_t *native); +/* Converts big-endian bytes to an integer in uECC native format. */ +void uECC_vli_bytesToNative(uECC_word_t *native, const uint8_t *bytes, int num_bytes); + +unsigned uECC_curve_num_words(uECC_Curve curve); +unsigned uECC_curve_num_bytes(uECC_Curve curve); +unsigned uECC_curve_num_bits(uECC_Curve curve); +unsigned uECC_curve_num_n_words(uECC_Curve curve); +unsigned uECC_curve_num_n_bytes(uECC_Curve curve); +unsigned uECC_curve_num_n_bits(uECC_Curve curve); + +const uECC_word_t *uECC_curve_p(uECC_Curve curve); +const uECC_word_t *uECC_curve_n(uECC_Curve curve); +const uECC_word_t *uECC_curve_G(uECC_Curve curve); +const uECC_word_t *uECC_curve_b(uECC_Curve curve); + +int uECC_valid_point(const uECC_word_t *point, uECC_Curve curve); + +/* Multiplies a point by a scalar. Points are represented by the X coordinate followed by + the Y coordinate in the same array, both coordinates are curve->num_words long. Note + that scalar must be curve->num_n_words long (NOT curve->num_words). */ +void uECC_point_mult(uECC_word_t *result, + const uECC_word_t *point, + const uECC_word_t *scalar, + uECC_Curve curve); + +/* Generates a random integer in the range 0 < random < top. + Both random and top have num_words words. */ +int uECC_generate_random_int(uECC_word_t *random, + const uECC_word_t *top, + wordcount_t num_words); + +#endif /* uECC_ENABLE_VLI_API */ + +#ifdef __cplusplus +} /* end of extern "C" */ +#endif + +#endif /* _UECC_VLI_H_ */ diff --git a/tools/sdk/include/micro-ecc/uECC_verify_antifault.h b/tools/sdk/include/micro-ecc/uECC_verify_antifault.h new file mode 100644 index 00000000000..fa14b24f665 --- /dev/null +++ b/tools/sdk/include/micro-ecc/uECC_verify_antifault.h @@ -0,0 +1,18 @@ +/* Copyright 2014, Kenneth MacKay. Licensed under the BSD 2-clause license. + + Modifications Copyright 2020, Espressif Systems (Shanghai) PTE LTD. Licensed under the BSD + 2-clause license. +*/ +#pragma once +#include "uECC.h" + +/* Version uECC_verify() that also copies message_hash to verified_hash + if the signature is valid, and does it in a way that is harder to attack + with fault injection. +*/ +int uECC_verify_antifault(const uint8_t *public_key, + const uint8_t *message_hash, + unsigned hash_size, + const uint8_t *signature, + uECC_Curve curve, + uint8_t *verified_hash); diff --git a/tools/sdk/include/mqtt/mqtt_client.h b/tools/sdk/include/mqtt/mqtt_client.h index 67c082825c3..5d019fa870a 100644 --- a/tools/sdk/include/mqtt/mqtt_client.h +++ b/tools/sdk/include/mqtt/mqtt_client.h @@ -12,11 +12,7 @@ #include #include "esp_err.h" -#include "mqtt_config.h" #include "esp_event.h" -#if CONFIG_ESP_TLS_USE_DS_PERIPHERAL -#include "rsa_sign_alt.h" -#endif #ifdef __cplusplus extern "C" { @@ -61,6 +57,13 @@ typedef enum { and current data offset updating. */ MQTT_EVENT_BEFORE_CONNECT, /*!< The event occurs before connecting */ + MQTT_EVENT_DELETED, /*!< Notification on delete of one message from the internal outbox, + if the message couldn't have been sent and acknowledged before expiring + defined in OUTBOX_EXPIRED_TIMEOUT_MS. + (events are not posted upon deletion of successfully acknowledged messages) + - This event id is posted only if MQTT_REPORT_DELETED_MESSAGES==1 + - Additional context: msg_id (id of the deleted message). + */ } esp_mqtt_event_id_t; /** @@ -306,8 +309,10 @@ int esp_mqtt_client_unsubscribe(esp_mqtt_client_handle_t client, const char *top * - This API might block for several seconds, either due to network timeout (10s) * or if publishing payloads longer than internal buffer (due to message * fragmentation) - * - Client doesn't have to be connected to send publish message - * (although it would drop all qos=0 messages, qos>1 messages would be enqueued) + * - Client doesn't have to be connected for this API to work, enqueueing the messages + * with qos>1 (returning -1 for all the qos=0 messages if disconnected). + * If MQTT_SKIP_PUBLISH_IF_DISCONNECTED is enabled, this API will not attempt to publish + * when the client is not connected and will always return -1. * - It is thread safe, please refer to `esp_mqtt_client_subscribe` for details * * @param client mqtt client handle @@ -322,6 +327,27 @@ int esp_mqtt_client_unsubscribe(esp_mqtt_client_handle_t client, const char *top */ int esp_mqtt_client_publish(esp_mqtt_client_handle_t client, const char *topic, const char *data, int len, int qos, int retain); +/** + * @brief Enqueue a message to the outbox, to be sent later. Typically used for messages with qos>0, but could + * be also used for qos=0 messages if store=true. + * + * This API generates and stores the publish message into the internal outbox and the actual sending + * to the network is performed in the mqtt-task context (in contrast to the esp_mqtt_client_publish() + * which sends the publish message immediately in the user task's context). + * Thus, it could be used as a non blocking version of esp_mqtt_client_publish(). + * + * @param client mqtt client handle + * @param topic topic string + * @param data payload string (set to NULL, sending empty payload message) + * @param len data length, if set to 0, length is calculated from payload string + * @param qos qos of publish message + * @param retain retain flag + * @param store if true, all messages are enqueued; otherwise only qos1 and qos 2 are enqueued + * + * @return message_id if queued successfully, -1 otherwise + */ +int esp_mqtt_client_enqueue(esp_mqtt_client_handle_t client, const char *topic, const char *data, int len, int qos, int retain, bool store); + /** * @brief Destroys the client handle * diff --git a/tools/sdk/include/mqtt/mqtt_config.h b/tools/sdk/include/mqtt/mqtt_config.h deleted file mode 100644 index d9b64c7594b..00000000000 --- a/tools/sdk/include/mqtt/mqtt_config.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is subject to the terms and conditions defined in - * file 'LICENSE', which is part of this source code package. - * Tuan PM - */ -#ifndef _MQTT_CONFIG_H_ -#define _MQTT_CONFIG_H_ - -#include "sdkconfig.h" - -#ifdef CONFIG_MQTT_PROTOCOL_311 -#define MQTT_PROTOCOL_311 -#endif - -#define MQTT_RECON_DEFAULT_MS (10*1000) -#define MQTT_POLL_READ_TIMEOUT_MS (1000) - -#if CONFIG_MQTT_BUFFER_SIZE -#define MQTT_BUFFER_SIZE_BYTE CONFIG_MQTT_BUFFER_SIZE -#else -#define MQTT_BUFFER_SIZE_BYTE 1024 -#endif - -#define MQTT_MAX_HOST_LEN 64 -#define MQTT_MAX_CLIENT_LEN 32 -#define MQTT_MAX_USERNAME_LEN 32 -#define MQTT_MAX_PASSWORD_LEN 65 -#define MQTT_MAX_LWT_TOPIC 32 -#define MQTT_MAX_LWT_MSG 128 - -#if CONFIG_MQTT_TASK_PRIORITY -#define MQTT_TASK_PRIORITY CONFIG_MQTT_TASK_PRIORITY -#else -#define MQTT_TASK_PRIORITY 5 -#endif - -#if CONFIG_MQTT_TASK_STACK_SIZE -#define MQTT_TASK_STACK CONFIG_MQTT_TASK_STACK_SIZE -#else -#define MQTT_TASK_STACK (6*1024) -#endif - -#define MQTT_KEEPALIVE_TICK (120) -#define MQTT_CMD_QUEUE_SIZE (10) -#define MQTT_NETWORK_TIMEOUT_MS (10000) - -#ifdef CONFIG_MQTT_TCP_DEFAULT_PORT -#define MQTT_TCP_DEFAULT_PORT CONFIG_MQTT_TCP_DEFAULT_PORT -#else -#define MQTT_TCP_DEFAULT_PORT 1883 -#endif - -#ifdef CONFIG_MQTT_SSL_DEFAULT_PORT -#define MQTT_SSL_DEFAULT_PORT CONFIG_MQTT_SSL_DEFAULT_PORT -#else -#define MQTT_SSL_DEFAULT_PORT 8883 -#endif - -#ifdef CONFIG_MQTT_WS_DEFAULT_PORT -#define MQTT_WS_DEFAULT_PORT CONFIG_MQTT_WS_DEFAULT_PORT -#else -#define MQTT_WS_DEFAULT_PORT 80 -#endif - -#ifdef MQTT_WSS_DEFAULT_PORT -#define MQTT_WSS_DEFAULT_PORT CONFIG_MQTT_WSS_DEFAULT_PORT -#else -#define MQTT_WSS_DEFAULT_PORT 443 -#endif - -#define MQTT_CORE_SELECTION_ENABLED CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED - -#ifdef CONFIG_MQTT_DISABLE_API_LOCKS -#define MQTT_DISABLE_API_LOCKS CONFIG_MQTT_DISABLE_API_LOCKS -#endif - -#ifdef CONFIG_MQTT_USE_CORE_0 -#define MQTT_TASK_CORE 0 -#else -#ifdef CONFIG_MQTT_USE_CORE_1 -#define MQTT_TASK_CORE 1 -#else -#define MQTT_TASK_CORE 0 -#endif -#endif - -#ifdef CONFIG_MQTT_OUTBOX_EXPIRED_TIMEOUT_MS -#define OUTBOX_EXPIRED_TIMEOUT_MS CONFIG_MQTT_OUTBOX_EXPIRED_TIMEOUT_MS -#else -#define OUTBOX_EXPIRED_TIMEOUT_MS (30*1000) -#endif - -#define MQTT_ENABLE_SSL CONFIG_MQTT_TRANSPORT_SSL -#define MQTT_ENABLE_WS CONFIG_MQTT_TRANSPORT_WEBSOCKET -#define MQTT_ENABLE_WSS CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE - - -#define OUTBOX_MAX_SIZE (4*1024) -#endif diff --git a/tools/sdk/include/mqtt/mqtt_supported_features.h b/tools/sdk/include/mqtt/mqtt_supported_features.h deleted file mode 100644 index eb7ad631ca0..00000000000 --- a/tools/sdk/include/mqtt/mqtt_supported_features.h +++ /dev/null @@ -1,63 +0,0 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _MQTT_SUPPORTED_FEATURES_H_ -#define _MQTT_SUPPORTED_FEATURES_H_ - -#if __has_include("esp_idf_version.h") -#include "esp_idf_version.h" -#endif - -/** - * @brief This header defines supported features of IDF which mqtt module - * could use depending on specific version of ESP-IDF. - * In case "esp_idf_version.h" were not found, all additional - * features would be disabled - */ - -#ifdef ESP_IDF_VERSION - -#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(3, 3, 0) -// Features supported from 3.3 -#define MQTT_SUPPORTED_FEATURE_EVENT_LOOP -#define MQTT_SUPPORTED_FEATURE_SKIP_CRT_CMN_NAME_CHECK -#endif - -#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 0, 0) -// Features supported in 4.0 -#define MQTT_SUPPORTED_FEATURE_WS_SUBPROTOCOL -#define MQTT_SUPPORTED_FEATURE_TRANSPORT_ERR_REPORTING -#endif - -#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 1, 0) -// Features supported in 4.1 -#define MQTT_SUPPORTED_FEATURE_PSK_AUTHENTICATION -#define MQTT_SUPPORTED_FEATURE_DER_CERTIFICATES -#define MQTT_SUPPORTED_FEATURE_ALPN -#define MQTT_SUPPORTED_FEATURE_CLIENT_KEY_PASSWORD -#endif - -#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) -// Features supported in 4.2 -#define MQTT_SUPPORTED_FEATURE_SECURE_ELEMENT -#endif - -#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 3, 0) -// Features supported in 4.3 -#define MQTT_SUPPORTED_FEATURE_DIGITAL_SIGNATURE -#define MQTT_SUPPORTED_FEATURE_TRANSPORT_SOCK_ERRNO_REPORTING -#endif - -#endif /* ESP_IDF_VERSION */ -#endif // _MQTT_SUPPORTED_FEATURES_H_ diff --git a/tools/sdk/include/soc/i2c_apll.h b/tools/sdk/include/soc/i2c_apll.h new file mode 100644 index 00000000000..935810afabd --- /dev/null +++ b/tools/sdk/include/soc/i2c_apll.h @@ -0,0 +1,136 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file i2c_apll.h + * @brief Register definitions for audio PLL (APLL) + * + * This file lists register fields of APLL, located on an internal configuration + * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by + * rtc_clk_apll_enable function in rtc_clk.c. + */ + +#define I2C_APLL 0X6D +#define I2C_APLL_HOSTID 3 + +#define I2C_APLL_IR_CAL_DELAY 0 +#define I2C_APLL_IR_CAL_DELAY_MSB 3 +#define I2C_APLL_IR_CAL_DELAY_LSB 0 + +#define I2C_APLL_IR_CAL_RSTB 0 +#define I2C_APLL_IR_CAL_RSTB_MSB 4 +#define I2C_APLL_IR_CAL_RSTB_LSB 4 + +#define I2C_APLL_IR_CAL_START 0 +#define I2C_APLL_IR_CAL_START_MSB 5 +#define I2C_APLL_IR_CAL_START_LSB 5 + +#define I2C_APLL_IR_CAL_UNSTOP 0 +#define I2C_APLL_IR_CAL_UNSTOP_MSB 6 +#define I2C_APLL_IR_CAL_UNSTOP_LSB 6 + +#define I2C_APLL_OC_ENB_FCAL 0 +#define I2C_APLL_OC_ENB_FCAL_MSB 7 +#define I2C_APLL_OC_ENB_FCAL_LSB 7 + +#define I2C_APLL_IR_CAL_EXT_CAP 1 +#define I2C_APLL_IR_CAL_EXT_CAP_MSB 4 +#define I2C_APLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_APLL_IR_CAL_ENX_CAP 1 +#define I2C_APLL_IR_CAL_ENX_CAP_MSB 5 +#define I2C_APLL_IR_CAL_ENX_CAP_LSB 5 + +#define I2C_APLL_OC_LBW 1 +#define I2C_APLL_OC_LBW_MSB 6 +#define I2C_APLL_OC_LBW_LSB 6 + +#define I2C_APLL_IR_CAL_CK_DIV 2 +#define I2C_APLL_IR_CAL_CK_DIV_MSB 3 +#define I2C_APLL_IR_CAL_CK_DIV_LSB 0 + +#define I2C_APLL_OC_DCHGP 2 +#define I2C_APLL_OC_DCHGP_MSB 6 +#define I2C_APLL_OC_DCHGP_LSB 4 + +#define I2C_APLL_OC_ENB_VCON 2 +#define I2C_APLL_OC_ENB_VCON_MSB 7 +#define I2C_APLL_OC_ENB_VCON_LSB 7 + +#define I2C_APLL_OR_CAL_CAP 3 +#define I2C_APLL_OR_CAL_CAP_MSB 4 +#define I2C_APLL_OR_CAL_CAP_LSB 0 + +#define I2C_APLL_OR_CAL_UDF 3 +#define I2C_APLL_OR_CAL_UDF_MSB 5 +#define I2C_APLL_OR_CAL_UDF_LSB 5 + +#define I2C_APLL_OR_CAL_OVF 3 +#define I2C_APLL_OR_CAL_OVF_MSB 6 +#define I2C_APLL_OR_CAL_OVF_LSB 6 + +#define I2C_APLL_OR_CAL_END 3 +#define I2C_APLL_OR_CAL_END_MSB 7 +#define I2C_APLL_OR_CAL_END_LSB 7 + +#define I2C_APLL_OR_OUTPUT_DIV 4 +#define I2C_APLL_OR_OUTPUT_DIV_MSB 4 +#define I2C_APLL_OR_OUTPUT_DIV_LSB 0 + +#define I2C_APLL_OC_TSCHGP 4 +#define I2C_APLL_OC_TSCHGP_MSB 6 +#define I2C_APLL_OC_TSCHGP_LSB 6 + +#define I2C_APLL_EN_FAST_CAL 4 +#define I2C_APLL_EN_FAST_CAL_MSB 7 +#define I2C_APLL_EN_FAST_CAL_LSB 7 + +#define I2C_APLL_OC_DHREF_SEL 5 +#define I2C_APLL_OC_DHREF_SEL_MSB 1 +#define I2C_APLL_OC_DHREF_SEL_LSB 0 + +#define I2C_APLL_OC_DLREF_SEL 5 +#define I2C_APLL_OC_DLREF_SEL_MSB 3 +#define I2C_APLL_OC_DLREF_SEL_LSB 2 + +#define I2C_APLL_SDM_DITHER 5 +#define I2C_APLL_SDM_DITHER_MSB 4 +#define I2C_APLL_SDM_DITHER_LSB 4 + +#define I2C_APLL_SDM_STOP 5 +#define I2C_APLL_SDM_STOP_MSB 5 +#define I2C_APLL_SDM_STOP_LSB 5 + +#define I2C_APLL_SDM_RSTB 5 +#define I2C_APLL_SDM_RSTB_MSB 6 +#define I2C_APLL_SDM_RSTB_LSB 6 + +#define I2C_APLL_OC_DVDD 6 +#define I2C_APLL_OC_DVDD_MSB 4 +#define I2C_APLL_OC_DVDD_LSB 0 + +#define I2C_APLL_DSDM2 7 +#define I2C_APLL_DSDM2_MSB 5 +#define I2C_APLL_DSDM2_LSB 0 + +#define I2C_APLL_DSDM1 8 +#define I2C_APLL_DSDM1_MSB 7 +#define I2C_APLL_DSDM1_LSB 0 + +#define I2C_APLL_DSDM0 9 +#define I2C_APLL_DSDM0_MSB 7 +#define I2C_APLL_DSDM0_LSB 0 + diff --git a/tools/sdk/include/soc/i2c_bbpll.h b/tools/sdk/include/soc/i2c_bbpll.h new file mode 100644 index 00000000000..6889bc7321e --- /dev/null +++ b/tools/sdk/include/soc/i2c_bbpll.h @@ -0,0 +1,208 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file i2c_apll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 4 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DIV_10_8 2 +#define I2C_BBPLL_OC_DIV_10_8_MSB 6 +#define I2C_BBPLL_OC_DIV_10_8_LSB 4 + +#define I2C_BBPLL_OC_LREF 2 +#define I2C_BBPLL_OC_LREF_MSB 7 +#define I2C_BBPLL_OC_LREF_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_OC_ENB_FCAL 4 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 0 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 4 +#define I2C_BBPLL_OC_DCHGP_MSB 3 +#define I2C_BBPLL_OC_DCHGP_LSB 1 + +#define I2C_BBPLL_OC_DHREF_SEL 4 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 4 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OC_DCUR 5 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_OC_BST_DIV 5 +#define I2C_BBPLL_OC_BST_DIV_MSB 3 +#define I2C_BBPLL_OC_BST_DIV_LSB 3 + +#define I2C_BBPLL_OC_BST_E2C 5 +#define I2C_BBPLL_OC_BST_E2C_MSB 4 +#define I2C_BBPLL_OC_BST_E2C_LSB 4 + +#define I2C_BBPLL_OC_TSCHGP 5 +#define I2C_BBPLL_OC_TSCHGP_MSB 5 +#define I2C_BBPLL_OC_TSCHGP_LSB 5 + +#define I2C_BBPLL_OC_BW 5 +#define I2C_BBPLL_OC_BW_MSB 7 +#define I2C_BBPLL_OC_BW_LSB 6 + +#define I2C_BBPLL_OR_LOCK1 6 +#define I2C_BBPLL_OR_LOCK1_MSB 0 +#define I2C_BBPLL_OR_LOCK1_LSB 0 + +#define I2C_BBPLL_OR_LOCK2 6 +#define I2C_BBPLL_OR_LOCK2_MSB 1 +#define I2C_BBPLL_OR_LOCK2_LSB 1 + +#define I2C_BBPLL_OR_CAL_CAP 7 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 7 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 7 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 7 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_BBADC_DELAY1 8 +#define I2C_BBPLL_BBADC_DELAY1_MSB 1 +#define I2C_BBPLL_BBADC_DELAY1_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 8 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DELAY3 8 +#define I2C_BBPLL_BBADC_DELAY3_MSB 5 +#define I2C_BBPLL_BBADC_DELAY3_LSB 4 + +#define I2C_BBPLL_BBADC_DELAY4 8 +#define I2C_BBPLL_BBADC_DELAY4_MSB 7 +#define I2C_BBPLL_BBADC_DELAY4_LSB 6 + +#define I2C_BBPLL_BBADC_DELAY5 9 +#define I2C_BBPLL_BBADC_DELAY5_MSB 1 +#define I2C_BBPLL_BBADC_DELAY5_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY6 9 +#define I2C_BBPLL_BBADC_DELAY6_MSB 3 +#define I2C_BBPLL_BBADC_DELAY6_LSB 2 + +#define I2C_BBPLL_BBADC_DSMP 9 +#define I2C_BBPLL_BBADC_DSMP_MSB 7 +#define I2C_BBPLL_BBADC_DSMP_LSB 4 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 1 +#define I2C_BBPLL_DTEST_LSB 0 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 3 +#define I2C_BBPLL_ENT_ADC_LSB 2 + +#define I2C_BBPLL_BBADC_DIV 10 +#define I2C_BBPLL_BBADC_DIV_MSB 5 +#define I2C_BBPLL_BBADC_DIV_LSB 4 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 6 +#define I2C_BBPLL_ENT_PLL_LSB 6 + +#define I2C_BBPLL_OC_ENB_VCON 10 +#define I2C_BBPLL_OC_ENB_VCON_MSB 7 +#define I2C_BBPLL_OC_ENB_VCON_LSB 7 + +#define I2C_BBPLL_DIV_DAC 11 +#define I2C_BBPLL_DIV_DAC_MSB 0 +#define I2C_BBPLL_DIV_DAC_LSB 0 + +#define I2C_BBPLL_DIV_CPU 11 +#define I2C_BBPLL_DIV_CPU_MSB 1 +#define I2C_BBPLL_DIV_CPU_LSB 1 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 11 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_BBADC_CAL_9_8 11 +#define I2C_BBPLL_BBADC_CAL_9_8_MSB 4 +#define I2C_BBPLL_BBADC_CAL_9_8_LSB 3 + +#define I2C_BBPLL_BBADC_DCM 11 +#define I2C_BBPLL_BBADC_DCM_MSB 6 +#define I2C_BBPLL_BBADC_DCM_LSB 5 + +#define I2C_BBPLL_ENDIV5 11 +#define I2C_BBPLL_ENDIV5_MSB 7 +#define I2C_BBPLL_ENDIV5_LSB 7 + +#define I2C_BBPLL_BBADC_CAL_7_0 12 +#define I2C_BBPLL_BBADC_CAL_7_0_MSB 7 +#define I2C_BBPLL_BBADC_CAL_7_0_LSB 0 + diff --git a/tools/sdk/include/soc/i2c_rtc_clk.h b/tools/sdk/include/soc/i2c_rtc_clk.h new file mode 100644 index 00000000000..3b7a323cd6d --- /dev/null +++ b/tools/sdk/include/soc/i2c_rtc_clk.h @@ -0,0 +1,78 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "i2c_apll.h" +#include "i2c_bbpll.h" +#include + +/* Analog function control register */ +#define ANA_CONFIG_REG 0x6000E044 +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) +/* Clear to enable APLL */ +#define I2C_APLL_M (BIT(14)) +/* Clear to enable BBPLL */ +#define I2C_BBPLL_M (BIT(17)) + +/* ROM functions which read/write internal control bus */ +uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); +uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); +void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); +void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); + +#ifdef BOOTLOADER_BUILD + +/** + * If compiling for the bootloader, ROM functions can be called directly, + * without the need of a lock. + */ +#define regi2c_ctrl_read_reg rom_i2c_readReg +#define regi2c_ctrl_read_reg_mask rom_i2c_readReg_Mask +#define regi2c_ctrl_write_reg rom_i2c_writeReg +#define regi2c_ctrl_write_reg_mask rom_i2c_writeReg_Mask + +#else + +#define i2c_read_reg_raw rom_i2c_readReg +#define i2c_read_reg_mask_raw rom_i2c_readReg_Mask +#define i2c_write_reg_raw rom_i2c_writeReg +#define i2c_write_reg_mask_raw rom_i2c_writeReg_Mask + +uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add); +uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); +void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); +void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); + +#endif // BOOTLOADER_BUILD + +/* Convenience macros for the above functions, these use register definitions + * from i2c_apll.h/i2c_bbpll.h header files. + */ +#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \ + regi2c_ctrl_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) + +#define I2C_READREG_MASK_RTC(block, reg_add) \ + regi2c_ctrl_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) + +#define I2C_WRITEREG_RTC(block, reg_add, indata) \ + regi2c_ctrl_write_reg(block, block##_HOSTID, reg_add, indata) + +#define I2C_READREG_RTC(block, reg_add) \ + regi2c_ctrl_read_reg(block, block##_HOSTID, reg_add) + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/include/soc/include/soc/adc_channel.h b/tools/sdk/include/soc/include/soc/adc_channel.h new file mode 100644 index 00000000000..e8835d35f8f --- /dev/null +++ b/tools/sdk/include/soc/include/soc/adc_channel.h @@ -0,0 +1,72 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_ADC_CHANNEL_H +#define _SOC_ADC_CHANNEL_H + +#define ADC1_GPIO36_CHANNEL ADC1_CHANNEL_0 +#define ADC1_CHANNEL_0_GPIO_NUM 36 + +#define ADC1_GPIO37_CHANNEL ADC1_CHANNEL_1 +#define ADC1_CHANNEL_1_GPIO_NUM 37 + +#define ADC1_GPIO38_CHANNEL ADC1_CHANNEL_2 +#define ADC1_CHANNEL_2_GPIO_NUM 38 + +#define ADC1_GPIO39_CHANNEL ADC1_CHANNEL_3 +#define ADC1_CHANNEL_3_GPIO_NUM 39 + +#define ADC1_GPIO32_CHANNEL ADC1_CHANNEL_4 +#define ADC1_CHANNEL_4_GPIO_NUM 32 + +#define ADC1_GPIO33_CHANNEL ADC1_CHANNEL_5 +#define ADC1_CHANNEL_5_GPIO_NUM 33 + +#define ADC1_GPIO34_CHANNEL ADC1_CHANNEL_6 +#define ADC1_CHANNEL_6_GPIO_NUM 34 + +#define ADC1_GPIO35_CHANNEL ADC1_CHANNEL_7 +#define ADC1_CHANNEL_7_GPIO_NUM 35 + +#define ADC2_GPIO4_CHANNEL ADC2_CHANNEL_0 +#define ADC2_CHANNEL_0_GPIO_NUM 4 + +#define ADC2_GPIO0_CHANNEL ADC2_CHANNEL_1 +#define ADC2_CHANNEL_1_GPIO_NUM 0 + +#define ADC2_GPIO2_CHANNEL ADC2_CHANNEL_2 +#define ADC2_CHANNEL_2_GPIO_NUM 2 + +#define ADC2_GPIO15_CHANNEL ADC2_CHANNEL_3 +#define ADC2_CHANNEL_3_GPIO_NUM 15 + +#define ADC2_GPIO13_CHANNEL ADC2_CHANNEL_4 +#define ADC2_CHANNEL_4_GPIO_NUM 13 + +#define ADC2_GPIO12_CHANNEL ADC2_CHANNEL_5 +#define ADC2_CHANNEL_5_GPIO_NUM 12 + +#define ADC2_GPIO14_CHANNEL ADC2_CHANNEL_6 +#define ADC2_CHANNEL_6_GPIO_NUM 14 + +#define ADC2_GPIO27_CHANNEL ADC2_CHANNEL_7 +#define ADC2_CHANNEL_7_GPIO_NUM 27 + +#define ADC2_GPIO25_CHANNEL ADC2_CHANNEL_8 +#define ADC2_CHANNEL_8_GPIO_NUM 25 + +#define ADC2_GPIO26_CHANNEL ADC2_CHANNEL_9 +#define ADC2_CHANNEL_9_GPIO_NUM 26 + +#endif diff --git a/tools/sdk/include/soc/include/soc/apb_ctrl_reg.h b/tools/sdk/include/soc/include/soc/apb_ctrl_reg.h new file mode 100644 index 00000000000..2e5ea54c4c7 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/apb_ctrl_reg.h @@ -0,0 +1,294 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_REG_H_ +#define _SOC_APB_CTRL_REG_H_ + +#include "soc.h" +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) +/* APB_CTRL_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_QUICK_CLK_CHNG (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_M (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_V 0x1 +#define APB_CTRL_QUICK_CLK_CHNG_S 13 +/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_V 0x1 +#define APB_CTRL_RST_TICK_CNT_S 12 +/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (BIT(11)) +#define APB_CTRL_CLK_EN_V 0x1 +#define APB_CTRL_CLK_EN_S 11 +/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (BIT(10)) +#define APB_CTRL_CLK_320M_EN_V 0x1 +#define APB_CTRL_CLK_320M_EN_S 10 +/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define APB_CTRL_PRE_DIV_CNT 0x000003FF +#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) +#define APB_CTRL_PRE_DIV_CNT_V 0x3FF +#define APB_CTRL_PRE_DIV_CNT_S 0 + +#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) +/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ +/*description: */ +#define APB_CTRL_XTAL_TICK_NUM 0x000000FF +#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S)) +#define APB_CTRL_XTAL_TICK_NUM_V 0xFF +#define APB_CTRL_XTAL_TICK_NUM_S 0 + +#define APB_CTRL_PLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x8) +/* APB_CTRL_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */ +/*description: */ +#define APB_CTRL_PLL_TICK_NUM 0x000000FF +#define APB_CTRL_PLL_TICK_NUM_M ((APB_CTRL_PLL_TICK_NUM_V)<<(APB_CTRL_PLL_TICK_NUM_S)) +#define APB_CTRL_PLL_TICK_NUM_V 0xFF +#define APB_CTRL_PLL_TICK_NUM_S 0 + +#define APB_CTRL_CK8M_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0xC) +/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */ +/*description: */ +#define APB_CTRL_CK8M_TICK_NUM 0x000000FF +#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S)) +#define APB_CTRL_CK8M_TICK_NUM_V 0xFF +#define APB_CTRL_CK8M_TICK_NUM_S 0 + +#define APB_CTRL_APB_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x10) +/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data + is from GPIO matrix*/ +#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_M (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x1 +#define APB_CTRL_SARADC_DATA_TO_I2S_S 26 +/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data + in this case the resolution should not be larger than 11 bits.*/ +#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_M (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x1 +#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25 +/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x1 +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24 +/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x1 +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23 +/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000F +#define APB_CTRL_SARADC_SAR2_PATT_LEN_M ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S)) +#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0xF +#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19 +/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000F +#define APB_CTRL_SARADC_SAR1_PATT_LEN_M ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S)) +#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0xF +#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15 +/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ +/*description: SAR clock divider*/ +#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000FF +#define APB_CTRL_SARADC_SAR_CLK_DIV_M ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S)) +#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0xFF +#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7 +/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x1 +#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6 +/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ +#define APB_CTRL_SARADC_SAR_SEL (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_M (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_V 0x1 +#define APB_CTRL_SARADC_SAR_SEL_S 5 +/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: single mode 1: double mode 2: alternate mode*/ +#define APB_CTRL_SARADC_WORK_MODE 0x00000003 +#define APB_CTRL_SARADC_WORK_MODE_M ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S)) +#define APB_CTRL_SARADC_WORK_MODE_V 0x3 +#define APB_CTRL_SARADC_WORK_MODE_S 3 +/* APB_CTRL_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled + by PWDET CTRL*/ +#define APB_CTRL_SARADC_SAR2_MUX (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_M (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_V 0x1 +#define APB_CTRL_SARADC_SAR2_MUX_S 2 +/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_START (BIT(1)) +#define APB_CTRL_SARADC_START_M (BIT(1)) +#define APB_CTRL_SARADC_START_V 0x1 +#define APB_CTRL_SARADC_START_S 1 +/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_START_FORCE (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_M (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_V 0x1 +#define APB_CTRL_SARADC_START_FORCE_S 0 + +#define APB_CTRL_APB_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x14) +/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ +#define APB_CTRL_SARADC_SAR2_INV (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_M (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_V 0x1 +#define APB_CTRL_SARADC_SAR2_INV_S 10 +/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ +#define APB_CTRL_SARADC_SAR1_INV (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_M (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_V 0x1 +#define APB_CTRL_SARADC_SAR1_INV_S 9 +/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ +/*description: max conversion number*/ +#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000FF +#define APB_CTRL_SARADC_MAX_MEAS_NUM_M ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S)) +#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0xFF +#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1 +/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0 + +#define APB_CTRL_APB_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x18) +/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */ +/*description: sample cycles*/ +#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000FF +#define APB_CTRL_SARADC_SAMPLE_CYCLE_M ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S)) +#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0xFF +#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24 +/* APB_CTRL_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */ +/*description: */ +#define APB_CTRL_SARADC_START_WAIT 0x000000FF +#define APB_CTRL_SARADC_START_WAIT_M ((APB_CTRL_SARADC_START_WAIT_V)<<(APB_CTRL_SARADC_START_WAIT_S)) +#define APB_CTRL_SARADC_START_WAIT_V 0xFF +#define APB_CTRL_SARADC_START_WAIT_S 16 +/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */ +/*description: */ +#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000FF +#define APB_CTRL_SARADC_STANDBY_WAIT_M ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S)) +#define APB_CTRL_SARADC_STANDBY_WAIT_V 0xFF +#define APB_CTRL_SARADC_STANDBY_WAIT_S 8 +/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ +/*description: */ +#define APB_CTRL_SARADC_RSTB_WAIT 0x000000FF +#define APB_CTRL_SARADC_RSTB_WAIT_M ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S)) +#define APB_CTRL_SARADC_RSTB_WAIT_V 0xFF +#define APB_CTRL_SARADC_RSTB_WAIT_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x1C) +/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x20) +/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x24) +/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x28) +/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x2C) +/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x30) +/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x34) +/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x38) +/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0 + +#define APB_CTRL_APLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x3C) +/* APB_CTRL_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */ +/*description: */ +#define APB_CTRL_APLL_TICK_NUM 0x000000FF +#define APB_CTRL_APLL_TICK_NUM_M ((APB_CTRL_APLL_TICK_NUM_V)<<(APB_CTRL_APLL_TICK_NUM_S)) +#define APB_CTRL_APLL_TICK_NUM_V 0xFF +#define APB_CTRL_APLL_TICK_NUM_S 0 + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x7C) +/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ +/*description: */ +#define APB_CTRL_DATE 0xFFFFFFFF +#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) +#define APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_CTRL_DATE_S 0 + + + + +#endif /*_SOC_APB_CTRL_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/apb_ctrl_struct.h b/tools/sdk/include/soc/include/soc/apb_ctrl_struct.h new file mode 100644 index 00000000000..a871af84212 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/apb_ctrl_struct.h @@ -0,0 +1,132 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_STRUCT_H_ +#define _SOC_APB_CTRL_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + union { + struct { + volatile uint32_t pre_div: 10; + volatile uint32_t clk_320m_en: 1; + volatile uint32_t clk_en: 1; + volatile uint32_t rst_tick: 1; + volatile uint32_t quick_clk_chng: 1; + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }clk_conf; + union { + struct { + volatile uint32_t xtal_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }xtal_tick_conf; + union { + struct { + volatile uint32_t pll_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }pll_tick_conf; + union { + struct { + volatile uint32_t ck8m_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }ck8m_tick_conf; + union { + struct { + volatile uint32_t start_force: 1; + volatile uint32_t start: 1; + volatile uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/ + volatile uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ + volatile uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ + volatile uint32_t sar_clk_gated: 1; + volatile uint32_t sar_clk_div: 8; /*SAR clock divider*/ + volatile uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + volatile uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + volatile uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ + volatile uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ + volatile uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ + volatile uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ + volatile uint32_t reserved27: 5; + }; + volatile uint32_t val; + }saradc_ctrl; + union { + struct { + volatile uint32_t meas_num_limit: 1; + volatile uint32_t max_meas_num: 8; /*max conversion number*/ + volatile uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ + volatile uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ + volatile uint32_t reserved11: 21; + }; + volatile uint32_t val; + }saradc_ctrl2; + union { + struct { + volatile uint32_t rstb_wait: 8; + volatile uint32_t standby_wait: 8; + volatile uint32_t start_wait: 8; + volatile uint32_t sample_cycle: 8; /*sample cycles*/ + }; + volatile uint32_t val; + }saradc_fsm; + volatile uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/ + union { + struct { + volatile uint32_t apll_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }apll_tick_conf; + volatile uint32_t reserved_40; + volatile uint32_t reserved_44; + volatile uint32_t reserved_48; + volatile uint32_t reserved_4c; + volatile uint32_t reserved_50; + volatile uint32_t reserved_54; + volatile uint32_t reserved_58; + volatile uint32_t reserved_5c; + volatile uint32_t reserved_60; + volatile uint32_t reserved_64; + volatile uint32_t reserved_68; + volatile uint32_t reserved_6c; + volatile uint32_t reserved_70; + volatile uint32_t reserved_74; + volatile uint32_t reserved_78; + volatile uint32_t date; /**/ +} apb_ctrl_dev_t; + + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_APB_CTRL_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/bb_reg.h b/tools/sdk/include/soc/include/soc/bb_reg.h new file mode 100644 index 00000000000..69d2f43d206 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/bb_reg.h @@ -0,0 +1,42 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_BB_REG_H_ +#define _SOC_BB_REG_H_ + +/* Some of the baseband control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054) +#define BB_FFT_FORCE_PU (BIT(3)) +#define BB_FFT_FORCE_PU_M (BIT(3)) +#define BB_FFT_FORCE_PU_V 1 +#define BB_FFT_FORCE_PU_S 3 +#define BB_FFT_FORCE_PD (BIT(2)) +#define BB_FFT_FORCE_PD_M (BIT(2)) +#define BB_FFT_FORCE_PD_V 1 +#define BB_FFT_FORCE_PD_S 2 +#define BB_DC_EST_FORCE_PU (BIT(1)) +#define BB_DC_EST_FORCE_PU_M (BIT(1)) +#define BB_DC_EST_FORCE_PU_V 1 +#define BB_DC_EST_FORCE_PU_S 1 +#define BB_DC_EST_FORCE_PD (BIT(0)) +#define BB_DC_EST_FORCE_PD_M (BIT(0)) +#define BB_DC_EST_FORCE_PD_V 1 +#define BB_DC_EST_FORCE_PD_S 0 + + +#endif /* _SOC_BB_REG_H_ */ + diff --git a/tools/sdk/include/soc/include/soc/boot_mode.h b/tools/sdk/include/soc/include/soc/boot_mode.h new file mode 100644 index 00000000000..5106e10cfbd --- /dev/null +++ b/tools/sdk/include/soc/include/soc/boot_mode.h @@ -0,0 +1,104 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_BOOT_MODE_H_ +#define _SOC_BOOT_MODE_H_ + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXXX(v) (((v)&0x10)==0x10) + +/*HSPI Boot*/ +#define IS_010XX(v) (((v)&0x1c)==0x08) + +/*Download Boot, SDIO/UART0/UART1*/ +#define IS_00XXX(v) (((v)&0x18)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_00X00(v) (((v)&0x1b)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_00X01(v) (((v)&0x1b)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_00X10(v) (((v)&0x1b)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_00X11(v) (((v)&0x1b)==0x03) + +/*ATE/ANALOG Mode*/ +#define IS_01110(v) (((v)&0x1f)==0x0e) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_01111(v) (((v)&0x1f)==0x0f) + +/*legacy SPI Boot*/ +#define IS_01100(v) (((v)&0x1f)==0x0c) + +/*SDIO_Slave download Mode V1.1*/ +#define IS_01101(v) (((v)&0x1f)==0x0d) + + + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_01111(BOOT_MODE_GET()) + +/*all spi boot including spi/hspi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET())) + +/*all faster spi boot including spi/hspi*/ +#define ETS_IS_FAST_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET())) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_SPI_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET())) + +/*all spi boot including hspi/legacy*/ +#define ETS_IS_HSPI_FLASH_BOOT() IS_010XX(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_00X00(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_00X01(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_00X10(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_00X11(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_01101(BOOT_MODE_GET()) + +/*do not include download mode*/ +#define ETS_IS_SDIO_BOOT() IS_01101(BOOT_MODE_GET()) + +/*joint download boot*/ +#define ETS_IS_SDIO_UART_BOOT() IS_00XXX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_01110(BOOT_MODE_GET()) + +/*A bit to control flash boot print*/ +#define ETS_IS_PRINT_BOOT() (BOOT_MODE_GET() & 0x2) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 + +#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/tools/sdk/include/soc/include/soc/can_struct.h b/tools/sdk/include/soc/include/soc/can_struct.h new file mode 100644 index 00000000000..a2c1ea63fc2 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/can_struct.h @@ -0,0 +1,213 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_CAN_STRUCT_H_ +#define _SOC_CAN_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* -------------------------- Register Definitions -------------------------- */ + +/* The CAN peripheral's registers are 8bits, however the ESP32 can only access + * peripheral registers every 32bits. Therefore each CAN register is mapped to + * the least significant byte of every 32bits. + */ +typedef union { + struct { + uint32_t byte: 8; /* LSB */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; +} can_reg_t; + +typedef union { + struct { + uint32_t reset: 1; /* MOD.0 Reset Mode */ + uint32_t listen_only: 1; /* MOD.1 Listen Only Mode */ + uint32_t self_test: 1; /* MOD.2 Self Test Mode */ + uint32_t acceptance_filter: 1; /* MOD.3 Acceptance Filter Mode */ + uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */ + }; + uint32_t val; +} can_mode_reg_t; + +typedef union { + struct { + uint32_t tx_req: 1; /* CMR.0 Transmission Request */ + uint32_t abort_tx: 1; /* CMR.1 Abort Transmission */ + uint32_t release_rx_buff: 1; /* CMR.2 Release Receive Buffer */ + uint32_t clear_data_overrun: 1; /* CMR.3 Clear Data Overrun */ + uint32_t self_rx_req: 1; /* CMR.4 Self Reception Request */ + uint32_t reserved27: 27; /* Internal Reserved */ + }; + uint32_t val; +} can_cmd_reg_t; + +typedef union { + struct { + uint32_t rx_buff: 1; /* SR.0 Receive Buffer Status */ + uint32_t data_overrun: 1; /* SR.1 Data Overrun Status */ + uint32_t tx_buff: 1; /* SR.2 Transmit Buffer Status */ + uint32_t tx_complete: 1; /* SR.3 Transmission Complete Status */ + uint32_t rx: 1; /* SR.4 Receive Status */ + uint32_t tx: 1; /* SR.5 Transmit Status */ + uint32_t error: 1; /* SR.6 Error Status */ + uint32_t bus: 1; /* SR.7 Bus Status */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; +} can_status_reg_t; + +typedef union { + struct { + uint32_t rx: 1; /* IR.0 Receive Interrupt */ + uint32_t tx: 1; /* IR.1 Transmit Interrupt */ + uint32_t err_warn: 1; /* IR.2 Error Interrupt */ + uint32_t data_overrun: 1; /* IR.3 Data Overrun Interrupt */ + uint32_t reserved1: 1; /* Internal Reserved (Wake-up not supported) */ + uint32_t err_passive: 1; /* IR.5 Error Passive Interrupt */ + uint32_t arb_lost: 1; /* IR.6 Arbitration Lost Interrupt */ + uint32_t bus_err: 1; /* IR.7 Bus Error Interrupt */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; +} can_intr_reg_t; + +typedef union { + struct { + uint32_t rx: 1; /* IER.0 Receive Interrupt Enable */ + uint32_t tx: 1; /* IER.1 Transmit Interrupt Enable */ + uint32_t err_warn: 1; /* IER.2 Error Interrupt Enable */ + uint32_t data_overrun: 1; /* IER.3 Data Overrun Interrupt Enable */ + uint32_t brp_div: 1; /* THIS IS NOT AN INTERRUPT. brp_div will prescale BRP by 2. Only available on ESP32 Revision 2 or later. Reserved otherwise */ + uint32_t err_passive: 1; /* IER.5 Error Passive Interrupt Enable */ + uint32_t arb_lost: 1; /* IER.6 Arbitration Lost Interrupt Enable */ + uint32_t bus_err: 1; /* IER.7 Bus Error Interrupt Enable */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; +} can_intr_en_reg_t; + +typedef union { + struct { + uint32_t baud_rate_prescaler: 6; /* BTR0[5:0] Baud Rate Prescaler */ + uint32_t sync_jump_width: 2; /* BTR0[7:6] Synchronization Jump Width*/ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; +} can_bus_tim_0_reg_t; + +typedef union { + struct { + uint32_t time_seg_1: 4; /* BTR1[3:0] Timing Segment 1 */ + uint32_t time_seg_2: 3; /* BTR1[6:4] Timing Segment 2 */ + uint32_t sampling: 1; /* BTR1.7 Sampling*/ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; +} can_bus_tim_1_reg_t; + +typedef union { + struct { + uint32_t arbitration_lost_capture: 5; /* ALC[4:0] Arbitration lost capture */ + uint32_t reserved27: 27; /* Internal Reserved */ + }; + uint32_t val; +} can_arb_lost_cap_reg_t; + +typedef union { + struct { + uint32_t segment: 5; /* ECC[4:0] Error Code Segment 0 to 5 */ + uint32_t direction: 1; /* ECC.5 Error Direction (TX/RX) */ + uint32_t error_code: 2; /* ECC[7:6] Error Code */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; +} can_err_code_cap_reg_t; + +typedef struct { + can_reg_t code_reg[4]; + can_reg_t mask_reg[4]; + uint32_t reserved32[5]; +} can_acc_filter_t; + +typedef union { + struct { + uint32_t rx_message_counter: 7; /* RMC[6:0] RX Message Counter */ + uint32_t reserved25: 25; /* Internal Reserved */ + }; + uint32_t val; +} can_rx_msg_cnt_reg_t; + +typedef union { + struct { + uint32_t clock_divider: 3; /* CDR[2:0] CLKOUT frequency selector based of fOSC */ + uint32_t clock_off: 1; /* CDR.3 CLKOUT enable/disable */ + uint32_t reserved3: 3; /* Internal Reserved. RXINTEN and CBP not supported */ + uint32_t can_mode: 1; /* CDR.7 BasicCAN:0 PeliCAN:1 */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; +} can_clk_div_reg_t; + +/* ---------------------------- Register Layout ------------------------------ */ + +typedef volatile struct { + //Configuration and Control Registers + can_mode_reg_t mode_reg; /* Address 0 */ + can_cmd_reg_t command_reg; /* Address 1 */ + can_status_reg_t status_reg; /* Address 2 */ + can_intr_reg_t interrupt_reg; /* Address 3 */ + can_intr_en_reg_t interrupt_enable_reg; /* Address 4 */ + uint32_t reserved_05; /* Address 5 */ + can_bus_tim_0_reg_t bus_timing_0_reg; /* Address 6 */ + can_bus_tim_1_reg_t bus_timing_1_reg; /* Address 7 */ + uint32_t reserved_08; /* Address 8 (Output control not supported) */ + uint32_t reserved_09; /* Address 9 (Test Register not supported) */ + uint32_t reserved_10; /* Address 10 */ + + //Capture and Counter Registers + can_arb_lost_cap_reg_t arbitration_lost_captue_reg; /* Address 11 */ + can_err_code_cap_reg_t error_code_capture_reg; /* Address 12 */ + can_reg_t error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */ + can_reg_t rx_error_counter_reg; /* RXERR[7:0] Receive Error Counter: Address 14 */ + can_reg_t tx_error_counter_reg; /* TXERR[7:0] Transmit Error Counter: Address 15 */ + + //Shared Registers (TX Buff/RX Buff/Acc Filter) + union { + can_acc_filter_t acceptance_filter; + can_reg_t tx_rx_buffer[13]; + }; /* Address 16-28 TX/RX Buffer and Acc Filter*/; + + //Misc Registers + can_rx_msg_cnt_reg_t rx_message_counter_reg; /* Address 29 */ + can_reg_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */ + can_clk_div_reg_t clock_divider_reg; /* Address 31 */ + + //Start of RX FIFO +} can_dev_t; + +_Static_assert(sizeof(can_dev_t) == 128, "CAN registers should be 32 * 4 bytes"); + +extern can_dev_t CAN; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_CAN_STRUCT_H_ */ + diff --git a/tools/sdk/include/soc/include/soc/clkout_channel.h b/tools/sdk/include/soc/include/soc/clkout_channel.h new file mode 100644 index 00000000000..5161e3f0b65 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/clkout_channel.h @@ -0,0 +1,26 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_CLKOUT_CHANNEL_H +#define _SOC_CLKOUT_CHANNEL_H + +//CLKOUT channels +#define CLKOUT_GPIO0_DIRECT_CHANNEL CLKOUT_CHANNEL_1 +#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 0 +#define CLKOUT_GPIO3_DIRECT_CHANNEL CLKOUT_CHANNEL_2 +#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 3 +#define CLKOUT_GPIO1_DIRECT_CHANNEL CLKOUT_CHANNEL_3 +#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 1 + +#endif diff --git a/tools/sdk/include/soc/include/soc/cpu.h b/tools/sdk/include/soc/include/soc/cpu.h new file mode 100644 index 00000000000..190786a433b --- /dev/null +++ b/tools/sdk/include/soc/include/soc/cpu.h @@ -0,0 +1,134 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_CPU_H +#define _SOC_CPU_H + +#include +#include +#include +#include "xtensa/corebits.h" +#include "xtensa/config/core.h" + +/* C macros for xtensa special register read/write/exchange */ + +#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval)); +#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval)); +#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval)); + +/** @brief Read current stack pointer address + * + */ +static inline void *get_sp() +{ + void *sp; + asm volatile ("mov %0, sp;" : "=r" (sp)); + return sp; +} + +/* Functions to set page attributes for Region Protection option in the CPU. + * See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2). + */ + +static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr) +{ + asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr)); +} + + +static inline void cpu_write_itlb(unsigned vpn, unsigned attr) +{ + asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr)); +} + +static inline void cpu_init_memctl() +{ +#if XCHAL_ERRATUM_572 + uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT; + WSR(MEMCTL, memctl); +#endif // XCHAL_ERRATUM_572 +} + +/** + * @brief Configure memory region protection + * + * Make page 0 access raise an exception. + * Also protect some other unused pages so we can catch weirdness. + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + */ + +static inline void cpu_configure_region_protection() +{ + const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000}; + for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) { + cpu_write_dtlb(pages_to_protect[i], 0xf); + cpu_write_itlb(pages_to_protect[i], 0xf); + } + cpu_write_dtlb(0x20000000, 0); + cpu_write_itlb(0x20000000, 0); +} + +/** + * @brief Stall CPU using RTC controller + * @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP) + */ +void esp_cpu_stall(int cpu_id); + +/** + * @brief Un-stall CPU using RTC controller + * @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP) + */ +void esp_cpu_unstall(int cpu_id); + +/** + * @brief Reset CPU using RTC controller + * @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP) + */ +void esp_cpu_reset(int cpu_id); + + +/** + * @brief Returns true if a JTAG debugger is attached to CPU + * OCD (on chip debug) port. + * + * @note If "Make exception and panic handlers JTAG/OCD aware" + * is disabled, this function always returns false. + */ +bool esp_cpu_in_ocd_debug_mode(); + +/** + * @brief Convert the PC register value to its true address + * + * The address of the current instruction is not stored as an exact uint32_t + * representation in PC register. This function will convert the value stored in + * the PC register to a uint32_t address. + * + * @param pc_raw The PC as stored in register format. + * + * @return Address in uint32_t format + */ +static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc) +{ + if (pc & 0x80000000) { + //Top two bits of a0 (return address) specify window increment. Overwrite to map to address space. + pc = (pc & 0x3fffffff) | 0x40000000; + } + //Minus 3 to get PC of previous instruction (i.e. instruction executed before return address) + return pc - 3; +} + +#endif diff --git a/tools/sdk/include/soc/include/soc/dac_channel.h b/tools/sdk/include/soc/include/soc/dac_channel.h new file mode 100644 index 00000000000..241a067bb24 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/dac_channel.h @@ -0,0 +1,24 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_DAC_CHANNEL_H +#define _SOC_DAC_CHANNEL_H + +#define DAC_GPIO25_CHANNEL DAC_CHANNEL_1 +#define DAC_CHANNEL_1_GPIO_NUM 25 + +#define DAC_GPIO26_CHANNEL DAC_CHANNEL_2 +#define DAC_CHANNEL_2_GPIO_NUM 26 + +#endif diff --git a/tools/sdk/include/soc/include/soc/dport_access.h b/tools/sdk/include/soc/include/soc/dport_access.h new file mode 100644 index 00000000000..2639e46ef14 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/dport_access.h @@ -0,0 +1,202 @@ +// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _DPORT_ACCESS_H_ +#define _DPORT_ACCESS_H_ + +#include +#include "esp_attr.h" +#include "esp_dport_access.h" +#include "soc.h" +#include "uart_reg.h" +#include "xtensa/xtruntime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//Registers Operation {{ + +// The _DPORT_xxx register read macros access DPORT memory directly (as opposed to +// DPORT_REG_READ which applies SMP-safe protections). +// +// There are several ways to read the DPORT registers: +// 1) Use DPORT_REG_READ versions to be SMP-safe in IDF apps. +// This method uses the pre-read APB implementation(*) without stall other CPU. +// This is beneficial for single readings. +// 2) If you want to make a sequence of DPORT reads to buffer, +// use dport_read_buffer(buff_out, address, num_words), +// it is the faster method and it doesn't stop other CPU. +// 3) If you want to make a sequence of DPORT reads, but you don't want to stop other CPU +// and you want to do it faster then you need use DPORT_SEQUENCE_REG_READ(). +// The difference from the first is that the user himself must disable interrupts while DPORT reading. +// Note that disable interrupt need only if the chip has two cores. +// 4) If you want to make a sequence of DPORT reads, +// use DPORT_STALL_OTHER_CPU_START() macro explicitly +// and then use _DPORT_REG_READ macro while other CPU is stalled. +// After completing read operations, use DPORT_STALL_OTHER_CPU_END(). +// This method uses stall other CPU while reading DPORT registers. +// Useful for compatibility, as well as for large consecutive readings. +// This method is slower, but must be used if ROM functions or +// other code is called which accesses DPORT without any other workaround. +// *) The pre-readable APB register before reading the DPORT register +// helps synchronize the operation of the two CPUs, +// so that reading on different CPUs no longer causes random errors APB register. + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +/** + * @brief Read value from register, SMP-safe version. + * + * This method uses the pre-reading of the APB register before reading the register of the DPORT. + * This implementation is useful for reading DORT registers for single reading without stall other CPU. + * There is disable/enable interrupt. + * + * @param reg Register address + * @return Value + */ +static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg) +{ +#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM) + return _DPORT_REG_READ(reg); +#else + return esp_dport_access_reg_read(reg); +#endif +} + +/** + * @brief Read value from register, NOT SMP-safe version. + * + * This method uses the pre-reading of the APB register before reading the register of the DPORT. + * There is not disable/enable interrupt. + * The difference from DPORT_REG_READ() is that the user himself must disable interrupts while DPORT reading. + * This implementation is useful for reading DORT registers in loop without stall other CPU. Note the usage example. + * The recommended way to read registers sequentially without stall other CPU + * is to use the method esp_dport_read_buffer(buff_out, address, num_words). It allows you to read registers in the buffer. + * + * \code{c} + * // This example shows how to use it. + * { // Use curly brackets to limit the visibility of variables in macros DPORT_INTERRUPT_DISABLE/RESTORE. + * DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU. + * for (i = 0; i < max; ++i) { + * array[i] = DPORT_SEQUENCE_REG_READ(Address + i * 4); // reading DPORT registers + * } + * DPORT_INTERRUPT_RESTORE(); // restore the previous interrupt level + * } + * \endcode + * + * @param reg Register address + * @return Value + */ +static inline uint32_t IRAM_ATTR DPORT_SEQUENCE_REG_READ(uint32_t reg) +{ +#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM) + return _DPORT_REG_READ(reg); +#else + return esp_dport_access_sequence_reg_read(reg); +#endif +} + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +/** + * @brief Read value from register, SMP-safe version. + * + * This method uses the pre-reading of the APB register before reading the register of the DPORT. + * This implementation is useful for reading DORT registers for single reading without stall other CPU. + * + * @param reg Register address + * @return Value + */ +static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t reg) +{ +#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM) + return _DPORT_REG_READ(reg); +#else + return esp_dport_access_reg_read(reg); +#endif +} + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif + +#endif /* _DPORT_ACCESS_H_ */ diff --git a/tools/sdk/include/soc/include/soc/dport_reg.h b/tools/sdk/include/soc/include/soc/dport_reg.h new file mode 100644 index 00000000000..9cc3320b39b --- /dev/null +++ b/tools/sdk/include/soc/include/soc/dport_reg.h @@ -0,0 +1,4288 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_DPORT_REG_H_ +#define _SOC_DPORT_REG_H_ + +#include "soc.h" + +#ifndef __ASSEMBLER__ +#include "dport_access.h" +#endif + +/* Registers defined in this header file must be accessed using special macros, + * prefixed with DPORT_. See soc/dport_access.h file for details. + */ + +#define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000) +/* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_BOOT_REMAP (BIT(0)) +#define DPORT_PRO_BOOT_REMAP_M (BIT(0)) +#define DPORT_PRO_BOOT_REMAP_V 0x1 +#define DPORT_PRO_BOOT_REMAP_S 0 + +#define DPORT_APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004) +/* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_BOOT_REMAP (BIT(0)) +#define DPORT_APP_BOOT_REMAP_M (BIT(0)) +#define DPORT_APP_BOOT_REMAP_V 0x1 +#define DPORT_APP_BOOT_REMAP_S 0 + +#define DPORT_ACCESS_CHECK_REG (DR_REG_DPORT_BASE + 0x008) +/* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_ACCESS_CHECK_APP (BIT(8)) +#define DPORT_ACCESS_CHECK_APP_M (BIT(8)) +#define DPORT_ACCESS_CHECK_APP_V 0x1 +#define DPORT_ACCESS_CHECK_APP_S 8 +/* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_ACCESS_CHECK_PRO (BIT(0)) +#define DPORT_ACCESS_CHECK_PRO_M (BIT(0)) +#define DPORT_ACCESS_CHECK_PRO_V 0x1 +#define DPORT_ACCESS_CHECK_PRO_S 0 + +#define DPORT_PRO_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x00C) +/* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK0_M ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S)) +#define DPORT_PRODPORT_APB_MASK0_V 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK0_S 0 + +#define DPORT_PRO_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x010) +/* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK1_M ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S)) +#define DPORT_PRODPORT_APB_MASK1_V 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK1_S 0 + +#define DPORT_APP_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x014) +/* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK0_M ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S)) +#define DPORT_APPDPORT_APB_MASK0_V 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK0_S 0 + +#define DPORT_APP_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x018) +/* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK1_M ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S)) +#define DPORT_APPDPORT_APB_MASK1_V 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK1_S 0 + +#define DPORT_PERI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x01C) +/* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PERI_CLK_EN 0xFFFFFFFF +#define DPORT_PERI_CLK_EN_M ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S)) +#define DPORT_PERI_CLK_EN_V 0xFFFFFFFF +#define DPORT_PERI_CLK_EN_S 0 + +#define DPORT_PERI_RST_EN_REG (DR_REG_DPORT_BASE + 0x020) +/* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PERI_RST_EN 0xFFFFFFFF +#define DPORT_PERI_RST_EN_M ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S)) +#define DPORT_PERI_RST_EN_V 0xFFFFFFFF +#define DPORT_PERI_RST_EN_S 0 + +/* The following bits apply to DPORT_PERI_CLK_EN_REG, DPORT_PERI_RST_EN_REG + */ +#define DPORT_PERI_EN_AES (1<<0) +#define DPORT_PERI_EN_SHA (1<<1) +#define DPORT_PERI_EN_RSA (1<<2) +/* NB: Secure boot reset will hold SHA & AES in reset */ +#define DPORT_PERI_EN_SECUREBOOT (1<<3) +/* NB: Digital signature reset will hold AES & RSA in reset */ +#define DPORT_PERI_EN_DIGITAL_SIGNATURE (1<<4) + +#define DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024) +/* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_WIFI_BB_CFG 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_M ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S)) +#define DPORT_WIFI_BB_CFG_V 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_S 0 + +#define DPORT_WIFI_BB_CFG_2_REG (DR_REG_DPORT_BASE + 0x028) +/* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_2_M ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S)) +#define DPORT_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_2_S 0 + +#define DPORT_APPCPU_CTRL_A_REG (DR_REG_DPORT_BASE + 0x02C) +/* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APPCPU_RESETTING (BIT(0)) +#define DPORT_APPCPU_RESETTING_M (BIT(0)) +#define DPORT_APPCPU_RESETTING_V 0x1 +#define DPORT_APPCPU_RESETTING_S 0 + +#define DPORT_APPCPU_CTRL_B_REG (DR_REG_DPORT_BASE + 0x030) +/* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APPCPU_CLKGATE_EN (BIT(0)) +#define DPORT_APPCPU_CLKGATE_EN_M (BIT(0)) +#define DPORT_APPCPU_CLKGATE_EN_V 0x1 +#define DPORT_APPCPU_CLKGATE_EN_S 0 + +#define DPORT_APPCPU_CTRL_C_REG (DR_REG_DPORT_BASE + 0x034) +/* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APPCPU_RUNSTALL (BIT(0)) +#define DPORT_APPCPU_RUNSTALL_M (BIT(0)) +#define DPORT_APPCPU_RUNSTALL_V 0x1 +#define DPORT_APPCPU_RUNSTALL_S 0 + +#define DPORT_APPCPU_CTRL_D_REG (DR_REG_DPORT_BASE + 0x038) +/* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF +#define DPORT_APPCPU_BOOT_ADDR_M ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S)) +#define DPORT_APPCPU_BOOT_ADDR_V 0xFFFFFFFF +#define DPORT_APPCPU_BOOT_ADDR_S 0 + +#define DPORT_CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C) +/* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_FAST_CLK_RTC_SEL (BIT(3)) +#define DPORT_FAST_CLK_RTC_SEL_M (BIT(3)) +#define DPORT_FAST_CLK_RTC_SEL_V 0x1 +#define DPORT_FAST_CLK_RTC_SEL_S 3 +/* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LOWSPEED_CLK_SEL (BIT(2)) +#define DPORT_LOWSPEED_CLK_SEL_M (BIT(2)) +#define DPORT_LOWSPEED_CLK_SEL_V 0x1 +#define DPORT_LOWSPEED_CLK_SEL_S 2 +/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_CPUPERIOD_SEL 0x00000003 +#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) +#define DPORT_CPUPERIOD_SEL_V 0x3 +#define DPORT_CPUPERIOD_SEL_S 0 +#define DPORT_CPUPERIOD_SEL_80 0 +#define DPORT_CPUPERIOD_SEL_160 1 +#define DPORT_CPUPERIOD_SEL_240 2 + +#define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) +/* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_DRAM_HL (BIT(16)) +#define DPORT_PRO_DRAM_HL_M (BIT(16)) +#define DPORT_PRO_DRAM_HL_V 0x1 +#define DPORT_PRO_DRAM_HL_S 16 +/* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SLAVE_REQ (BIT(15)) +#define DPORT_SLAVE_REQ_M (BIT(15)) +#define DPORT_SLAVE_REQ_V 0x1 +#define DPORT_SLAVE_REQ_S 15 +/* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_SPI_REQ (BIT(14)) +#define DPORT_AHB_SPI_REQ_M (BIT(14)) +#define DPORT_AHB_SPI_REQ_V 0x1 +#define DPORT_AHB_SPI_REQ_S 14 +/* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_SLAVE_REQ (BIT(13)) +#define DPORT_PRO_SLAVE_REQ_M (BIT(13)) +#define DPORT_PRO_SLAVE_REQ_V 0x1 +#define DPORT_PRO_SLAVE_REQ_S 13 +/* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_AHB_SPI_REQ (BIT(12)) +#define DPORT_PRO_AHB_SPI_REQ_M (BIT(12)) +#define DPORT_PRO_AHB_SPI_REQ_V 0x1 +#define DPORT_PRO_AHB_SPI_REQ_S 12 +/* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_DRAM_SPLIT (BIT(11)) +#define DPORT_PRO_DRAM_SPLIT_M (BIT(11)) +#define DPORT_PRO_DRAM_SPLIT_V 0x1 +#define DPORT_PRO_DRAM_SPLIT_S 11 +/* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10)) +#define DPORT_PRO_SINGLE_IRAM_ENA_M (BIT(10)) +#define DPORT_PRO_SINGLE_IRAM_ENA_V 0x1 +#define DPORT_PRO_SINGLE_IRAM_ENA_S 10 +/* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9)) +#define DPORT_PRO_CACHE_LOCK_3_EN_M (BIT(9)) +#define DPORT_PRO_CACHE_LOCK_3_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_3_EN_S 9 +/* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8)) +#define DPORT_PRO_CACHE_LOCK_2_EN_M (BIT(8)) +#define DPORT_PRO_CACHE_LOCK_2_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_2_EN_S 8 +/* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7)) +#define DPORT_PRO_CACHE_LOCK_1_EN_M (BIT(7)) +#define DPORT_PRO_CACHE_LOCK_1_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_1_EN_S 7 +/* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6)) +#define DPORT_PRO_CACHE_LOCK_0_EN_M (BIT(6)) +#define DPORT_PRO_CACHE_LOCK_0_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_0_EN_S 6 +/* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5)) +#define DPORT_PRO_CACHE_FLUSH_DONE_M (BIT(5)) +#define DPORT_PRO_CACHE_FLUSH_DONE_V 0x1 +#define DPORT_PRO_CACHE_FLUSH_DONE_S 5 +/* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4)) +#define DPORT_PRO_CACHE_FLUSH_ENA_M (BIT(4)) +#define DPORT_PRO_CACHE_FLUSH_ENA_V 0x1 +#define DPORT_PRO_CACHE_FLUSH_ENA_S 4 +/* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_ENABLE (BIT(3)) +#define DPORT_PRO_CACHE_ENABLE_M (BIT(3)) +#define DPORT_PRO_CACHE_ENABLE_V 0x1 +#define DPORT_PRO_CACHE_ENABLE_S 3 +/* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MODE (BIT(2)) +#define DPORT_PRO_CACHE_MODE_M (BIT(2)) +#define DPORT_PRO_CACHE_MODE_V 0x1 +#define DPORT_PRO_CACHE_MODE_S 2 + +#define DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) +/* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13)) +#define DPORT_PRO_CACHE_MMU_IA_CLR_M (BIT(13)) +#define DPORT_PRO_CACHE_MMU_IA_CLR_V 0x1 +#define DPORT_PRO_CACHE_MMU_IA_CLR_S 13 +/* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CMMU_PD (BIT(12)) +#define DPORT_PRO_CMMU_PD_M (BIT(12)) +#define DPORT_PRO_CMMU_PD_V 0x1 +#define DPORT_PRO_CMMU_PD_S 12 +/* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CMMU_FORCE_ON (BIT(11)) +#define DPORT_PRO_CMMU_FORCE_ON_M (BIT(11)) +#define DPORT_PRO_CMMU_FORCE_ON_V 0x1 +#define DPORT_PRO_CMMU_FORCE_ON_S 11 +/* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003 +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S)) +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V 0x3 +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9 +/* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ +/*description: */ +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007 +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S)) +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V 0x7 +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6 +/* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5)) +#define DPORT_PRO_CACHE_MASK_OPSDRAM_M (BIT(5)) +#define DPORT_PRO_CACHE_MASK_OPSDRAM_V 0x1 +#define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5 +/* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4)) +#define DPORT_PRO_CACHE_MASK_DROM0_M (BIT(4)) +#define DPORT_PRO_CACHE_MASK_DROM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_DROM0_S 4 +/* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3)) +#define DPORT_PRO_CACHE_MASK_DRAM1_M (BIT(3)) +#define DPORT_PRO_CACHE_MASK_DRAM1_V 0x1 +#define DPORT_PRO_CACHE_MASK_DRAM1_S 3 +/* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2)) +#define DPORT_PRO_CACHE_MASK_IROM0_M (BIT(2)) +#define DPORT_PRO_CACHE_MASK_IROM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_IROM0_S 2 +/* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1)) +#define DPORT_PRO_CACHE_MASK_IRAM1_M (BIT(1)) +#define DPORT_PRO_CACHE_MASK_IRAM1_V 0x1 +#define DPORT_PRO_CACHE_MASK_IRAM1_S 1 +/* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0)) +#define DPORT_PRO_CACHE_MASK_IRAM0_M (BIT(0)) +#define DPORT_PRO_CACHE_MASK_IRAM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_IRAM0_S 0 + +#define DPORT_PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048) +/* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C) +/* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050) +/* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054) +/* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058) +/* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_DRAM_HL (BIT(14)) +#define DPORT_APP_DRAM_HL_M (BIT(14)) +#define DPORT_APP_DRAM_HL_V 0x1 +#define DPORT_APP_DRAM_HL_S 14 +/* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_SLAVE_REQ (BIT(13)) +#define DPORT_APP_SLAVE_REQ_M (BIT(13)) +#define DPORT_APP_SLAVE_REQ_V 0x1 +#define DPORT_APP_SLAVE_REQ_S 13 +/* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_AHB_SPI_REQ (BIT(12)) +#define DPORT_APP_AHB_SPI_REQ_M (BIT(12)) +#define DPORT_APP_AHB_SPI_REQ_V 0x1 +#define DPORT_APP_AHB_SPI_REQ_S 12 +/* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_DRAM_SPLIT (BIT(11)) +#define DPORT_APP_DRAM_SPLIT_M (BIT(11)) +#define DPORT_APP_DRAM_SPLIT_V 0x1 +#define DPORT_APP_DRAM_SPLIT_S 11 +/* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_SINGLE_IRAM_ENA (BIT(10)) +#define DPORT_APP_SINGLE_IRAM_ENA_M (BIT(10)) +#define DPORT_APP_SINGLE_IRAM_ENA_V 0x1 +#define DPORT_APP_SINGLE_IRAM_ENA_S 10 +/* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_3_EN (BIT(9)) +#define DPORT_APP_CACHE_LOCK_3_EN_M (BIT(9)) +#define DPORT_APP_CACHE_LOCK_3_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_3_EN_S 9 +/* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_2_EN (BIT(8)) +#define DPORT_APP_CACHE_LOCK_2_EN_M (BIT(8)) +#define DPORT_APP_CACHE_LOCK_2_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_2_EN_S 8 +/* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_1_EN (BIT(7)) +#define DPORT_APP_CACHE_LOCK_1_EN_M (BIT(7)) +#define DPORT_APP_CACHE_LOCK_1_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_1_EN_S 7 +/* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_0_EN (BIT(6)) +#define DPORT_APP_CACHE_LOCK_0_EN_M (BIT(6)) +#define DPORT_APP_CACHE_LOCK_0_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_0_EN_S 6 +/* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_FLUSH_DONE (BIT(5)) +#define DPORT_APP_CACHE_FLUSH_DONE_M (BIT(5)) +#define DPORT_APP_CACHE_FLUSH_DONE_V 0x1 +#define DPORT_APP_CACHE_FLUSH_DONE_S 5 +/* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_FLUSH_ENA (BIT(4)) +#define DPORT_APP_CACHE_FLUSH_ENA_M (BIT(4)) +#define DPORT_APP_CACHE_FLUSH_ENA_V 0x1 +#define DPORT_APP_CACHE_FLUSH_ENA_S 4 +/* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_ENABLE (BIT(3)) +#define DPORT_APP_CACHE_ENABLE_M (BIT(3)) +#define DPORT_APP_CACHE_ENABLE_V 0x1 +#define DPORT_APP_CACHE_ENABLE_S 3 +/* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_MODE (BIT(2)) +#define DPORT_APP_CACHE_MODE_M (BIT(2)) +#define DPORT_APP_CACHE_MODE_V 0x1 +#define DPORT_APP_CACHE_MODE_S 2 + +#define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C) +/* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13)) +#define DPORT_APP_CACHE_MMU_IA_CLR_M (BIT(13)) +#define DPORT_APP_CACHE_MMU_IA_CLR_V 0x1 +#define DPORT_APP_CACHE_MMU_IA_CLR_S 13 +/* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CMMU_PD (BIT(12)) +#define DPORT_APP_CMMU_PD_M (BIT(12)) +#define DPORT_APP_CMMU_PD_V 0x1 +#define DPORT_APP_CMMU_PD_S 12 +/* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CMMU_FORCE_ON (BIT(11)) +#define DPORT_APP_CMMU_FORCE_ON_M (BIT(11)) +#define DPORT_APP_CMMU_FORCE_ON_V 0x1 +#define DPORT_APP_CMMU_FORCE_ON_S 11 +/* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003 +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_M ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S)) +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_V 0x3 +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9 +/* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ +/*description: */ +#define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007 +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_M ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S)) +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_V 0x7 +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6 +/* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5)) +#define DPORT_APP_CACHE_MASK_OPSDRAM_M (BIT(5)) +#define DPORT_APP_CACHE_MASK_OPSDRAM_V 0x1 +#define DPORT_APP_CACHE_MASK_OPSDRAM_S 5 +/* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_DROM0 (BIT(4)) +#define DPORT_APP_CACHE_MASK_DROM0_M (BIT(4)) +#define DPORT_APP_CACHE_MASK_DROM0_V 0x1 +#define DPORT_APP_CACHE_MASK_DROM0_S 4 +/* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3)) +#define DPORT_APP_CACHE_MASK_DRAM1_M (BIT(3)) +#define DPORT_APP_CACHE_MASK_DRAM1_V 0x1 +#define DPORT_APP_CACHE_MASK_DRAM1_S 3 +/* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_IROM0 (BIT(2)) +#define DPORT_APP_CACHE_MASK_IROM0_M (BIT(2)) +#define DPORT_APP_CACHE_MASK_IROM0_V 0x1 +#define DPORT_APP_CACHE_MASK_IROM0_S 2 +/* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1)) +#define DPORT_APP_CACHE_MASK_IRAM1_M (BIT(1)) +#define DPORT_APP_CACHE_MASK_IRAM1_V 0x1 +#define DPORT_APP_CACHE_MASK_IRAM1_S 1 +/* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0)) +#define DPORT_APP_CACHE_MASK_IRAM0_M (BIT(0)) +#define DPORT_APP_CACHE_MASK_IRAM0_V 0x1 +#define DPORT_APP_CACHE_MASK_IRAM0_S 0 + +#define DPORT_APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060) +/* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064) +/* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068) +/* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C) +/* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0 + +#define DPORT_TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070) +/* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_TRACEMEM_MUX_MODE 0x00000003 +#define DPORT_TRACEMEM_MUX_MODE_M ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S)) +#define DPORT_TRACEMEM_MUX_MODE_V 0x3 +#define DPORT_TRACEMEM_MUX_MODE_S 0 + +#define DPORT_PRO_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074) +/* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_TRACEMEM_ENA (BIT(0)) +#define DPORT_PRO_TRACEMEM_ENA_M (BIT(0)) +#define DPORT_PRO_TRACEMEM_ENA_V 0x1 +#define DPORT_PRO_TRACEMEM_ENA_S 0 + +#define DPORT_APP_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x078) +/* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_TRACEMEM_ENA (BIT(0)) +#define DPORT_APP_TRACEMEM_ENA_M (BIT(0)) +#define DPORT_APP_TRACEMEM_ENA_V 0x1 +#define DPORT_APP_TRACEMEM_ENA_S 0 + +#define DPORT_CACHE_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x07C) +/* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_CACHE_MUX_MODE 0x00000003 +#define DPORT_CACHE_MUX_MODE_M ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S)) +#define DPORT_CACHE_MUX_MODE_V 0x3 +#define DPORT_CACHE_MUX_MODE_S 0 + +#define DPORT_IMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x080) +/* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_IMMU_PAGE_MODE 0x00000003 +#define DPORT_IMMU_PAGE_MODE_M ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S)) +#define DPORT_IMMU_PAGE_MODE_V 0x3 +#define DPORT_IMMU_PAGE_MODE_S 1 +/* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0)) +#define DPORT_INTERNAL_SRAM_IMMU_ENA_M (BIT(0)) +#define DPORT_INTERNAL_SRAM_IMMU_ENA_V 0x1 +#define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0 + +#define DPORT_DMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x084) +/* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_DMMU_PAGE_MODE 0x00000003 +#define DPORT_DMMU_PAGE_MODE_M ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S)) +#define DPORT_DMMU_PAGE_MODE_V 0x3 +#define DPORT_DMMU_PAGE_MODE_S 1 +/* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0)) +#define DPORT_INTERNAL_SRAM_DMMU_ENA_M (BIT(0)) +#define DPORT_INTERNAL_SRAM_DMMU_ENA_V 0x1 +#define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0 + +#define DPORT_ROM_MPU_ENA_REG (DR_REG_DPORT_BASE + 0x088) +/* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_ROM_MPU_ENA (BIT(2)) +#define DPORT_APP_ROM_MPU_ENA_M (BIT(2)) +#define DPORT_APP_ROM_MPU_ENA_V 0x1 +#define DPORT_APP_ROM_MPU_ENA_S 2 +/* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_ROM_MPU_ENA (BIT(1)) +#define DPORT_PRO_ROM_MPU_ENA_M (BIT(1)) +#define DPORT_PRO_ROM_MPU_ENA_V 0x1 +#define DPORT_PRO_ROM_MPU_ENA_S 1 +/* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_MPU_ENA (BIT(0)) +#define DPORT_SHARE_ROM_MPU_ENA_M (BIT(0)) +#define DPORT_SHARE_ROM_MPU_ENA_V 0x1 +#define DPORT_SHARE_ROM_MPU_ENA_S 0 + +#define DPORT_MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C) +/* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_LSLP_MEM_PD_MASK (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_V 0x1 +#define DPORT_LSLP_MEM_PD_MASK_S 0 + +#define DPORT_ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090) +/* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_PD 0x0000003F +#define DPORT_SHARE_ROM_PD_M ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S)) +#define DPORT_SHARE_ROM_PD_V 0x3F +#define DPORT_SHARE_ROM_PD_S 2 +/* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define DPORT_APP_ROM_PD (BIT(1)) +#define DPORT_APP_ROM_PD_M (BIT(1)) +#define DPORT_APP_ROM_PD_V 0x1 +#define DPORT_APP_ROM_PD_S 1 +/* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define DPORT_PRO_ROM_PD (BIT(0)) +#define DPORT_PRO_ROM_PD_M (BIT(0)) +#define DPORT_PRO_ROM_PD_V 0x1 +#define DPORT_PRO_ROM_PD_S 0 + +#define DPORT_ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094) +/* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_FO 0x0000003F +#define DPORT_SHARE_ROM_FO_M ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S)) +#define DPORT_SHARE_ROM_FO_V 0x3F +#define DPORT_SHARE_ROM_FO_S 2 +/* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: */ +#define DPORT_APP_ROM_FO (BIT(1)) +#define DPORT_APP_ROM_FO_M (BIT(1)) +#define DPORT_APP_ROM_FO_V 0x1 +#define DPORT_APP_ROM_FO_S 1 +/* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: */ +#define DPORT_PRO_ROM_FO (BIT(0)) +#define DPORT_PRO_ROM_FO_M (BIT(0)) +#define DPORT_PRO_ROM_FO_V 0x1 +#define DPORT_PRO_ROM_FO_S 0 + +#define DPORT_SRAM_PD_CTRL_0_REG (DR_REG_DPORT_BASE + 0x098) +/* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_SRAM_PD_0 0xFFFFFFFF +#define DPORT_SRAM_PD_0_M ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S)) +#define DPORT_SRAM_PD_0_V 0xFFFFFFFF +#define DPORT_SRAM_PD_0_S 0 + +#define DPORT_SRAM_PD_CTRL_1_REG (DR_REG_DPORT_BASE + 0x09C) +/* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define DPORT_SRAM_PD_1 (BIT(0)) +#define DPORT_SRAM_PD_1_M (BIT(0)) +#define DPORT_SRAM_PD_1_V 0x1 +#define DPORT_SRAM_PD_1_S 0 + +#define DPORT_SRAM_FO_CTRL_0_REG (DR_REG_DPORT_BASE + 0x0A0) +/* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define DPORT_SRAM_FO_0 0xFFFFFFFF +#define DPORT_SRAM_FO_0_M ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S)) +#define DPORT_SRAM_FO_0_V 0xFFFFFFFF +#define DPORT_SRAM_FO_0_S 0 + +#define DPORT_SRAM_FO_CTRL_1_REG (DR_REG_DPORT_BASE + 0x0A4) +/* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: */ +#define DPORT_SRAM_FO_1 (BIT(0)) +#define DPORT_SRAM_FO_1_M (BIT(0)) +#define DPORT_SRAM_FO_1_V 0x1 +#define DPORT_SRAM_FO_1_S 0 + +#define DPORT_IRAM_DRAM_AHB_SEL_REG (DR_REG_DPORT_BASE + 0x0A8) +/* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */ +/*description: */ +#define DPORT_MAC_DUMP_MODE 0x00000003 +#define DPORT_MAC_DUMP_MODE_M ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S)) +#define DPORT_MAC_DUMP_MODE_V 0x3 +#define DPORT_MAC_DUMP_MODE_S 5 +/* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_AHB (BIT(4)) +#define DPORT_MASK_AHB_M (BIT(4)) +#define DPORT_MASK_AHB_V 0x1 +#define DPORT_MASK_AHB_S 4 +/* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_APP_DRAM (BIT(3)) +#define DPORT_MASK_APP_DRAM_M (BIT(3)) +#define DPORT_MASK_APP_DRAM_V 0x1 +#define DPORT_MASK_APP_DRAM_S 3 +/* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_PRO_DRAM (BIT(2)) +#define DPORT_MASK_PRO_DRAM_M (BIT(2)) +#define DPORT_MASK_PRO_DRAM_V 0x1 +#define DPORT_MASK_PRO_DRAM_S 2 +/* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_APP_IRAM (BIT(1)) +#define DPORT_MASK_APP_IRAM_M (BIT(1)) +#define DPORT_MASK_APP_IRAM_V 0x1 +#define DPORT_MASK_APP_IRAM_S 1 +/* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_PRO_IRAM (BIT(0)) +#define DPORT_MASK_PRO_IRAM_M (BIT(0)) +#define DPORT_MASK_PRO_IRAM_V 0x1 +#define DPORT_MASK_PRO_IRAM_S 0 + +#define DPORT_TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC) +/* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_TAG_PD (BIT(9)) +#define DPORT_APP_CACHE_TAG_PD_M (BIT(9)) +#define DPORT_APP_CACHE_TAG_PD_V 0x1 +#define DPORT_APP_CACHE_TAG_PD_S 9 +/* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8)) +#define DPORT_APP_CACHE_TAG_FORCE_ON_M (BIT(8)) +#define DPORT_APP_CACHE_TAG_FORCE_ON_V 0x1 +#define DPORT_APP_CACHE_TAG_FORCE_ON_S 8 +/* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_TAG_PD (BIT(1)) +#define DPORT_PRO_CACHE_TAG_PD_M (BIT(1)) +#define DPORT_PRO_CACHE_TAG_PD_V 0x1 +#define DPORT_PRO_CACHE_TAG_PD_S 1 +/* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0)) +#define DPORT_PRO_CACHE_TAG_FORCE_ON_M (BIT(0)) +#define DPORT_PRO_CACHE_TAG_FORCE_ON_V 0x1 +#define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0 + +#define DPORT_AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0) +/* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007 +#define DPORT_AHB_LITE_SDHOST_PID_REG_M ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S)) +#define DPORT_AHB_LITE_SDHOST_PID_REG_V 0x7 +#define DPORT_AHB_LITE_SDHOST_PID_REG_S 11 +/* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10)) +#define DPORT_AHB_LITE_MASK_APPDPORT_M (BIT(10)) +#define DPORT_AHB_LITE_MASK_APPDPORT_V 0x1 +#define DPORT_AHB_LITE_MASK_APPDPORT_S 10 +/* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9)) +#define DPORT_AHB_LITE_MASK_PRODPORT_M (BIT(9)) +#define DPORT_AHB_LITE_MASK_PRODPORT_V 0x1 +#define DPORT_AHB_LITE_MASK_PRODPORT_S 9 +/* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_SDIO (BIT(8)) +#define DPORT_AHB_LITE_MASK_SDIO_M (BIT(8)) +#define DPORT_AHB_LITE_MASK_SDIO_V 0x1 +#define DPORT_AHB_LITE_MASK_SDIO_S 8 +/* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_APP (BIT(4)) +#define DPORT_AHB_LITE_MASK_APP_M (BIT(4)) +#define DPORT_AHB_LITE_MASK_APP_V 0x1 +#define DPORT_AHB_LITE_MASK_APP_S 4 +/* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_PRO (BIT(0)) +#define DPORT_AHB_LITE_MASK_PRO_M (BIT(0)) +#define DPORT_AHB_LITE_MASK_PRO_V 0x1 +#define DPORT_AHB_LITE_MASK_PRO_S 0 + +#define DPORT_AHB_MPU_TABLE_0_REG (DR_REG_DPORT_BASE + 0x0B4) +/* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF +#define DPORT_AHB_ACCESS_GRANT_0_M ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S)) +#define DPORT_AHB_ACCESS_GRANT_0_V 0xFFFFFFFF +#define DPORT_AHB_ACCESS_GRANT_0_S 0 + +#define DPORT_AHB_MPU_TABLE_1_REG (DR_REG_DPORT_BASE + 0x0B8) +/* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */ +/*description: */ +#define DPORT_AHB_ACCESS_GRANT_1 0x000001FF +#define DPORT_AHB_ACCESS_GRANT_1_M ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S)) +#define DPORT_AHB_ACCESS_GRANT_1_V 0x1FF +#define DPORT_AHB_ACCESS_GRANT_1_S 0 + +#define DPORT_HOST_INF_SEL_REG (DR_REG_DPORT_BASE + 0x0BC) +/* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define DPORT_LINK_DEVICE_SEL 0x000000FF +#define DPORT_LINK_DEVICE_SEL_M ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S)) +#define DPORT_LINK_DEVICE_SEL_V 0xFF +#define DPORT_LINK_DEVICE_SEL_S 8 +/* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define DPORT_PERI_IO_SWAP 0x000000FF +#define DPORT_PERI_IO_SWAP_M ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S)) +#define DPORT_PERI_IO_SWAP_V 0xFF +#define DPORT_PERI_IO_SWAP_S 0 + +#define DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0) +/* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */ +/*description: */ +#define DPORT_PERIP_CLK_EN 0xFFFFFFFF +#define DPORT_PERIP_CLK_EN_M ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S)) +#define DPORT_PERIP_CLK_EN_V 0xFFFFFFFF +#define DPORT_PERIP_CLK_EN_S 0 + +#define DPORT_PWM3_CLK_EN (BIT(26)) +#define DPORT_PWM2_CLK_EN (BIT(25)) +#define DPORT_UART_MEM_CLK_EN (BIT(24)) +#define DPORT_UART2_CLK_EN (BIT(23)) +#define DPORT_SPI_DMA_CLK_EN (BIT(22)) +#define DPORT_I2S1_CLK_EN (BIT(21)) +#define DPORT_PWM1_CLK_EN (BIT(20)) +#define DPORT_CAN_CLK_EN (BIT(19)) +#define DPORT_I2C_EXT1_CLK_EN (BIT(18)) +#define DPORT_PWM0_CLK_EN (BIT(17)) +#define DPORT_SPI_CLK_EN_2 (BIT(16)) /** Deprecated, please use DPORT_SPI3_CLK_EN **/ +#define DPORT_SPI3_CLK_EN (BIT(16)) +#define DPORT_TIMERGROUP1_CLK_EN (BIT(15)) +#define DPORT_EFUSE_CLK_EN (BIT(14)) +#define DPORT_TIMERGROUP_CLK_EN (BIT(13)) +#define DPORT_UHCI1_CLK_EN (BIT(12)) +#define DPORT_LEDC_CLK_EN (BIT(11)) +#define DPORT_PCNT_CLK_EN (BIT(10)) +#define DPORT_RMT_CLK_EN (BIT(9)) +#define DPORT_UHCI0_CLK_EN (BIT(8)) +#define DPORT_I2C_EXT0_CLK_EN (BIT(7)) +#define DPORT_SPI_CLK_EN (BIT(6)) /** Deprecated, please use DPORT_SPI2_CLK_EN **/ +#define DPORT_SPI2_CLK_EN (BIT(6)) +#define DPORT_UART1_CLK_EN (BIT(5)) +#define DPORT_I2S0_CLK_EN (BIT(4)) +#define DPORT_WDG_CLK_EN (BIT(3)) +#define DPORT_UART_CLK_EN (BIT(2)) +#define DPORT_SPI_CLK_EN_1 (BIT(1)) /** Deprecated, please use DPORT_SPI01_CLK_EN **/ +#define DPORT_SPI01_CLK_EN (BIT(1)) +#define DPORT_TIMERS_CLK_EN (BIT(0)) +#define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4) +/* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PERIP_RST 0xFFFFFFFF +#define DPORT_PERIP_RST_M ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S)) +#define DPORT_PERIP_RST_V 0xFFFFFFFF +#define DPORT_PERIP_RST_S 0 +#define DPORT_PWM3_RST (BIT(26)) +#define DPORT_PWM2_RST (BIT(25)) +#define DPORT_UART_MEM_RST (BIT(24)) +#define DPORT_UART2_RST (BIT(23)) +#define DPORT_SPI_DMA_RST (BIT(22)) +#define DPORT_I2S1_RST (BIT(21)) +#define DPORT_PWM1_RST (BIT(20)) +#define DPORT_CAN_RST (BIT(19)) +#define DPORT_I2C_EXT1_RST (BIT(18)) +#define DPORT_PWM0_RST (BIT(17)) +#define DPORT_SPI_RST_2 (BIT(16)) /** Deprecated, please use DPORT_SPI3_RST **/ +#define DPORT_SPI3_RST (BIT(16)) +#define DPORT_TIMERGROUP1_RST (BIT(15)) +#define DPORT_EFUSE_RST (BIT(14)) +#define DPORT_TIMERGROUP_RST (BIT(13)) +#define DPORT_UHCI1_RST (BIT(12)) +#define DPORT_LEDC_RST (BIT(11)) +#define DPORT_PCNT_RST (BIT(10)) +#define DPORT_RMT_RST (BIT(9)) +#define DPORT_UHCI0_RST (BIT(8)) +#define DPORT_I2C_EXT0_RST (BIT(7)) +#define DPORT_SPI_RST (BIT(6)) /** Deprecated, please use DPORT_SPI2_RST **/ +#define DPORT_SPI2_RST (BIT(6)) +#define DPORT_UART1_RST (BIT(5)) +#define DPORT_I2S0_RST (BIT(4)) +#define DPORT_WDG_RST (BIT(3)) +#define DPORT_UART_RST (BIT(2)) +#define DPORT_SPI_RST_1 (BIT(1)) /** Deprecated, please use DPORT_SPI01_RST **/ +#define DPORT_SPI01_RST (BIT(1)) +#define DPORT_TIMERS_RST (BIT(0)) +#define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8) +/* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SPI_DECRYPT_ENABLE (BIT(12)) +#define DPORT_SPI_DECRYPT_ENABLE_M (BIT(12)) +#define DPORT_SPI_DECRYPT_ENABLE_V 0x1 +#define DPORT_SPI_DECRYPT_ENABLE_S 12 +/* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SPI_ENCRYPT_ENABLE (BIT(8)) +#define DPORT_SPI_ENCRYPT_ENABLE_M (BIT(8)) +#define DPORT_SPI_ENCRYPT_ENABLE_V 0x1 +#define DPORT_SPI_ENCRYPT_ENABLE_S 8 +/* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SLAVE_SPI_MASK_APP (BIT(4)) +#define DPORT_SLAVE_SPI_MASK_APP_M (BIT(4)) +#define DPORT_SLAVE_SPI_MASK_APP_V 0x1 +#define DPORT_SLAVE_SPI_MASK_APP_S 4 +/* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SLAVE_SPI_MASK_PRO (BIT(0)) +#define DPORT_SLAVE_SPI_MASK_PRO_M (BIT(0)) +#define DPORT_SLAVE_SPI_MASK_PRO_V 0x1 +#define DPORT_SLAVE_SPI_MASK_PRO_S 0 + +#define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC) +/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/*description: */ +#define DPORT_WIFI_CLK_EN 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S)) +#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_S 0 + +/* Mask for all Wifi clock bits - 1, 2, 10 */ +#define DPORT_WIFI_CLK_WIFI_EN 0x00000406 +#define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S)) +#define DPORT_WIFI_CLK_WIFI_EN_V 0x406 +#define DPORT_WIFI_CLK_WIFI_EN_S 0 +/* Mask for all Bluetooth clock bits - 11, 16, 17 */ +#define DPORT_WIFI_CLK_BT_EN 0x61 +#define DPORT_WIFI_CLK_BT_EN_M ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S)) +#define DPORT_WIFI_CLK_BT_EN_V 0x61 +#define DPORT_WIFI_CLK_BT_EN_S 11 +/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */ +#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 +//bluetooth baseband bit11 +#define DPORT_BT_BASEBAND_EN BIT(11) +//bluetooth LC bit16 and bit17 +#define DPORT_BT_LC_EN (BIT(16)|BIT(17)) + +/* Remaining single bit clock masks */ +#define DPORT_WIFI_CLK_SDIOSLAVE_EN BIT(4) +#define DPORT_WIFI_CLK_UNUSED_BIT5 BIT(5) +#define DPORT_WIFI_CLK_UNUSED_BIT12 BIT(12) +#define DPORT_WIFI_CLK_SDIO_HOST_EN BIT(13) +#define DPORT_WIFI_CLK_EMAC_EN BIT(14) +#define DPORT_WIFI_CLK_RNG_EN BIT(15) + +#define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) +/* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_RW_BTLP_RST (BIT(10)) +#define DPORT_RW_BTMAC_RST (BIT(9)) +#define DPORT_MACPWR_RST (BIT(8)) +#define DPORT_EMAC_RST (BIT(7)) +#define DPORT_SDIO_HOST_RST (BIT(6)) +#define DPORT_SDIO_RST (BIT(5)) +#define DPORT_BTMAC_RST (BIT(4)) +#define DPORT_BT_RST (BIT(3)) +#define DPORT_MAC_RST (BIT(2)) +#define DPORT_FE_RST (BIT(1)) +#define DPORT_BB_RST (BIT(0)) + +#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) +/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_BTEXTWAKEUP_REQ (BIT(12)) +#define DPORT_BTEXTWAKEUP_REQ_M (BIT(12)) +#define DPORT_BTEXTWAKEUP_REQ_V 0x1 +#define DPORT_BTEXTWAKEUP_REQ_S 12 +/* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ +/*description: */ +#define DPORT_BT_LPCK_DIV_NUM 0x00000FFF +#define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) +#define DPORT_BT_LPCK_DIV_NUM_V 0xFFF +#define DPORT_BT_LPCK_DIV_NUM_S 0 + +#define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_DPORT_BASE + 0x0D8) +/* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_V 0x1 +#define DPORT_LPCLK_SEL_XTAL32K_S 27 +/* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_XTAL (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_V 0x1 +#define DPORT_LPCLK_SEL_XTAL_S 26 +/* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_8M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_V 0x1 +#define DPORT_LPCLK_SEL_8M_S 25 +/* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 +#define DPORT_LPCLK_SEL_RTC_SLOW_S 24 +/* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ +/*description: */ +#define DPORT_BT_LPCK_DIV_A 0x00000FFF +#define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) +#define DPORT_BT_LPCK_DIV_A_V 0xFFF +#define DPORT_BT_LPCK_DIV_A_S 12 +/* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ +/*description: */ +#define DPORT_BT_LPCK_DIV_B 0x00000FFF +#define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) +#define DPORT_BT_LPCK_DIV_B_V 0xFFF +#define DPORT_BT_LPCK_DIV_B_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC) +/* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_0_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0) +/* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_1_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4) +/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_2_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8) +/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_3_S 0 + +#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0EC) +/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S)) +#define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_0_S 0 + +#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0F0) +/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S)) +#define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_1_S 0 + +#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x0F4) +/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S)) +#define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_2_S 0 + +#define DPORT_APP_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0F8) +/* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_0_M ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S)) +#define DPORT_APP_INTR_STATUS_0_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_0_S 0 + +#define DPORT_APP_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0FC) +/* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_1_M ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S)) +#define DPORT_APP_INTR_STATUS_1_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_1_S 0 + +#define DPORT_APP_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x100) +/* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_2_M ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S)) +#define DPORT_APP_INTR_STATUS_2_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_2_S 0 + +#define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104) +/* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_MAC_INTR_MAP 0x0000001F +#define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S)) +#define DPORT_PRO_MAC_INTR_MAP_V 0x1F +#define DPORT_PRO_MAC_INTR_MAP_S 0 + +#define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108) +/* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_MAC_NMI_MAP 0x0000001F +#define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S)) +#define DPORT_PRO_MAC_NMI_MAP_V 0x1F +#define DPORT_PRO_MAC_NMI_MAP_S 0 + +#define DPORT_PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C) +/* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_BB_INT_MAP 0x0000001F +#define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S)) +#define DPORT_PRO_BB_INT_MAP_V 0x1F +#define DPORT_PRO_BB_INT_MAP_S 0 + +#define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110) +/* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F +#define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S)) +#define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F +#define DPORT_PRO_BT_MAC_INT_MAP_S 0 + +#define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114) +/* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_BT_BB_INT_MAP 0x0000001F +#define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S)) +#define DPORT_PRO_BT_BB_INT_MAP_V 0x1F +#define DPORT_PRO_BT_BB_INT_MAP_S 0 + +#define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118) +/* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F +#define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S)) +#define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F +#define DPORT_PRO_BT_BB_NMI_MAP_S 0 + +#define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C) +/* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F +#define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S)) +#define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F +#define DPORT_PRO_RWBT_IRQ_MAP_S 0 + +#define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120) +/* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F +#define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S)) +#define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F +#define DPORT_PRO_RWBLE_IRQ_MAP_S 0 + +#define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124) +/* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RWBT_NMI_MAP 0x0000001F +#define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S)) +#define DPORT_PRO_RWBT_NMI_MAP_V 0x1F +#define DPORT_PRO_RWBT_NMI_MAP_S 0 + +#define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128) +/* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F +#define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S)) +#define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F +#define DPORT_PRO_RWBLE_NMI_MAP_S 0 + +#define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C) +/* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SLC0_INTR_MAP 0x0000001F +#define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S)) +#define DPORT_PRO_SLC0_INTR_MAP_V 0x1F +#define DPORT_PRO_SLC0_INTR_MAP_S 0 + +#define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130) +/* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SLC1_INTR_MAP 0x0000001F +#define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S)) +#define DPORT_PRO_SLC1_INTR_MAP_V 0x1F +#define DPORT_PRO_SLC1_INTR_MAP_S 0 + +#define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134) +/* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F +#define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S)) +#define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F +#define DPORT_PRO_UHCI0_INTR_MAP_S 0 + +#define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138) +/* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F +#define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S)) +#define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F +#define DPORT_PRO_UHCI1_INTR_MAP_S 0 + +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C) +/* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140) +/* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144) +/* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148) +/* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C) +/* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150) +/* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154) +/* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158) +/* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C) +/* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S)) +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 + +#define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160) +/* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164) +/* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168) +/* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C) +/* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170) +/* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174) +/* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_0_MAP_M ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S)) +#define DPORT_PRO_SPI_INTR_0_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_0_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178) +/* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S)) +#define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_1_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C) +/* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S)) +#define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_2_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180) +/* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S)) +#define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_3_MAP_S 0 + +#define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184) +/* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_I2S0_INT_MAP 0x0000001F +#define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S)) +#define DPORT_PRO_I2S0_INT_MAP_V 0x1F +#define DPORT_PRO_I2S0_INT_MAP_S 0 + +#define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188) +/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_I2S1_INT_MAP 0x0000001F +#define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S)) +#define DPORT_PRO_I2S1_INT_MAP_V 0x1F +#define DPORT_PRO_I2S1_INT_MAP_S 0 + +#define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C) +/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UART_INTR_MAP 0x0000001F +#define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S)) +#define DPORT_PRO_UART_INTR_MAP_V 0x1F +#define DPORT_PRO_UART_INTR_MAP_S 0 + +#define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190) +/* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UART1_INTR_MAP 0x0000001F +#define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S)) +#define DPORT_PRO_UART1_INTR_MAP_V 0x1F +#define DPORT_PRO_UART1_INTR_MAP_S 0 + +#define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194) +/* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UART2_INTR_MAP 0x0000001F +#define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S)) +#define DPORT_PRO_UART2_INTR_MAP_V 0x1F +#define DPORT_PRO_UART2_INTR_MAP_S 0 + +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198) +/* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S)) +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define DPORT_PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C) +/* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_EMAC_INT_MAP 0x0000001F +#define DPORT_PRO_EMAC_INT_MAP_M ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S)) +#define DPORT_PRO_EMAC_INT_MAP_V 0x1F +#define DPORT_PRO_EMAC_INT_MAP_S 0 + +#define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0) +/* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PWM0_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S)) +#define DPORT_PRO_PWM0_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM0_INTR_MAP_S 0 + +#define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4) +/* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PWM1_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S)) +#define DPORT_PRO_PWM1_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM1_INTR_MAP_S 0 + +#define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8) +/* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PWM2_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S)) +#define DPORT_PRO_PWM2_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM2_INTR_MAP_S 0 + +#define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC) +/* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PWM3_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S)) +#define DPORT_PRO_PWM3_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM3_INTR_MAP_S 0 + +#define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0) +/* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_LEDC_INT_MAP 0x0000001F +#define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S)) +#define DPORT_PRO_LEDC_INT_MAP_V 0x1F +#define DPORT_PRO_LEDC_INT_MAP_S 0 + +#define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4) +/* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_EFUSE_INT_MAP 0x0000001F +#define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S)) +#define DPORT_PRO_EFUSE_INT_MAP_V 0x1F +#define DPORT_PRO_EFUSE_INT_MAP_S 0 + +#define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8) +/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CAN_INT_MAP 0x0000001F +#define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S)) +#define DPORT_PRO_CAN_INT_MAP_V 0x1F +#define DPORT_PRO_CAN_INT_MAP_S 0 + +#define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC) +/* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F +#define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S)) +#define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F +#define DPORT_PRO_RTC_CORE_INTR_MAP_S 0 + +#define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0) +/* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RMT_INTR_MAP 0x0000001F +#define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S)) +#define DPORT_PRO_RMT_INTR_MAP_V 0x1F +#define DPORT_PRO_RMT_INTR_MAP_S 0 + +#define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4) +/* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PCNT_INTR_MAP 0x0000001F +#define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S)) +#define DPORT_PRO_PCNT_INTR_MAP_V 0x1F +#define DPORT_PRO_PCNT_INTR_MAP_S 0 + +#define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8) +/* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F +#define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S)) +#define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F +#define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0 + +#define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC) +/* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F +#define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S)) +#define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F +#define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0 + +#define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0) +/* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RSA_INTR_MAP 0x0000001F +#define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S)) +#define DPORT_PRO_RSA_INTR_MAP_V 0x1F +#define DPORT_PRO_RSA_INTR_MAP_S 0 + +#define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4) +/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0 + +#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8) +/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0 + +#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC) +/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0 + +#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0) +/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_WDG_INT_MAP 0x0000001F +#define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S)) +#define DPORT_PRO_WDG_INT_MAP_V 0x1F +#define DPORT_PRO_WDG_INT_MAP_S 0 + +#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4) +/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F +#define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S)) +#define DPORT_PRO_TIMER_INT1_MAP_V 0x1F +#define DPORT_PRO_TIMER_INT1_MAP_S 0 + +#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8) +/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F +#define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S)) +#define DPORT_PRO_TIMER_INT2_MAP_V 0x1F +#define DPORT_PRO_TIMER_INT2_MAP_S 0 + +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC) +/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0) +/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4) +/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8) +/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC) +/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200) +/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204) +/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208) +/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C) +/* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F +#define DPORT_PRO_MMU_IA_INT_MAP_M ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S)) +#define DPORT_PRO_MMU_IA_INT_MAP_V 0x1F +#define DPORT_PRO_MMU_IA_INT_MAP_S 0 + +#define DPORT_PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210) +/* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F +#define DPORT_PRO_MPU_IA_INT_MAP_M ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S)) +#define DPORT_PRO_MPU_IA_INT_MAP_V 0x1F +#define DPORT_PRO_MPU_IA_INT_MAP_S 0 + +#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214) +/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F +#define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S)) +#define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F +#define DPORT_PRO_CACHE_IA_INT_MAP_S 0 + +#define DPORT_APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218) +/* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_MAC_INTR_MAP 0x0000001F +#define DPORT_APP_MAC_INTR_MAP_M ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S)) +#define DPORT_APP_MAC_INTR_MAP_V 0x1F +#define DPORT_APP_MAC_INTR_MAP_S 0 + +#define DPORT_APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C) +/* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_MAC_NMI_MAP 0x0000001F +#define DPORT_APP_MAC_NMI_MAP_M ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S)) +#define DPORT_APP_MAC_NMI_MAP_V 0x1F +#define DPORT_APP_MAC_NMI_MAP_S 0 + +#define DPORT_APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220) +/* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_BB_INT_MAP 0x0000001F +#define DPORT_APP_BB_INT_MAP_M ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S)) +#define DPORT_APP_BB_INT_MAP_V 0x1F +#define DPORT_APP_BB_INT_MAP_S 0 + +#define DPORT_APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224) +/* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_BT_MAC_INT_MAP 0x0000001F +#define DPORT_APP_BT_MAC_INT_MAP_M ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S)) +#define DPORT_APP_BT_MAC_INT_MAP_V 0x1F +#define DPORT_APP_BT_MAC_INT_MAP_S 0 + +#define DPORT_APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228) +/* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_BT_BB_INT_MAP 0x0000001F +#define DPORT_APP_BT_BB_INT_MAP_M ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S)) +#define DPORT_APP_BT_BB_INT_MAP_V 0x1F +#define DPORT_APP_BT_BB_INT_MAP_S 0 + +#define DPORT_APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C) +/* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_BT_BB_NMI_MAP 0x0000001F +#define DPORT_APP_BT_BB_NMI_MAP_M ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S)) +#define DPORT_APP_BT_BB_NMI_MAP_V 0x1F +#define DPORT_APP_BT_BB_NMI_MAP_S 0 + +#define DPORT_APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230) +/* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RWBT_IRQ_MAP 0x0000001F +#define DPORT_APP_RWBT_IRQ_MAP_M ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S)) +#define DPORT_APP_RWBT_IRQ_MAP_V 0x1F +#define DPORT_APP_RWBT_IRQ_MAP_S 0 + +#define DPORT_APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234) +/* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F +#define DPORT_APP_RWBLE_IRQ_MAP_M ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S)) +#define DPORT_APP_RWBLE_IRQ_MAP_V 0x1F +#define DPORT_APP_RWBLE_IRQ_MAP_S 0 + +#define DPORT_APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238) +/* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RWBT_NMI_MAP 0x0000001F +#define DPORT_APP_RWBT_NMI_MAP_M ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S)) +#define DPORT_APP_RWBT_NMI_MAP_V 0x1F +#define DPORT_APP_RWBT_NMI_MAP_S 0 + +#define DPORT_APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C) +/* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RWBLE_NMI_MAP 0x0000001F +#define DPORT_APP_RWBLE_NMI_MAP_M ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S)) +#define DPORT_APP_RWBLE_NMI_MAP_V 0x1F +#define DPORT_APP_RWBLE_NMI_MAP_S 0 + +#define DPORT_APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240) +/* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SLC0_INTR_MAP 0x0000001F +#define DPORT_APP_SLC0_INTR_MAP_M ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S)) +#define DPORT_APP_SLC0_INTR_MAP_V 0x1F +#define DPORT_APP_SLC0_INTR_MAP_S 0 + +#define DPORT_APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244) +/* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SLC1_INTR_MAP 0x0000001F +#define DPORT_APP_SLC1_INTR_MAP_M ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S)) +#define DPORT_APP_SLC1_INTR_MAP_V 0x1F +#define DPORT_APP_SLC1_INTR_MAP_S 0 + +#define DPORT_APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248) +/* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UHCI0_INTR_MAP 0x0000001F +#define DPORT_APP_UHCI0_INTR_MAP_M ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S)) +#define DPORT_APP_UHCI0_INTR_MAP_V 0x1F +#define DPORT_APP_UHCI0_INTR_MAP_S 0 + +#define DPORT_APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C) +/* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UHCI1_INTR_MAP 0x0000001F +#define DPORT_APP_UHCI1_INTR_MAP_M ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S)) +#define DPORT_APP_UHCI1_INTR_MAP_V 0x1F +#define DPORT_APP_UHCI1_INTR_MAP_S 0 + +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250) +/* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254) +/* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258) +/* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C) +/* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260) +/* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264) +/* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268) +/* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C) +/* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270) +/* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S)) +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V 0x1F +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0 + +#define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274) +/* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S)) +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278) +/* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C) +/* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280) +/* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284) +/* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define DPORT_APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288) +/* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI_INTR_0_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_0_MAP_M ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S)) +#define DPORT_APP_SPI_INTR_0_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_0_MAP_S 0 + +#define DPORT_APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C) +/* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI_INTR_1_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_1_MAP_M ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S)) +#define DPORT_APP_SPI_INTR_1_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_1_MAP_S 0 + +#define DPORT_APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290) +/* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI_INTR_2_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_2_MAP_M ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S)) +#define DPORT_APP_SPI_INTR_2_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_2_MAP_S 0 + +#define DPORT_APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294) +/* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI_INTR_3_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_3_MAP_M ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S)) +#define DPORT_APP_SPI_INTR_3_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_3_MAP_S 0 + +#define DPORT_APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298) +/* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_I2S0_INT_MAP 0x0000001F +#define DPORT_APP_I2S0_INT_MAP_M ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S)) +#define DPORT_APP_I2S0_INT_MAP_V 0x1F +#define DPORT_APP_I2S0_INT_MAP_S 0 + +#define DPORT_APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C) +/* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_I2S1_INT_MAP 0x0000001F +#define DPORT_APP_I2S1_INT_MAP_M ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S)) +#define DPORT_APP_I2S1_INT_MAP_V 0x1F +#define DPORT_APP_I2S1_INT_MAP_S 0 + +#define DPORT_APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0) +/* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UART_INTR_MAP 0x0000001F +#define DPORT_APP_UART_INTR_MAP_M ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S)) +#define DPORT_APP_UART_INTR_MAP_V 0x1F +#define DPORT_APP_UART_INTR_MAP_S 0 + +#define DPORT_APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4) +/* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UART1_INTR_MAP 0x0000001F +#define DPORT_APP_UART1_INTR_MAP_M ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S)) +#define DPORT_APP_UART1_INTR_MAP_V 0x1F +#define DPORT_APP_UART1_INTR_MAP_S 0 + +#define DPORT_APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8) +/* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UART2_INTR_MAP 0x0000001F +#define DPORT_APP_UART2_INTR_MAP_M ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S)) +#define DPORT_APP_UART2_INTR_MAP_V 0x1F +#define DPORT_APP_UART2_INTR_MAP_S 0 + +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC) +/* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S)) +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define DPORT_APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0) +/* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_EMAC_INT_MAP 0x0000001F +#define DPORT_APP_EMAC_INT_MAP_M ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S)) +#define DPORT_APP_EMAC_INT_MAP_V 0x1F +#define DPORT_APP_EMAC_INT_MAP_S 0 + +#define DPORT_APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4) +/* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PWM0_INTR_MAP 0x0000001F +#define DPORT_APP_PWM0_INTR_MAP_M ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S)) +#define DPORT_APP_PWM0_INTR_MAP_V 0x1F +#define DPORT_APP_PWM0_INTR_MAP_S 0 + +#define DPORT_APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8) +/* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PWM1_INTR_MAP 0x0000001F +#define DPORT_APP_PWM1_INTR_MAP_M ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S)) +#define DPORT_APP_PWM1_INTR_MAP_V 0x1F +#define DPORT_APP_PWM1_INTR_MAP_S 0 + +#define DPORT_APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC) +/* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PWM2_INTR_MAP 0x0000001F +#define DPORT_APP_PWM2_INTR_MAP_M ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S)) +#define DPORT_APP_PWM2_INTR_MAP_V 0x1F +#define DPORT_APP_PWM2_INTR_MAP_S 0 + +#define DPORT_APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0) +/* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PWM3_INTR_MAP 0x0000001F +#define DPORT_APP_PWM3_INTR_MAP_M ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S)) +#define DPORT_APP_PWM3_INTR_MAP_V 0x1F +#define DPORT_APP_PWM3_INTR_MAP_S 0 + +#define DPORT_APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4) +/* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_LEDC_INT_MAP 0x0000001F +#define DPORT_APP_LEDC_INT_MAP_M ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S)) +#define DPORT_APP_LEDC_INT_MAP_V 0x1F +#define DPORT_APP_LEDC_INT_MAP_S 0 + +#define DPORT_APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8) +/* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_EFUSE_INT_MAP 0x0000001F +#define DPORT_APP_EFUSE_INT_MAP_M ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S)) +#define DPORT_APP_EFUSE_INT_MAP_V 0x1F +#define DPORT_APP_EFUSE_INT_MAP_S 0 + +#define DPORT_APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC) +/* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CAN_INT_MAP 0x0000001F +#define DPORT_APP_CAN_INT_MAP_M ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S)) +#define DPORT_APP_CAN_INT_MAP_V 0x1F +#define DPORT_APP_CAN_INT_MAP_S 0 + +#define DPORT_APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0) +/* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F +#define DPORT_APP_RTC_CORE_INTR_MAP_M ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S)) +#define DPORT_APP_RTC_CORE_INTR_MAP_V 0x1F +#define DPORT_APP_RTC_CORE_INTR_MAP_S 0 + +#define DPORT_APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4) +/* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RMT_INTR_MAP 0x0000001F +#define DPORT_APP_RMT_INTR_MAP_M ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S)) +#define DPORT_APP_RMT_INTR_MAP_V 0x1F +#define DPORT_APP_RMT_INTR_MAP_S 0 + +#define DPORT_APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8) +/* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PCNT_INTR_MAP 0x0000001F +#define DPORT_APP_PCNT_INTR_MAP_M ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S)) +#define DPORT_APP_PCNT_INTR_MAP_V 0x1F +#define DPORT_APP_PCNT_INTR_MAP_S 0 + +#define DPORT_APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC) +/* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F +#define DPORT_APP_I2C_EXT0_INTR_MAP_M ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S)) +#define DPORT_APP_I2C_EXT0_INTR_MAP_V 0x1F +#define DPORT_APP_I2C_EXT0_INTR_MAP_S 0 + +#define DPORT_APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0) +/* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F +#define DPORT_APP_I2C_EXT1_INTR_MAP_M ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S)) +#define DPORT_APP_I2C_EXT1_INTR_MAP_V 0x1F +#define DPORT_APP_I2C_EXT1_INTR_MAP_S 0 + +#define DPORT_APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4) +/* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RSA_INTR_MAP 0x0000001F +#define DPORT_APP_RSA_INTR_MAP_M ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S)) +#define DPORT_APP_RSA_INTR_MAP_V 0x1F +#define DPORT_APP_RSA_INTR_MAP_S 0 + +#define DPORT_APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8) +/* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI1_DMA_INT_MAP_M ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S)) +#define DPORT_APP_SPI1_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI1_DMA_INT_MAP_S 0 + +#define DPORT_APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC) +/* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI2_DMA_INT_MAP_M ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S)) +#define DPORT_APP_SPI2_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI2_DMA_INT_MAP_S 0 + +#define DPORT_APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0) +/* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI3_DMA_INT_MAP_M ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S)) +#define DPORT_APP_SPI3_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI3_DMA_INT_MAP_S 0 + +#define DPORT_APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4) +/* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_WDG_INT_MAP 0x0000001F +#define DPORT_APP_WDG_INT_MAP_M ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S)) +#define DPORT_APP_WDG_INT_MAP_V 0x1F +#define DPORT_APP_WDG_INT_MAP_S 0 + +#define DPORT_APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8) +/* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TIMER_INT1_MAP 0x0000001F +#define DPORT_APP_TIMER_INT1_MAP_M ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S)) +#define DPORT_APP_TIMER_INT1_MAP_V 0x1F +#define DPORT_APP_TIMER_INT1_MAP_S 0 + +#define DPORT_APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC) +/* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TIMER_INT2_MAP 0x0000001F +#define DPORT_APP_TIMER_INT2_MAP_M ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S)) +#define DPORT_APP_TIMER_INT2_MAP_V 0x1F +#define DPORT_APP_TIMER_INT2_MAP_S 0 + +#define DPORT_APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300) +/* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_T0_EDGE_INT_MAP_M ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304) +/* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_T1_EDGE_INT_MAP_M ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308) +/* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C) +/* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310) +/* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_M ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314) +/* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_M ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318) +/* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C) +/* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320) +/* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_MMU_IA_INT_MAP 0x0000001F +#define DPORT_APP_MMU_IA_INT_MAP_M ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S)) +#define DPORT_APP_MMU_IA_INT_MAP_V 0x1F +#define DPORT_APP_MMU_IA_INT_MAP_S 0 + +#define DPORT_APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324) +/* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_MPU_IA_INT_MAP 0x0000001F +#define DPORT_APP_MPU_IA_INT_MAP_M ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S)) +#define DPORT_APP_MPU_IA_INT_MAP_V 0x1F +#define DPORT_APP_MPU_IA_INT_MAP_S 0 + +#define DPORT_APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328) +/* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F +#define DPORT_APP_CACHE_IA_INT_MAP_M ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S)) +#define DPORT_APP_CACHE_IA_INT_MAP_V 0x1F +#define DPORT_APP_CACHE_IA_INT_MAP_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART_REG (DR_REG_DPORT_BASE + 0x32C) +/* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART_ACCESS_GRANT_CONFIG_M ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI1_REG (DR_REG_DPORT_BASE + 0x330) +/* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_M ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI0_REG (DR_REG_DPORT_BASE + 0x334) +/* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_M ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_GPIO_REG (DR_REG_DPORT_BASE + 0x338) +/* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_M ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S)) +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_FE2_REG (DR_REG_DPORT_BASE + 0x33C) +/* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_FE2_ACCESS_GRANT_CONFIG_M ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_FE2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_FE_REG (DR_REG_DPORT_BASE + 0x340) +/* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_FE_ACCESS_GRANT_CONFIG_M ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S)) +#define DPORT_FE_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_FE_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMER_REG (DR_REG_DPORT_BASE + 0x344) +/* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_M ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RTC_REG (DR_REG_DPORT_BASE + 0x348) +/* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RTC_ACCESS_GRANT_CONFIG_M ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RTC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (DR_REG_DPORT_BASE + 0x34C) +/* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S)) +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_WDG_REG (DR_REG_DPORT_BASE + 0x350) +/* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_WDG_ACCESS_GRANT_CONFIG_M ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S)) +#define DPORT_WDG_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_HINF_REG (DR_REG_DPORT_BASE + 0x354) +/* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_HINF_ACCESS_GRANT_CONFIG_M ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S)) +#define DPORT_HINF_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (DR_REG_DPORT_BASE + 0x358) +/* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_MISC_REG (DR_REG_DPORT_BASE + 0x35C) +/* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_MISC_ACCESS_GRANT_CONFIG_M ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_MISC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_REG (DR_REG_DPORT_BASE + 0x360) +/* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2C_ACCESS_GRANT_CONFIG_M ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2C_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2S0_REG (DR_REG_DPORT_BASE + 0x364) +/* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_M ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART1_REG (DR_REG_DPORT_BASE + 0x368) +/* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART1_ACCESS_GRANT_CONFIG_M ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BT_REG (DR_REG_DPORT_BASE + 0x36C) +/* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BT_ACCESS_GRANT_CONFIG_M ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG (DR_REG_DPORT_BASE + 0x370) +/* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (DR_REG_DPORT_BASE + 0x374) +/* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (DR_REG_DPORT_BASE + 0x378) +/* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (DR_REG_DPORT_BASE + 0x37C) +/* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RMT_REG (DR_REG_DPORT_BASE + 0x380) +/* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RMT_ACCESS_GRANT_CONFIG_M ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RMT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PCNT_REG (DR_REG_DPORT_BASE + 0x384) +/* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_M ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SLC_REG (DR_REG_DPORT_BASE + 0x388) +/* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SLC_ACCESS_GRANT_CONFIG_M ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SLC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_LEDC_REG (DR_REG_DPORT_BASE + 0x38C) +/* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_M ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (DR_REG_DPORT_BASE + 0x390) +/* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S)) +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (DR_REG_DPORT_BASE + 0x394) +/* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BB_REG (DR_REG_DPORT_BASE + 0x398) +/* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BB_ACCESS_GRANT_CONFIG_M ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BB_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BB_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM0_REG (DR_REG_DPORT_BASE + 0x39C) +/* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_M ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (DR_REG_DPORT_BASE + 0x3A0) +/* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (DR_REG_DPORT_BASE + 0x3A4) +/* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI2_REG (DR_REG_DPORT_BASE + 0x3A8) +/* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_M ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI3_REG (DR_REG_DPORT_BASE + 0x3AC) +/* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_M ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (DR_REG_DPORT_BASE + 0x3B0) +/* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S)) +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (DR_REG_DPORT_BASE + 0x3B4) +/* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (DR_REG_DPORT_BASE + 0x3B8) +/* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_EMAC_REG (DR_REG_DPORT_BASE + 0x3BC) +/* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_M ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_CAN_REG (DR_REG_DPORT_BASE + 0x3C0) +/* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_CAN_ACCESS_GRANT_CONFIG_M ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S)) +#define DPORT_CAN_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM1_REG (DR_REG_DPORT_BASE + 0x3C4) +/* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_M ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2S1_REG (DR_REG_DPORT_BASE + 0x3C8) +/* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_M ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART2_REG (DR_REG_DPORT_BASE + 0x3CC) +/* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART2_ACCESS_GRANT_CONFIG_M ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM2_REG (DR_REG_DPORT_BASE + 0x3D0) +/* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_M ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM3_REG (DR_REG_DPORT_BASE + 0x3D4) +/* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_M ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RWBT_REG (DR_REG_DPORT_BASE + 0x3D8) +/* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_M ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG (DR_REG_DPORT_BASE + 0x3DC) +/* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG (DR_REG_DPORT_BASE + 0x3E0) +/* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWR_REG (DR_REG_DPORT_BASE + 0x3E4) +/* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWR_ACCESS_GRANT_CONFIG_M ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWR_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_MEM_ACCESS_DBUG0_REG (DR_REG_DPORT_BASE + 0x3E8) +/* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S)) +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26 +/* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_IA 0x00000FFF +#define DPORT_INTERNAL_SRAM_IA_M ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S)) +#define DPORT_INTERNAL_SRAM_IA_V 0xFFF +#define DPORT_INTERNAL_SRAM_IA_S 14 +/* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_AD_M ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S)) +#define DPORT_INTERNAL_SRAM_MMU_AD_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_AD_S 10 +/* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_IA 0x0000000F +#define DPORT_SHARE_ROM_IA_M ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S)) +#define DPORT_SHARE_ROM_IA_V 0xF +#define DPORT_SHARE_ROM_IA_S 6 +/* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_MPU_AD 0x00000003 +#define DPORT_SHARE_ROM_MPU_AD_M ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S)) +#define DPORT_SHARE_ROM_MPU_AD_V 0x3 +#define DPORT_SHARE_ROM_MPU_AD_S 4 +/* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_ROM_IA (BIT(3)) +#define DPORT_APP_ROM_IA_M (BIT(3)) +#define DPORT_APP_ROM_IA_V 0x1 +#define DPORT_APP_ROM_IA_S 3 +/* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_ROM_MPU_AD (BIT(2)) +#define DPORT_APP_ROM_MPU_AD_M (BIT(2)) +#define DPORT_APP_ROM_MPU_AD_V 0x1 +#define DPORT_APP_ROM_MPU_AD_S 2 +/* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_ROM_IA (BIT(1)) +#define DPORT_PRO_ROM_IA_M (BIT(1)) +#define DPORT_PRO_ROM_IA_V 0x1 +#define DPORT_PRO_ROM_IA_S 1 +/* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_ROM_MPU_AD (BIT(0)) +#define DPORT_PRO_ROM_MPU_AD_M (BIT(0)) +#define DPORT_PRO_ROM_MPU_AD_V 0x1 +#define DPORT_PRO_ROM_MPU_AD_S 0 + +#define DPORT_MEM_ACCESS_DBUG1_REG (DR_REG_DPORT_BASE + 0x3EC) +/* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHBLITE_IA (BIT(10)) +#define DPORT_AHBLITE_IA_M (BIT(10)) +#define DPORT_AHBLITE_IA_V 0x1 +#define DPORT_AHBLITE_IA_S 10 +/* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHBLITE_ACCESS_DENY (BIT(9)) +#define DPORT_AHBLITE_ACCESS_DENY_M (BIT(9)) +#define DPORT_AHBLITE_ACCESS_DENY_V 0x1 +#define DPORT_AHBLITE_ACCESS_DENY_S 9 +/* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_ACCESS_DENY (BIT(8)) +#define DPORT_AHB_ACCESS_DENY_M (BIT(8)) +#define DPORT_AHB_ACCESS_DENY_V 0x1 +#define DPORT_AHB_ACCESS_DENY_S 8 +/* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_PIDGEN_IA 0x00000003 +#define DPORT_PIDGEN_IA_M ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S)) +#define DPORT_PIDGEN_IA_V 0x3 +#define DPORT_PIDGEN_IA_S 6 +/* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_ARB_IA 0x00000003 +#define DPORT_ARB_IA_M ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S)) +#define DPORT_ARB_IA_V 0x3 +#define DPORT_ARB_IA_S 4 +/* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_MISS_M ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S)) +#define DPORT_INTERNAL_SRAM_MMU_MISS_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_MISS_S 0 + +#define DPORT_PRO_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x3F0) +/* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_RX_END (BIT(23)) +#define DPORT_PRO_RX_END_M (BIT(23)) +#define DPORT_PRO_RX_END_V 0x1 +#define DPORT_PRO_RX_END_S 23 +/* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_SLAVE_WDATA_V (BIT(22)) +#define DPORT_PRO_SLAVE_WDATA_V_M (BIT(22)) +#define DPORT_PRO_SLAVE_WDATA_V_V 0x1 +#define DPORT_PRO_SLAVE_WDATA_V_S 22 +/* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_SLAVE_WR (BIT(21)) +#define DPORT_PRO_SLAVE_WR_M (BIT(21)) +#define DPORT_PRO_SLAVE_WR_V 0x1 +#define DPORT_PRO_SLAVE_WR_S 21 +/* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_TX_END (BIT(20)) +#define DPORT_PRO_TX_END_M (BIT(20)) +#define DPORT_PRO_TX_END_V 0x1 +#define DPORT_PRO_TX_END_S 20 +/* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_WR_BAK_TO_READ (BIT(19)) +#define DPORT_PRO_WR_BAK_TO_READ_M (BIT(19)) +#define DPORT_PRO_WR_BAK_TO_READ_V 0x1 +#define DPORT_PRO_WR_BAK_TO_READ_S 19 +/* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_STATE 0x00000FFF +#define DPORT_PRO_CACHE_STATE_M ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S)) +#define DPORT_PRO_CACHE_STATE_V 0xFFF +#define DPORT_PRO_CACHE_STATE_S 7 +/* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_IA 0x0000003F +#define DPORT_PRO_CACHE_IA_M ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S)) +#define DPORT_PRO_CACHE_IA_V 0x3F +#define DPORT_PRO_CACHE_IA_S 1 +/* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MMU_IA (BIT(0)) +#define DPORT_PRO_CACHE_MMU_IA_M (BIT(0)) +#define DPORT_PRO_CACHE_MMU_IA_V 0x1 +#define DPORT_PRO_CACHE_MMU_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x3F4) +/* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF +#define DPORT_PRO_CTAG_RAM_RDATA_M ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S)) +#define DPORT_PRO_CTAG_RAM_RDATA_V 0xFFFFFFFF +#define DPORT_PRO_CTAG_RAM_RDATA_S 0 + +#define DPORT_PRO_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x3F8) +/* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_VADDR 0x07FFFFFF +#define DPORT_PRO_CACHE_VADDR_M ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S)) +#define DPORT_PRO_CACHE_VADDR_V 0x7FFFFFF +#define DPORT_PRO_CACHE_VADDR_S 0 + +#define DPORT_PRO_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x3FC) +/* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15)) +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M (BIT(15)) +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V 0x1 +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15 +/* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S)) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9 +/* This is the contents of DPORT_PRO_CPU_DISABLED_CACHE_IA field expanded */ +/* The following bits will be set upon invalid access for different memory + * regions: */ +/* Port of the APP CPU cache when cache is used in high/low or odd/even mode */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE BIT(9) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1 +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9 +/* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 BIT(10) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_M BIT(10) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_V 1 +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_S 10 +/* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0 BIT(11) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_M BIT(11) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_V 1 +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_S 11 +/* IRAM1: 0x4040_0000 ~ 0x407F_FFFF(RO) */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 BIT(12) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_M BIT(12) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_V 1 +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_S 12 +/* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0 BIT(13) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_M BIT(13) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_V 1 +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_S 13 +/* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 BIT(14) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_M BIT(14) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_V 1 +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_S 14 + +/* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define DPORT_PRO_MMU_RDATA 0x000001FF +#define DPORT_PRO_MMU_RDATA_M ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S)) +#define DPORT_PRO_MMU_RDATA_V 0x1FF +#define DPORT_PRO_MMU_RDATA_S 0 + +#define DPORT_PRO_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x400) +/* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF +#define DPORT_PRO_DRAM1ADDR0_IA_M ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S)) +#define DPORT_PRO_DRAM1ADDR0_IA_V 0xFFFFF +#define DPORT_PRO_DRAM1ADDR0_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x404) +/* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF +#define DPORT_PRO_DROM0ADDR0_IA_M ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S)) +#define DPORT_PRO_DROM0ADDR0_IA_V 0xFFFFF +#define DPORT_PRO_DROM0ADDR0_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x408) +/* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF +#define DPORT_PRO_IRAM0ADDR_IA_M ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S)) +#define DPORT_PRO_IRAM0ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IRAM0ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x40C) +/* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF +#define DPORT_PRO_IRAM1ADDR_IA_M ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S)) +#define DPORT_PRO_IRAM1ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IRAM1ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x410) +/* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF +#define DPORT_PRO_IROM0ADDR_IA_M ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S)) +#define DPORT_PRO_IROM0ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IROM0ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x414) +/* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF +#define DPORT_PRO_OPSDRAMADDR_IA_M ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S)) +#define DPORT_PRO_OPSDRAMADDR_IA_V 0xFFFFF +#define DPORT_PRO_OPSDRAMADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x418) +/* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_RX_END (BIT(23)) +#define DPORT_APP_RX_END_M (BIT(23)) +#define DPORT_APP_RX_END_V 0x1 +#define DPORT_APP_RX_END_S 23 +/* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_SLAVE_WDATA_V (BIT(22)) +#define DPORT_APP_SLAVE_WDATA_V_M (BIT(22)) +#define DPORT_APP_SLAVE_WDATA_V_V 0x1 +#define DPORT_APP_SLAVE_WDATA_V_S 22 +/* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_SLAVE_WR (BIT(21)) +#define DPORT_APP_SLAVE_WR_M (BIT(21)) +#define DPORT_APP_SLAVE_WR_V 0x1 +#define DPORT_APP_SLAVE_WR_S 21 +/* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_TX_END (BIT(20)) +#define DPORT_APP_TX_END_M (BIT(20)) +#define DPORT_APP_TX_END_V 0x1 +#define DPORT_APP_TX_END_S 20 +/* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_WR_BAK_TO_READ (BIT(19)) +#define DPORT_APP_WR_BAK_TO_READ_M (BIT(19)) +#define DPORT_APP_WR_BAK_TO_READ_V 0x1 +#define DPORT_APP_WR_BAK_TO_READ_S 19 +/* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_STATE 0x00000FFF +#define DPORT_APP_CACHE_STATE_M ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S)) +#define DPORT_APP_CACHE_STATE_V 0xFFF +#define DPORT_APP_CACHE_STATE_S 7 +/* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_IA 0x0000003F +#define DPORT_APP_CACHE_IA_M ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S)) +#define DPORT_APP_CACHE_IA_V 0x3F +#define DPORT_APP_CACHE_IA_S 1 +/* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_MMU_IA (BIT(0)) +#define DPORT_APP_CACHE_MMU_IA_M (BIT(0)) +#define DPORT_APP_CACHE_MMU_IA_V 0x1 +#define DPORT_APP_CACHE_MMU_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x41C) +/* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF +#define DPORT_APP_CTAG_RAM_RDATA_M ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S)) +#define DPORT_APP_CTAG_RAM_RDATA_V 0xFFFFFFFF +#define DPORT_APP_CTAG_RAM_RDATA_S 0 + +#define DPORT_APP_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x420) +/* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_VADDR 0x07FFFFFF +#define DPORT_APP_CACHE_VADDR_M ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S)) +#define DPORT_APP_CACHE_VADDR_V 0x7FFFFFF +#define DPORT_APP_CACHE_VADDR_S 0 + +#define DPORT_APP_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x424) +/* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15)) +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_M (BIT(15)) +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_V 0x1 +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15 +/* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F +#define DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S)) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F +#define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9 +/* This is the contents of DPORT_APP_CPU_DISABLED_CACHE_IA field expanded */ +/* The following bits will be set upon invalid access for different memory + * regions: */ +/* Port of the PRO CPU cache when cache is used in high/low or odd/even mode */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE BIT(9) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1 +#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9 +/* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 BIT(10) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_M BIT(10) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_V 1 +#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_S 10 +/* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0 BIT(11) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_M BIT(11) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_V 1 +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_S 11 +/* IRAM1: 0x4040_0000 ~ 0x407F_FFFF(RO) */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 BIT(12) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_M BIT(12) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_V 1 +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_S 12 +/* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0 BIT(13) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_M BIT(13) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_V 1 +#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_S 13 +/* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0 BIT(14) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_M BIT(14) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_V 1 +#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_S 14 + +/* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define DPORT_APP_MMU_RDATA 0x000001FF +#define DPORT_APP_MMU_RDATA_M ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S)) +#define DPORT_APP_MMU_RDATA_V 0x1FF +#define DPORT_APP_MMU_RDATA_S 0 + +#define DPORT_APP_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x428) +/* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF +#define DPORT_APP_DRAM1ADDR0_IA_M ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S)) +#define DPORT_APP_DRAM1ADDR0_IA_V 0xFFFFF +#define DPORT_APP_DRAM1ADDR0_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x42C) +/* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF +#define DPORT_APP_DROM0ADDR0_IA_M ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S)) +#define DPORT_APP_DROM0ADDR0_IA_V 0xFFFFF +#define DPORT_APP_DROM0ADDR0_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x430) +/* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF +#define DPORT_APP_IRAM0ADDR_IA_M ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S)) +#define DPORT_APP_IRAM0ADDR_IA_V 0xFFFFF +#define DPORT_APP_IRAM0ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x434) +/* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF +#define DPORT_APP_IRAM1ADDR_IA_M ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S)) +#define DPORT_APP_IRAM1ADDR_IA_V 0xFFFFF +#define DPORT_APP_IRAM1ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x438) +/* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_IROM0ADDR_IA 0x000FFFFF +#define DPORT_APP_IROM0ADDR_IA_M ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S)) +#define DPORT_APP_IROM0ADDR_IA_V 0xFFFFF +#define DPORT_APP_IROM0ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x43C) +/* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF +#define DPORT_APP_OPSDRAMADDR_IA_M ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S)) +#define DPORT_APP_OPSDRAMADDR_IA_V 0xFFFFF +#define DPORT_APP_OPSDRAMADDR_IA_S 0 + +#define DPORT_PRO_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x440) +/* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8)) +#define DPORT_PRO_CPU_PDEBUG_ENABLE_M (BIT(8)) +#define DPORT_PRO_CPU_PDEBUG_ENABLE_V 0x1 +#define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8 +/* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4)) +#define DPORT_PRO_CPU_RECORD_DISABLE_M (BIT(4)) +#define DPORT_PRO_CPU_RECORD_DISABLE_V 0x1 +#define DPORT_PRO_CPU_RECORD_DISABLE_S 4 +/* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0)) +#define DPORT_PRO_CPU_RECORD_ENABLE_M (BIT(0)) +#define DPORT_PRO_CPU_RECORD_ENABLE_V 0x1 +#define DPORT_PRO_CPU_RECORD_ENABLE_S 0 + +#define DPORT_PRO_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x444) +/* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CPU_RECORDING (BIT(0)) +#define DPORT_PRO_CPU_RECORDING_M (BIT(0)) +#define DPORT_PRO_CPU_RECORDING_V 0x1 +#define DPORT_PRO_CPU_RECORDING_S 0 + +#define DPORT_PRO_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x448) +/* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PID 0x00000007 +#define DPORT_RECORD_PRO_PID_M ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S)) +#define DPORT_RECORD_PRO_PID_V 0x7 +#define DPORT_RECORD_PRO_PID_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x44C) +/* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S)) +#define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGINST_S 0 +/* register layout: + * SIZE [7..0] : Instructions normally complete in the W stage. The size of the instruction in the W is given + * by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing + * instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG. + * ISRC [14..12] : Instruction source. +** LOOP [23..20] : Loopback status. +** CINTLEVEL [27..24]: CINTLEVEL. +*/ +#define DPORT_RECORD_PDEBUGINST_SZ_M ((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S)) +#define DPORT_RECORD_PDEBUGINST_SZ_V 0xFF +#define DPORT_RECORD_PDEBUGINST_SZ_S 0 +#define DPORT_RECORD_PDEBUGINST_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V) +#define DPORT_RECORD_PDEBUGINST_ISRC_M ((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S)) +#define DPORT_RECORD_PDEBUGINST_ISRC_V 0x07 +#define DPORT_RECORD_PDEBUGINST_ISRC_S 12 +#define DPORT_RECORD_PDEBUGINST_ISRC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V) +// #define DPORT_RECORD_PDEBUGINST_LOOP_M ((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S)) +// #define DPORT_RECORD_PDEBUGINST_LOOP_V 0x0F +// #define DPORT_RECORD_PDEBUGINST_LOOP_S 20 +// #define DPORT_RECORD_PDEBUGINST_LOOP(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V) +#define DPORT_RECORD_PDEBUGINST_LOOP_REP (BIT(20)) /* loopback will occur */ +#define DPORT_RECORD_PDEBUGINST_LOOP (BIT(21)) /* last inst of loop */ +#define DPORT_RECORD_PDEBUGINST_CINTL_M ((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S)) +#define DPORT_RECORD_PDEBUGINST_CINTL_V 0x0F +#define DPORT_RECORD_PDEBUGINST_CINTL_S 24 +#define DPORT_RECORD_PDEBUGINST_CINTL(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V) + +#define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450) +/* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF +#define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S)) +#define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF +#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0 +/* register layout: + * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0 + * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0 +*/ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S)) +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V 0x3F +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S 0 +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V) +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO 0x00 /* Power shut off */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP 0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL 0x04 /* Control transfer bubble */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM 0x08 /* I-cache miss (incl uncached miss) */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM 0x0C /* D-cache miss (excl uncached miss) */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0 0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. + The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1 0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL 0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB 0x18 /* HW ITLB refill. The refill address and data are available on + DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM 0x1A /* ITLB miss */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB 0x1C /* HW DTLB refill. The refill address and data are available on + DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM 0x1E /* DTLB miss */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL 0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC 0x24 /* HW-corrected memory error */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI 0x28 /* WAITI mode */ +#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER 0x3C /* all other bubbles */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M ((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S)) +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V 0x3F +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S 0 +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V) +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX 0x00 /* JX */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX 0x04 /* CALLX */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET 0x08 /* All call returns */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET 0x0C /* All exception returns */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B 0x10 /* Branch taken or loop not taken */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J 0x14 /* J */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL 0x18 /* CALL */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN 0x1C /* Branch not taken */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP 0x20 /* Loop instruction (taken) */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I 0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB 0x28 /* WSR/XSR to LBEGIN */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID 0x2C /* WSR to MMID */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR 0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER 0x34 /* RER or WER */ +#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF 0x3C /* Default */ + +#define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454) +/* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S)) +#define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGDATA_S 0 +/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP: + * + * HALT [17]: HALT instruction (TX only) + * MEMW [16]: MEMW, EXTW or EXCW instruction dependency + * REG [12]: register dependencies or resource (e.g.TIE ports) conflicts + * STR [11]: store release (instruction) dependency + * LSU [8] : various LSU dependencies (MHT access, prefetch, cache access insts, s32c1i, etc) + * OTHER[0] : all other hold dependencies resulting from data or resource dependencies +*/ +#define DPORT_RECORD_PDEBUGDATA_DEP_HALT (BIT(17)) +#define DPORT_RECORD_PDEBUGDATA_DEP_MEMW (BIT(16)) +#define DPORT_RECORD_PDEBUGDATA_DEP_REG (BIT(12)) +#define DPORT_RECORD_PDEBUGDATA_DEP_STR (BIT(11)) +#define DPORT_RECORD_PDEBUGDATA_DEP_LSU (BIT(8)) +#define DPORT_RECORD_PDEBUGDATA_DEP_OTHER (BIT(0)) +/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXCn: + * + * EXCCAUSE[21..16]: Processor exception cause + * EXCVEC [4..0] : Encoded Exception Vector +*/ +#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S)) +#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V 0x3F +#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S 16 +#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V) +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S)) +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_V 0x1F +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_S 0 +#define DPORT_RECORD_PDEBUGDATA_EXCVEC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V) +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_NONE 0x00 /* no vector */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_RST 0x01 /* Reset */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBG 0x02 /* Debug (repl corresp level “n”) */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_NMI 0x03 /* NMI (repl corresp level “n”) */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_USR 0x04 /* User */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_KRNL 0x05 /* Kernel */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBL 0x06 /* Double */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_EMEM 0x07 /* Memory Error */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF4 0x0A /* Window Overflow 4 */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF4 0x0B /* Window Underflow 4 */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF8 0x0C /* Window Overflow 8 */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF8 0x0D /* Window Underflow 8 */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF12 0x0E /* Window Overflow 12 */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF12 0x0F /* Window Underflow 12 */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT2 0x10 /* Int Level 2 (n/a if debug/NMI) */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT3 0x11 /* Int Level 3 (n/a if debug/NMI) */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT4 0x12 /* Int Level 4 (n/a if debug/NMI) */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT5 0x13 /* Int Level 5 (n/a if debug/NMI) */ +#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT6 0x14 /* Int Level 6 (n/a if debug/NMI) */ +/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL: + * + * ITERDIV[19] : Iterative divide stall. + * ITERMUL[18] : Iterative multiply stall. + * BANKCONFL[16]: Bank-conflict stall. + * BPLOAD[15] : Bypass load stall. + * LSPROC[14] : Load/store miss-processing stall. + * L32R[13] : FastL32R stall. + * BPIFETCH[12] : Bypass I fetch stall. + * RUNSTALL[10] : RunStall. + * TIE[9] : TIE port stall. + * IPIF[8] : Instruction RAM inbound-PIF stall. + * IRAMBUSY[7] : Instruction RAM/ROM busy stall. + * ICM[6] : I-cache-miss stall. + * LSU[4] : The LSU will stall the pipeline under various local memory access conflict situations. + * DCM[3] : D-cache-miss stall. + * BUFFCONFL[2] : Store buffer conflict stall. + * BUFF[1] : Store buffer full stall. +*/ +#define DPORT_RECORD_PDEBUGDATA_STALL_ITERDIV (BIT(19)) +#define DPORT_RECORD_PDEBUGDATA_STALL_ITERMUL (BIT(18)) +#define DPORT_RECORD_PDEBUGDATA_STALL_BANKCONFL (BIT(16)) +#define DPORT_RECORD_PDEBUGDATA_STALL_BPLOAD (BIT(15)) +#define DPORT_RECORD_PDEBUGDATA_STALL_LSPROC (BIT(14)) +#define DPORT_RECORD_PDEBUGDATA_STALL_L32R (BIT(13)) +#define DPORT_RECORD_PDEBUGDATA_STALL_BPIFETCH (BIT(12)) +#define DPORT_RECORD_PDEBUGDATA_STALL_RUN (BIT(10)) +#define DPORT_RECORD_PDEBUGDATA_STALL_TIE (BIT(9)) +#define DPORT_RECORD_PDEBUGDATA_STALL_IPIF (BIT(8)) +#define DPORT_RECORD_PDEBUGDATA_STALL_IRAMBUSY (BIT(7)) +#define DPORT_RECORD_PDEBUGDATA_STALL_ICM (BIT(6)) +#define DPORT_RECORD_PDEBUGDATA_STALL_LSU (BIT(4)) +#define DPORT_RECORD_PDEBUGDATA_STALL_DCM (BIT(3)) +#define DPORT_RECORD_PDEBUGDATA_STALL_BUFFCONFL (BIT(2)) +#define DPORT_RECORD_PDEBUGDATA_STALL_BUFF (BIT(1)) +/* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR: + * + * XSR[10] : XSR Instruction + * WSR[9] : WSR Instruction + * RSR[8] : RSR Instruction + * SR[7..0] : Special Register Number +*/ +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_XSR (BIT(10)) +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WSR (BIT(9)) +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RSR (BIT(8)) +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S)) +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V 0xFF +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S 0 +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V) +/* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER: + * + * ER[13..2]: ER Address + * WER[1] : WER Instruction + * RER[0] : RER Instruction +*/ +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S)) +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V 0xFFF +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S 2 +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V) +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WER (BIT(1)) +#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RER (BIT(0)) + + +#define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458) +/* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGPC_M ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S)) +#define DPORT_RECORD_PRO_PDEBUGPC_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGPC_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x45C) +/* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0 +/* register layout: + * TYPE [3..0] : Type of instruction in LS. + * SZ [7..4] : Operand size. + * DTLBM [8] : Data TLB miss. + * DCM [9] : D-cache miss. + * DCH [10] : D-cache hit. + * UC [12] : Uncached. + * WB [13] : Writeback. + * COH [16] : Coherency. + * STCOH [18..17]: Coherent state. + * TGT [23..20] : Local target. +*/ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_M ((DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TYPE_S)) +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_V 0x0F +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S 0 +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TYPE_S) & DPORT_RECORD_PDEBUGLS0STAT_TYPE_V) +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_NONE 0x00 /* neither */ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_ITLBR 0x01 /* hw itlb refill */ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_DTLBR 0x02 /* hw dtlb refill */ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_LD 0x05 /* load */ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_STR 0x06 /* store */ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_L32R 0x08 /* l32r */ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S32CLI1 0x0A /* s32ci1 */ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_CTI 0x0C /* cache test inst */ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWXSR 0x0E /* rsr/wsr/xsr */ +#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWER 0x0F /* rer/wer */ +#define DPORT_RECORD_PDEBUGLS0STAT_SZ_M ((DPORT_RECORD_PDEBUGLS0STAT_SZ_V)<<(DPORT_RECORD_PDEBUGLS0STAT_SZ_S)) +#define DPORT_RECORD_PDEBUGLS0STAT_SZ_V 0x0F +#define DPORT_RECORD_PDEBUGLS0STAT_SZ_S 4 +#define DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_SZ_S) & DPORT_RECORD_PDEBUGLS0STAT_SZ_V) +#define DPORT_RECORD_PDEBUGLS0STAT_SZB(_r_) ((8<>DPORT_RECORD_PDEBUGLS0STAT_STCOH_S) & DPORT_RECORD_PDEBUGLS0STAT_STCOH_V) +#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_NONE 0x0 /* neither shared nor exclusive nor modified */ +#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_SHARED 0x1 /* shared */ +#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_EXCL 0x2 /* exclusive */ +#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_MOD 0x3 /* modified */ +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_M ((DPORT_RECORD_PDEBUGLS0STAT_TGT_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TGT_S)) +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_V 0x0F +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_S 20 +#define DPORT_RECORD_PDEBUGLS0STAT_TGT(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TGT_S) & DPORT_RECORD_PDEBUGLS0STAT_TGT_V) +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_EXT 0x0 /* not to local memory */ +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM0 0x2 /* 001x: InstRAM (0/1) */ +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM1 0x3 /* 001x: InstRAM (0/1) */ +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM0 0x4 /* 010x: InstROM (0/1) */ +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM1 0x5 /* 010x: InstROM (0/1) */ +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM0 0x0A /* 101x: DataRAM (0/1) */ +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM1 0x0B /* 101x: DataRAM (0/1) */ +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM0 0xE /* 111x: DataROM (0/1) */ +#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM1 0xF /* 111x: DataROM (0/1) */ +// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM(_t_) (((_t_)&0xE)=0x2) /* 001x: InstRAM (0/1) */ +// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM(_t_) (((_t_)&0xE)=0x4) /* 010x: InstROM (0/1) */ +// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM(_t_) (((_t_)&0xE)=0x2) /* 101x: DataRAM (0/1) */ +// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM(_t_) (((_t_)&0xE)=0x2) /* 111x: DataROM (0/1) */ + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460) +/* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x464) +/* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_M ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0 + +#define DPORT_APP_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x468) +/* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8)) +#define DPORT_APP_CPU_PDEBUG_ENABLE_M (BIT(8)) +#define DPORT_APP_CPU_PDEBUG_ENABLE_V 0x1 +#define DPORT_APP_CPU_PDEBUG_ENABLE_S 8 +/* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CPU_RECORD_DISABLE (BIT(4)) +#define DPORT_APP_CPU_RECORD_DISABLE_M (BIT(4)) +#define DPORT_APP_CPU_RECORD_DISABLE_V 0x1 +#define DPORT_APP_CPU_RECORD_DISABLE_S 4 +/* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CPU_RECORD_ENABLE (BIT(0)) +#define DPORT_APP_CPU_RECORD_ENABLE_M (BIT(0)) +#define DPORT_APP_CPU_RECORD_ENABLE_V 0x1 +#define DPORT_APP_CPU_RECORD_ENABLE_S 0 + +#define DPORT_APP_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x46C) +/* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CPU_RECORDING (BIT(0)) +#define DPORT_APP_CPU_RECORDING_M (BIT(0)) +#define DPORT_APP_CPU_RECORDING_V 0x1 +#define DPORT_APP_CPU_RECORDING_S 0 + +#define DPORT_APP_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x470) +/* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PID 0x00000007 +#define DPORT_RECORD_APP_PID_M ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S)) +#define DPORT_RECORD_APP_PID_V 0x7 +#define DPORT_RECORD_APP_PID_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x474) +/* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGINST_M ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S)) +#define DPORT_RECORD_APP_PDEBUGINST_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGINST_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x478) +/* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF +#define DPORT_RECORD_APP_PDEBUGSTATUS_M ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S)) +#define DPORT_RECORD_APP_PDEBUGSTATUS_V 0xFF +#define DPORT_RECORD_APP_PDEBUGSTATUS_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x47C) +/* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGDATA_M ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S)) +#define DPORT_RECORD_APP_PDEBUGDATA_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGDATA_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x480) +/* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGPC_M ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S)) +#define DPORT_RECORD_APP_PDEBUGPC_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGPC_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x484) +/* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0STAT_M ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S)) +#define DPORT_RECORD_APP_PDEBUGLS0STAT_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x488) +/* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_M ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S)) +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x48C) +/* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0DATA_M ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S)) +#define DPORT_RECORD_APP_PDEBUGLS0DATA_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0 + +#define DPORT_RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490) +/* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RSA_PD (BIT(0)) +#define DPORT_RSA_PD_M (BIT(0)) +#define DPORT_RSA_PD_V 0x1 +#define DPORT_RSA_PD_S 0 + +#define DPORT_ROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x494) +/* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_ROM_MPU_TABLE0 0x00000003 +#define DPORT_ROM_MPU_TABLE0_M ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S)) +#define DPORT_ROM_MPU_TABLE0_V 0x3 +#define DPORT_ROM_MPU_TABLE0_S 0 + +#define DPORT_ROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x498) +/* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_ROM_MPU_TABLE1 0x00000003 +#define DPORT_ROM_MPU_TABLE1_M ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S)) +#define DPORT_ROM_MPU_TABLE1_V 0x3 +#define DPORT_ROM_MPU_TABLE1_S 0 + +#define DPORT_ROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x49C) +/* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_ROM_MPU_TABLE2 0x00000003 +#define DPORT_ROM_MPU_TABLE2_M ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S)) +#define DPORT_ROM_MPU_TABLE2_V 0x3 +#define DPORT_ROM_MPU_TABLE2_S 0 + +#define DPORT_ROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4A0) +/* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_ROM_MPU_TABLE3 0x00000003 +#define DPORT_ROM_MPU_TABLE3_M ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S)) +#define DPORT_ROM_MPU_TABLE3_V 0x3 +#define DPORT_ROM_MPU_TABLE3_S 0 + +#define DPORT_SHROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x4A4) +/* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE0 0x00000003 +#define DPORT_SHROM_MPU_TABLE0_M ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S)) +#define DPORT_SHROM_MPU_TABLE0_V 0x3 +#define DPORT_SHROM_MPU_TABLE0_S 0 + +#define DPORT_SHROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x4A8) +/* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE1 0x00000003 +#define DPORT_SHROM_MPU_TABLE1_M ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S)) +#define DPORT_SHROM_MPU_TABLE1_V 0x3 +#define DPORT_SHROM_MPU_TABLE1_S 0 + +#define DPORT_SHROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x4AC) +/* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE2 0x00000003 +#define DPORT_SHROM_MPU_TABLE2_M ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S)) +#define DPORT_SHROM_MPU_TABLE2_V 0x3 +#define DPORT_SHROM_MPU_TABLE2_S 0 + +#define DPORT_SHROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4B0) +/* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE3 0x00000003 +#define DPORT_SHROM_MPU_TABLE3_M ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S)) +#define DPORT_SHROM_MPU_TABLE3_V 0x3 +#define DPORT_SHROM_MPU_TABLE3_S 0 + +#define DPORT_SHROM_MPU_TABLE4_REG (DR_REG_DPORT_BASE + 0x4B4) +/* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE4 0x00000003 +#define DPORT_SHROM_MPU_TABLE4_M ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S)) +#define DPORT_SHROM_MPU_TABLE4_V 0x3 +#define DPORT_SHROM_MPU_TABLE4_S 0 + +#define DPORT_SHROM_MPU_TABLE5_REG (DR_REG_DPORT_BASE + 0x4B8) +/* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE5 0x00000003 +#define DPORT_SHROM_MPU_TABLE5_M ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S)) +#define DPORT_SHROM_MPU_TABLE5_V 0x3 +#define DPORT_SHROM_MPU_TABLE5_S 0 + +#define DPORT_SHROM_MPU_TABLE6_REG (DR_REG_DPORT_BASE + 0x4BC) +/* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE6 0x00000003 +#define DPORT_SHROM_MPU_TABLE6_M ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S)) +#define DPORT_SHROM_MPU_TABLE6_V 0x3 +#define DPORT_SHROM_MPU_TABLE6_S 0 + +#define DPORT_SHROM_MPU_TABLE7_REG (DR_REG_DPORT_BASE + 0x4C0) +/* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE7 0x00000003 +#define DPORT_SHROM_MPU_TABLE7_M ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S)) +#define DPORT_SHROM_MPU_TABLE7_V 0x3 +#define DPORT_SHROM_MPU_TABLE7_S 0 + +#define DPORT_SHROM_MPU_TABLE8_REG (DR_REG_DPORT_BASE + 0x4C4) +/* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE8 0x00000003 +#define DPORT_SHROM_MPU_TABLE8_M ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S)) +#define DPORT_SHROM_MPU_TABLE8_V 0x3 +#define DPORT_SHROM_MPU_TABLE8_S 0 + +#define DPORT_SHROM_MPU_TABLE9_REG (DR_REG_DPORT_BASE + 0x4C8) +/* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE9 0x00000003 +#define DPORT_SHROM_MPU_TABLE9_M ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S)) +#define DPORT_SHROM_MPU_TABLE9_V 0x3 +#define DPORT_SHROM_MPU_TABLE9_S 0 + +#define DPORT_SHROM_MPU_TABLE10_REG (DR_REG_DPORT_BASE + 0x4CC) +/* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE10 0x00000003 +#define DPORT_SHROM_MPU_TABLE10_M ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S)) +#define DPORT_SHROM_MPU_TABLE10_V 0x3 +#define DPORT_SHROM_MPU_TABLE10_S 0 + +#define DPORT_SHROM_MPU_TABLE11_REG (DR_REG_DPORT_BASE + 0x4D0) +/* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE11 0x00000003 +#define DPORT_SHROM_MPU_TABLE11_M ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S)) +#define DPORT_SHROM_MPU_TABLE11_V 0x3 +#define DPORT_SHROM_MPU_TABLE11_S 0 + +#define DPORT_SHROM_MPU_TABLE12_REG (DR_REG_DPORT_BASE + 0x4D4) +/* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE12 0x00000003 +#define DPORT_SHROM_MPU_TABLE12_M ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S)) +#define DPORT_SHROM_MPU_TABLE12_V 0x3 +#define DPORT_SHROM_MPU_TABLE12_S 0 + +#define DPORT_SHROM_MPU_TABLE13_REG (DR_REG_DPORT_BASE + 0x4D8) +/* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE13 0x00000003 +#define DPORT_SHROM_MPU_TABLE13_M ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S)) +#define DPORT_SHROM_MPU_TABLE13_V 0x3 +#define DPORT_SHROM_MPU_TABLE13_S 0 + +#define DPORT_SHROM_MPU_TABLE14_REG (DR_REG_DPORT_BASE + 0x4DC) +/* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE14 0x00000003 +#define DPORT_SHROM_MPU_TABLE14_M ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S)) +#define DPORT_SHROM_MPU_TABLE14_V 0x3 +#define DPORT_SHROM_MPU_TABLE14_S 0 + +#define DPORT_SHROM_MPU_TABLE15_REG (DR_REG_DPORT_BASE + 0x4E0) +/* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE15 0x00000003 +#define DPORT_SHROM_MPU_TABLE15_M ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S)) +#define DPORT_SHROM_MPU_TABLE15_V 0x3 +#define DPORT_SHROM_MPU_TABLE15_S 0 + +#define DPORT_SHROM_MPU_TABLE16_REG (DR_REG_DPORT_BASE + 0x4E4) +/* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE16 0x00000003 +#define DPORT_SHROM_MPU_TABLE16_M ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S)) +#define DPORT_SHROM_MPU_TABLE16_V 0x3 +#define DPORT_SHROM_MPU_TABLE16_S 0 + +#define DPORT_SHROM_MPU_TABLE17_REG (DR_REG_DPORT_BASE + 0x4E8) +/* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE17 0x00000003 +#define DPORT_SHROM_MPU_TABLE17_M ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S)) +#define DPORT_SHROM_MPU_TABLE17_V 0x3 +#define DPORT_SHROM_MPU_TABLE17_S 0 + +#define DPORT_SHROM_MPU_TABLE18_REG (DR_REG_DPORT_BASE + 0x4EC) +/* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE18 0x00000003 +#define DPORT_SHROM_MPU_TABLE18_M ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S)) +#define DPORT_SHROM_MPU_TABLE18_V 0x3 +#define DPORT_SHROM_MPU_TABLE18_S 0 + +#define DPORT_SHROM_MPU_TABLE19_REG (DR_REG_DPORT_BASE + 0x4F0) +/* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE19 0x00000003 +#define DPORT_SHROM_MPU_TABLE19_M ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S)) +#define DPORT_SHROM_MPU_TABLE19_V 0x3 +#define DPORT_SHROM_MPU_TABLE19_S 0 + +#define DPORT_SHROM_MPU_TABLE20_REG (DR_REG_DPORT_BASE + 0x4F4) +/* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE20 0x00000003 +#define DPORT_SHROM_MPU_TABLE20_M ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S)) +#define DPORT_SHROM_MPU_TABLE20_V 0x3 +#define DPORT_SHROM_MPU_TABLE20_S 0 + +#define DPORT_SHROM_MPU_TABLE21_REG (DR_REG_DPORT_BASE + 0x4F8) +/* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE21 0x00000003 +#define DPORT_SHROM_MPU_TABLE21_M ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S)) +#define DPORT_SHROM_MPU_TABLE21_V 0x3 +#define DPORT_SHROM_MPU_TABLE21_S 0 + +#define DPORT_SHROM_MPU_TABLE22_REG (DR_REG_DPORT_BASE + 0x4FC) +/* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE22 0x00000003 +#define DPORT_SHROM_MPU_TABLE22_M ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S)) +#define DPORT_SHROM_MPU_TABLE22_V 0x3 +#define DPORT_SHROM_MPU_TABLE22_S 0 + +#define DPORT_SHROM_MPU_TABLE23_REG (DR_REG_DPORT_BASE + 0x500) +/* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE23 0x00000003 +#define DPORT_SHROM_MPU_TABLE23_M ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S)) +#define DPORT_SHROM_MPU_TABLE23_V 0x3 +#define DPORT_SHROM_MPU_TABLE23_S 0 + +#define DPORT_IMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x504) +/* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ +/*description: */ +#define DPORT_IMMU_TABLE0 0x0000007F +#define DPORT_IMMU_TABLE0_M ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S)) +#define DPORT_IMMU_TABLE0_V 0x7F +#define DPORT_IMMU_TABLE0_S 0 + +#define DPORT_IMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x508) +/* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ +/*description: */ +#define DPORT_IMMU_TABLE1 0x0000007F +#define DPORT_IMMU_TABLE1_M ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S)) +#define DPORT_IMMU_TABLE1_V 0x7F +#define DPORT_IMMU_TABLE1_S 0 + +#define DPORT_IMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x50C) +/* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ +/*description: */ +#define DPORT_IMMU_TABLE2 0x0000007F +#define DPORT_IMMU_TABLE2_M ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S)) +#define DPORT_IMMU_TABLE2_V 0x7F +#define DPORT_IMMU_TABLE2_S 0 + +#define DPORT_IMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x510) +/* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ +/*description: */ +#define DPORT_IMMU_TABLE3 0x0000007F +#define DPORT_IMMU_TABLE3_M ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S)) +#define DPORT_IMMU_TABLE3_V 0x7F +#define DPORT_IMMU_TABLE3_S 0 + +#define DPORT_IMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x514) +/* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ +/*description: */ +#define DPORT_IMMU_TABLE4 0x0000007F +#define DPORT_IMMU_TABLE4_M ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S)) +#define DPORT_IMMU_TABLE4_V 0x7F +#define DPORT_IMMU_TABLE4_S 0 + +#define DPORT_IMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x518) +/* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ +/*description: */ +#define DPORT_IMMU_TABLE5 0x0000007F +#define DPORT_IMMU_TABLE5_M ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S)) +#define DPORT_IMMU_TABLE5_V 0x7F +#define DPORT_IMMU_TABLE5_S 0 + +#define DPORT_IMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x51C) +/* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ +/*description: */ +#define DPORT_IMMU_TABLE6 0x0000007F +#define DPORT_IMMU_TABLE6_M ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S)) +#define DPORT_IMMU_TABLE6_V 0x7F +#define DPORT_IMMU_TABLE6_S 0 + +#define DPORT_IMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x520) +/* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ +/*description: */ +#define DPORT_IMMU_TABLE7 0x0000007F +#define DPORT_IMMU_TABLE7_M ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S)) +#define DPORT_IMMU_TABLE7_V 0x7F +#define DPORT_IMMU_TABLE7_S 0 + +#define DPORT_IMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x524) +/* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ +/*description: */ +#define DPORT_IMMU_TABLE8 0x0000007F +#define DPORT_IMMU_TABLE8_M ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S)) +#define DPORT_IMMU_TABLE8_V 0x7F +#define DPORT_IMMU_TABLE8_S 0 + +#define DPORT_IMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x528) +/* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ +/*description: */ +#define DPORT_IMMU_TABLE9 0x0000007F +#define DPORT_IMMU_TABLE9_M ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S)) +#define DPORT_IMMU_TABLE9_V 0x7F +#define DPORT_IMMU_TABLE9_S 0 + +#define DPORT_IMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x52C) +/* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ +/*description: */ +#define DPORT_IMMU_TABLE10 0x0000007F +#define DPORT_IMMU_TABLE10_M ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S)) +#define DPORT_IMMU_TABLE10_V 0x7F +#define DPORT_IMMU_TABLE10_S 0 + +#define DPORT_IMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x530) +/* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ +/*description: */ +#define DPORT_IMMU_TABLE11 0x0000007F +#define DPORT_IMMU_TABLE11_M ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S)) +#define DPORT_IMMU_TABLE11_V 0x7F +#define DPORT_IMMU_TABLE11_S 0 + +#define DPORT_IMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x534) +/* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ +/*description: */ +#define DPORT_IMMU_TABLE12 0x0000007F +#define DPORT_IMMU_TABLE12_M ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S)) +#define DPORT_IMMU_TABLE12_V 0x7F +#define DPORT_IMMU_TABLE12_S 0 + +#define DPORT_IMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x538) +/* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ +/*description: */ +#define DPORT_IMMU_TABLE13 0x0000007F +#define DPORT_IMMU_TABLE13_M ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S)) +#define DPORT_IMMU_TABLE13_V 0x7F +#define DPORT_IMMU_TABLE13_S 0 + +#define DPORT_IMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x53C) +/* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: */ +#define DPORT_IMMU_TABLE14 0x0000007F +#define DPORT_IMMU_TABLE14_M ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S)) +#define DPORT_IMMU_TABLE14_V 0x7F +#define DPORT_IMMU_TABLE14_S 0 + +#define DPORT_IMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x540) +/* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ +/*description: */ +#define DPORT_IMMU_TABLE15 0x0000007F +#define DPORT_IMMU_TABLE15_M ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S)) +#define DPORT_IMMU_TABLE15_V 0x7F +#define DPORT_IMMU_TABLE15_S 0 + +#define DPORT_DMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x544) +/* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ +/*description: */ +#define DPORT_DMMU_TABLE0 0x0000007F +#define DPORT_DMMU_TABLE0_M ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S)) +#define DPORT_DMMU_TABLE0_V 0x7F +#define DPORT_DMMU_TABLE0_S 0 + +#define DPORT_DMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x548) +/* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ +/*description: */ +#define DPORT_DMMU_TABLE1 0x0000007F +#define DPORT_DMMU_TABLE1_M ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S)) +#define DPORT_DMMU_TABLE1_V 0x7F +#define DPORT_DMMU_TABLE1_S 0 + +#define DPORT_DMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x54C) +/* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ +/*description: */ +#define DPORT_DMMU_TABLE2 0x0000007F +#define DPORT_DMMU_TABLE2_M ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S)) +#define DPORT_DMMU_TABLE2_V 0x7F +#define DPORT_DMMU_TABLE2_S 0 + +#define DPORT_DMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x550) +/* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ +/*description: */ +#define DPORT_DMMU_TABLE3 0x0000007F +#define DPORT_DMMU_TABLE3_M ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S)) +#define DPORT_DMMU_TABLE3_V 0x7F +#define DPORT_DMMU_TABLE3_S 0 + +#define DPORT_DMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x554) +/* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ +/*description: */ +#define DPORT_DMMU_TABLE4 0x0000007F +#define DPORT_DMMU_TABLE4_M ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S)) +#define DPORT_DMMU_TABLE4_V 0x7F +#define DPORT_DMMU_TABLE4_S 0 + +#define DPORT_DMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x558) +/* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ +/*description: */ +#define DPORT_DMMU_TABLE5 0x0000007F +#define DPORT_DMMU_TABLE5_M ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S)) +#define DPORT_DMMU_TABLE5_V 0x7F +#define DPORT_DMMU_TABLE5_S 0 + +#define DPORT_DMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x55C) +/* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ +/*description: */ +#define DPORT_DMMU_TABLE6 0x0000007F +#define DPORT_DMMU_TABLE6_M ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S)) +#define DPORT_DMMU_TABLE6_V 0x7F +#define DPORT_DMMU_TABLE6_S 0 + +#define DPORT_DMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x560) +/* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ +/*description: */ +#define DPORT_DMMU_TABLE7 0x0000007F +#define DPORT_DMMU_TABLE7_M ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S)) +#define DPORT_DMMU_TABLE7_V 0x7F +#define DPORT_DMMU_TABLE7_S 0 + +#define DPORT_DMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x564) +/* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ +/*description: */ +#define DPORT_DMMU_TABLE8 0x0000007F +#define DPORT_DMMU_TABLE8_M ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S)) +#define DPORT_DMMU_TABLE8_V 0x7F +#define DPORT_DMMU_TABLE8_S 0 + +#define DPORT_DMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x568) +/* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ +/*description: */ +#define DPORT_DMMU_TABLE9 0x0000007F +#define DPORT_DMMU_TABLE9_M ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S)) +#define DPORT_DMMU_TABLE9_V 0x7F +#define DPORT_DMMU_TABLE9_S 0 + +#define DPORT_DMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x56C) +/* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ +/*description: */ +#define DPORT_DMMU_TABLE10 0x0000007F +#define DPORT_DMMU_TABLE10_M ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S)) +#define DPORT_DMMU_TABLE10_V 0x7F +#define DPORT_DMMU_TABLE10_S 0 + +#define DPORT_DMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x570) +/* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ +/*description: */ +#define DPORT_DMMU_TABLE11 0x0000007F +#define DPORT_DMMU_TABLE11_M ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S)) +#define DPORT_DMMU_TABLE11_V 0x7F +#define DPORT_DMMU_TABLE11_S 0 + +#define DPORT_DMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x574) +/* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ +/*description: */ +#define DPORT_DMMU_TABLE12 0x0000007F +#define DPORT_DMMU_TABLE12_M ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S)) +#define DPORT_DMMU_TABLE12_V 0x7F +#define DPORT_DMMU_TABLE12_S 0 + +#define DPORT_DMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x578) +/* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ +/*description: */ +#define DPORT_DMMU_TABLE13 0x0000007F +#define DPORT_DMMU_TABLE13_M ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S)) +#define DPORT_DMMU_TABLE13_V 0x7F +#define DPORT_DMMU_TABLE13_S 0 + +#define DPORT_DMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x57C) +/* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: */ +#define DPORT_DMMU_TABLE14 0x0000007F +#define DPORT_DMMU_TABLE14_M ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S)) +#define DPORT_DMMU_TABLE14_V 0x7F +#define DPORT_DMMU_TABLE14_S 0 + +#define DPORT_DMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x580) +/* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ +/*description: */ +#define DPORT_DMMU_TABLE15 0x0000007F +#define DPORT_DMMU_TABLE15_M ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S)) +#define DPORT_DMMU_TABLE15_V 0x7F +#define DPORT_DMMU_TABLE15_S 0 + +#define DPORT_PRO_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x584) +/* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0)) +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_M (BIT(0)) +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_V 0x1 +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0 + +#define DPORT_PRO_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x588) +/* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_PRO_INTRUSION_RECORD 0x0000000F +#define DPORT_PRO_INTRUSION_RECORD_M ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S)) +#define DPORT_PRO_INTRUSION_RECORD_V 0xF +#define DPORT_PRO_INTRUSION_RECORD_S 0 + +#define DPORT_APP_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x58C) +/* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0)) +#define DPORT_APP_INTRUSION_RECORD_RESET_N_M (BIT(0)) +#define DPORT_APP_INTRUSION_RECORD_RESET_N_V 0x1 +#define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0 + +#define DPORT_APP_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x590) +/* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_APP_INTRUSION_RECORD 0x0000000F +#define DPORT_APP_INTRUSION_RECORD_M ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S)) +#define DPORT_APP_INTRUSION_RECORD_V 0xF +#define DPORT_APP_INTRUSION_RECORD_S 0 + +#define DPORT_FRONT_END_MEM_PD_REG (DR_REG_DPORT_BASE + 0x594) +/* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PBUS_MEM_FORCE_PD (BIT(3)) +#define DPORT_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define DPORT_PBUS_MEM_FORCE_PD_V 0x1 +#define DPORT_PBUS_MEM_FORCE_PD_S 3 +/* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PBUS_MEM_FORCE_PU (BIT(2)) +#define DPORT_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define DPORT_PBUS_MEM_FORCE_PU_V 0x1 +#define DPORT_PBUS_MEM_FORCE_PU_S 2 +/* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AGC_MEM_FORCE_PD (BIT(1)) +#define DPORT_AGC_MEM_FORCE_PD_M (BIT(1)) +#define DPORT_AGC_MEM_FORCE_PD_V 0x1 +#define DPORT_AGC_MEM_FORCE_PD_S 1 +/* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_AGC_MEM_FORCE_PU (BIT(0)) +#define DPORT_AGC_MEM_FORCE_PU_M (BIT(0)) +#define DPORT_AGC_MEM_FORCE_PU_V 0x1 +#define DPORT_AGC_MEM_FORCE_PU_S 0 + +#define DPORT_MMU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x598) +/* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define DPORT_MMU_IA_INT_EN 0x00FFFFFF +#define DPORT_MMU_IA_INT_EN_M ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S)) +#define DPORT_MMU_IA_INT_EN_V 0xFFFFFF +#define DPORT_MMU_IA_INT_EN_S 0 + +#define DPORT_MPU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x59C) +/* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */ +/*description: */ +#define DPORT_MPU_IA_INT_EN 0x0001FFFF +#define DPORT_MPU_IA_INT_EN_M ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S)) +#define DPORT_MPU_IA_INT_EN_V 0x1FFFF +#define DPORT_MPU_IA_INT_EN_S 0 + +#define DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0) +/* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/*description: Interrupt enable bits for various invalid cache access reasons*/ +#define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF +#define DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S)) +#define DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF +#define DPORT_CACHE_IA_INT_EN_S 0 +/* Contents of DPORT_CACHE_IA_INT_EN field: */ +/* DPORT_CACHE_IA_INT_PRO_OPPOSITE : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: PRO CPU invalid access to APP CPU cache when cache disabled */ +#define DPORT_CACHE_IA_INT_PRO_OPPOSITE BIT(19) +#define DPORT_CACHE_IA_INT_PRO_OPPOSITE_M BIT(19) +#define DPORT_CACHE_IA_INT_PRO_OPPOSITE_V (1) +#define DPORT_CACHE_IA_INT_PRO_OPPOSITE_S (19) +/* DPORT_CACHE_IA_INT_PRO_DRAM1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: PRO CPU invalid access to DRAM1 when cache is disabled */ +#define DPORT_CACHE_IA_INT_PRO_DRAM1 BIT(18) +#define DPORT_CACHE_IA_INT_PRO_DRAM1_M BIT(18) +#define DPORT_CACHE_IA_INT_PRO_DRAM1_V (1) +#define DPORT_CACHE_IA_INT_PRO_DRAM1_S (18) +/* DPORT_CACHE_IA_INT_PRO_IROM0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: PRO CPU invalid access to IROM0 when cache is disabled */ +#define DPORT_CACHE_IA_INT_PRO_IROM0 BIT(17) +#define DPORT_CACHE_IA_INT_PRO_IROM0_M BIT(17) +#define DPORT_CACHE_IA_INT_PRO_IROM0_V (1) +#define DPORT_CACHE_IA_INT_PRO_IROM0_S (17) +/* DPORT_CACHE_IA_INT_PRO_IRAM1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: PRO CPU invalid access to IRAM1 when cache is disabled */ +#define DPORT_CACHE_IA_INT_PRO_IRAM1 BIT(16) +#define DPORT_CACHE_IA_INT_PRO_IRAM1_M BIT(16) +#define DPORT_CACHE_IA_INT_PRO_IRAM1_V (1) +#define DPORT_CACHE_IA_INT_PRO_IRAM1_S (16) +/* DPORT_CACHE_IA_INT_PRO_IRAM0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: PRO CPU invalid access to IRAM0 when cache is disabled */ +#define DPORT_CACHE_IA_INT_PRO_IRAM0 BIT(15) +#define DPORT_CACHE_IA_INT_PRO_IRAM0_M BIT(15) +#define DPORT_CACHE_IA_INT_PRO_IRAM0_V (1) +#define DPORT_CACHE_IA_INT_PRO_IRAM0_S (15) +/* DPORT_CACHE_IA_INT_PRO_DROM0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: PRO CPU invalid access to DROM0 when cache is disabled */ +#define DPORT_CACHE_IA_INT_PRO_DROM0 BIT(14) +#define DPORT_CACHE_IA_INT_PRO_DROM0_M BIT(14) +#define DPORT_CACHE_IA_INT_PRO_DROM0_V (1) +#define DPORT_CACHE_IA_INT_PRO_DROM0_S (14) +/* DPORT_CACHE_IA_INT_APP_OPPOSITE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: APP CPU invalid access to APP CPU cache when cache disabled */ +#define DPORT_CACHE_IA_INT_APP_OPPOSITE BIT(5) +#define DPORT_CACHE_IA_INT_APP_OPPOSITE_M BIT(5) +#define DPORT_CACHE_IA_INT_APP_OPPOSITE_V (1) +#define DPORT_CACHE_IA_INT_APP_OPPOSITE_S (5) +/* DPORT_CACHE_IA_INT_APP_DRAM1 : R/W ;bitpos:43] ;default: 1'b0 ; */ +/*description: APP CPU invalid access to DRAM1 when cache is disabled */ +#define DPORT_CACHE_IA_INT_APP_DRAM1 BIT(4) +#define DPORT_CACHE_IA_INT_APP_DRAM1_M BIT(4) +#define DPORT_CACHE_IA_INT_APP_DRAM1_V (1) +#define DPORT_CACHE_IA_INT_APP_DRAM1_S (4) +/* DPORT_CACHE_IA_INT_APP_IROM0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: APP CPU invalid access to IROM0 when cache is disabled */ +#define DPORT_CACHE_IA_INT_APP_IROM0 BIT(3) +#define DPORT_CACHE_IA_INT_APP_IROM0_M BIT(3) +#define DPORT_CACHE_IA_INT_APP_IROM0_V (1) +#define DPORT_CACHE_IA_INT_APP_IROM0_S (3) +/* DPORT_CACHE_IA_INT_APP_IRAM1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: APP CPU invalid access to IRAM1 when cache is disabled */ +#define DPORT_CACHE_IA_INT_APP_IRAM1 BIT(2) +#define DPORT_CACHE_IA_INT_APP_IRAM1_M BIT(2) +#define DPORT_CACHE_IA_INT_APP_IRAM1_V (1) +#define DPORT_CACHE_IA_INT_APP_IRAM1_S (2) +/* DPORT_CACHE_IA_INT_APP_IRAM0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: APP CPU invalid access to IRAM0 when cache is disabled */ +#define DPORT_CACHE_IA_INT_APP_IRAM0 BIT(1) +#define DPORT_CACHE_IA_INT_APP_IRAM0_M BIT(1) +#define DPORT_CACHE_IA_INT_APP_IRAM0_V (1) +#define DPORT_CACHE_IA_INT_APP_IRAM0_S (1) +/* DPORT_CACHE_IA_INT_APP_DROM0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: APP CPU invalid access to DROM0 when cache is disabled */ +#define DPORT_CACHE_IA_INT_APP_DROM0 BIT(0) +#define DPORT_CACHE_IA_INT_APP_DROM0_M BIT(0) +#define DPORT_CACHE_IA_INT_APP_DROM0_V (1) +#define DPORT_CACHE_IA_INT_APP_DROM0_S (0) + +#define DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4) +/* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SW_BOOTLOADER_SEL (BIT(0)) +#define DPORT_SW_BOOTLOADER_SEL_M (BIT(0)) +#define DPORT_SW_BOOTLOADER_SEL_V 0x1 +#define DPORT_SW_BOOTLOADER_SEL_S 0 + +#define DPORT_SPI_DMA_CHAN_SEL_REG (DR_REG_DPORT_BASE + 0x5A8) +/* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ +/*description: */ +#define DPORT_SPI3_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI3_DMA_CHAN_SEL_M ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S)) +#define DPORT_SPI3_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI3_DMA_CHAN_SEL_S 4 +/* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */ +/*description: */ +#define DPORT_SPI2_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI2_DMA_CHAN_SEL_M ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S)) +#define DPORT_SPI2_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI2_DMA_CHAN_SEL_S 2 +/* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */ +/*description: */ +#define DPORT_SPI1_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI1_DMA_CHAN_SEL_M ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S)) +#define DPORT_SPI1_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI1_DMA_CHAN_SEL_S 0 + +#define DPORT_PRO_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5AC) +/* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_PRO_OUT_VECBASE_SEL 0x00000003 +#define DPORT_PRO_OUT_VECBASE_SEL_M ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S)) +#define DPORT_PRO_OUT_VECBASE_SEL_V 0x3 +#define DPORT_PRO_OUT_VECBASE_SEL_S 0 + +#define DPORT_PRO_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B0) +/* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: */ +#define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF +#define DPORT_PRO_OUT_VECBASE_REG_M ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S)) +#define DPORT_PRO_OUT_VECBASE_REG_V 0x3FFFFF +#define DPORT_PRO_OUT_VECBASE_REG_S 0 + +#define DPORT_APP_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5B4) +/* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_APP_OUT_VECBASE_SEL 0x00000003 +#define DPORT_APP_OUT_VECBASE_SEL_M ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S)) +#define DPORT_APP_OUT_VECBASE_SEL_V 0x3 +#define DPORT_APP_OUT_VECBASE_SEL_S 0 + +#define DPORT_APP_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B8) +/* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: */ +#define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF +#define DPORT_APP_OUT_VECBASE_REG_M ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S)) +#define DPORT_APP_OUT_VECBASE_REG_V 0x3FFFFF +#define DPORT_APP_OUT_VECBASE_REG_S 0 + +#define DPORT_DATE_REG (DR_REG_DPORT_BASE + 0xFFC) +/* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */ +/*description: */ +#define DPORT_DATE 0x0FFFFFFF +#define DPORT_DATE_M ((DPORT_DATE_V)<<(DPORT_DATE_S)) +#define DPORT_DATE_V 0xFFFFFFF +#define DPORT_DATE_S 0 +#define DPORT_DPORT_DATE_VERSION 0x1605190 + +/* Flash MMU table for PRO CPU */ +#define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF10000) + +/* Flash MMU table for APP CPU */ +#define DPORT_APP_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF12000) + +#define DPORT_FLASH_MMU_TABLE_SIZE 0x100 + +#define DPORT_FLASH_MMU_TABLE_INVALID_VAL 0x100 + +#endif /*_SOC_DPORT_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/efuse_reg.h b/tools/sdk/include/soc/include/soc/efuse_reg.h new file mode 100644 index 00000000000..bbe96771370 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/efuse_reg.h @@ -0,0 +1,1188 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_EFUSE_REG_H_ +#define _SOC_EFUSE_REG_H_ + + +#include "soc.h" +#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) +/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; */ +/*description: read for flash_crypt_cnt*/ +#define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007F +#define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S)) +#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x7F +#define EFUSE_RD_FLASH_CRYPT_CNT_S 20 +/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */ +/*description: read for efuse_rd_disable*/ +#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F +#define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S)) +#define EFUSE_RD_EFUSE_RD_DIS_V 0xF +#define EFUSE_RD_EFUSE_RD_DIS_S 16 + +/* Read disable bits for efuse blocks 1-3 */ +#define EFUSE_RD_DIS_BLK1 (1<<16) +#define EFUSE_RD_DIS_BLK2 (1<<17) +#define EFUSE_RD_DIS_BLK3 (1<<18) +/* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS + in efuse block 0 +*/ +#define EFUSE_RD_DIS_BLK0_PARTIAL (1<<19) + +/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: read for efuse_wr_disable*/ +#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF +#define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S)) +#define EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF +#define EFUSE_RD_EFUSE_WR_DIS_S 0 + +/* Write disable bits */ +#define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */ +#define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2) +#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */ +#define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */ +#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */ +#define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */ +#define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */ +#define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ +#define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */ +#define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */ +#define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */ +#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ + +#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) +/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: read for low 32bit WIFI_MAC_Address*/ +#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF +#define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S)) +#define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF +#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 + +#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) +/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: read for high 24bit WIFI_MAC_Address*/ +#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF +#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) +#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF +#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 + +#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) +/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: bit is set to 1 for rev1 silicon*/ +#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S)) +#define EFUSE_RD_CHIP_VER_REV1_V 0x1 +#define EFUSE_RD_CHIP_VER_REV1_S 15 +/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ +/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ +#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S)) +#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 +#define EFUSE_RD_BLK3_PART_RESERVE_S 14 +/* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: If set, the ESP32's maximum CPU frequency has been rated*/ +#define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S)) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1 +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 +/* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ +#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S)) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 +/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ +/*description: chip package */ +#define EFUSE_RD_CHIP_VER_PKG 0x00000007 +#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S)) +#define EFUSE_RD_CHIP_VER_PKG_V 0x7 +#define EFUSE_RD_CHIP_VER_PKG_S 9 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 +/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_hd*/ +#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 +/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) +#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) +#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 +#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 +/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_CHIP_VER_32PAD (BIT(2)) +#define EFUSE_RD_CHIP_VER_32PAD_M (BIT(2)) +#define EFUSE_RD_CHIP_VER_32PAD_V 0x1 +#define EFUSE_RD_CHIP_VER_32PAD_S 2 +/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) +#define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) +#define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 +#define EFUSE_RD_CHIP_VER_DIS_BT_S 1 +/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 + +#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) +/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: read for sdio_force*/ +#define EFUSE_RD_SDIO_FORCE (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_V 0x1 +#define EFUSE_RD_SDIO_FORCE_S 16 +/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: read for SDIO_TIEH*/ +#define EFUSE_RD_SDIO_TIEH (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_V 0x1 +#define EFUSE_RD_SDIO_TIEH_S 15 +/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: read for XPD_SDIO_REG*/ +#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_V 0x1 +#define EFUSE_RD_XPD_SDIO_REG_S 14 +/* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ +/*description: True ADC reference voltage */ +#define EFUSE_RD_ADC_VREF 0x0000001F +#define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V)<<(EFUSE_RD_ADC_VREF_S)) +#define EFUSE_RD_ADC_VREF_V 0x1F +#define EFUSE_RD_ADC_VREF_S 8 +/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer + * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore + * SDIO_DREFH/M/L is only available in older versions of ESP32 */ +/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_RD_SDIO_DREFL 0x00000003 +#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S)) +#define EFUSE_RD_SDIO_DREFL_V 0x3 +#define EFUSE_RD_SDIO_DREFL_S 12 +/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_RD_SDIO_DREFM 0x00000003 +#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S)) +#define EFUSE_RD_SDIO_DREFM_V 0x3 +#define EFUSE_RD_SDIO_DREFM_S 10 +/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_RD_SDIO_DREFH 0x00000003 +#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S)) +#define EFUSE_RD_SDIO_DREFH_V 0x3 +#define EFUSE_RD_SDIO_DREFH_S 8 +/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define EFUSE_RD_CK8M_FREQ 0x000000FF +#define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S)) +#define EFUSE_RD_CK8M_FREQ_V 0xFF +#define EFUSE_RD_CK8M_FREQ_S 0 + +#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) +/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */ +/*description: read for flash_crypt_config*/ +#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F +#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) +#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF +#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 +/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */ +/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO) + BIT[27] is the sign bit, 0: + , 1: - + BIT[26:24] is the difference value, unit: 0.017V + volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ +#define EFUSE_RD_DIG_VOL_L6 0x0F +#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) +#define EFUSE_RD_DIG_VOL_L6_V 0x0F +#define EFUSE_RD_DIG_VOL_L6_S 24 +/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ +/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. +0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/ +#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) +#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 +/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */ +/* Deprecated */ +#define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/ +#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/ +#define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/ +#define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/ +/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_cs0*/ +#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 +/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_d*/ +#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 +/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_q*/ +#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 +/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_clk*/ +#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 + +#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) +/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: read for key_status*/ +#define EFUSE_RD_KEY_STATUS (BIT(10)) +#define EFUSE_RD_KEY_STATUS_M (BIT(10)) +#define EFUSE_RD_KEY_STATUS_V 0x1 +#define EFUSE_RD_KEY_STATUS_S 10 +/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: read for download_dis_cache*/ +#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 +#define EFUSE_RD_DISABLE_DL_CACHE_S 9 +/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: read for download_dis_decrypt*/ +#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) +#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 +#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 +/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: read for download_dis_encrypt*/ +#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 +#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 +/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: read for JTAG_disable*/ +#define EFUSE_RD_DISABLE_JTAG (BIT(6)) +#define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) +#define EFUSE_RD_DISABLE_JTAG_V 0x1 +#define EFUSE_RD_DISABLE_JTAG_S 6 +/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: read for abstract_done_1*/ +#define EFUSE_RD_ABS_DONE_1 (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_M (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_V 0x1 +#define EFUSE_RD_ABS_DONE_1_S 5 +/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: read for abstract_done_0*/ +#define EFUSE_RD_ABS_DONE_0 (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_M (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_V 0x1 +#define EFUSE_RD_ABS_DONE_0_S 4 +/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 +#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 +/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: read for console_debug_disable*/ +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 +/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: read for coding_scheme*/ +#define EFUSE_RD_CODING_SCHEME 0x00000003 +#define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S)) +#define EFUSE_RD_CODING_SCHEME_V 0x3 +#define EFUSE_RD_CODING_SCHEME_S 0 + +#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 +#define EFUSE_CODING_SCHEME_VAL_34 0x1 +#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 + +#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) +/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; */ +/*description: program for flash_crypt_cnt*/ +#define EFUSE_FLASH_CRYPT_CNT 0x0000007F +#define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S)) +#define EFUSE_FLASH_CRYPT_CNT_V 0x7F +#define EFUSE_FLASH_CRYPT_CNT_S 20 +/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */ +/*description: program for efuse_rd_disable*/ +#define EFUSE_RD_DIS 0x0000000F +#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) +#define EFUSE_RD_DIS_V 0xF +#define EFUSE_RD_DIS_S 16 +/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: program for efuse_wr_disable*/ +#define EFUSE_WR_DIS 0x0000FFFF +#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) +#define EFUSE_WR_DIS_V 0xFFFF +#define EFUSE_WR_DIS_S 0 + +#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) +/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: program for low 32bit WIFI_MAC_Address*/ +#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF +#define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S)) +#define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF +#define EFUSE_WIFI_MAC_CRC_LOW_S 0 + +#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) +/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: program for high 24bit WIFI_MAC_Address*/ +#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF +#define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S)) +#define EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF +#define EFUSE_WIFI_MAC_CRC_HIGH_S 0 + +#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) +/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S)) +#define EFUSE_CHIP_VER_REV1_V 0x1 +#define EFUSE_CHIP_VER_REV1_S 15 +/* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ +/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ +#define EFUSE_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S)) +#define EFUSE_BLK3_PART_RESERVE_V 0x1 +#define EFUSE_BLK3_PART_RESERVE_S 14 +/* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: If set, the ESP32's maximum CPU frequency has been rated*/ +#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S)) +#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1 +#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 +/* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ +#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S)) +#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 +#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 +/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_PKG 0x00000007 +#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S)) +#define EFUSE_CHIP_VER_PKG_V 0x7 +#define EFUSE_CHIP_VER_PKG_S 9 +#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0 +#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1 +#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 +#define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 +#define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 +/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_hd*/ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S)) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_HD_S 4 +/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) +#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) +#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 +#define EFUSE_CHIP_VER_DIS_CACHE_S 3 +/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_32PAD (BIT(2)) +#define EFUSE_CHIP_VER_32PAD_M (BIT(2)) +#define EFUSE_CHIP_VER_32PAD_V 0x1 +#define EFUSE_CHIP_VER_32PAD_S 2 +/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_DIS_BT (BIT(1)) +#define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) +#define EFUSE_CHIP_VER_DIS_BT_V 0x1 +#define EFUSE_CHIP_VER_DIS_BT_S 1 +/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) +#define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) +#define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 +#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 + +#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) +/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: program for sdio_force*/ +#define EFUSE_SDIO_FORCE (BIT(16)) +#define EFUSE_SDIO_FORCE_M (BIT(16)) +#define EFUSE_SDIO_FORCE_V 0x1 +#define EFUSE_SDIO_FORCE_S 16 +/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: program for SDIO_TIEH*/ +#define EFUSE_SDIO_TIEH (BIT(15)) +#define EFUSE_SDIO_TIEH_M (BIT(15)) +#define EFUSE_SDIO_TIEH_V 0x1 +#define EFUSE_SDIO_TIEH_S 15 +/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: program for XPD_SDIO_REG*/ +#define EFUSE_XPD_SDIO_REG (BIT(14)) +#define EFUSE_XPD_SDIO_REG_M (BIT(14)) +#define EFUSE_XPD_SDIO_REG_V 0x1 +#define EFUSE_XPD_SDIO_REG_S 14 +/* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ +/*description: True ADC reference voltage */ +#define EFUSE_ADC_VREF 0x0000001F +#define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V)<<(EFUSE_ADC_VREF_S)) +#define EFUSE_ADC_VREF_V 0x1F +#define EFUSE_ADC_VREF_S 8 +/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer + * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore + * SDIO_DREFH/M/L is only available in older versions of ESP32 */ +/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_SDIO_DREFL 0x00000003 +#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) +#define EFUSE_SDIO_DREFL_V 0x3 +#define EFUSE_SDIO_DREFL_S 12 +/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_SDIO_DREFM 0x00000003 +#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) +#define EFUSE_SDIO_DREFM_V 0x3 +#define EFUSE_SDIO_DREFM_S 10 +/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_SDIO_DREFH 0x00000003 +#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) +#define EFUSE_SDIO_DREFH_V 0x3 +#define EFUSE_SDIO_DREFH_S 8 +/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define EFUSE_CK8M_FREQ 0x000000FF +#define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S)) +#define EFUSE_CK8M_FREQ_V 0xFF +#define EFUSE_CK8M_FREQ_S 0 + +#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) +/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */ +/*description: program for flash_crypt_config*/ +#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F +#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S)) +#define EFUSE_FLASH_CRYPT_CONFIG_V 0xF +#define EFUSE_FLASH_CRYPT_CONFIG_S 28 +/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */ +/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W) + BIT[27] is the sign bit, 0: + , 1: - + BIT[26:24] is the difference value, unit: 0.017V + volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ +#define EFUSE_DIG_VOL_L6 0x0F +#define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) +#define EFUSE_DIG_VOL_L6_V 0x0F +#define EFUSE_DIG_VOL_L6_S 24 +/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */ +/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. +0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/ +#define EFUSE_VOL_LEVEL_HP_INV 0x03 +#define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) +#define EFUSE_VOL_LEVEL_HP_INV_V 0x03 +#define EFUSE_VOL_LEVEL_HP_INV_S 22 +/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */ +/* Deprecated */ +#define EFUSE_INST_CONFIG 0x000000FF /** Deprecated **/ +#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) /** Deprecated **/ +#define EFUSE_INST_CONFIG_V 0xFF /** Deprecated **/ +#define EFUSE_INST_CONFIG_S 20 /** Deprecated **/ +/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_cs0*/ +#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S)) +#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 +/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_d*/ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S)) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_D_S 10 +/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_q*/ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S)) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_Q_S 5 +/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_clk*/ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S)) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_CLK_S 0 + +#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) +/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: program for key_status*/ +#define EFUSE_KEY_STATUS (BIT(10)) +#define EFUSE_KEY_STATUS_M (BIT(10)) +#define EFUSE_KEY_STATUS_V 0x1 +#define EFUSE_KEY_STATUS_S 10 +/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: program for download_dis_cache*/ +#define EFUSE_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_V 0x1 +#define EFUSE_DISABLE_DL_CACHE_S 9 +/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: program for download_dis_decrypt*/ +#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_V 0x1 +#define EFUSE_DISABLE_DL_DECRYPT_S 8 +/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: program for download_dis_encrypt*/ +#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 +#define EFUSE_DISABLE_DL_ENCRYPT_S 7 +/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: program for JTAG_disable*/ +#define EFUSE_DISABLE_JTAG (BIT(6)) +#define EFUSE_DISABLE_JTAG_M (BIT(6)) +#define EFUSE_DISABLE_JTAG_V 0x1 +#define EFUSE_DISABLE_JTAG_S 6 +/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: program for abstract_done_1*/ +#define EFUSE_ABS_DONE_1 (BIT(5)) +#define EFUSE_ABS_DONE_1_M (BIT(5)) +#define EFUSE_ABS_DONE_1_V 0x1 +#define EFUSE_ABS_DONE_1_S 5 +/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: program for abstract_done_0*/ +#define EFUSE_ABS_DONE_0 (BIT(4)) +#define EFUSE_ABS_DONE_0_M (BIT(4)) +#define EFUSE_ABS_DONE_0_V 0x1 +#define EFUSE_ABS_DONE_0_S 4 +/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_V 0x1 +#define EFUSE_DISABLE_SDIO_HOST_S 3 +/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: program for console_debug_disable*/ +#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) +#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 +#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 +/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: program for coding_scheme*/ +#define EFUSE_CODING_SCHEME 0x00000003 +#define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S)) +#define EFUSE_CODING_SCHEME_V 0x3 +#define EFUSE_CODING_SCHEME_S 0 + +#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) +/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT0 0xFFFFFFFF +#define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S)) +#define EFUSE_BLK1_DOUT0_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT0_S 0 + +#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) +/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT1 0xFFFFFFFF +#define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S)) +#define EFUSE_BLK1_DOUT1_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT1_S 0 + +#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) +/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT2 0xFFFFFFFF +#define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S)) +#define EFUSE_BLK1_DOUT2_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT2_S 0 + +#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) +/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT3 0xFFFFFFFF +#define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S)) +#define EFUSE_BLK1_DOUT3_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT3_S 0 + +#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) +/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT4 0xFFFFFFFF +#define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S)) +#define EFUSE_BLK1_DOUT4_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT4_S 0 + +#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) +/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT5 0xFFFFFFFF +#define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S)) +#define EFUSE_BLK1_DOUT5_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT5_S 0 + +#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) +/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT6 0xFFFFFFFF +#define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S)) +#define EFUSE_BLK1_DOUT6_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT6_S 0 + +#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) +/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT7 0xFFFFFFFF +#define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S)) +#define EFUSE_BLK1_DOUT7_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT7_S 0 + +#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) +/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT0 0xFFFFFFFF +#define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S)) +#define EFUSE_BLK2_DOUT0_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT0_S 0 + +#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) +/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT1 0xFFFFFFFF +#define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S)) +#define EFUSE_BLK2_DOUT1_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT1_S 0 + +#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) +/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT2 0xFFFFFFFF +#define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S)) +#define EFUSE_BLK2_DOUT2_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT2_S 0 + +#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) +/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT3 0xFFFFFFFF +#define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S)) +#define EFUSE_BLK2_DOUT3_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT3_S 0 + +#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) +/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT4 0xFFFFFFFF +#define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S)) +#define EFUSE_BLK2_DOUT4_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT4_S 0 + +#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) +/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT5 0xFFFFFFFF +#define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S)) +#define EFUSE_BLK2_DOUT5_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT5_S 0 + +#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) +/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT6 0xFFFFFFFF +#define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S)) +#define EFUSE_BLK2_DOUT6_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT6_S 0 + +#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) +/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT7 0xFFFFFFFF +#define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S)) +#define EFUSE_BLK2_DOUT7_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT7_S 0 + +#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) +/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT0 0xFFFFFFFF +#define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S)) +#define EFUSE_BLK3_DOUT0_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT0_S 0 + +#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) +/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT1 0xFFFFFFFF +#define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S)) +#define EFUSE_BLK3_DOUT1_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT1_S 0 + +#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) +/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT2 0xFFFFFFFF +#define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S)) +#define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT2_S 0 + +/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration + * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ +#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) +/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT3 0xFFFFFFFF +#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S)) +#define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT3_S 0 +/* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ +/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ +#define EFUSE_RD_ADC2_TP_HIGH 0x1FF +#define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V)<<(EFUSE_RD_ADC2_TP_HIGH_S)) +#define EFUSE_RD_ADC2_TP_HIGH_V 0x1FF +#define EFUSE_RD_ADC2_TP_HIGH_S 23 +/* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ +/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ +#define EFUSE_RD_ADC2_TP_LOW 0x7F +#define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V)<<(EFUSE_RD_ADC2_TP_LOW_S)) +#define EFUSE_RD_ADC2_TP_LOW_V 0x7F +#define EFUSE_RD_ADC2_TP_LOW_S 16 +/* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ +/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ +#define EFUSE_RD_ADC1_TP_HIGH 0x1FF +#define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V)<<(EFUSE_RD_ADC1_TP_HIGH_S)) +#define EFUSE_RD_ADC1_TP_HIGH_V 0x1FF +#define EFUSE_RD_ADC1_TP_HIGH_S 7 +/* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ +/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ +#define EFUSE_RD_ADC1_TP_LOW 0x7F +#define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V)<<(EFUSE_RD_ADC1_TP_LOW_S)) +#define EFUSE_RD_ADC1_TP_LOW_V 0x7F +#define EFUSE_RD_ADC1_TP_LOW_S 0 + +#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) +/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT4 0xFFFFFFFF +#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S)) +#define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT4_S 0 +/* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ +/*description: Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE */ +#define EFUSE_RD_CAL_RESERVED 0x0000FFFF +#define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V)<<(EFUSE_RD_CAL_RESERVED_S)) +#define EFUSE_RD_CAL_RESERVED_V 0xFFFF +#define EFUSE_RD_CAL_RESERVED_S 0 + +#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) +/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT5 0xFFFFFFFF +#define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S)) +#define EFUSE_BLK3_DOUT5_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT5_S 0 + +#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) +/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT6 0xFFFFFFFF +#define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S)) +#define EFUSE_BLK3_DOUT6_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT6_S 0 + +#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) +/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT7 0xFFFFFFFF +#define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S)) +#define EFUSE_BLK3_DOUT7_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT7_S 0 + +#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) +/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN0 0xFFFFFFFF +#define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S)) +#define EFUSE_BLK1_DIN0_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN0_S 0 + +#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) +/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN1 0xFFFFFFFF +#define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S)) +#define EFUSE_BLK1_DIN1_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN1_S 0 + +#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) +/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN2 0xFFFFFFFF +#define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S)) +#define EFUSE_BLK1_DIN2_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN2_S 0 + +#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) +/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN3 0xFFFFFFFF +#define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S)) +#define EFUSE_BLK1_DIN3_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN3_S 0 + +#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) +/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN4 0xFFFFFFFF +#define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S)) +#define EFUSE_BLK1_DIN4_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN4_S 0 + +#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) +/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN5 0xFFFFFFFF +#define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S)) +#define EFUSE_BLK1_DIN5_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN5_S 0 + +#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) +/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN6 0xFFFFFFFF +#define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S)) +#define EFUSE_BLK1_DIN6_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN6_S 0 + +#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) +/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN7 0xFFFFFFFF +#define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S)) +#define EFUSE_BLK1_DIN7_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN7_S 0 + +#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) +/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN0 0xFFFFFFFF +#define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S)) +#define EFUSE_BLK2_DIN0_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN0_S 0 + +#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) +/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN1 0xFFFFFFFF +#define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S)) +#define EFUSE_BLK2_DIN1_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN1_S 0 + +#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) +/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN2 0xFFFFFFFF +#define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S)) +#define EFUSE_BLK2_DIN2_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN2_S 0 + +#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) +/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN3 0xFFFFFFFF +#define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S)) +#define EFUSE_BLK2_DIN3_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN3_S 0 + +#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) +/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN4 0xFFFFFFFF +#define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S)) +#define EFUSE_BLK2_DIN4_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN4_S 0 + +#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) +/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN5 0xFFFFFFFF +#define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S)) +#define EFUSE_BLK2_DIN5_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN5_S 0 + +#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) +/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN6 0xFFFFFFFF +#define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S)) +#define EFUSE_BLK2_DIN6_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN6_S 0 + +#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) +/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN7 0xFFFFFFFF +#define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S)) +#define EFUSE_BLK2_DIN7_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN7_S 0 + +#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) +/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN0 0xFFFFFFFF +#define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S)) +#define EFUSE_BLK3_DIN0_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN0_S 0 + +#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) +/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN1 0xFFFFFFFF +#define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S)) +#define EFUSE_BLK3_DIN1_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN1_S 0 + +#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) +/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN2 0xFFFFFFFF +#define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S)) +#define EFUSE_BLK3_DIN2_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN2_S 0 + +/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration + * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ +#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) +/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN3 0xFFFFFFFF +#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S)) +#define EFUSE_BLK3_DIN3_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN3_S 0 +/* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ +/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ +#define EFUSE_ADC2_TP_HIGH 0x1FF +#define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V)<<(EFUSE_ADC2_TP_HIGH_S)) +#define EFUSE_ADC2_TP_HIGH_V 0x1FF +#define EFUSE_ADC2_TP_HIGH_S 23 +/* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ +/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ +#define EFUSE_ADC2_TP_LOW 0x7F +#define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V)<<(EFUSE_ADC2_TP_LOW_S)) +#define EFUSE_ADC2_TP_LOW_V 0x7F +#define EFUSE_ADC2_TP_LOW_S 16 +/* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ +/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ +#define EFUSE_ADC1_TP_HIGH 0x1FF +#define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V)<<(EFUSE_ADC1_TP_HIGH_S)) +#define EFUSE_ADC1_TP_HIGH_V 0x1FF +#define EFUSE_ADC1_TP_HIGH_S 7 +/* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ +/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ +#define EFUSE_ADC1_TP_LOW 0x7F +#define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V)<<(EFUSE_ADC1_TP_LOW_S)) +#define EFUSE_ADC1_TP_LOW_V 0x7F +#define EFUSE_ADC1_TP_LOW_S 0 + +#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) +/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN4 0xFFFFFFFF +#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S)) +#define EFUSE_BLK3_DIN4_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN4_S 0 +/* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ +/*description: Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE */ +#define EFUSE_CAL_RESERVED 0x0000FFFF +#define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V)<<(EFUSE_CAL_RESERVED_S)) +#define EFUSE_CAL_RESERVED_V 0xFFFF +#define EFUSE_CAL_RESERVED_S 0 + +#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) +/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN5 0xFFFFFFFF +#define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S)) +#define EFUSE_BLK3_DIN5_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN5_S 0 + +#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) +/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN6 0xFFFFFFFF +#define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S)) +#define EFUSE_BLK3_DIN6_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN6_S 0 + +#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) +/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN7 0xFFFFFFFF +#define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S)) +#define EFUSE_BLK3_DIN7_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN7_S 0 + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) +/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (BIT(16)) +#define EFUSE_CLK_EN_V 0x1 +#define EFUSE_CLK_EN_S 16 +/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */ +/*description: efuse timing configure*/ +#define EFUSE_CLK_SEL1 0x000000FF +#define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S)) +#define EFUSE_CLK_SEL1_V 0xFF +#define EFUSE_CLK_SEL1_S 8 +/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */ +/*description: efuse timing configure*/ +#define EFUSE_CLK_SEL0 0x000000FF +#define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S)) +#define EFUSE_CLK_SEL0_V 0xFF +#define EFUSE_CLK_SEL0_S 0 + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) +/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: */ +#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 +#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 +/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: efuse operation code*/ +#define EFUSE_OP_CODE 0x0000FFFF +#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) +#define EFUSE_OP_CODE_V 0xFFFF +#define EFUSE_OP_CODE_S 0 + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) +/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define EFUSE_DEBUG 0xFFFFFFFF +#define EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S)) +#define EFUSE_DEBUG_V 0xFFFFFFFF +#define EFUSE_DEBUG_S 0 + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) +/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: command for program*/ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (BIT(1)) +#define EFUSE_PGM_CMD_V 0x1 +#define EFUSE_PGM_CMD_S 1 +/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: command for read*/ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (BIT(0)) +#define EFUSE_READ_CMD_V 0x1 +#define EFUSE_READ_CMD_S 0 + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) +/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program done interrupt raw status*/ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_V 0x1 +#define EFUSE_PGM_DONE_INT_RAW_S 1 +/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: read done interrupt raw status*/ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_V 0x1 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) +/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program done interrupt status*/ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_V 0x1 +#define EFUSE_PGM_DONE_INT_ST_S 1 +/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: read done interrupt status*/ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_V 0x1 +#define EFUSE_READ_DONE_INT_ST_S 0 + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) +/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program done interrupt enable*/ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_V 0x1 +#define EFUSE_PGM_DONE_INT_ENA_S 1 +/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: read done interrupt enable*/ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_V 0x1 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) +/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program done interrupt clear*/ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_V 0x1 +#define EFUSE_PGM_DONE_INT_CLR_S 1 +/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: read done interrupt clear*/ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_V 0x1 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) +/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */ +/*description: efuse timing configure*/ +#define EFUSE_DAC_CLK_DIV 0x000000FF +#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) +#define EFUSE_DAC_CLK_DIV_V 0xFF +#define EFUSE_DAC_CLK_DIV_S 0 + +#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) +/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */ +/*description: the decode result of 3/4 coding scheme has warning*/ +#define EFUSE_DEC_WARNINGS 0x00000FFF +#define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S)) +#define EFUSE_DEC_WARNINGS_V 0xFFF +#define EFUSE_DEC_WARNINGS_S 0 + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) +/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */ +/*description: */ +#define EFUSE_DATE 0xFFFFFFFF +#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) +#define EFUSE_DATE_V 0xFFFFFFFF +#define EFUSE_DATE_S 0 + + + + +#endif /*_SOC_EFUSE_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/emac_ex_reg.h b/tools/sdk/include/soc/include/soc/emac_ex_reg.h new file mode 100644 index 00000000000..e43217e0833 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/emac_ex_reg.h @@ -0,0 +1,161 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _EMAC_EX_H_ +#define _EMAC_EX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" +#define REG_EMAC_EX_BASE (DR_REG_EMAC_BASE + 0x800) + +#define EMAC_EX_CLKOUT_CONF_REG (REG_EMAC_EX_BASE + 0x0000) +#define EMAC_EX_CLK_OUT_DLY_NUM 0x00000003 +#define EMAC_EX_CLK_OUT_DLY_NUM_M (EMAC_EX_CLK_OUT_DLY_NUM_V << EMAC_EX_CLK_OUT_DLY_NUM_S) +#define EMAC_EX_CLK_OUT_DLY_NUM_V 0x00000003 +#define EMAC_EX_CLK_OUT_DLY_NUM_S 8 +#define EMAC_EX_CLK_OUT_H_DIV_NUM 0x0000000F +#define EMAC_EX_CLK_OUT_H_DIV_NUM_M (EMAC_EX_CLK_OUT_H_DIV_NUM_V << EMAC_EX_CLK_OUT_H_DIV_NUM_S) +#define EMAC_EX_CLK_OUT_H_DIV_NUM_V 0x0000000F +#define EMAC_EX_CLK_OUT_H_DIV_NUM_S 4 +#define EMAC_EX_CLK_OUT_DIV_NUM 0x0000000F +#define EMAC_EX_CLK_OUT_DIV_NUM_M (EMAC_EX_CLK_OUT_DIV_NUM_V << EMAC_EX_CLK_OUT_DIV_NUM_S) +#define EMAC_EX_CLK_OUT_DIV_NUM_V 0x0000000F +#define EMAC_EX_CLK_OUT_DIV_NUM_S 0 + +#define EMAC_EX_OSCCLK_CONF_REG (REG_EMAC_EX_BASE + 0x0004) +#define EMAC_EX_OSC_CLK_SEL (BIT(24)) +#define EMAC_EX_OSC_CLK_SEL_M (BIT(24)) +#define EMAC_EX_OSC_CLK_SEL_V 1 +#define EMAC_EX_OSC_CLK_SEL_S 24 +#define EMAC_EX_OSC_H_DIV_NUM_100M 0x0000003F +#define EMAC_EX_OSC_H_DIV_NUM_100M_M (EMAC_EX_OSC_H_DIV_NUM_100M_V << EMAC_EX_OSC_H_DIV_NUM_100M_S) +#define EMAC_EX_OSC_H_DIV_NUM_100M_V 0x0000003F +#define EMAC_EX_OSC_H_DIV_NUM_100M_S 18 +#define EMAC_EX_OSC_DIV_NUM_100M 0x0000003F +#define EMAC_EX_OSC_DIV_NUM_100M_M (EMAC_EX_OSC_DIV_NUM_100M_V << EMAC_EX_OSC_DIV_NUM_100M_S) +#define EMAC_EX_OSC_DIV_NUM_100M_V 0x0000003F +#define EMAC_EX_OSC_DIV_NUM_100M_S 12 +#define EMAC_EX_OSC_H_DIV_NUM_10M 0x0000003F +#define EMAC_EX_OSC_H_DIV_NUM_10M_M (EMAC_EX_OSC_H_DIV_NUM_10M_V << EMAC_EX_OSC_H_DIV_NUM_10M_S) +#define EMAC_EX_OSC_H_DIV_NUM_10M_V 0x0000003F +#define EMAC_EX_OSC_H_DIV_NUM_10M_S 6 +#define EMAC_EX_OSC_DIV_NUM_10M 0x0000003F +#define EMAC_EX_OSC_DIV_NUM_10M_M (EMAC_EX_OSC_DIV_NUM_10M_V << EMAC_EX_OSC_DIV_NUM_10M_S) +#define EMAC_EX_OSC_DIV_NUM_10M_V 0x0000003F +#define EMAC_EX_OSC_DIV_NUM_10M_S 0 + +#define EMAC_EX_CLK_CTRL_REG (REG_EMAC_EX_BASE + 0x0008) +#define EMAC_EX_CLK_EN (BIT(5)) +#define EMAC_EX_CLK_EN_M (BIT(5)) +#define EMAC_EX_CLK_EN_V 1 +#define EMAC_EX_CLK_EN_S 5 +#define EMAC_EX_MII_CLK_RX_EN (BIT(4)) +#define EMAC_EX_MII_CLK_RX_EN_M (BIT(4)) +#define EMAC_EX_MII_CLK_RX_EN_V 1 +#define EMAC_EX_MII_CLK_RX_EN_S 4 +#define EMAC_EX_MII_CLK_TX_EN (BIT(3)) +#define EMAC_EX_MII_CLK_TX_EN_M (BIT(3)) +#define EMAC_EX_MII_CLK_TX_EN_V 1 +#define EMAC_EX_MII_CLK_TX_EN_S 3 +#define EMAC_EX_RX_125_CLK_EN (BIT(2)) +#define EMAC_EX_RX_125_CLK_EN_M (BIT(2)) +#define EMAC_EX_RX_125_CLK_EN_V 1 +#define EMAC_EX_RX_125_CLK_EN_S 2 +#define EMAC_EX_INT_OSC_EN (BIT(1)) +#define EMAC_EX_INT_OSC_EN_M (BIT(1)) +#define EMAC_EX_INT_OSC_EN_V 1 +#define EMAC_EX_INT_OSC_EN_S 1 +#define EMAC_EX_EXT_OSC_EN (BIT(0)) +#define EMAC_EX_EXT_OSC_EN_M (BIT(0)) +#define EMAC_EX_EXT_OSC_EN_V 1 +#define EMAC_EX_EXT_OSC_EN_S 0 + +#define EMAC_EX_PHYINF_CONF_REG (REG_EMAC_EX_BASE + 0x000c) +#define EMAC_EX_TX_ERR_OUT_EN (BIT(20)) +#define EMAC_EX_TX_ERR_OUT_EN_M (BIT(20)) +#define EMAC_EX_TX_ERR_OUT_EN_V 1 +#define EMAC_EX_TX_ERR_OUT_EN_S 20 +#define EMAC_EX_SCR_SMI_DLY_RX_SYNC (BIT(19)) +#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_M (BIT(19)) +#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_V 1 +#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_S 19 +#define EMAC_EX_PMT_CTRL_EN (BIT(18)) +#define EMAC_EX_PMT_CTRL_EN_M (BIT(18)) +#define EMAC_EX_PMT_CTRL_EN_V 1 +#define EMAC_EX_PMT_CTRL_EN_S 18 +#define EMAC_EX_SBD_CLK_GATING_EN (BIT(17)) +#define EMAC_EX_SBD_CLK_GATING_EN_M (BIT(17)) +#define EMAC_EX_SBD_CLK_GATING_EN_V 1 +#define EMAC_EX_SBD_CLK_GATING_EN_S 17 +#define EMAC_EX_SS_MODE (BIT(16)) +#define EMAC_EX_SS_MODE_M (BIT(16)) +#define EMAC_EX_SS_MODE_V 1 +#define EMAC_EX_SS_MODE_S 16 +#define EMAC_EX_PHY_INTF_SEL 0x00000007 +#define EMAC_EX_PHY_INTF_SEL_M (EMAC_EX_PHY_INTF_SEL_V << EMAC_EX_PHY_INTF_SEL_S) +#define EMAC_EX_PHY_INTF_SEL_V 0x00000007 +#define EMAC_EX_PHY_INTF_SEL_S 13 +#define EMAC_EX_REVMII_PHY_ADDR 0x0000001F +#define EMAC_EX_REVMII_PHY_ADDR_M (EMAC_EX_REVMII_PHY_ADDR_V << EMAC_EX_REVMII_PHY_ADDR_S) +#define EMAC_EX_REVMII_PHY_ADDR_V 0x0000001F +#define EMAC_EX_REVMII_PHY_ADDR_S 8 +#define EMAC_EX_CORE_PHY_ADDR 0x0000001F +#define EMAC_EX_CORE_PHY_ADDR_M (EMAC_EX_CORE_PHY_ADDR_V << EMAC_EX_CORE_PHY_ADDR_S) +#define EMAC_EX_CORE_PHY_ADDR_V 0x0000001F +#define EMAC_EX_CORE_PHY_ADDR_S 3 +#define EMAC_EX_SBD_FLOWCTRL (BIT(2)) +#define EMAC_EX_SBD_FLOWCTRL_M (BIT(2)) +#define EMAC_EX_SBD_FLOWCTRL_V 1 +#define EMAC_EX_SBD_FLOWCTRL_S 2 +#define EMAC_EX_EXT_REVMII_RX_CLK_SEL (BIT(1)) +#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_M (BIT(1)) +#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_V 1 +#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_S 1 +#define EMAC_EX_INT_REVMII_RX_CLK_SEL (BIT(0)) +#define EMAC_EX_INT_REVMII_RX_CLK_SEL_M (BIT(0)) +#define EMAC_EX_INT_REVMII_RX_CLK_SEL_V 1 +#define EMAC_EX_INT_REVMII_RX_CLK_SEL_S 0 + +#define EMAC_EX_PHY_INTF_RMII 4 + +#define EMAC_EX_EMAC_PD_SEL_REG (REG_EMAC_EX_BASE + 0x0010) +#define EMAC_EX_RAM_PD_EN 0x00000003 +#define EMAC_EX_RAM_PD_EN_M (EMAC_EX_RAM_PD_EN_V << EMAC_EX_RAM_PD_EN_S) +#define EMAC_EX_RAM_PD_EN_V 0x00000003 +#define EMAC_EX_RAM_PD_EN_S 0 + +#define EMAC_EX_DATE_REG (REG_EMAC_EX_BASE + 0x00fc) +#define EMAC_EX_DATE 0xFFFFFFFF +#define EMAC_EX_DATE_M (EMAC_EX_DATE_V << EMAC_EX_DATE_S) +#define EMAC_EX_DATE_V 0xFFFFFFFF +#define EMAC_EX_DATE_S 0 +#define EMAC_EX_DATE_VERSION 0x16042200 +#define EMAC_EX_DATE_VERSION_M (EMAC_EX_DATE_VERSION_V << EMAC_EX_DATE_VERSION_S) +#define EMAC_EX_DATE_VERSION_V 0x16042200 + +#define EMAC_CLK_EN_REG 0x3ff000cc +#define EMAC_CLK_EN_REG_M (EMAC_CLK_EN_REG_V << EMAC_CLK_EN_REG_S) +#define EMAC_CLK_EN_REG_V 0x3ff000cc +#define EMAC_CLK_EN (BIT(14)) +#define EMAC_CLK_EN_M (BIT(14)) +#define EMAC_CLK_EN_V 1 + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/tools/sdk/include/soc/include/soc/emac_reg_v2.h b/tools/sdk/include/soc/include/soc/emac_reg_v2.h new file mode 100644 index 00000000000..72af5bfe365 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/emac_reg_v2.h @@ -0,0 +1,1460 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_EMAC_REG_H_ +#define _SOC_EMAC_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define EMAC_DMABUSMODE_REG (DR_REG_EMAC_BASE + 0x0000) +/* EMAC_DMAMIXEDBURST : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: When this bit is set high and the FIXED_BURST bit is low the + AHB master interface starts all bursts of a length more than 16 with INCR (undefined burst) whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less.*/ +#define EMAC_DMAMIXEDBURST (BIT(26)) +#define EMAC_DMAMIXEDBURST_M (BIT(26)) +#define EMAC_DMAMIXEDBURST_V 0x1 +#define EMAC_DMAMIXEDBURST_S 26 +/* EMAC_DMAADDRALIBEA : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: When this bit is set high and the FIXED_BURST bit is 1 the AHB + interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0 the first burst (accessing the start address of data buffer) is not aligned but subsequent bursts are aligned to the address.*/ +#define EMAC_DMAADDRALIBEA (BIT(25)) +#define EMAC_DMAADDRALIBEA_M (BIT(25)) +#define EMAC_DMAADDRALIBEA_V 0x1 +#define EMAC_DMAADDRALIBEA_S 25 +/* EMAC_PBLX8_MODE : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: When set high this bit multiplies the programmed PBL value (Bits[22:17] + and Bits[13:8]) eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending on the PBL value.*/ +#define EMAC_PBLX8_MODE (BIT(24)) +#define EMAC_PBLX8_MODE_M (BIT(24)) +#define EMAC_PBLX8_MODE_V 0x1 +#define EMAC_PBLX8_MODE_S 24 +/* EMAC_USE_SEP_PBL : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: When set high this bit configures the Rx DMA to use the value + configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When reset to low the PBL value in Bits[13:8] is applicable for both DMA engines.*/ +#define EMAC_USE_SEP_PBL (BIT(23)) +#define EMAC_USE_SEP_PBL_M (BIT(23)) +#define EMAC_USE_SEP_PBL_V 0x1 +#define EMAC_USE_SEP_PBL_S 23 +/* EMAC_RX_DMA_PBL : R/W ;bitpos:[22:17] ;default: 6'h1 ; */ +/*description: This field indicates the maximum number of beats to be transferred + in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst transfer on the host bus. You can program RPBL with values of 1 2 4 8 16 and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is set high.*/ +#define EMAC_RX_DMA_PBL 0x0000003F +#define EMAC_RX_DMA_PBL_M ((EMAC_RX_DMA_PBL_V)<<(EMAC_RX_DMA_PBL_S)) +#define EMAC_RX_DMA_PBL_V 0x3F +#define EMAC_RX_DMA_PBL_S 17 +/* EMAC_FIXED_BURST : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: This bit controls whether the AHB master interface performs fixed + burst transfers or not. When set the AHB interface uses only SINGLE INCR4 INCR8 or INCR16 during start of the normal burst transfers. When reset the AHB interface uses SINGLE and INCR burst transfer Operations.*/ +#define EMAC_FIXED_BURST (BIT(16)) +#define EMAC_FIXED_BURST_M (BIT(16)) +#define EMAC_FIXED_BURST_V 0x1 +#define EMAC_FIXED_BURST_S 16 +/* EMAC_PRI_RATIO : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: These bits control the priority ratio in the weighted round-robin + arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit: 2'b00 -- 1: 1 2'b01 -- 2: 0 2'b10 -- 3: 1 2'b11 -- 4: 1*/ +#define EMAC_PRI_RATIO 0x00000003 +#define EMAC_PRI_RATIO_M ((EMAC_PRI_RATIO_V)<<(EMAC_PRI_RATIO_S)) +#define EMAC_PRI_RATIO_V 0x3 +#define EMAC_PRI_RATIO_S 14 +/* EMAC_PROG_BURST_LEN : R/W ;bitpos:[13:8] ;default: 6'h1 ; */ +/*description: These bits indicate the maximum number of beats to be transferred + in one DMA transaction. If the number of beats to be transferred is more than 32 then perform the following steps: 1. Set the PBLx8 mode 2. Set the PBL(PROG_BURST_LEN).*/ +#define EMAC_PROG_BURST_LEN 0x0000003F +#define EMAC_PROG_BURST_LEN_M ((EMAC_PROG_BURST_LEN_V)<<(EMAC_PROG_BURST_LEN_S)) +#define EMAC_PROG_BURST_LEN_V 0x3F +#define EMAC_PROG_BURST_LEN_S 8 +/* EMAC_ALT_DESC_SIZE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: When set the size of the alternate descriptor increases to 32 bytes.*/ +#define EMAC_ALT_DESC_SIZE (BIT(7)) +#define EMAC_ALT_DESC_SIZE_M (BIT(7)) +#define EMAC_ALT_DESC_SIZE_V 0x1 +#define EMAC_ALT_DESC_SIZE_S 7 +/* EMAC_DESC_SKIP_LEN : R/W ;bitpos:[6:2] ;default: 5'h0 ; */ +/*description: This bit specifies the number of Word to skip between two unchained + descriptors.The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_LEN) value is equal to zero the descriptor table is taken as contiguous by the DMA in Ring mode.*/ +#define EMAC_DESC_SKIP_LEN 0x0000001F +#define EMAC_DESC_SKIP_LEN_M ((EMAC_DESC_SKIP_LEN_V)<<(EMAC_DESC_SKIP_LEN_S)) +#define EMAC_DESC_SKIP_LEN_V 0x1F +#define EMAC_DESC_SKIP_LEN_S 2 +/* EMAC_DMA_ARB_SCH : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: This bit specifies the arbitration scheme between the transmit + and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX priority specified in PR (bit[15:14]). 1'b1 Fixed priority (Rx priority to Tx).*/ +#define EMAC_DMA_ARB_SCH (BIT(1)) +#define EMAC_DMA_ARB_SCH_M (BIT(1)) +#define EMAC_DMA_ARB_SCH_V 0x1 +#define EMAC_DMA_ARB_SCH_S 1 +/* EMAC_SW_RST : R_WS_SC ;bitpos:[0] ;default: 1'h1 ; */ +/*description: When this bit is set the MAC DMA Controller resets the logic + and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit.*/ +#define EMAC_SW_RST (BIT(0)) +#define EMAC_SW_RST_M (BIT(0)) +#define EMAC_SW_RST_V 0x1 +#define EMAC_SW_RST_S 0 + +#define EMAC_DMATXPOLLDEMAND_REG (DR_REG_EMAC_BASE + 0x0004) +/* EMAC_TRANS_POLL_DEMAND : RO_WT ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: When these bits are written with any value the DMA reads the + current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes.*/ +#define EMAC_TRANS_POLL_DEMAND 0xFFFFFFFF +#define EMAC_TRANS_POLL_DEMAND_M ((EMAC_TRANS_POLL_DEMAND_V)<<(EMAC_TRANS_POLL_DEMAND_S)) +#define EMAC_TRANS_POLL_DEMAND_V 0xFFFFFFFF +#define EMAC_TRANS_POLL_DEMAND_S 0 + +#define EMAC_DMARXPOLLDEMAND_REG (DR_REG_EMAC_BASE + 0x0008) +/* EMAC_RECV_POLL_DEMAND : RO_WT ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: When these bits are written with any value the DMA reads the + current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state.*/ +#define EMAC_RECV_POLL_DEMAND 0xFFFFFFFF +#define EMAC_RECV_POLL_DEMAND_M ((EMAC_RECV_POLL_DEMAND_V)<<(EMAC_RECV_POLL_DEMAND_S)) +#define EMAC_RECV_POLL_DEMAND_V 0xFFFFFFFF +#define EMAC_RECV_POLL_DEMAND_S 0 + +#define EMAC_DMARXBASEADDR_REG (DR_REG_EMAC_BASE + 0x000C) +/* EMAC_START_RECV_LIST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This field contains the base address of the first descriptor + in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.*/ +#define EMAC_START_RECV_LIST 0xFFFFFFFF +#define EMAC_START_RECV_LIST_M ((EMAC_START_RECV_LIST_V)<<(EMAC_START_RECV_LIST_S)) +#define EMAC_START_RECV_LIST_V 0xFFFFFFFF +#define EMAC_START_RECV_LIST_S 0 + +#define EMAC_DMATXBASEADDR_REG (DR_REG_EMAC_BASE + 0x0010) +/* EMAC_START_TRANS_LIST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This field contains the base address of the first descriptor + in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only.*/ +#define EMAC_START_TRANS_LIST 0xFFFFFFFF +#define EMAC_START_TRANS_LIST_M ((EMAC_START_TRANS_LIST_V)<<(EMAC_START_TRANS_LIST_S)) +#define EMAC_START_TRANS_LIST_V 0xFFFFFFFF +#define EMAC_START_TRANS_LIST_S 0 + +#define EMAC_DMASTATUS_REG (DR_REG_EMAC_BASE + 0x0014) +/* EMAC_TS_TRI_INT : RO ;bitpos:[29] ;default: 1'h0 ; */ +/*description: This bit indicates an interrupt event in the Timestamp Generator + block of the ETH_MAC.The software must read the corresponding registers in the ETH_MAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0.*/ +#define EMAC_TS_TRI_INT (BIT(29)) +#define EMAC_TS_TRI_INT_M (BIT(29)) +#define EMAC_TS_TRI_INT_V 0x1 +#define EMAC_TS_TRI_INT_S 29 +/* EMAC_PMT_INT : RO ;bitpos:[28] ;default: 1'h0 ; */ +/*description: This bit indicates an interrupt event in the PMT module of the + ETH_MAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0.*/ +#define EMAC_PMT_INT (BIT(28)) +#define EMAC_PMT_INT_M (BIT(28)) +#define EMAC_PMT_INT_V 0x1 +#define EMAC_PMT_INT_S 28 +/* EMAC_ERROR_BITS : RO ;bitpos:[25:23] ;default: 3'h0 ; */ +/*description: This field indicates the type of error that caused a Bus Error + for example error response on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate an interrupt. 3'b000: Error during Rx DMA Write Data Transfer. 3'b011: Error during Tx DMA Read Data Transfer. 3'b100: Error during Rx DMA Descriptor Write Access. 3'b101: Error during Tx DMA Descriptor Write Access. 3'b110: Error during Rx DMA Descriptor Read Access. 3'b111: Error during Tx DMA Descriptor Read Access.*/ +#define EMAC_ERROR_BITS 0x00000007 +#define EMAC_ERROR_BITS_M ((EMAC_ERROR_BITS_V)<<(EMAC_ERROR_BITS_S)) +#define EMAC_ERROR_BITS_V 0x7 +#define EMAC_ERROR_BITS_S 23 +/* EMAC_TRANS_PROC_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: This field indicates the Transmit DMA FSM state. This field does + not generate an interrupt. 3'b000: Stopped. Reset or Stop Transmit Command issued. 3'b001: Running. Fetching Transmit Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for TX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Transmit Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from transmit buffer to host memory.*/ +#define EMAC_TRANS_PROC_STATE 0x00000007 +#define EMAC_TRANS_PROC_STATE_M ((EMAC_TRANS_PROC_STATE_V)<<(EMAC_TRANS_PROC_STATE_S)) +#define EMAC_TRANS_PROC_STATE_V 0x7 +#define EMAC_TRANS_PROC_STATE_S 20 +/* EMAC_RECV_PROC_STATE : RO ;bitpos:[19:17] ;default: 3'h0 ; */ +/*description: This field indicates the Receive DMA FSM state. This field does + not generate an interrupt. 3'b000: Stopped. Reset or Stop Receive Command issued. 3'b001: Running. Fetching Receive Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for RX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Receive Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from receive buffer to host memory.*/ +#define EMAC_RECV_PROC_STATE 0x00000007 +#define EMAC_RECV_PROC_STATE_M ((EMAC_RECV_PROC_STATE_V)<<(EMAC_RECV_PROC_STATE_S)) +#define EMAC_RECV_PROC_STATE_V 0x7 +#define EMAC_RECV_PROC_STATE_S 17 +/* EMAC_NORM_INT_SUMM : R_SS_WC ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Normal Interrupt Summary bit value is the logical OR of the following + bits when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared.*/ +#define EMAC_NORM_INT_SUMM (BIT(16)) +#define EMAC_NORM_INT_SUMM_M (BIT(16)) +#define EMAC_NORM_INT_SUMM_V 0x1 +#define EMAC_NORM_INT_SUMM_S 16 +/* EMAC_ABN_INT_SUMM : R_SS_WC ;bitpos:[15] ;default: 1'h0 ; */ +/*description: Abnormal Interrupt Summary bit value is the logical OR of the + following when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive FIFO Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes AIS to be set is cleared.*/ +#define EMAC_ABN_INT_SUMM (BIT(15)) +#define EMAC_ABN_INT_SUMM_M (BIT(15)) +#define EMAC_ABN_INT_SUMM_V 0x1 +#define EMAC_ABN_INT_SUMM_S 15 +/* EMAC_EARLY_RECV_INT : R_SS_WC ;bitpos:[14] ;default: 1'h0 ; */ +/*description: This bit indicates that the DMA filled the first data buffer + of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever occurs earlier).*/ +#define EMAC_EARLY_RECV_INT (BIT(14)) +#define EMAC_EARLY_RECV_INT_M (BIT(14)) +#define EMAC_EARLY_RECV_INT_V 0x1 +#define EMAC_EARLY_RECV_INT_S 14 +/* EMAC_FATAL_BUS_ERR_INT : R_SS_WC ;bitpos:[13] ;default: 1'h0 ; */ +/*description: This bit indicates that a bus error occurred as described in + Bits [25:23]. When this bit is set the corresponding DMA engine disables all of its bus accesses.*/ +#define EMAC_FATAL_BUS_ERR_INT (BIT(13)) +#define EMAC_FATAL_BUS_ERR_INT_M (BIT(13)) +#define EMAC_FATAL_BUS_ERR_INT_V 0x1 +#define EMAC_FATAL_BUS_ERR_INT_S 13 +/* EMAC_EARLY_TRANS_INT : R_SS_WC ;bitpos:[10] ;default: 1'h0 ; */ +/*description: This bit indicates that the frame to be transmitted is fully + transferred to the MTL Transmit FIFO.*/ +#define EMAC_EARLY_TRANS_INT (BIT(10)) +#define EMAC_EARLY_TRANS_INT_M (BIT(10)) +#define EMAC_EARLY_TRANS_INT_V 0x1 +#define EMAC_EARLY_TRANS_INT_S 10 +/* EMAC_RECV_WDT_TO : R_SS_WC ;bitpos:[9] ;default: 1'h0 ; */ +/*description: When set this bit indicates that the Receive Watchdog Timer + expired while receiving the current frame and the current frame is truncated after the watchdog timeout.*/ +#define EMAC_RECV_WDT_TO (BIT(9)) +#define EMAC_RECV_WDT_TO_M (BIT(9)) +#define EMAC_RECV_WDT_TO_V 0x1 +#define EMAC_RECV_WDT_TO_S 9 +/* EMAC_RECV_PROC_STOP : R_SS_WC ;bitpos:[8] ;default: 1'h0 ; */ +/*description: This bit is asserted when the Receive Process enters the Stopped state.*/ +#define EMAC_RECV_PROC_STOP (BIT(8)) +#define EMAC_RECV_PROC_STOP_M (BIT(8)) +#define EMAC_RECV_PROC_STOP_V 0x1 +#define EMAC_RECV_PROC_STOP_S 8 +/* EMAC_RECV_BUF_UNAVAIL : R_SS_WC ;bitpos:[7] ;default: 1'h0 ; */ +/*description: This bit indicates that the host owns the Next Descriptor in + the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA.*/ +#define EMAC_RECV_BUF_UNAVAIL (BIT(7)) +#define EMAC_RECV_BUF_UNAVAIL_M (BIT(7)) +#define EMAC_RECV_BUF_UNAVAIL_V 0x1 +#define EMAC_RECV_BUF_UNAVAIL_S 7 +/* EMAC_RECV_INT : R_SS_WC ;bitpos:[6] ;default: 1'h0 ; */ +/*description: This bit indicates that the frame reception is complete. When + reception is complete the Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor and the specific frame status information is updated in the descriptor. The reception remains in the Running state.*/ +#define EMAC_RECV_INT (BIT(6)) +#define EMAC_RECV_INT_M (BIT(6)) +#define EMAC_RECV_INT_V 0x1 +#define EMAC_RECV_INT_S 6 +/* EMAC_TRANS_UNDFLOW : R_SS_WC ;bitpos:[5] ;default: 1'h0 ; */ +/*description: This bit indicates that the Transmit Buffer had an Underflow + during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.*/ +#define EMAC_TRANS_UNDFLOW (BIT(5)) +#define EMAC_TRANS_UNDFLOW_M (BIT(5)) +#define EMAC_TRANS_UNDFLOW_V 0x1 +#define EMAC_TRANS_UNDFLOW_S 5 +/* EMAC_RECV_OVFLOW : R_SS_WC ;bitpos:[4] ;default: 1'h0 ; */ +/*description: This bit indicates that the Receive Buffer had an Overflow during + frame reception. If the partial frame is transferred to the application the overflow status is set in RDES0[11].*/ +#define EMAC_RECV_OVFLOW (BIT(4)) +#define EMAC_RECV_OVFLOW_M (BIT(4)) +#define EMAC_RECV_OVFLOW_V 0x1 +#define EMAC_RECV_OVFLOW_S 4 +/* EMAC_TRANS_JABBER_TO : R_SS_WC ;bitpos:[3] ;default: 1'h0 ; */ +/*description: This bit indicates that the Transmit Jabber Timer expired which + happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.*/ +#define EMAC_TRANS_JABBER_TO (BIT(3)) +#define EMAC_TRANS_JABBER_TO_M (BIT(3)) +#define EMAC_TRANS_JABBER_TO_V 0x1 +#define EMAC_TRANS_JABBER_TO_S 3 +/* EMAC_TRANS_BUF_UNAVAIL : R_SS_WC ;bitpos:[2] ;default: 1'h0 ; */ +/*description: This bit indicates that the host owns the Next Descriptor in + the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand Command.*/ +#define EMAC_TRANS_BUF_UNAVAIL (BIT(2)) +#define EMAC_TRANS_BUF_UNAVAIL_M (BIT(2)) +#define EMAC_TRANS_BUF_UNAVAIL_V 0x1 +#define EMAC_TRANS_BUF_UNAVAIL_S 2 +/* EMAC_TRANS_PROC_STOP : R_SS_WC ;bitpos:[1] ;default: 1'h0 ; */ +/*description: This bit is set when the transmission is stopped.*/ +#define EMAC_TRANS_PROC_STOP (BIT(1)) +#define EMAC_TRANS_PROC_STOP_M (BIT(1)) +#define EMAC_TRANS_PROC_STOP_V 0x1 +#define EMAC_TRANS_PROC_STOP_S 1 +/* EMAC_TRANS_INT : R_SS_WC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit indicates that the frame transmission is complete. When + transmission is complete Bit[31] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descriptor.*/ +#define EMAC_TRANS_INT (BIT(0)) +#define EMAC_TRANS_INT_M (BIT(0)) +#define EMAC_TRANS_INT_V 0x1 +#define EMAC_TRANS_INT_S 0 + +#define EMAC_DMAOPERATION_MODE_REG (DR_REG_EMAC_BASE + 0x0018) +/* EMAC_DIS_DROP_TCPIP_ERR_FRAM : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC does not drop the frames which + only have errors detected by the Receive Checksum engine.When this bit is reset all error frames are dropped if the Fwd_Err_Frame bit is reset.*/ +#define EMAC_DIS_DROP_TCPIP_ERR_FRAM (BIT(26)) +#define EMAC_DIS_DROP_TCPIP_ERR_FRAM_M (BIT(26)) +#define EMAC_DIS_DROP_TCPIP_ERR_FRAM_V 0x1 +#define EMAC_DIS_DROP_TCPIP_ERR_FRAM_S 26 +/* EMAC_RX_STORE_FORWARD : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: When this bit is set the MTL reads a frame from the Rx FIFO + only after the complete frame has been written to it.*/ +#define EMAC_RX_STORE_FORWARD (BIT(25)) +#define EMAC_RX_STORE_FORWARD_M (BIT(25)) +#define EMAC_RX_STORE_FORWARD_V 0x1 +#define EMAC_RX_STORE_FORWARD_S 25 +/* EMAC_DIS_FLUSH_RECV_FRAMES : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: When this bit is set the Rx DMA does not flush any frames because + of the unavailability of receive descriptors or buffers.*/ +#define EMAC_DIS_FLUSH_RECV_FRAMES (BIT(24)) +#define EMAC_DIS_FLUSH_RECV_FRAMES_M (BIT(24)) +#define EMAC_DIS_FLUSH_RECV_FRAMES_V 0x1 +#define EMAC_DIS_FLUSH_RECV_FRAMES_S 24 +/* EMAC_TX_STR_FWD : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: When this bit is set transmission starts when a full frame resides + in the MTL Transmit FIFO. When this bit is set the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored.*/ +#define EMAC_TX_STR_FWD (BIT(21)) +#define EMAC_TX_STR_FWD_M (BIT(21)) +#define EMAC_TX_STR_FWD_V 0x1 +#define EMAC_TX_STR_FWD_S 21 +/* EMAC_FLUSH_TX_FIFO : R_WS_SC ;bitpos:[20] ;default: 1'h0 ; */ +/*description: When this bit is set the transmit FIFO controller logic is reset + to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete.*/ +#define EMAC_FLUSH_TX_FIFO (BIT(20)) +#define EMAC_FLUSH_TX_FIFO_M (BIT(20)) +#define EMAC_FLUSH_TX_FIFO_V 0x1 +#define EMAC_FLUSH_TX_FIFO_S 20 +/* EMAC_TX_THRESH_CTRL : R/W ;bitpos:[16:14] ;default: 3'h0 ; */ +/*description: These bits control the threshold level of the MTL Transmit FIFO. + Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3'b000: 64 3'b001: 128 3'b010: 192 3'b011: 256 3'b100: 40 3'b101: 32 3'b110: 24 3'b111: 16 .*/ +#define EMAC_TX_THRESH_CTRL 0x00000007 +#define EMAC_TX_THRESH_CTRL_M ((EMAC_TX_THRESH_CTRL_V)<<(EMAC_TX_THRESH_CTRL_S)) +#define EMAC_TX_THRESH_CTRL_V 0x7 +#define EMAC_TX_THRESH_CTRL_S 14 +/* EMAC_START_STOP_TRANSMISSION_COMMAND : R/W ;bitpos:[13] ;default: 1'h0 ; */ +/*description: When this bit is set transmission is placed in the Running state + and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset the transmission process is placed in the Stopped state after completing the transmission of the current frame.*/ +#define EMAC_START_STOP_TRANSMISSION_COMMAND (BIT(13)) +#define EMAC_START_STOP_TRANSMISSION_COMMAND_M (BIT(13)) +#define EMAC_START_STOP_TRANSMISSION_COMMAND_V 0x1 +#define EMAC_START_STOP_TRANSMISSION_COMMAND_S 13 +/* EMAC_FWD_ERR_FRAME : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: When this bit is reset the Rx FIFO drops frames with error status + (CRC error collision error giant frame watchdog timeout or overflow).*/ +#define EMAC_FWD_ERR_FRAME (BIT(7)) +#define EMAC_FWD_ERR_FRAME_M (BIT(7)) +#define EMAC_FWD_ERR_FRAME_V 0x1 +#define EMAC_FWD_ERR_FRAME_S 7 +/* EMAC_FWD_UNDER_GF : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: When set the Rx FIFO forwards Undersized frames (that is frames + with no Error and length less than 64 bytes) including pad-bytes and CRC.*/ +#define EMAC_FWD_UNDER_GF (BIT(6)) +#define EMAC_FWD_UNDER_GF_M (BIT(6)) +#define EMAC_FWD_UNDER_GF_V 0x1 +#define EMAC_FWD_UNDER_GF_S 6 +/* EMAC_DROP_GFRM : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: When set the MAC drops the received giant frames in the Rx FIFO + that is frames that are larger than the computed giant frame limit.*/ +#define EMAC_DROP_GFRM (BIT(5)) +#define EMAC_DROP_GFRM_M (BIT(5)) +#define EMAC_DROP_GFRM_V 0x1 +#define EMAC_DROP_GFRM_S 5 +/* EMAC_RX_THRESH_CTRL : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: These two bits control the threshold level of the MTL Receive + FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2'b00: 64， 2'b01: 32， 2'b10: 96， 2'b11: 128 .*/ +#define EMAC_RX_THRESH_CTRL 0x00000003 +#define EMAC_RX_THRESH_CTRL_M ((EMAC_RX_THRESH_CTRL_V)<<(EMAC_RX_THRESH_CTRL_S)) +#define EMAC_RX_THRESH_CTRL_V 0x3 +#define EMAC_RX_THRESH_CTRL_S 3 +/* EMAC_OPT_SECOND_FRAME : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: When this bit is set it instructs the DMA to process the second + frame of the Transmit data even before the status for the first frame is obtained.*/ +#define EMAC_OPT_SECOND_FRAME (BIT(2)) +#define EMAC_OPT_SECOND_FRAME_M (BIT(2)) +#define EMAC_OPT_SECOND_FRAME_V 0x1 +#define EMAC_OPT_SECOND_FRAME_S 2 +/* EMAC_START_STOP_RX : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: When this bit is set the Receive process is placed in the Running + state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame.*/ +#define EMAC_START_STOP_RX (BIT(1)) +#define EMAC_START_STOP_RX_M (BIT(1)) +#define EMAC_START_STOP_RX_V 0x1 +#define EMAC_START_STOP_RX_S 1 + +#define EMAC_DMAIN_EN_REG (DR_REG_EMAC_BASE + 0x001C) +/* EMAC_DMAIN_NISE : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: When this bit is set normal interrupt summary is enabled. When + this bit is reset normal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt.*/ +#define EMAC_DMAIN_NISE (BIT(16)) +#define EMAC_DMAIN_NISE_M (BIT(16)) +#define EMAC_DMAIN_NISE_V 0x1 +#define EMAC_DMAIN_NISE_S 16 +/* EMAC_DMAIN_AISE : R/W ;bitpos:[15] ;default: 1'h0 ; */ +/*description: When this bit is set abnormal interrupt summary is enabled. + When this bit is reset the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error.*/ +#define EMAC_DMAIN_AISE (BIT(15)) +#define EMAC_DMAIN_AISE_M (BIT(15)) +#define EMAC_DMAIN_AISE_V 0x1 +#define EMAC_DMAIN_AISE_S 15 +/* EMAC_DMAIN_ERIE : R/W ;bitpos:[14] ;default: 1'h0 ; */ +/*description: When this bit is set with Normal Interrupt Summary Enable (Bit[16]) + the Early Receive Interrupt is enabled. When this bit is reset the Early Receive Interrupt is disabled.*/ +#define EMAC_DMAIN_ERIE (BIT(14)) +#define EMAC_DMAIN_ERIE_M (BIT(14)) +#define EMAC_DMAIN_ERIE_V 0x1 +#define EMAC_DMAIN_ERIE_S 14 +/* EMAC_DMAIN_FBEE : R/W ;bitpos:[13] ;default: 1'h0 ; */ +/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) + the Fatal Bus Error Interrupt is enabled. When this bit is reset the Fatal Bus Error Enable Interrupt is disabled.*/ +#define EMAC_DMAIN_FBEE (BIT(13)) +#define EMAC_DMAIN_FBEE_M (BIT(13)) +#define EMAC_DMAIN_FBEE_V 0x1 +#define EMAC_DMAIN_FBEE_S 13 +/* EMAC_DMAIN_ETIE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: When this bit is set with an Abnormal Interrupt Summary Enable + (Bit[15]) the Early Transmit Interrupt is enabled. When this bit is reset the Early Transmit Interrupt is disabled.*/ +#define EMAC_DMAIN_ETIE (BIT(10)) +#define EMAC_DMAIN_ETIE_M (BIT(10)) +#define EMAC_DMAIN_ETIE_V 0x1 +#define EMAC_DMAIN_ETIE_S 10 +/* EMAC_DMAIN_RWTE : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) + the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset the Receive Watchdog Timeout Interrupt is disabled.*/ +#define EMAC_DMAIN_RWTE (BIT(9)) +#define EMAC_DMAIN_RWTE_M (BIT(9)) +#define EMAC_DMAIN_RWTE_V 0x1 +#define EMAC_DMAIN_RWTE_S 9 +/* EMAC_DMAIN_RSE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) + the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped Interrupt is disabled.*/ +#define EMAC_DMAIN_RSE (BIT(8)) +#define EMAC_DMAIN_RSE_M (BIT(8)) +#define EMAC_DMAIN_RSE_V 0x1 +#define EMAC_DMAIN_RSE_S 8 +/* EMAC_DMAIN_RBUE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) + the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset the Receive Buffer Unavailable Interrupt is disabled.*/ +#define EMAC_DMAIN_RBUE (BIT(7)) +#define EMAC_DMAIN_RBUE_M (BIT(7)) +#define EMAC_DMAIN_RBUE_V 0x1 +#define EMAC_DMAIN_RBUE_S 7 +/* EMAC_DMAIN_RIE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: When this bit is set with Normal Interrupt Summary Enable (Bit[16]) + the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled.*/ +#define EMAC_DMAIN_RIE (BIT(6)) +#define EMAC_DMAIN_RIE_M (BIT(6)) +#define EMAC_DMAIN_RIE_V 0x1 +#define EMAC_DMAIN_RIE_S 6 +/* EMAC_DMAIN_UIE : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) + the Transmit Underflow Interrupt is enabled. When this bit is reset the Underflow Interrupt is disabled.*/ +#define EMAC_DMAIN_UIE (BIT(5)) +#define EMAC_DMAIN_UIE_M (BIT(5)) +#define EMAC_DMAIN_UIE_V 0x1 +#define EMAC_DMAIN_UIE_S 5 +/* EMAC_DMAIN_OIE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) + the Receive Overflow Interrupt is enabled. When this bit is reset the Overflow Interrupt is disabled.*/ +#define EMAC_DMAIN_OIE (BIT(4)) +#define EMAC_DMAIN_OIE_M (BIT(4)) +#define EMAC_DMAIN_OIE_V 0x1 +#define EMAC_DMAIN_OIE_S 4 +/* EMAC_DMAIN_TJTE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) + the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset the Transmit Jabber Timeout Interrupt is disabled.*/ +#define EMAC_DMAIN_TJTE (BIT(3)) +#define EMAC_DMAIN_TJTE_M (BIT(3)) +#define EMAC_DMAIN_TJTE_V 0x1 +#define EMAC_DMAIN_TJTE_S 3 +/* EMAC_DMAIN_TBUE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: When this bit is set with Normal Interrupt Summary Enable (Bit + 16) the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable Interrupt is Disabled.*/ +#define EMAC_DMAIN_TBUE (BIT(2)) +#define EMAC_DMAIN_TBUE_M (BIT(2)) +#define EMAC_DMAIN_TBUE_V 0x1 +#define EMAC_DMAIN_TBUE_S 2 +/* EMAC_DMAIN_TSE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) + the Transmission Stopped Interrupt is enabled. When this bit is reset the Transmission Stopped Interrupt is disabled.*/ +#define EMAC_DMAIN_TSE (BIT(1)) +#define EMAC_DMAIN_TSE_M (BIT(1)) +#define EMAC_DMAIN_TSE_V 0x1 +#define EMAC_DMAIN_TSE_S 1 +/* EMAC_DMAIN_TIE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When this bit is set with Normal Interrupt Summary Enable (Bit[16]) + the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled.*/ +#define EMAC_DMAIN_TIE (BIT(0)) +#define EMAC_DMAIN_TIE_M (BIT(0)) +#define EMAC_DMAIN_TIE_V 0x1 +#define EMAC_DMAIN_TIE_S 0 + +#define EMAC_DMAMISSEDFR_REG (DR_REG_EMAC_BASE + 0x0020) +/* EMAC_OVERFLOW_BFOC : R_SS_RC ;bitpos:[28] ;default: 1'h0 ; */ +/*description: This bit is set every time the Overflow Frame Counter (Bits[27:17]) + overflows that is the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/ +#define EMAC_OVERFLOW_BFOC (BIT(28)) +#define EMAC_OVERFLOW_BFOC_M (BIT(28)) +#define EMAC_OVERFLOW_BFOC_V 0x1 +#define EMAC_OVERFLOW_BFOC_S 28 +/* EMAC_OVERFLOW_FC : R_SS_RC ;bitpos:[27:17] ;default: 11'h0 ; */ +/*description: This field indicates the number of frames missed by the application. + This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read.*/ +#define EMAC_OVERFLOW_FC 0x000007FF +#define EMAC_OVERFLOW_FC_M ((EMAC_OVERFLOW_FC_V)<<(EMAC_OVERFLOW_FC_S)) +#define EMAC_OVERFLOW_FC_V 0x7FF +#define EMAC_OVERFLOW_FC_S 17 +/* EMAC_OVERFLOW_BMFC : R_SS_RC ;bitpos:[16] ;default: 1'h0 ; */ +/*description: This bit is set every time Missed Frame Counter (Bits[15:0]) + overflows that is the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/ +#define EMAC_OVERFLOW_BMFC (BIT(16)) +#define EMAC_OVERFLOW_BMFC_M (BIT(16)) +#define EMAC_OVERFLOW_BMFC_V 0x1 +#define EMAC_OVERFLOW_BMFC_S 16 +/* EMAC_MISSED_FC : R_SS_RC ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This field indicates the number of frames missed by the controller + because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read.*/ +#define EMAC_MISSED_FC 0x0000FFFF +#define EMAC_MISSED_FC_M ((EMAC_MISSED_FC_V)<<(EMAC_MISSED_FC_S)) +#define EMAC_MISSED_FC_V 0xFFFF +#define EMAC_MISSED_FC_S 0 + +#define EMAC_DMARINTWDTIMER_REG (DR_REG_EMAC_BASE + 0x0024) +/* EMAC_RIWTC : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: This bit indicates the number of system clock cycles multiplied + by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame.*/ +#define EMAC_RIWTC 0x000000FF +#define EMAC_RIWTC_M ((EMAC_RIWTC_V)<<(EMAC_RIWTC_S)) +#define EMAC_RIWTC_V 0xFF +#define EMAC_RIWTC_S 0 + +#define EMAC_DMATXCURRDESC_REG (DR_REG_EMAC_BASE + 0x0048) +/* EMAC_TRANS_DSCR_ADDR_PTR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The address of the current receive descriptor list. Cleared on + Reset.Pointer updated by the DMA during operation.*/ +#define EMAC_TRANS_DSCR_ADDR_PTR 0xFFFFFFFF +#define EMAC_TRANS_DSCR_ADDR_PTR_M ((EMAC_TRANS_DSCR_ADDR_PTR_V)<<(EMAC_TRANS_DSCR_ADDR_PTR_S)) +#define EMAC_TRANS_DSCR_ADDR_PTR_V 0xFFFFFFFF +#define EMAC_TRANS_DSCR_ADDR_PTR_S 0 + +#define EMAC_DMARXCURRDESC_REG (DR_REG_EMAC_BASE + 0x004C) +/* EMAC_RECV_DSCR_ADDR_PTR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The address of the current receive descriptor list. Cleared on + Reset.Pointer updated by the DMA during operation.*/ +#define EMAC_RECV_DSCR_ADDR_PTR 0xFFFFFFFF +#define EMAC_RECV_DSCR_ADDR_PTR_M ((EMAC_RECV_DSCR_ADDR_PTR_V)<<(EMAC_RECV_DSCR_ADDR_PTR_S)) +#define EMAC_RECV_DSCR_ADDR_PTR_V 0xFFFFFFFF +#define EMAC_RECV_DSCR_ADDR_PTR_S 0 + +#define EMAC_DMATXCURRADDR_BUF_REG (DR_REG_EMAC_BASE + 0x0050) +/* EMAC_TRANS_BUFF_ADDR_PTR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The address of the current receive descriptor list. Cleared on + Reset.Pointer updated by the DMA during operation.*/ +#define EMAC_TRANS_BUFF_ADDR_PTR 0xFFFFFFFF +#define EMAC_TRANS_BUFF_ADDR_PTR_M ((EMAC_TRANS_BUFF_ADDR_PTR_V)<<(EMAC_TRANS_BUFF_ADDR_PTR_S)) +#define EMAC_TRANS_BUFF_ADDR_PTR_V 0xFFFFFFFF +#define EMAC_TRANS_BUFF_ADDR_PTR_S 0 + +#define EMAC_DMARXCURRADDR_BUF_REG (DR_REG_EMAC_BASE + 0x0054) +/* EMAC_RECV_BUFF_ADDR_PTR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The address of the current receive descriptor list. Cleared on + Reset.Pointer updated by the DMA during operation.*/ +#define EMAC_RECV_BUFF_ADDR_PTR 0xFFFFFFFF +#define EMAC_RECV_BUFF_ADDR_PTR_M ((EMAC_RECV_BUFF_ADDR_PTR_V)<<(EMAC_RECV_BUFF_ADDR_PTR_S)) +#define EMAC_RECV_BUFF_ADDR_PTR_V 0xFFFFFFFF +#define EMAC_RECV_BUFF_ADDR_PTR_S 0 + +#define EMAC_GMACCONFIG_REG (DR_REG_EMAC_BASE + 0x1000) +/* EMAC_SAIRC : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: This field controls the source address insertion or replacement + for all transmitted frames.Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. 2'b10: If Bit[30] is set to 0 the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted frames. 2'b11: If Bit[30] is set to 0 the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames.*/ +#define EMAC_SAIRC 0x00000007 +#define EMAC_SAIRC_M ((EMAC_SAIRC_V)<<(EMAC_SAIRC_S)) +#define EMAC_SAIRC_V 0x7 +#define EMAC_SAIRC_S 28 +/* EMAC_ASS2KP : R/W ;bitpos:[27] ;default: 1'h0 ; */ +/*description: When set the MAC considers all frames with up to 2 000 bytes + length as normal packets.When Bit[20] (JE) is not set the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set setting this bit has no effect on Giant Frame status.*/ +#define EMAC_ASS2KP (BIT(27)) +#define EMAC_ASS2KP_M (BIT(27)) +#define EMAC_ASS2KP_V 0x1 +#define EMAC_ASS2KP_S 27 +/* EMAC_EMACWATCHDOG : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC disables the watchdog timer on + the receiver. The MAC can receive frames of up to 16 383 bytes. When this bit is reset the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is set high) or the value programmed in Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes.*/ +#define EMAC_EMACWATCHDOG (BIT(23)) +#define EMAC_EMACWATCHDOG_M (BIT(23)) +#define EMAC_EMACWATCHDOG_V 0x1 +#define EMAC_EMACWATCHDOG_S 23 +/* EMAC_EMACJABBER : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC disables the jabber timer on the + transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data (10 240 if JE is set high) during Transmission.*/ +#define EMAC_EMACJABBER (BIT(22)) +#define EMAC_EMACJABBER_M (BIT(22)) +#define EMAC_EMACJABBER_V 0x1 +#define EMAC_EMACJABBER_S 22 +/* EMAC_EMACJUMBOFRAME : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC allows Jumbo frames of 9 018 bytes + (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.*/ +#define EMAC_EMACJUMBOFRAME (BIT(20)) +#define EMAC_EMACJUMBOFRAME_M (BIT(20)) +#define EMAC_EMACJUMBOFRAME_V 0x1 +#define EMAC_EMACJUMBOFRAME_S 20 +/* EMAC_EMACINTERFRAMEGAP : R/W ;bitpos:[19:17] ;default: 1'h0 ; */ +/*description: These bits control the minimum IFG between frames during transmission. + 3'b000: 96 bit times. 3'b001: 88 bit times. 3'b010: 80 bit times. 3'b111: 40 bit times. In the half-duplex mode the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered.*/ +#define EMAC_EMACINTERFRAMEGAP 0x00000007 +#define EMAC_EMACINTERFRAMEGAP_M ((EMAC_EMACINTERFRAMEGAP_V)<<(EMAC_EMACINTERFRAMEGAP_S)) +#define EMAC_EMACINTERFRAMEGAP_V 0x7 +#define EMAC_EMACINTERFRAMEGAP_S 17 +/* EMAC_EMACDISABLECRS : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: When set high this bit makes the MAC transmitter ignore the + MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions.*/ +#define EMAC_EMACDISABLECRS (BIT(16)) +#define EMAC_EMACDISABLECRS_M (BIT(16)) +#define EMAC_EMACDISABLECRS_V 0x1 +#define EMAC_EMACDISABLECRS_S 16 +/* EMAC_EMACMII : R/W ;bitpos:[15] ;default: 1'h0 ; */ +/*description: This bit selects the Ethernet line speed. It should be set to + 1 for 10 or 100 Mbps operations.In 10 or 100 Mbps operations this bit along with FES(EMACFESPEED) bit it selects the exact linespeed. In the 10/100 Mbps-only operations the bit is always 1.*/ +#define EMAC_EMACMII (BIT(15)) +#define EMAC_EMACMII_M (BIT(15)) +#define EMAC_EMACMII_V 0x1 +#define EMAC_EMACMII_S 15 +/* EMAC_EMACFESPEED : R/W ;bitpos:[14] ;default: 1'h0 ; */ +/*description: This bit selects the speed in the MII RMII interface. 0: 10 Mbps. 1: 100 Mbps.*/ +#define EMAC_EMACFESPEED (BIT(14)) +#define EMAC_EMACFESPEED_M (BIT(14)) +#define EMAC_EMACFESPEED_V 0x1 +#define EMAC_EMACFESPEED_S 14 +/* EMAC_EMACRXOWN : R/W ;bitpos:[13] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC disables the reception of frames + when the TX_EN is asserted in the half-duplex mode. When this bit is reset the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full duplex mode.*/ +#define EMAC_EMACRXOWN (BIT(13)) +#define EMAC_EMACRXOWN_M (BIT(13)) +#define EMAC_EMACRXOWN_V 0x1 +#define EMAC_EMACRXOWN_S 13 +/* EMAC_EMACLOOPBACK : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC operates in the loopback mode MII. + The MII Receive clock input (CLK_RX) is required for the loopback to work properly because the transmit clock is not looped-back internally.*/ +#define EMAC_EMACLOOPBACK (BIT(12)) +#define EMAC_EMACLOOPBACK_M (BIT(12)) +#define EMAC_EMACLOOPBACK_V 0x1 +#define EMAC_EMACLOOPBACK_S 12 +/* EMAC_EMACDUPLEX : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC operates in the full-duplex mode + where it can transmit and receive simultaneously. This bit is read only with default value of 1'b1 in the full-duplex-mode.*/ +#define EMAC_EMACDUPLEX (BIT(11)) +#define EMAC_EMACDUPLEX_M (BIT(11)) +#define EMAC_EMACDUPLEX_V 0x1 +#define EMAC_EMACDUPLEX_S 11 +/* EMAC_EMACRXIPCOFFLOAD : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC calculates the 16-bit one's complement + of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset this function is disabled.*/ +#define EMAC_EMACRXIPCOFFLOAD (BIT(10)) +#define EMAC_EMACRXIPCOFFLOAD_M (BIT(10)) +#define EMAC_EMACRXIPCOFFLOAD_V 0x1 +#define EMAC_EMACRXIPCOFFLOAD_S 10 +/* EMAC_EMACRETRY : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC attempts only one transmission. + When a collision occurs on the MII interface the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex Mode.*/ +#define EMAC_EMACRETRY (BIT(9)) +#define EMAC_EMACRETRY_M (BIT(9)) +#define EMAC_EMACRETRY_V 0x1 +#define EMAC_EMACRETRY_S 9 +/* EMAC_EMACPADCRCSTRIP : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC strips the Pad or FCS field on + the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset the MAC passes all incoming frames without modifying them to the Host.*/ +#define EMAC_EMACPADCRCSTRIP (BIT(7)) +#define EMAC_EMACPADCRCSTRIP_M (BIT(7)) +#define EMAC_EMACPADCRCSTRIP_V 0x1 +#define EMAC_EMACPADCRCSTRIP_S 7 +/* EMAC_EMACBACKOFFLIMIT : R/W ;bitpos:[6:5] ;default: 2'h0 ; */ +/*description: The Back-Off limit determines the random integer number (r) of + slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode. 00: k= min (n 10). 01: k = min (n 8). 10: k = min (n 4). 11: k = min (n 1) n = retransmission attempt. The random integer r takes the value in the Range 0 ~ 2000.*/ +#define EMAC_EMACBACKOFFLIMIT 0x00000003 +#define EMAC_EMACBACKOFFLIMIT_M ((EMAC_EMACBACKOFFLIMIT_V)<<(EMAC_EMACBACKOFFLIMIT_S)) +#define EMAC_EMACBACKOFFLIMIT_V 0x3 +#define EMAC_EMACBACKOFFLIMIT_S 5 +/* EMAC_EMACDEFERRALCHECK : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: Deferral Check.*/ +#define EMAC_EMACDEFERRALCHECK (BIT(4)) +#define EMAC_EMACDEFERRALCHECK_M (BIT(4)) +#define EMAC_EMACDEFERRALCHECK_V 0x1 +#define EMAC_EMACDEFERRALCHECK_S 4 +/* EMAC_EMACTX : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: When this bit is set the transmit state machine of the MAC is + enabled for transmission on the MII. When this bit is reset the MAC transmit state machine is disabled after the completion of the transmission of the current frame and does not transmit any further frames.*/ +#define EMAC_EMACTX (BIT(3)) +#define EMAC_EMACTX_M (BIT(3)) +#define EMAC_EMACTX_V 0x1 +#define EMAC_EMACTX_S 3 +/* EMAC_EMACRX : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: When this bit is set the receiver state machine of the MAC is + enabled for receiving frames from the MII. When this bit is reset the MAC receive state machine is disabled after the completion of the reception of the current frame and does not receive any further frames from the MII.*/ +#define EMAC_EMACRX (BIT(2)) +#define EMAC_EMACRX_M (BIT(2)) +#define EMAC_EMACRX_V 0x1 +#define EMAC_EMACRX_S 2 +/* EMAC_PLTF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: These bits control the number of preamble bytes that are added + to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/ +#define EMAC_PLTF 0x00000003 +#define EMAC_PLTF_M ((EMAC_PLTF_V)<<(EMAC_PLTF_S)) +#define EMAC_PLTF_V 0x3 +#define EMAC_PLTF_S 0 + +#define EMAC_GMACFF_REG (DR_REG_EMAC_BASE + 0x1004) +/* EMAC_RECEIVE_ALL : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC Receiver module passes all received + frames irrespective of whether they pass the address filter or not to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter.*/ +#define EMAC_RECEIVE_ALL (BIT(31)) +#define EMAC_RECEIVE_ALL_M (BIT(31)) +#define EMAC_RECEIVE_ALL_V 0x1 +#define EMAC_RECEIVE_ALL_S 31 +/* EMAC_SAFE : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC compares the SA field of the received + frames with the values programmed in the enabled SA registers. If the comparison fails the MAC drops the frame. When this bit is reset the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison.*/ +#define EMAC_SAFE (BIT(9)) +#define EMAC_SAFE_M (BIT(9)) +#define EMAC_SAFE_V 0x1 +#define EMAC_SAFE_S 9 +/* EMAC_SAIF : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: When this bit is set the Address Check block operates in inverse + filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset frames whose SA does not match the SA registers are marked as failing the SA Address filter.*/ +#define EMAC_SAIF (BIT(8)) +#define EMAC_SAIF_M (BIT(8)) +#define EMAC_SAIF_V 0x1 +#define EMAC_SAIF_S 8 +/* EMAC_PCF : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: These bits control the forwarding of all control frames (including + unicast and multicast Pause frames). 2'b00: MAC filters all control frames from reaching the application. 2'b01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. 2'b10: MAC forwards all control frames to application even if they fail the Address Filter. 2'b11: MAC forwards control frames that pass the Address Filter.The following conditions should be true for the Pause frames processing: Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register (Flow Control Register) to 1. Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set. Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.*/ +#define EMAC_PCF 0x00000003 +#define EMAC_PCF_M ((EMAC_PCF_V)<<(EMAC_PCF_S)) +#define EMAC_PCF_V 0x3 +#define EMAC_PCF_S 6 +/* EMAC_DBF : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: When this bit is set the AFM(Address Filtering Module) module + blocks all incoming broadcast frames. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast Frames.*/ +#define EMAC_DBF (BIT(5)) +#define EMAC_DBF_M (BIT(5)) +#define EMAC_DBF_V 0x1 +#define EMAC_DBF_S 5 +/* EMAC_PAM : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: When set this bit indicates that all received frames with a + multicast destination address (first bit in the destination address field is '1') are passed.*/ +#define EMAC_PAM (BIT(4)) +#define EMAC_PAM_M (BIT(4)) +#define EMAC_PAM_V 0x1 +#define EMAC_PAM_S 4 +/* EMAC_DAIF : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: When this bit is set the Address Check block operates in inverse + filtering mode for the DA address comparison for both unicast and multicast frames. When reset normal filtering of frames is performed.*/ +#define EMAC_DAIF (BIT(3)) +#define EMAC_DAIF_M (BIT(3)) +#define EMAC_DAIF_V 0x1 +#define EMAC_DAIF_S 3 +/* EMAC_PMODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When this bit is set the Address Filter module passes all incoming + frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set.*/ +#define EMAC_PMODE (BIT(0)) +#define EMAC_PMODE_M (BIT(0)) +#define EMAC_PMODE_V 0x1 +#define EMAC_PMODE_S 0 + +#define EMAC_GMIIADDR_REG (DR_REG_EMAC_BASE + 0x1010) +/* EMAC_MIIDEV : R/W ;bitpos:[15:11] ;default: 6'h0 ; */ +/*description: This field indicates which of the 32 possible PHY devices are being accessed.*/ +#define EMAC_MIIDEV 0x0000001F +#define EMAC_MIIDEV_M ((EMAC_MIIDEV_V)<<(EMAC_MIIDEV_S)) +#define EMAC_MIIDEV_V 0x1F +#define EMAC_MIIDEV_S 11 +/* EMAC_MIIREG : R/W ;bitpos:[10:6] ;default: 5'h0 ; */ +/*description: These bits select the desired MII register in the selected PHY device.*/ +#define EMAC_MIIREG 0x0000001F +#define EMAC_MIIREG_M ((EMAC_MIIREG_V)<<(EMAC_MIIREG_S)) +#define EMAC_MIIREG_V 0x1F +#define EMAC_MIIREG_S 6 +/* EMAC_MIICSRCLK : R/W ;bitpos:[5:2] ;default: 5'h0 ; */ +/*description: CSR clock range: 1.0 MHz ~ 2.5 MHz. 4'b0000: When the APB clock + frequency is 80 MHz the MDC clock frequency is APB CLK/42 4'b0000: When the APB clock frequency is 40 MHz the MDC clock frequency is APB CLK/26.*/ +#define EMAC_MIICSRCLK 0x0000000F +#define EMAC_MIICSRCLK_M ((EMAC_MIICSRCLK_V)<<(EMAC_MIICSRCLK_S)) +#define EMAC_MIICSRCLK_V 0xF +#define EMAC_MIICSRCLK_S 2 +/* EMAC_MIIWRITE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: When set this bit indicates to the PHY that this is a Write + operation using the MII Data register. If this bit is not set it indicates that this is a Read operation that is placing the data in the MII Data register.*/ +#define EMAC_MIIWRITE (BIT(1)) +#define EMAC_MIIWRITE_M (BIT(1)) +#define EMAC_MIIWRITE_V 0x1 +#define EMAC_MIIWRITE_S 1 +/* EMAC_MIIBUSY : R_WS_SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit should read logic 0 before writing to PHY Addr Register + and PHY data Register.During a PHY register access the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present.*/ +#define EMAC_MIIBUSY (BIT(0)) +#define EMAC_MIIBUSY_M (BIT(0)) +#define EMAC_MIIBUSY_V 0x1 +#define EMAC_MIIBUSY_S 0 + +#define EMAC_MIIDATA_REG (DR_REG_EMAC_BASE + 0x1014) +/* EMAC_MII_DATA : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This field contains the 16-bit data value read from the PHY after + a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation.*/ +#define EMAC_MII_DATA 0x0000FFFF +#define EMAC_MII_DATA_M ((EMAC_MII_DATA_V)<<(EMAC_MII_DATA_S)) +#define EMAC_MII_DATA_V 0xFFFF +#define EMAC_MII_DATA_S 0 + +#define EMAC_GMACFC_REG (DR_REG_EMAC_BASE + 0x1018) +/* EMAC_PAUSE_TIME : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: This field holds the value to be used in the Pause Time field + in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.*/ +#define EMAC_PAUSE_TIME 0x0000FFFF +#define EMAC_PAUSE_TIME_M ((EMAC_PAUSE_TIME_V)<<(EMAC_PAUSE_TIME_S)) +#define EMAC_PAUSE_TIME_V 0xFFFF +#define EMAC_PAUSE_TIME_S 16 +/* EMAC_DZPQ : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: When this bit is set it disables the automatic generation of + the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset normal operation with automatic Zero-Quanta Pause frame generation is enabled.*/ +#define EMAC_DZPQ (BIT(7)) +#define EMAC_DZPQ_M (BIT(7)) +#define EMAC_DZPQ_V 0x1 +#define EMAC_DZPQ_S 7 +/* EMAC_PLT : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: This field configures the threshold of the Pause timer automatic + retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example if PT = 100H (256 slot-times) and PLT = 01 then a second Pause frame is automatically transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: 2'b00: The threshold is Pause time minus 4 slot times (PT-4 slot times). 2'b01: The threshold is Pause time minus 28 slot times (PT-28 slot times). 2'b10: The threshold is Pause time minus 144 slot times (PT-144 slot times). 2'b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface.*/ +#define EMAC_PLT 0x00000003 +#define EMAC_PLT_M ((EMAC_PLT_V)<<(EMAC_PLT_S)) +#define EMAC_PLT_V 0x3 +#define EMAC_PLT_S 4 +/* EMAC_UPFD : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: A pause frame is processed when it has the unique multicast address + specified in the IEEE Std 802.3. When this bit is set the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the EMACADDR0 High Register and EMACADDR0 Low Register. When this bit is reset the MAC only detects Pause frames with unique multicast address.*/ +#define EMAC_UPFD (BIT(3)) +#define EMAC_UPFD_M (BIT(3)) +#define EMAC_UPFD_V 0x1 +#define EMAC_UPFD_S 3 +/* EMAC_RFCE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: When this bit is set the MAC decodes the received Pause frame + and disables its transmitter for a specified (Pause) time. When this bit is reset the decode function of the Pause frame is disabled.*/ +#define EMAC_RFCE (BIT(2)) +#define EMAC_RFCE_M (BIT(2)) +#define EMAC_RFCE_V 0x1 +#define EMAC_RFCE_S 2 +/* EMAC_TFCE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: In the full-duplex mode when this bit is set the MAC enables + the flow control operation to transmit Pause frames. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode when this bit is set the MAC enables the backpressure operation. When this bit is reset the backpressure feature is Disabled.*/ +#define EMAC_TFCE (BIT(1)) +#define EMAC_TFCE_M (BIT(1)) +#define EMAC_TFCE_V 0x1 +#define EMAC_TFCE_S 1 +/* EMAC_FCBBA : R_WS_SC(FCB)/R_W(BPA) ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit initiates a Pause frame in the full-duplex mode and + activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame the Application must set this bit to 1'b1. During a transfer of the Control Frame this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode when this bit is set (and TFCE is set) then backpressure is asserted by the MAC. During backpressure when the MAC receives a new frame the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode the BPA(backpressure activate) is automatically disabled.*/ +#define EMAC_FCBBA (BIT(0)) +#define EMAC_FCBBA_M (BIT(0)) +#define EMAC_FCBBA_V 0x1 +#define EMAC_FCBBA_S 0 + +#define EMAC_DEBUG_REG (DR_REG_EMAC_BASE + 0x1024) +/* EMAC_MTLTSFFS : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: When high this bit indicates that the MTL TxStatus FIFO is full. + Therefore the MTL cannot accept any more frames for transmission.*/ +#define EMAC_MTLTSFFS (BIT(25)) +#define EMAC_MTLTSFFS_M (BIT(25)) +#define EMAC_MTLTSFFS_V 0x1 +#define EMAC_MTLTSFFS_S 25 +/* EMAC_MTLTFNES : RO ;bitpos:[24] ;default: 1'h0 ; */ +/*description: When high this bit indicates that the MTL Tx FIFO is not empty + and some data is left for Transmission.*/ +#define EMAC_MTLTFNES (BIT(24)) +#define EMAC_MTLTFNES_M (BIT(24)) +#define EMAC_MTLTFNES_V 0x1 +#define EMAC_MTLTFNES_S 24 +/* EMAC_MTLTFWCS : RO ;bitpos:[22] ;default: 1'h0 ; */ +/*description: When high this bit indicates that the MTL Tx FIFO Write Controller + is active and is transferring data to the Tx FIFO.*/ +#define EMAC_MTLTFWCS (BIT(22)) +#define EMAC_MTLTFWCS_M (BIT(22)) +#define EMAC_MTLTFWCS_V 0x1 +#define EMAC_MTLTFWCS_S 22 +/* EMAC_MTLTFRCS : RO ;bitpos:[21:20] ;default: 2'h0 ; */ +/*description: This field indicates the state of the Tx FIFO Read Controller: + 2'b00: IDLE state. 2'b01: READ state (transferring data to the MAC transmitter). 2'b10: Waiting for TxStatus from the MAC transmitter. 2'b11: Writing the received TxStatus or flushing the Tx FIFO.*/ +#define EMAC_MTLTFRCS 0x00000003 +#define EMAC_MTLTFRCS_M ((EMAC_MTLTFRCS_V)<<(EMAC_MTLTFRCS_S)) +#define EMAC_MTLTFRCS_V 0x3 +#define EMAC_MTLTFRCS_S 20 +/* EMAC_MACTP : RO ;bitpos:[19] ;default: 1'h0 ; */ +/*description: When high this bit indicates that the MAC transmitter is in + the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission.*/ +#define EMAC_MACTP (BIT(19)) +#define EMAC_MACTP_M (BIT(19)) +#define EMAC_MACTP_V 0x1 +#define EMAC_MACTP_S 19 +/* EMAC_MACTFCS : RO ;bitpos:[18:17] ;default: 2'h0 ; */ +/*description: This field indicates the state of the MAC Transmit Frame Controller + module: 2'b00: IDLE state. 2'b01: Waiting for status of previous frame or IFG or backoff period to be over. 2'b10: Generating and transmitting a Pause frame (in the full-duplex mode). 2'b11: Transferring input frame for transmission.*/ +#define EMAC_MACTFCS 0x00000003 +#define EMAC_MACTFCS_M ((EMAC_MACTFCS_V)<<(EMAC_MACTFCS_S)) +#define EMAC_MACTFCS_V 0x3 +#define EMAC_MACTFCS_S 17 +/* EMAC_MACTPES : RO ;bitpos:[16] ;default: 1'h0 ; */ +/*description: When high this bit indicates that the MAC MII transmit protocol + engine is actively transmitting data and is not in the IDLE state.*/ +#define EMAC_MACTPES (BIT(16)) +#define EMAC_MACTPES_M (BIT(16)) +#define EMAC_MACTPES_V 0x1 +#define EMAC_MACTPES_S 16 +/* EMAC_MTLRFFLS : RO ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: This field gives the status of the fill-level of the Rx FIFO: + 2'b00: Rx FIFO Empty. 2'b01: Rx FIFO fill-level below flow-control deactivate threshold. 2'b10: Rx FIFO fill-level above flow-control activate threshold. 2'b11: Rx FIFO Full.*/ +#define EMAC_MTLRFFLS 0x00000003 +#define EMAC_MTLRFFLS_M ((EMAC_MTLRFFLS_V)<<(EMAC_MTLRFFLS_S)) +#define EMAC_MTLRFFLS_V 0x3 +#define EMAC_MTLRFFLS_S 8 +/* EMAC_MTLRFRCS : RO ;bitpos:[6:5] ;default: 2'h0 ; */ +/*description: This field gives the state of the Rx FIFO read Controller: 2'b00: + IDLE state.2'b01: Reading frame data.2'b10: Reading frame status (or timestamp).2'b11: Flushing the frame data and status.*/ +#define EMAC_MTLRFRCS 0x00000003 +#define EMAC_MTLRFRCS_M ((EMAC_MTLRFRCS_V)<<(EMAC_MTLRFRCS_S)) +#define EMAC_MTLRFRCS_V 0x3 +#define EMAC_MTLRFRCS_S 5 +/* EMAC_MTLRFWCAS : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: When high this bit indicates that the MTL Rx FIFO Write Controller + is active and is transferring a received frame to the FIFO.*/ +#define EMAC_MTLRFWCAS (BIT(4)) +#define EMAC_MTLRFWCAS_M (BIT(4)) +#define EMAC_MTLRFWCAS_V 0x1 +#define EMAC_MTLRFWCAS_S 4 +/* EMAC_MACRFFCS : RO ;bitpos:[2:1] ;default: 2'h0 ; */ +/*description: When high this field indicates the active state of the FIFO + Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller.*/ +#define EMAC_MACRFFCS 0x00000003 +#define EMAC_MACRFFCS_M ((EMAC_MACRFFCS_V)<<(EMAC_MACRFFCS_S)) +#define EMAC_MACRFFCS_V 0x3 +#define EMAC_MACRFFCS_S 1 +/* EMAC_MACRPES : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When high this bit indicates that the MAC MII receive protocol + engine is actively receiving data and not in IDLE state.*/ +#define EMAC_MACRPES (BIT(0)) +#define EMAC_MACRPES_M (BIT(0)) +#define EMAC_MACRPES_V 0x1 +#define EMAC_MACRPES_S 0 + +#define EMAC_PMT_RWUFFR_REG (DR_REG_EMAC_BASE + 0x1028) +/* EMAC_WKUPPKTFILTER : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The MSB (31st bit) must be zero.Bit j[30:0] is the byte mask. + If Bit 1/2/3/4 (byte number) of the byte mask is set the CRC block processes the Filter 0/1/2/3 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type defining the destination address type of the pattern.When the bit is set the pattern applies to only multicast packets*/ +#define EMAC_WKUPPKTFILTER 0xFFFFFFFF +#define EMAC_WKUPPKTFILTER_M ((EMAC_WKUPPKTFILTER_V)<<(EMAC_WKUPPKTFILTER_S)) +#define EMAC_WKUPPKTFILTER_V 0xFFFFFFFF +#define EMAC_WKUPPKTFILTER_S 0 + +#define EMAC_PMT_CSR_REG (DR_REG_EMAC_BASE + 0x102C) +/* EMAC_RWKFILTRST : R_WS_SC ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When this bit is set it resets the RWKPTR register to 3’b000.*/ +#define EMAC_RWKFILTRST (BIT(31)) +#define EMAC_RWKFILTRST_M (BIT(31)) +#define EMAC_RWKFILTRST_V 0x1 +#define EMAC_RWKFILTRST_S 31 +/* EMAC_RWKPTR : RO ;bitpos:[28:24] ;default: 6'h0 ; */ +/*description: The maximum value of the pointer is 7 the detail information + please refer to PMT_RWUFFR.*/ +#define EMAC_RWKPTR 0x0000001F +#define EMAC_RWKPTR_M ((EMAC_RWKPTR_V)<<(EMAC_RWKPTR_S)) +#define EMAC_RWKPTR_V 0x1F +#define EMAC_RWKPTR_S 24 +/* EMAC_GLBLUCAST : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: When set enables any unicast packet filtered by the MAC (DAFilter) + address recognition to be a remote wake-up frame.*/ +#define EMAC_GLBLUCAST (BIT(9)) +#define EMAC_GLBLUCAST_M (BIT(9)) +#define EMAC_GLBLUCAST_V 0x1 +#define EMAC_GLBLUCAST_S 9 +/* EMAC_RWKPRCVD : R_SS_RC ;bitpos:[6] ;default: 1'h0 ; */ +/*description: When set this bit indicates the power management event is generated + because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register.*/ +#define EMAC_RWKPRCVD (BIT(6)) +#define EMAC_RWKPRCVD_M (BIT(6)) +#define EMAC_RWKPRCVD_V 0x1 +#define EMAC_RWKPRCVD_S 6 +/* EMAC_MGKPRCVD : R_SS_RC ;bitpos:[5] ;default: 1'h0 ; */ +/*description: When set this bit indicates that the power management event + is generated because of the reception of a magic packet. This bit is cleared by a Read into this register.*/ +#define EMAC_MGKPRCVD (BIT(5)) +#define EMAC_MGKPRCVD_M (BIT(5)) +#define EMAC_MGKPRCVD_V 0x1 +#define EMAC_MGKPRCVD_S 5 +/* EMAC_RWKPKTEN : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: When set enables generation of a power management event because + of remote wake-up frame reception*/ +#define EMAC_RWKPKTEN (BIT(2)) +#define EMAC_RWKPKTEN_M (BIT(2)) +#define EMAC_RWKPKTEN_V 0x1 +#define EMAC_RWKPKTEN_S 2 +/* EMAC_MGKPKTEN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: When set enables generation of a power management event because + of magic packet reception.*/ +#define EMAC_MGKPKTEN (BIT(1)) +#define EMAC_MGKPKTEN_M (BIT(1)) +#define EMAC_MGKPKTEN_V 0x1 +#define EMAC_MGKPKTEN_S 1 +/* EMAC_PWRDWN : R_WS_SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When set the MAC receiver drops all received frames until it + receives the expected magic packet or remote wake-up frame.This bit must only be set when MGKPKTEN GLBLUCAST or RWKPKTEN bit is set high.*/ +#define EMAC_PWRDWN (BIT(0)) +#define EMAC_PWRDWN_M (BIT(0)) +#define EMAC_PWRDWN_V 0x1 +#define EMAC_PWRDWN_S 0 + +#define EMAC_GMACLPI_CRS_REG (DR_REG_EMAC_BASE + 0x1030) +/* EMAC_LPITXA : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: This bit controls the behavior of the MAC when it is entering + or coming out of the LPI mode on the transmit side.If the LPITXA and LPIEN bits are set to 1 the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0 the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.*/ +#define EMAC_LPITXA (BIT(19)) +#define EMAC_LPITXA_M (BIT(19)) +#define EMAC_LPITXA_V 0x1 +#define EMAC_LPITXA_S 19 +/* EMAC_PLS : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: This bit indicates the link status of the PHY.When set the link + is considered to be okay (up) and when reset the link is considered to be down.*/ +#define EMAC_PLS (BIT(17)) +#define EMAC_PLS_M (BIT(17)) +#define EMAC_PLS_V 0x1 +#define EMAC_PLS_S 17 +/* EMAC_LPIEN : R_W_SC ;bitpos:[16] ;default: 1'h0 ; */ +/*description: When set this bit instructs the MAC Transmitter to enter the + LPI state. When reset this bit instructs the MAC to exit the LPI state and resume normal transmission.This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.*/ +#define EMAC_LPIEN (BIT(16)) +#define EMAC_LPIEN_M (BIT(16)) +#define EMAC_LPIEN_V 0x1 +#define EMAC_LPIEN_S 16 +/* EMAC_RLPIST : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: When set this bit indicates that the MAC is receiving the LPI + pattern on the MII interface.*/ +#define EMAC_RLPIST (BIT(9)) +#define EMAC_RLPIST_M (BIT(9)) +#define EMAC_RLPIST_V 0x1 +#define EMAC_RLPIST_S 9 +/* EMAC_TLPIST : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: When set this bit indicates that the MAC is transmitting the + LPI pattern on the MII interface.*/ +#define EMAC_TLPIST (BIT(8)) +#define EMAC_TLPIST_M (BIT(8)) +#define EMAC_TLPIST_V 0x1 +#define EMAC_TLPIST_S 8 +/* EMAC_RLPIEX : R_SS_RC ;bitpos:[3] ;default: 1'h0 ; */ +/*description: When set this bit indicates that the MAC Receiver has stopped + receiving the LPI pattern on the MII interface exited the LPI state and resumed the normal reception. This bit is cleared by a read into this register.*/ +#define EMAC_RLPIEX (BIT(3)) +#define EMAC_RLPIEX_M (BIT(3)) +#define EMAC_RLPIEX_V 0x1 +#define EMAC_RLPIEX_S 3 +/* EMAC_RLPIEN : R_SS_RC ;bitpos:[2] ;default: 1'h0 ; */ +/*description: When set this bit indicates that the MAC Receiver has received + an LPI pattern and entered the LPI state. This bit is cleared by a read into this register.*/ +#define EMAC_RLPIEN (BIT(2)) +#define EMAC_RLPIEN_M (BIT(2)) +#define EMAC_RLPIEN_V 0x1 +#define EMAC_RLPIEN_S 2 +/* EMAC_TLPIEX : R_SS_RC ;bitpos:[1] ;default: 1'h0 ; */ +/*description: When set this bit indicates that the MAC transmitter has exited + the LPI state after the user has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this register.*/ +#define EMAC_TLPIEX (BIT(1)) +#define EMAC_TLPIEX_M (BIT(1)) +#define EMAC_TLPIEX_V 0x1 +#define EMAC_TLPIEX_S 1 +/* EMAC_TLPIEN : R_SS_RC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When set this bit indicates that the MAC Transmitter has entered + the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.*/ +#define EMAC_TLPIEN (BIT(0)) +#define EMAC_TLPIEN_M (BIT(0)) +#define EMAC_TLPIEN_V 0x1 +#define EMAC_TLPIEN_S 0 + +#define EMAC_GMACLPITIMERSCONTROL_REG (DR_REG_EMAC_BASE + 0x1034) +/* EMAC_LPI_LS_TIMER : R/W ;bitpos:[25:16] ;default: 10'h3E8 ; */ +/*description: This field specifies the minimum time (in milliseconds) for which + the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard.*/ +#define EMAC_LPI_LS_TIMER 0x000003FF +#define EMAC_LPI_LS_TIMER_M ((EMAC_LPI_LS_TIMER_V)<<(EMAC_LPI_LS_TIMER_S)) +#define EMAC_LPI_LS_TIMER_V 0x3FF +#define EMAC_LPI_LS_TIMER_S 16 +/* EMAC_LPI_TW_TIMER : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This field specifies the minimum time (in microseconds) for which + the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.*/ +#define EMAC_LPI_TW_TIMER 0x0000FFFF +#define EMAC_LPI_TW_TIMER_M ((EMAC_LPI_TW_TIMER_V)<<(EMAC_LPI_TW_TIMER_S)) +#define EMAC_LPI_TW_TIMER_V 0xFFFF +#define EMAC_LPI_TW_TIMER_S 0 + +#define EMAC_INTS_REG (DR_REG_EMAC_BASE + 0x1038) +/* EMAC_LPIIS : RO ;bitpos:[10] ;default: 1'h0 ; */ +/*description: When the Energy Efficient Ethernet feature is enabled this bit + is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register).*/ +#define EMAC_LPIIS (BIT(10)) +#define EMAC_LPIIS_M (BIT(10)) +#define EMAC_LPIIS_V 0x1 +#define EMAC_LPIIS_S 10 +/* EMAC_PMTINTS : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: This bit is set when a magic packet or remote wake-up frame is + received in the power-down mode (see Bit[5] and Bit[6] in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit is valid only when you select the optional PMT module during core configuration.*/ +#define EMAC_PMTINTS (BIT(3)) +#define EMAC_PMTINTS_M (BIT(3)) +#define EMAC_PMTINTS_V 0x1 +#define EMAC_PMTINTS_S 3 + +#define EMAC_INTMASK_REG (DR_REG_EMAC_BASE + 0x103C) +/* EMAC_LPIINTMASK : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: When set this bit disables the assertion of the interrupt signal + because of the setting of the LPI Interrupt Status bit in Register (Interrupt Status Register).*/ +#define EMAC_LPIINTMASK (BIT(10)) +#define EMAC_LPIINTMASK_M (BIT(10)) +#define EMAC_LPIINTMASK_V 0x1 +#define EMAC_LPIINTMASK_S 10 +/* EMAC_PMTINTMASK : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: When set this bit disables the assertion of the interrupt signal + because of the setting of PMT Interrupt Status bit in Register (Interrupt Status Register).*/ +#define EMAC_PMTINTMASK (BIT(3)) +#define EMAC_PMTINTMASK_M (BIT(3)) +#define EMAC_PMTINTMASK_V 0x1 +#define EMAC_PMTINTMASK_S 3 + +#define EMAC_ADDR0HIGH_REG (DR_REG_EMAC_BASE + 0x1040) +/* EMAC_ADDRESS_ENABLE0 : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: This bit is always set to 1.*/ +#define EMAC_ADDRESS_ENABLE0 (BIT(31)) +#define EMAC_ADDRESS_ENABLE0_M (BIT(31)) +#define EMAC_ADDRESS_ENABLE0_V 0x1 +#define EMAC_ADDRESS_ENABLE0_S 31 +/* EMAC_ADDRESS0_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */ +/*description: This field contains the upper 16 bits (47:32) of the first 6-byte + MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/ +#define EMAC_ADDRESS0_HI 0x0000FFFF +#define EMAC_ADDRESS0_HI_M ((EMAC_ADDRESS0_HI_V)<<(EMAC_ADDRESS0_HI_S)) +#define EMAC_ADDRESS0_HI_V 0xFFFF +#define EMAC_ADDRESS0_HI_S 0 + +#define EMAC_ADDR0LOW_REG (DR_REG_EMAC_BASE + 0x1044) +/* EMAC_MAC_ADDRESS0_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */ +/*description: This field contains the lower 32 bits of the first 6-byte MAC + address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/ +#define EMAC_MAC_ADDRESS0_LOW 0xFFFFFFFF +#define EMAC_MAC_ADDRESS0_LOW_M ((EMAC_MAC_ADDRESS0_LOW_V)<<(EMAC_MAC_ADDRESS0_LOW_S)) +#define EMAC_MAC_ADDRESS0_LOW_V 0xFFFFFFFF +#define EMAC_MAC_ADDRESS0_LOW_S 0 + +#define EMAC_ADDR1HIGH_REG (DR_REG_EMAC_BASE + 0x1048) +/* EMAC_ADDRESS_ENABLE1 : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When this bit is set the address filter module uses the second + MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/ +#define EMAC_ADDRESS_ENABLE1 (BIT(31)) +#define EMAC_ADDRESS_ENABLE1_M (BIT(31)) +#define EMAC_ADDRESS_ENABLE1_V 0x1 +#define EMAC_ADDRESS_ENABLE1_S 31 +/* EMAC_SOURCE_ADDRESS : R/W ;bitpos:[30] ;default: 1'h0 ; */ +/*description: When this bit is set the EMACADDR1[47:0] is used to compare + with the SA fields of the received frame. When this bit is reset the EMACADDR1[47:0] is used to compare with the DA fields of the received frame.*/ +#define EMAC_SOURCE_ADDRESS (BIT(30)) +#define EMAC_SOURCE_ADDRESS_M (BIT(30)) +#define EMAC_SOURCE_ADDRESS_V 0x1 +#define EMAC_SOURCE_ADDRESS_S 30 +/* EMAC_MASK_BYTE_CONTROL : R/W ;bitpos:[29:24] ;default: 6'h0 ; */ +/*description: These bits are mask control bits for comparison of each of the + EMACADDR1 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR1 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR1 High [15:8]. Bit[28]: EMACADDR1 High [7:0]. Bit[27]: EMACADDR1 Low [31:24]. Bit[24]: EMACADDR1 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/ +#define EMAC_MASK_BYTE_CONTROL 0x0000003F +#define EMAC_MASK_BYTE_CONTROL_M ((EMAC_MASK_BYTE_CONTROL_V)<<(EMAC_MASK_BYTE_CONTROL_S)) +#define EMAC_MASK_BYTE_CONTROL_V 0x3F +#define EMAC_MASK_BYTE_CONTROL_S 24 +/* EMAC_MAC_ADDRESS1_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */ +/*description: This field contains the upper 16 bits Bits[47:32] of the second + 6-byte MAC Address.*/ +#define EMAC_MAC_ADDRESS1_HI 0x0000FFFF +#define EMAC_MAC_ADDRESS1_HI_M ((EMAC_MAC_ADDRESS1_HI_V)<<(EMAC_MAC_ADDRESS1_HI_S)) +#define EMAC_MAC_ADDRESS1_HI_V 0xFFFF +#define EMAC_MAC_ADDRESS1_HI_S 0 + +#define EMAC_ADDR1LOW_REG (DR_REG_EMAC_BASE + 0x104C) +/* EMAC_MAC_ADDRESS1_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */ +/*description: This field contains the lower 32 bits of the second 6-byte MAC + address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/ +#define EMAC_MAC_ADDRESS1_LOW 0xFFFFFFFF +#define EMAC_MAC_ADDRESS1_LOW_M ((EMAC_MAC_ADDRESS1_LOW_V)<<(EMAC_MAC_ADDRESS1_LOW_S)) +#define EMAC_MAC_ADDRESS1_LOW_V 0xFFFFFFFF +#define EMAC_MAC_ADDRESS1_LOW_S 0 + +#define EMAC_ADDR2HIGH_REG (DR_REG_EMAC_BASE + 0x1050) +/* EMAC_ADDRESS_ENABLE2 : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When this bit is set the address filter module uses the third + MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/ +#define EMAC_ADDRESS_ENABLE2 (BIT(31)) +#define EMAC_ADDRESS_ENABLE2_M (BIT(31)) +#define EMAC_ADDRESS_ENABLE2_V 0x1 +#define EMAC_ADDRESS_ENABLE2_S 31 +/* EMAC_SOURCE_ADDRESS2 : R/W ;bitpos:[30] ;default: 1'h0 ; */ +/*description: When this bit is set the EMACADDR2[47:0] is used to compare + with the SA fields of the received frame. When this bit is reset the EMACADDR2[47:0] is used to compare with the DA fields of the received frame.*/ +#define EMAC_SOURCE_ADDRESS2 (BIT(30)) +#define EMAC_SOURCE_ADDRESS2_M (BIT(30)) +#define EMAC_SOURCE_ADDRESS2_V 0x1 +#define EMAC_SOURCE_ADDRESS2_S 30 +/* EMAC_MASK_BYTE_CONTROL2 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */ +/*description: These bits are mask control bits for comparison of each of the + EMACADDR2 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR2 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR2 High [15:8]. Bit[28]: EMACADDR2 High [7:0]. Bit[27]: EMACADDR2 Low [31:24]. Bit[24]: EMACADDR2 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/ +#define EMAC_MASK_BYTE_CONTROL2 0x0000003F +#define EMAC_MASK_BYTE_CONTROL2_M ((EMAC_MASK_BYTE_CONTROL2_V)<<(EMAC_MASK_BYTE_CONTROL2_S)) +#define EMAC_MASK_BYTE_CONTROL2_V 0x3F +#define EMAC_MASK_BYTE_CONTROL2_S 24 +/* EMAC_MAC_ADDRESS2_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */ +/*description: This field contains the upper 16 bits Bits[47:32] of the third + 6-byte MAC address.*/ +#define EMAC_MAC_ADDRESS2_HI 0x0000FFFF +#define EMAC_MAC_ADDRESS2_HI_M ((EMAC_MAC_ADDRESS2_HI_V)<<(EMAC_MAC_ADDRESS2_HI_S)) +#define EMAC_MAC_ADDRESS2_HI_V 0xFFFF +#define EMAC_MAC_ADDRESS2_HI_S 0 + +#define EMAC_ADDR2LOW_REG (DR_REG_EMAC_BASE + 0x1054) +/* EMAC_MAC_ADDRESS2_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */ +/*description: This field contains the lower 32 bits of the third 6-byte MAC + address. The content of this field is undefined so the register needs to be configured after the initialization process.*/ +#define EMAC_MAC_ADDRESS2_LOW 0xFFFFFFFF +#define EMAC_MAC_ADDRESS2_LOW_M ((EMAC_MAC_ADDRESS2_LOW_V)<<(EMAC_MAC_ADDRESS2_LOW_S)) +#define EMAC_MAC_ADDRESS2_LOW_V 0xFFFFFFFF +#define EMAC_MAC_ADDRESS2_LOW_S 0 + +#define EMAC_ADDR3HIGH_REG (DR_REG_EMAC_BASE + 0x1058) +/* EMAC_ADDRESS_ENABLE3 : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When this bit is set the address filter module uses the fourth + MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/ +#define EMAC_ADDRESS_ENABLE3 (BIT(31)) +#define EMAC_ADDRESS_ENABLE3_M (BIT(31)) +#define EMAC_ADDRESS_ENABLE3_V 0x1 +#define EMAC_ADDRESS_ENABLE3_S 31 +/* EMAC_SOURCE_ADDRESS3 : R/W ;bitpos:[30] ;default: 1'h0 ; */ +/*description: When this bit is set the EMACADDR3[47:0] is used to compare + with the SA fields of the received frame. When this bit is reset the EMACADDR3[47:0] is used to compare with the DA fields of the received frame.*/ +#define EMAC_SOURCE_ADDRESS3 (BIT(30)) +#define EMAC_SOURCE_ADDRESS3_M (BIT(30)) +#define EMAC_SOURCE_ADDRESS3_V 0x1 +#define EMAC_SOURCE_ADDRESS3_S 30 +/* EMAC_MASK_BYTE_CONTROL3 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */ +/*description: These bits are mask control bits for comparison of each of the + EMACADDR3 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR3 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR3 High [15:8]. Bit[28]: EMACADDR3 High [7:0]. Bit[27]: EMACADDR3 Low [31:24]. Bit[24]: EMACADDR3 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/ +#define EMAC_MASK_BYTE_CONTROL3 0x0000003F +#define EMAC_MASK_BYTE_CONTROL3_M ((EMAC_MASK_BYTE_CONTROL3_V)<<(EMAC_MASK_BYTE_CONTROL3_S)) +#define EMAC_MASK_BYTE_CONTROL3_V 0x3F +#define EMAC_MASK_BYTE_CONTROL3_S 24 +/* EMAC_MAC_ADDRESS3_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */ +/*description: This field contains the upper 16 bits Bits[47:32] of the fourth + 6-byte MAC address.*/ +#define EMAC_MAC_ADDRESS3_HI 0x0000FFFF +#define EMAC_MAC_ADDRESS3_HI_M ((EMAC_MAC_ADDRESS3_HI_V)<<(EMAC_MAC_ADDRESS3_HI_S)) +#define EMAC_MAC_ADDRESS3_HI_V 0xFFFF +#define EMAC_MAC_ADDRESS3_HI_S 0 + +#define EMAC_ADDR3LOW_REG (DR_REG_EMAC_BASE + 0x105C) +/* EMAC_MAC_ADDRESS3_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */ +/*description: This field contains the lower 32 bits of the fourth 6-byte MAC + address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/ +#define EMAC_MAC_ADDRESS3_LOW 0xFFFFFFFF +#define EMAC_MAC_ADDRESS3_LOW_M ((EMAC_MAC_ADDRESS3_LOW_V)<<(EMAC_MAC_ADDRESS3_LOW_S)) +#define EMAC_MAC_ADDRESS3_LOW_V 0xFFFFFFFF +#define EMAC_MAC_ADDRESS3_LOW_S 0 + +#define EMAC_ADDR4HIGH_REG (DR_REG_EMAC_BASE + 0x1060) +/* EMAC_ADDRESS_ENABLE4 : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When this bit is set the address filter module uses the fifth + MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/ +#define EMAC_ADDRESS_ENABLE4 (BIT(31)) +#define EMAC_ADDRESS_ENABLE4_M (BIT(31)) +#define EMAC_ADDRESS_ENABLE4_V 0x1 +#define EMAC_ADDRESS_ENABLE4_S 31 +/* EMAC_SOURCE_ADDRESS4 : R/W ;bitpos:[30] ;default: 1'h0 ; */ +/*description: When this bit is set the EMACADDR4[47:0] is used to compare + with the SA fields of the received frame. When this bit is reset the EMACADDR4[47:0] is used to compare with the DA fields of the received frame.*/ +#define EMAC_SOURCE_ADDRESS4 (BIT(30)) +#define EMAC_SOURCE_ADDRESS4_M (BIT(30)) +#define EMAC_SOURCE_ADDRESS4_V 0x1 +#define EMAC_SOURCE_ADDRESS4_S 30 +/* EMAC_MASK_BYTE_CONTROL4 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */ +/*description: These bits are mask control bits for comparison of each of the + EMACADDR4 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR4 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR4 High [15:8]. Bit[28]: EMACADDR4 High [7:0]. Bit[27]: EMACADDR4 Low [31:24]. Bit[24]: EMACADDR4 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/ +#define EMAC_MASK_BYTE_CONTROL4 0x0000003F +#define EMAC_MASK_BYTE_CONTROL4_M ((EMAC_MASK_BYTE_CONTROL4_V)<<(EMAC_MASK_BYTE_CONTROL4_S)) +#define EMAC_MASK_BYTE_CONTROL4_V 0x3F +#define EMAC_MASK_BYTE_CONTROL4_S 24 +/* EMAC_MAC_ADDRESS4_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */ +/*description: This field contains the upper 16 bits Bits[47:32] of the fifth + 6-byte MAC address.*/ +#define EMAC_MAC_ADDRESS4_HI 0x0000FFFF +#define EMAC_MAC_ADDRESS4_HI_M ((EMAC_MAC_ADDRESS4_HI_V)<<(EMAC_MAC_ADDRESS4_HI_S)) +#define EMAC_MAC_ADDRESS4_HI_V 0xFFFF +#define EMAC_MAC_ADDRESS4_HI_S 0 + +#define EMAC_ADDR4LOW_REG (DR_REG_EMAC_BASE + 0x1064) +/* EMAC_MAC_ADDRESS4_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */ +/*description: This field contains the lower 32 bits of the fifth 6-byte MAC + address. The content of this field is undefined so the register needs to be configured after the initialization process.*/ +#define EMAC_MAC_ADDRESS4_LOW 0xFFFFFFFF +#define EMAC_MAC_ADDRESS4_LOW_M ((EMAC_MAC_ADDRESS4_LOW_V)<<(EMAC_MAC_ADDRESS4_LOW_S)) +#define EMAC_MAC_ADDRESS4_LOW_V 0xFFFFFFFF +#define EMAC_MAC_ADDRESS4_LOW_S 0 + +#define EMAC_ADDR5HIGH_REG (DR_REG_EMAC_BASE + 0x1068) +/* EMAC_ADDRESS_ENABLE5 : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When this bit is set the address filter module uses the sixth + MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/ +#define EMAC_ADDRESS_ENABLE5 (BIT(31)) +#define EMAC_ADDRESS_ENABLE5_M (BIT(31)) +#define EMAC_ADDRESS_ENABLE5_V 0x1 +#define EMAC_ADDRESS_ENABLE5_S 31 +/* EMAC_SOURCE_ADDRESS5 : R/W ;bitpos:[30] ;default: 1'h0 ; */ +/*description: When this bit is set the EMACADDR5[47:0] is used to compare + with the SA fields of the received frame. When this bit is reset the EMACADDR5[47:0] is used to compare with the DA fields of the received frame.*/ +#define EMAC_SOURCE_ADDRESS5 (BIT(30)) +#define EMAC_SOURCE_ADDRESS5_M (BIT(30)) +#define EMAC_SOURCE_ADDRESS5_V 0x1 +#define EMAC_SOURCE_ADDRESS5_S 30 +/* EMAC_MASK_BYTE_CONTROL5 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */ +/*description: These bits are mask control bits for comparison of each of the + EMACADDR5 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR5 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR5 High [15:8]. Bit[28]: EMACADDR5 High [7:0]. Bit[27]: EMACADDR5 Low [31:24]. Bit[24]: EMACADDR5 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/ +#define EMAC_MASK_BYTE_CONTROL5 0x0000003F +#define EMAC_MASK_BYTE_CONTROL5_M ((EMAC_MASK_BYTE_CONTROL5_V)<<(EMAC_MASK_BYTE_CONTROL5_S)) +#define EMAC_MASK_BYTE_CONTROL5_V 0x3F +#define EMAC_MASK_BYTE_CONTROL5_S 24 +/* EMAC_MAC_ADDRESS5_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */ +/*description: This field contains the upper 16 bits Bits[47:32] of the sixth + 6-byte MAC address.*/ +#define EMAC_MAC_ADDRESS5_HI 0x0000FFFF +#define EMAC_MAC_ADDRESS5_HI_M ((EMAC_MAC_ADDRESS5_HI_V)<<(EMAC_MAC_ADDRESS5_HI_S)) +#define EMAC_MAC_ADDRESS5_HI_V 0xFFFF +#define EMAC_MAC_ADDRESS5_HI_S 0 + +#define EMAC_ADDR5LOW_REG (DR_REG_EMAC_BASE + 0x106C) +/* EMAC_MAC_ADDRESS5_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */ +/*description: This field contains the lower 32 bits of the sixth 6-byte MAC + address. The content of this field is undefined so the register needs to be configured after the initialization process.*/ +#define EMAC_MAC_ADDRESS5_LOW 0xFFFFFFFF +#define EMAC_MAC_ADDRESS5_LOW_M ((EMAC_MAC_ADDRESS5_LOW_V)<<(EMAC_MAC_ADDRESS5_LOW_S)) +#define EMAC_MAC_ADDRESS5_LOW_V 0xFFFFFFFF +#define EMAC_MAC_ADDRESS5_LOW_S 0 + +#define EMAC_ADDR6HIGH_REG (DR_REG_EMAC_BASE + 0x1070) +/* EMAC_ADDRESS_ENABLE6 : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When this bit is set the address filter module uses the seventh + MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/ +#define EMAC_ADDRESS_ENABLE6 (BIT(31)) +#define EMAC_ADDRESS_ENABLE6_M (BIT(31)) +#define EMAC_ADDRESS_ENABLE6_V 0x1 +#define EMAC_ADDRESS_ENABLE6_S 31 +/* EMAC_SOURCE_ADDRESS6 : R/W ;bitpos:[30] ;default: 1'h0 ; */ +/*description: When this bit is set the EMACADDR6[47:0] is used to compare + with the SA fields of the received frame. When this bit is reset the EMACADDR6[47:0] is used to compare with the DA fields of the received frame.*/ +#define EMAC_SOURCE_ADDRESS6 (BIT(30)) +#define EMAC_SOURCE_ADDRESS6_M (BIT(30)) +#define EMAC_SOURCE_ADDRESS6_V 0x1 +#define EMAC_SOURCE_ADDRESS6_S 30 +/* EMAC_MASK_BYTE_CONTROL6 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */ +/*description: These bits are mask control bits for comparison of each of the + EMACADDR6 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR6 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR6 High [15:8]. Bit[28]: EMACADDR6 High [7:0]. Bit[27]: EMACADDR6 Low [31:24]. Bit[24]: EMACADDR6 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/ +#define EMAC_MASK_BYTE_CONTROL6 0x0000003F +#define EMAC_MASK_BYTE_CONTROL6_M ((EMAC_MASK_BYTE_CONTROL6_V)<<(EMAC_MASK_BYTE_CONTROL6_S)) +#define EMAC_MASK_BYTE_CONTROL6_V 0x3F +#define EMAC_MASK_BYTE_CONTROL6_S 24 +/* EMAC_MAC_ADDRESS6_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */ +/*description: This field contains the upper 16 bits Bits[47:32] of the seventh + 6-byte MAC Address.*/ +#define EMAC_MAC_ADDRESS6_HI 0x0000FFFF +#define EMAC_MAC_ADDRESS6_HI_M ((EMAC_MAC_ADDRESS6_HI_V)<<(EMAC_MAC_ADDRESS6_HI_S)) +#define EMAC_MAC_ADDRESS6_HI_V 0xFFFF +#define EMAC_MAC_ADDRESS6_HI_S 0 + +#define EMAC_ADDR6LOW_REG (DR_REG_EMAC_BASE + 0x1074) +/* EMAC_MAC_ADDRESS6_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */ +/*description: This field contains the lower 32 bits of the seventh 6-byte MAC + address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/ +#define EMAC_MAC_ADDRESS6_LOW 0xFFFFFFFF +#define EMAC_MAC_ADDRESS6_LOW_M ((EMAC_MAC_ADDRESS6_LOW_V)<<(EMAC_MAC_ADDRESS6_LOW_S)) +#define EMAC_MAC_ADDRESS6_LOW_V 0xFFFFFFFF +#define EMAC_MAC_ADDRESS6_LOW_S 0 + +#define EMAC_ADDR7HIGH_REG (DR_REG_EMAC_BASE + 0x1078) +/* EMAC_ADDRESS_ENABLE7 : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When this bit is set the address filter module uses the eighth + MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/ +#define EMAC_ADDRESS_ENABLE7 (BIT(31)) +#define EMAC_ADDRESS_ENABLE7_M (BIT(31)) +#define EMAC_ADDRESS_ENABLE7_V 0x1 +#define EMAC_ADDRESS_ENABLE7_S 31 +/* EMAC_SOURCE_ADDRESS7 : R/W ;bitpos:[30] ;default: 1'h0 ; */ +/*description: When this bit is set the EMACADDR7[47:0] is used to compare + with the SA fields of the received frame. When this bit is reset the EMACADDR7[47:0] is used to compare with the DA fields of the received frame.*/ +#define EMAC_SOURCE_ADDRESS7 (BIT(30)) +#define EMAC_SOURCE_ADDRESS7_M (BIT(30)) +#define EMAC_SOURCE_ADDRESS7_V 0x1 +#define EMAC_SOURCE_ADDRESS7_S 30 +/* EMAC_MASK_BYTE_CONTROL7 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */ +/*description: These bits are mask control bits for comparison of each of the + EMACADDR7 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR7 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR7 High [15:8]. Bit[28]: EMACADDR7 High [7:0]. Bit[27]: EMACADDR7 Low [31:24]. Bit[24]: EMACADDR7 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/ +#define EMAC_MASK_BYTE_CONTROL7 0x0000003F +#define EMAC_MASK_BYTE_CONTROL7_M ((EMAC_MASK_BYTE_CONTROL7_V)<<(EMAC_MASK_BYTE_CONTROL7_S)) +#define EMAC_MASK_BYTE_CONTROL7_V 0x3F +#define EMAC_MASK_BYTE_CONTROL7_S 24 +/* EMAC_MAC_ADDRESS7_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */ +/*description: This field contains the upper 16 bits Bits[47:32] of the eighth + 6-byte MAC Address.*/ +#define EMAC_MAC_ADDRESS7_HI 0x0000FFFF +#define EMAC_MAC_ADDRESS7_HI_M ((EMAC_MAC_ADDRESS7_HI_V)<<(EMAC_MAC_ADDRESS7_HI_S)) +#define EMAC_MAC_ADDRESS7_HI_V 0xFFFF +#define EMAC_MAC_ADDRESS7_HI_S 0 + +#define EMAC_ADDR7LOW_REG (DR_REG_EMAC_BASE + 0x107C) +/* EMAC_MAC_ADDRESS7_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */ +/*description: This field contains the lower 32 bits of the eighth 6-byte MAC + address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/ +#define EMAC_MAC_ADDRESS7_LOW 0xFFFFFFFF +#define EMAC_MAC_ADDRESS7_LOW_M ((EMAC_MAC_ADDRESS7_LOW_V)<<(EMAC_MAC_ADDRESS7_LOW_S)) +#define EMAC_MAC_ADDRESS7_LOW_V 0xFFFFFFFF +#define EMAC_MAC_ADDRESS7_LOW_S 0 + +#define EMAC_CSTATUS_REG (DR_REG_EMAC_BASE + 0x10D8) +/* EMAC_JABBER_TIMEOUT : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: This bit indicates whether there is jabber timeout error (1'b1) + in the received Frame.*/ +#define EMAC_JABBER_TIMEOUT (BIT(4)) +#define EMAC_JABBER_TIMEOUT_M (BIT(4)) +#define EMAC_JABBER_TIMEOUT_V 0x1 +#define EMAC_JABBER_TIMEOUT_S 4 +/* EMAC_LINK_SPEED : RO ;bitpos:[2:1] ;default: 1'h0 ; */ +/*description: This bit indicates the current speed of the link: 2'b00: 2.5 + MHz. 2'b01: 25 MHz. 2'b10: 125 MHz.*/ +#define EMAC_LINK_SPEED 0x00000003 +#define EMAC_LINK_SPEED_M ((EMAC_LINK_SPEED_V)<<(EMAC_LINK_SPEED_S)) +#define EMAC_LINK_SPEED_V 0x3 +#define EMAC_LINK_SPEED_S 1 +/* EMAC_LINK_MODE : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit indicates the current mode of operation of the link: + 1'b0: Half-duplex mode. 1'b1: Full-duplex mode.*/ +#define EMAC_LINK_MODE (BIT(0)) +#define EMAC_LINK_MODE_M (BIT(0)) +#define EMAC_LINK_MODE_V 0x1 +#define EMAC_LINK_MODE_S 0 + +#define EMAC_WDOGTO_REG (DR_REG_EMAC_BASE + 0x10DC) +/* EMAC_PWDOGEN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset + the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG.*/ +#define EMAC_PWDOGEN (BIT(16)) +#define EMAC_PWDOGEN_M (BIT(16)) +#define EMAC_PWDOGEN_V 0x1 +#define EMAC_PWDOGEN_S 16 +/* EMAC_WDOGTO : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG + is reset this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field such frame is terminated and declared as an error frame.*/ +#define EMAC_WDOGTO 0x00003FFF +#define EMAC_WDOGTO_M ((EMAC_WDOGTO_V)<<(EMAC_WDOGTO_S)) +#define EMAC_WDOGTO_V 0x3FFF +#define EMAC_WDOGTO_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_EMAC_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/fe_reg.h b/tools/sdk/include/soc/include/soc/fe_reg.h new file mode 100644 index 00000000000..7705586d7c3 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/fe_reg.h @@ -0,0 +1,41 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the RF frontend control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090) +#define FE_IQ_EST_FORCE_PU (BIT(5)) +#define FE_IQ_EST_FORCE_PU_M (BIT(5)) +#define FE_IQ_EST_FORCE_PU_V 1 +#define FE_IQ_EST_FORCE_PU_S 5 +#define FE_IQ_EST_FORCE_PD (BIT(4)) +#define FE_IQ_EST_FORCE_PD_M (BIT(4)) +#define FE_IQ_EST_FORCE_PD_V 1 +#define FE_IQ_EST_FORCE_PD_S 4 + +#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0) +#define FE2_TX_INF_FORCE_PU (BIT(10)) +#define FE2_TX_INF_FORCE_PU_M (BIT(10)) +#define FE2_TX_INF_FORCE_PU_V 1 +#define FE2_TX_INF_FORCE_PU_S 10 +#define FE2_TX_INF_FORCE_PD (BIT(9)) +#define FE2_TX_INF_FORCE_PD_M (BIT(9)) +#define FE2_TX_INF_FORCE_PD_V 1 +#define FE2_TX_INF_FORCE_PD_S 9 diff --git a/tools/sdk/include/soc/include/soc/frc_timer_reg.h b/tools/sdk/include/soc/include/soc/frc_timer_reg.h new file mode 100644 index 00000000000..a2152c5c91a --- /dev/null +++ b/tools/sdk/include/soc/include/soc/frc_timer_reg.h @@ -0,0 +1,52 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_FRC_TIMER_REG_H_ +#define _SOC_FRC_TIMER_REG_H_ + +#include "soc.h" + +/** + * These are the register definitions for "legacy" timers + */ + +#define REG_FRC_TIMER_BASE(i) (DR_REG_FRC_TIMER_BASE + i*0x20) + +#define FRC_TIMER_LOAD_REG(i) (REG_FRC_TIMER_BASE(i) + 0x0) // timer load value (23 bit for i==0, 32 bit for i==1) +#define FRC_TIMER_LOAD_VALUE(i) ((i == 0)?0x007FFFFF:0xffffffff) +#define FRC_TIMER_LOAD_VALUE_S 0 + +#define FRC_TIMER_COUNT_REG(i) (REG_FRC_TIMER_BASE(i) + 0x4) // timer count value (23 bit for i==0, 32 bit for i==1) +#define FRC_TIMER_COUNT ((i == 0)?0x007FFFFF:0xffffffff) +#define FRC_TIMER_COUNT_S 0 + +#define FRC_TIMER_CTRL_REG(i) (REG_FRC_TIMER_BASE(i) + 0x8) +#define FRC_TIMER_INT_STATUS (BIT(8)) // interrupt status (RO) +#define FRC_TIMER_ENABLE (BIT(7)) // enable timer +#define FRC_TIMER_AUTOLOAD (BIT(6)) // enable autoload +#define FRC_TIMER_PRESCALER 0x00000007 +#define FRC_TIMER_PRESCALER_S 1 +#define FRC_TIMER_PRESCALER_1 (0 << FRC_TIMER_PRESCALER_S) +#define FRC_TIMER_PRESCALER_16 (2 << FRC_TIMER_PRESCALER_S) +#define FRC_TIMER_PRESCALER_256 (4 << FRC_TIMER_PRESCALER_S) +#define FRC_TIMER_LEVEL_INT (BIT(0)) // 1: level, 0: edge + +#define FRC_TIMER_INT_REG(i) (REG_FRC_TIMER_BASE(i) + 0xC) +#define FRC_TIMER_INT_CLR (BIT(0)) // clear interrupt + +#define FRC_TIMER_ALARM_REG(i) (REG_FRC_TIMER_BASE(i) + 0x10) // timer alarm value; register only present for i == 1 +#define FRC_TIMER_ALARM 0xFFFFFFFF +#define FRC_TIMER_ALARM_S 0 + +#endif //_SOC_FRC_TIMER_REG_H_ diff --git a/tools/sdk/include/soc/include/soc/gpio_pins.h b/tools/sdk/include/soc/include/soc/gpio_pins.h new file mode 100644 index 00000000000..6c2bfb7418f --- /dev/null +++ b/tools/sdk/include/soc/include/soc/gpio_pins.h @@ -0,0 +1,28 @@ +// Copyright 2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _GPIO_PINS_H +#define _GPIO_PINS_H +#ifdef __cplusplus +extern "C" +{ +#endif + +#define GPIO_PIN_COUNT 40 + +#ifdef __cplusplus +} +#endif + +#endif // _GPIO_PINS_H diff --git a/tools/sdk/include/soc/include/soc/gpio_reg.h b/tools/sdk/include/soc/include/soc/gpio_reg.h new file mode 100644 index 00000000000..8168f4ba12b --- /dev/null +++ b/tools/sdk/include/soc/include/soc/gpio_reg.h @@ -0,0 +1,8238 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_REG_H_ +#define _SOC_GPIO_REG_H_ + +#include "soc.h" +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0000) +/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: NA*/ +#define GPIO_BT_SEL 0xFFFFFFFF +#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) +#define GPIO_BT_SEL_V 0xFFFFFFFF +#define GPIO_BT_SEL_S 0 + +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x0004) +/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output value*/ +#define GPIO_OUT_DATA 0xFFFFFFFF +#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) +#define GPIO_OUT_DATA_V 0xFFFFFFFF +#define GPIO_OUT_DATA_S 0 + +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x0008) +/* GPIO_OUT_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output value write 1 to set*/ +#define GPIO_OUT_DATA_W1TS 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TS_M ((GPIO_OUT_DATA_W1TS_V)<<(GPIO_OUT_DATA_W1TS_S)) +#define GPIO_OUT_DATA_W1TS_V 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TS_S 0 + +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0x000c) +/* GPIO_OUT_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output value write 1 to clear*/ +#define GPIO_OUT_DATA_W1TC 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TC_M ((GPIO_OUT_DATA_W1TC_V)<<(GPIO_OUT_DATA_W1TC_S)) +#define GPIO_OUT_DATA_W1TC_V 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TC_S 0 + +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x0010) +/* GPIO_OUT1_DATA : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output value*/ +#define GPIO_OUT1_DATA 0x000000FF +#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S)) +#define GPIO_OUT1_DATA_V 0xFF +#define GPIO_OUT1_DATA_S 0 + +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x0014) +/* GPIO_OUT1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output value write 1 to set*/ +#define GPIO_OUT1_DATA_W1TS 0x000000FF +#define GPIO_OUT1_DATA_W1TS_M ((GPIO_OUT1_DATA_W1TS_V)<<(GPIO_OUT1_DATA_W1TS_S)) +#define GPIO_OUT1_DATA_W1TS_V 0xFF +#define GPIO_OUT1_DATA_W1TS_S 0 + +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x0018) +/* GPIO_OUT1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output value write 1 to clear*/ +#define GPIO_OUT1_DATA_W1TC 0x000000FF +#define GPIO_OUT1_DATA_W1TC_M ((GPIO_OUT1_DATA_W1TC_V)<<(GPIO_OUT1_DATA_W1TC_S)) +#define GPIO_OUT1_DATA_W1TC_V 0xFF +#define GPIO_OUT1_DATA_W1TC_S 0 + +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x001c) +/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: SDIO PADS on/off control from outside*/ +#define GPIO_SDIO_SEL 0x000000FF +#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) +#define GPIO_SDIO_SEL_V 0xFF +#define GPIO_SDIO_SEL_S 0 + +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x0020) +/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output enable*/ +#define GPIO_ENABLE_DATA 0xFFFFFFFF +#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) +#define GPIO_ENABLE_DATA_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_S 0 + +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x0024) +/* GPIO_ENABLE_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output enable write 1 to set*/ +#define GPIO_ENABLE_DATA_W1TS 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TS_M ((GPIO_ENABLE_DATA_W1TS_V)<<(GPIO_ENABLE_DATA_W1TS_S)) +#define GPIO_ENABLE_DATA_W1TS_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TS_S 0 + +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x0028) +/* GPIO_ENABLE_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output enable write 1 to clear*/ +#define GPIO_ENABLE_DATA_W1TC 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TC_M ((GPIO_ENABLE_DATA_W1TC_V)<<(GPIO_ENABLE_DATA_W1TC_S)) +#define GPIO_ENABLE_DATA_W1TC_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TC_S 0 + +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x002c) +/* GPIO_ENABLE1_DATA : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output enable*/ +#define GPIO_ENABLE1_DATA 0x000000FF +#define GPIO_ENABLE1_DATA_M ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S)) +#define GPIO_ENABLE1_DATA_V 0xFF +#define GPIO_ENABLE1_DATA_S 0 + +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x0030) +/* GPIO_ENABLE1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output enable write 1 to set*/ +#define GPIO_ENABLE1_DATA_W1TS 0x000000FF +#define GPIO_ENABLE1_DATA_W1TS_M ((GPIO_ENABLE1_DATA_W1TS_V)<<(GPIO_ENABLE1_DATA_W1TS_S)) +#define GPIO_ENABLE1_DATA_W1TS_V 0xFF +#define GPIO_ENABLE1_DATA_W1TS_S 0 + +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x0034) +/* GPIO_ENABLE1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output enable write 1 to clear*/ +#define GPIO_ENABLE1_DATA_W1TC 0x000000FF +#define GPIO_ENABLE1_DATA_W1TC_M ((GPIO_ENABLE1_DATA_W1TC_V)<<(GPIO_ENABLE1_DATA_W1TC_S)) +#define GPIO_ENABLE1_DATA_W1TC_V 0xFF +#define GPIO_ENABLE1_DATA_W1TC_S 0 + +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) +/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ +/*description: {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} */ +#define GPIO_STRAPPING 0x0000FFFF +#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) +#define GPIO_STRAPPING_V 0xFFFF +#define GPIO_STRAPPING_S 0 + +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x003c) +/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default: ; */ +/*description: GPIO0~31 input value*/ +#define GPIO_IN_DATA 0xFFFFFFFF +#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) +#define GPIO_IN_DATA_V 0xFFFFFFFF +#define GPIO_IN_DATA_S 0 + +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x0040) +/* GPIO_IN1_DATA : RO ;bitpos:[7:0] ;default: ; */ +/*description: GPIO32~39 input value*/ +#define GPIO_IN1_DATA 0x000000FF +#define GPIO_IN1_DATA_M ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S)) +#define GPIO_IN1_DATA_V 0xFF +#define GPIO_IN1_DATA_S 0 + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x0044) +/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 interrupt status*/ +#define GPIO_STATUS_INT 0xFFFFFFFF +#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) +#define GPIO_STATUS_INT_V 0xFFFFFFFF +#define GPIO_STATUS_INT_S 0 + +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x0048) +/* GPIO_STATUS_INT_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 interrupt status write 1 to set*/ +#define GPIO_STATUS_INT_W1TS 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TS_M ((GPIO_STATUS_INT_W1TS_V)<<(GPIO_STATUS_INT_W1TS_S)) +#define GPIO_STATUS_INT_W1TS_V 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TS_S 0 + +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x004c) +/* GPIO_STATUS_INT_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 interrupt status write 1 to clear*/ +#define GPIO_STATUS_INT_W1TC 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TC_M ((GPIO_STATUS_INT_W1TC_V)<<(GPIO_STATUS_INT_W1TC_S)) +#define GPIO_STATUS_INT_W1TC_V 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TC_S 0 + +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x0050) +/* GPIO_STATUS1_INT : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 interrupt status*/ +#define GPIO_STATUS1_INT 0x000000FF +#define GPIO_STATUS1_INT_M ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S)) +#define GPIO_STATUS1_INT_V 0xFF +#define GPIO_STATUS1_INT_S 0 + +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x0054) +/* GPIO_STATUS1_INT_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 interrupt status write 1 to set*/ +#define GPIO_STATUS1_INT_W1TS 0x000000FF +#define GPIO_STATUS1_INT_W1TS_M ((GPIO_STATUS1_INT_W1TS_V)<<(GPIO_STATUS1_INT_W1TS_S)) +#define GPIO_STATUS1_INT_W1TS_V 0xFF +#define GPIO_STATUS1_INT_W1TS_S 0 + +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x0058) +/* GPIO_STATUS1_INT_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 interrupt status write 1 to clear*/ +#define GPIO_STATUS1_INT_W1TC 0x000000FF +#define GPIO_STATUS1_INT_W1TC_M ((GPIO_STATUS1_INT_W1TC_V)<<(GPIO_STATUS1_INT_W1TC_S)) +#define GPIO_STATUS1_INT_W1TC_V 0xFF +#define GPIO_STATUS1_INT_W1TC_S 0 + +#define GPIO_ACPU_INT_REG (DR_REG_GPIO_BASE + 0x0060) +/* GPIO_APPCPU_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 APP CPU interrupt status*/ +#define GPIO_APPCPU_INT 0xFFFFFFFF +#define GPIO_APPCPU_INT_M ((GPIO_APPCPU_INT_V)<<(GPIO_APPCPU_INT_S)) +#define GPIO_APPCPU_INT_V 0xFFFFFFFF +#define GPIO_APPCPU_INT_S 0 + +#define GPIO_ACPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x0064) +/* GPIO_APPCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 APP CPU non-maskable interrupt status*/ +#define GPIO_APPCPU_NMI_INT 0xFFFFFFFF +#define GPIO_APPCPU_NMI_INT_M ((GPIO_APPCPU_NMI_INT_V)<<(GPIO_APPCPU_NMI_INT_S)) +#define GPIO_APPCPU_NMI_INT_V 0xFFFFFFFF +#define GPIO_APPCPU_NMI_INT_S 0 + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x0068) +/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 PRO CPU interrupt status*/ +#define GPIO_PROCPU_INT 0xFFFFFFFF +#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) +#define GPIO_PROCPU_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_INT_S 0 + +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x006c) +/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 PRO CPU non-maskable interrupt status*/ +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_S 0 + +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x0070) +/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: SDIO's extent GPIO0~31 interrupt*/ +#define GPIO_SDIO_INT 0xFFFFFFFF +#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) +#define GPIO_SDIO_INT_V 0xFFFFFFFF +#define GPIO_SDIO_INT_S 0 + +#define GPIO_ACPU_INT1_REG (DR_REG_GPIO_BASE + 0x0074) +/* GPIO_APPCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 APP CPU interrupt status*/ +#define GPIO_APPCPU_INT_H 0x000000FF +#define GPIO_APPCPU_INT_H_M ((GPIO_APPCPU_INT_H_V)<<(GPIO_APPCPU_INT_H_S)) +#define GPIO_APPCPU_INT_H_V 0xFF +#define GPIO_APPCPU_INT_H_S 0 + +#define GPIO_ACPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0078) +/* GPIO_APPCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 APP CPU non-maskable interrupt status*/ +#define GPIO_APPCPU_NMI_INT_H 0x000000FF +#define GPIO_APPCPU_NMI_INT_H_M ((GPIO_APPCPU_NMI_INT_H_V)<<(GPIO_APPCPU_NMI_INT_H_S)) +#define GPIO_APPCPU_NMI_INT_H_V 0xFF +#define GPIO_APPCPU_NMI_INT_H_S 0 + +#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x007c) +/* GPIO_PROCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 PRO CPU interrupt status*/ +#define GPIO_PROCPU_INT_H 0x000000FF +#define GPIO_PROCPU_INT_H_M ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S)) +#define GPIO_PROCPU_INT_H_V 0xFF +#define GPIO_PROCPU_INT_H_S 0 + +#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0080) +/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 PRO CPU non-maskable interrupt status*/ +#define GPIO_PROCPU_NMI_INT_H 0x000000FF +#define GPIO_PROCPU_NMI_INT_H_M ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S)) +#define GPIO_PROCPU_NMI_INT_H_V 0xFF +#define GPIO_PROCPU_NMI_INT_H_S 0 + +#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x0084) +/* GPIO_SDIO_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: SDIO's extent GPIO32~39 interrupt*/ +#define GPIO_SDIO_INT_H 0x000000FF +#define GPIO_SDIO_INT_H_M ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S)) +#define GPIO_SDIO_INT_H_V 0xFF +#define GPIO_SDIO_INT_H_S 0 + +#define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4) +#define GPIO_PIN_INT_ENA 0x0000001F +#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S)) +#define GPIO_PIN_INT_ENA_V 0x0000001F +#define GPIO_PIN_INT_ENA_S 13 +#define GPIO_PIN_CONFIG 0x00000003 +#define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S)) +#define GPIO_PIN_CONFIG_V 0x00000003 +#define GPIO_PIN_CONFIG_S 11 +#define GPIO_PIN_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN_WAKEUP_ENABLE_S 10 +#define GPIO_PIN_INT_TYPE 0x00000007 +#define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S)) +#define GPIO_PIN_INT_TYPE_V 0x00000007 +#define GPIO_PIN_INT_TYPE_S 7 +#define GPIO_PIN_PAD_DRIVER (BIT(2)) +#define GPIO_PIN_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN_PAD_DRIVER_V 0x1 +#define GPIO_PIN_PAD_DRIVER_S 2 + +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x0088) +/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN0_INT_ENA 0x0000001F +#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) +#define GPIO_PIN0_INT_ENA_V 0x1F +#define GPIO_PIN0_INT_ENA_S 13 +/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) +#define GPIO_PIN0_CONFIG_V 0x3 +#define GPIO_PIN0_CONFIG_S 11 +/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) +#define GPIO_PIN0_INT_TYPE_V 0x7 +#define GPIO_PIN0_INT_TYPE_S 7 +/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_V 0x1 +#define GPIO_PIN0_PAD_DRIVER_S 2 + +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x008c) +/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN1_INT_ENA 0x0000001F +#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) +#define GPIO_PIN1_INT_ENA_V 0x1F +#define GPIO_PIN1_INT_ENA_S 13 +/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) +#define GPIO_PIN1_CONFIG_V 0x3 +#define GPIO_PIN1_CONFIG_S 11 +/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) +#define GPIO_PIN1_INT_TYPE_V 0x7 +#define GPIO_PIN1_INT_TYPE_S 7 +/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_V 0x1 +#define GPIO_PIN1_PAD_DRIVER_S 2 + +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x0090) +/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN2_INT_ENA 0x0000001F +#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) +#define GPIO_PIN2_INT_ENA_V 0x1F +#define GPIO_PIN2_INT_ENA_S 13 +/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) +#define GPIO_PIN2_CONFIG_V 0x3 +#define GPIO_PIN2_CONFIG_S 11 +/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) +#define GPIO_PIN2_INT_TYPE_V 0x7 +#define GPIO_PIN2_INT_TYPE_S 7 +/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_V 0x1 +#define GPIO_PIN2_PAD_DRIVER_S 2 + +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x0094) +/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN3_INT_ENA 0x0000001F +#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) +#define GPIO_PIN3_INT_ENA_V 0x1F +#define GPIO_PIN3_INT_ENA_S 13 +/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) +#define GPIO_PIN3_CONFIG_V 0x3 +#define GPIO_PIN3_CONFIG_S 11 +/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) +#define GPIO_PIN3_INT_TYPE_V 0x7 +#define GPIO_PIN3_INT_TYPE_S 7 +/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_V 0x1 +#define GPIO_PIN3_PAD_DRIVER_S 2 + +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x0098) +/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN4_INT_ENA 0x0000001F +#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) +#define GPIO_PIN4_INT_ENA_V 0x1F +#define GPIO_PIN4_INT_ENA_S 13 +/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) +#define GPIO_PIN4_CONFIG_V 0x3 +#define GPIO_PIN4_CONFIG_S 11 +/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) +#define GPIO_PIN4_INT_TYPE_V 0x7 +#define GPIO_PIN4_INT_TYPE_S 7 +/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_V 0x1 +#define GPIO_PIN4_PAD_DRIVER_S 2 + +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x009c) +/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN5_INT_ENA 0x0000001F +#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) +#define GPIO_PIN5_INT_ENA_V 0x1F +#define GPIO_PIN5_INT_ENA_S 13 +/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) +#define GPIO_PIN5_CONFIG_V 0x3 +#define GPIO_PIN5_CONFIG_S 11 +/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) +#define GPIO_PIN5_INT_TYPE_V 0x7 +#define GPIO_PIN5_INT_TYPE_S 7 +/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_V 0x1 +#define GPIO_PIN5_PAD_DRIVER_S 2 + +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x00a0) +/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN6_INT_ENA 0x0000001F +#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) +#define GPIO_PIN6_INT_ENA_V 0x1F +#define GPIO_PIN6_INT_ENA_S 13 +/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) +#define GPIO_PIN6_CONFIG_V 0x3 +#define GPIO_PIN6_CONFIG_S 11 +/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) +#define GPIO_PIN6_INT_TYPE_V 0x7 +#define GPIO_PIN6_INT_TYPE_S 7 +/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_V 0x1 +#define GPIO_PIN6_PAD_DRIVER_S 2 + +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x00a4) +/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN7_INT_ENA 0x0000001F +#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) +#define GPIO_PIN7_INT_ENA_V 0x1F +#define GPIO_PIN7_INT_ENA_S 13 +/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) +#define GPIO_PIN7_CONFIG_V 0x3 +#define GPIO_PIN7_CONFIG_S 11 +/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) +#define GPIO_PIN7_INT_TYPE_V 0x7 +#define GPIO_PIN7_INT_TYPE_S 7 +/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_V 0x1 +#define GPIO_PIN7_PAD_DRIVER_S 2 + +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x00a8) +/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN8_INT_ENA 0x0000001F +#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) +#define GPIO_PIN8_INT_ENA_V 0x1F +#define GPIO_PIN8_INT_ENA_S 13 +/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) +#define GPIO_PIN8_CONFIG_V 0x3 +#define GPIO_PIN8_CONFIG_S 11 +/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) +#define GPIO_PIN8_INT_TYPE_V 0x7 +#define GPIO_PIN8_INT_TYPE_S 7 +/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_V 0x1 +#define GPIO_PIN8_PAD_DRIVER_S 2 + +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x00ac) +/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN9_INT_ENA 0x0000001F +#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) +#define GPIO_PIN9_INT_ENA_V 0x1F +#define GPIO_PIN9_INT_ENA_S 13 +/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) +#define GPIO_PIN9_CONFIG_V 0x3 +#define GPIO_PIN9_CONFIG_S 11 +/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) +#define GPIO_PIN9_INT_TYPE_V 0x7 +#define GPIO_PIN9_INT_TYPE_S 7 +/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_V 0x1 +#define GPIO_PIN9_PAD_DRIVER_S 2 + +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x00b0) +/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN10_INT_ENA 0x0000001F +#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) +#define GPIO_PIN10_INT_ENA_V 0x1F +#define GPIO_PIN10_INT_ENA_S 13 +/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) +#define GPIO_PIN10_CONFIG_V 0x3 +#define GPIO_PIN10_CONFIG_S 11 +/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) +#define GPIO_PIN10_INT_TYPE_V 0x7 +#define GPIO_PIN10_INT_TYPE_S 7 +/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_V 0x1 +#define GPIO_PIN10_PAD_DRIVER_S 2 + +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x00b4) +/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN11_INT_ENA 0x0000001F +#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) +#define GPIO_PIN11_INT_ENA_V 0x1F +#define GPIO_PIN11_INT_ENA_S 13 +/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) +#define GPIO_PIN11_CONFIG_V 0x3 +#define GPIO_PIN11_CONFIG_S 11 +/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) +#define GPIO_PIN11_INT_TYPE_V 0x7 +#define GPIO_PIN11_INT_TYPE_S 7 +/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_V 0x1 +#define GPIO_PIN11_PAD_DRIVER_S 2 + +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x00b8) +/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN12_INT_ENA 0x0000001F +#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) +#define GPIO_PIN12_INT_ENA_V 0x1F +#define GPIO_PIN12_INT_ENA_S 13 +/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) +#define GPIO_PIN12_CONFIG_V 0x3 +#define GPIO_PIN12_CONFIG_S 11 +/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) +#define GPIO_PIN12_INT_TYPE_V 0x7 +#define GPIO_PIN12_INT_TYPE_S 7 +/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_V 0x1 +#define GPIO_PIN12_PAD_DRIVER_S 2 + +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x00bc) +/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN13_INT_ENA 0x0000001F +#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) +#define GPIO_PIN13_INT_ENA_V 0x1F +#define GPIO_PIN13_INT_ENA_S 13 +/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) +#define GPIO_PIN13_CONFIG_V 0x3 +#define GPIO_PIN13_CONFIG_S 11 +/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) +#define GPIO_PIN13_INT_TYPE_V 0x7 +#define GPIO_PIN13_INT_TYPE_S 7 +/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_V 0x1 +#define GPIO_PIN13_PAD_DRIVER_S 2 + +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x00c0) +/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN14_INT_ENA 0x0000001F +#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) +#define GPIO_PIN14_INT_ENA_V 0x1F +#define GPIO_PIN14_INT_ENA_S 13 +/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) +#define GPIO_PIN14_CONFIG_V 0x3 +#define GPIO_PIN14_CONFIG_S 11 +/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) +#define GPIO_PIN14_INT_TYPE_V 0x7 +#define GPIO_PIN14_INT_TYPE_S 7 +/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_V 0x1 +#define GPIO_PIN14_PAD_DRIVER_S 2 + +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x00c4) +/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN15_INT_ENA 0x0000001F +#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) +#define GPIO_PIN15_INT_ENA_V 0x1F +#define GPIO_PIN15_INT_ENA_S 13 +/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) +#define GPIO_PIN15_CONFIG_V 0x3 +#define GPIO_PIN15_CONFIG_S 11 +/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) +#define GPIO_PIN15_INT_TYPE_V 0x7 +#define GPIO_PIN15_INT_TYPE_S 7 +/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_V 0x1 +#define GPIO_PIN15_PAD_DRIVER_S 2 + +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x00c8) +/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN16_INT_ENA 0x0000001F +#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) +#define GPIO_PIN16_INT_ENA_V 0x1F +#define GPIO_PIN16_INT_ENA_S 13 +/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) +#define GPIO_PIN16_CONFIG_V 0x3 +#define GPIO_PIN16_CONFIG_S 11 +/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) +#define GPIO_PIN16_INT_TYPE_V 0x7 +#define GPIO_PIN16_INT_TYPE_S 7 +/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_V 0x1 +#define GPIO_PIN16_PAD_DRIVER_S 2 + +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x00cc) +/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN17_INT_ENA 0x0000001F +#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) +#define GPIO_PIN17_INT_ENA_V 0x1F +#define GPIO_PIN17_INT_ENA_S 13 +/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) +#define GPIO_PIN17_CONFIG_V 0x3 +#define GPIO_PIN17_CONFIG_S 11 +/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) +#define GPIO_PIN17_INT_TYPE_V 0x7 +#define GPIO_PIN17_INT_TYPE_S 7 +/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_V 0x1 +#define GPIO_PIN17_PAD_DRIVER_S 2 + +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x00d0) +/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN18_INT_ENA 0x0000001F +#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) +#define GPIO_PIN18_INT_ENA_V 0x1F +#define GPIO_PIN18_INT_ENA_S 13 +/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) +#define GPIO_PIN18_CONFIG_V 0x3 +#define GPIO_PIN18_CONFIG_S 11 +/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) +#define GPIO_PIN18_INT_TYPE_V 0x7 +#define GPIO_PIN18_INT_TYPE_S 7 +/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_V 0x1 +#define GPIO_PIN18_PAD_DRIVER_S 2 + +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x00d4) +/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN19_INT_ENA 0x0000001F +#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) +#define GPIO_PIN19_INT_ENA_V 0x1F +#define GPIO_PIN19_INT_ENA_S 13 +/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) +#define GPIO_PIN19_CONFIG_V 0x3 +#define GPIO_PIN19_CONFIG_S 11 +/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) +#define GPIO_PIN19_INT_TYPE_V 0x7 +#define GPIO_PIN19_INT_TYPE_S 7 +/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_V 0x1 +#define GPIO_PIN19_PAD_DRIVER_S 2 + +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x00d8) +/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-mask interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-mask interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN20_INT_ENA 0x0000001F +#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) +#define GPIO_PIN20_INT_ENA_V 0x1F +#define GPIO_PIN20_INT_ENA_S 13 +/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) +#define GPIO_PIN20_CONFIG_V 0x3 +#define GPIO_PIN20_CONFIG_S 11 +/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) +#define GPIO_PIN20_INT_TYPE_V 0x7 +#define GPIO_PIN20_INT_TYPE_S 7 +/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_V 0x1 +#define GPIO_PIN20_PAD_DRIVER_S 2 + +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x00dc) +/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN21_INT_ENA 0x0000001F +#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) +#define GPIO_PIN21_INT_ENA_V 0x1F +#define GPIO_PIN21_INT_ENA_S 13 +/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) +#define GPIO_PIN21_CONFIG_V 0x3 +#define GPIO_PIN21_CONFIG_S 11 +/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) +#define GPIO_PIN21_INT_TYPE_V 0x7 +#define GPIO_PIN21_INT_TYPE_S 7 +/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_V 0x1 +#define GPIO_PIN21_PAD_DRIVER_S 2 + +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x00e0) +/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: */ +#define GPIO_PIN22_INT_ENA 0x0000001F +#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) +#define GPIO_PIN22_INT_ENA_V 0x1F +#define GPIO_PIN22_INT_ENA_S 13 +/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) +#define GPIO_PIN22_CONFIG_V 0x3 +#define GPIO_PIN22_CONFIG_S 11 +/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) +#define GPIO_PIN22_INT_TYPE_V 0x7 +#define GPIO_PIN22_INT_TYPE_S 7 +/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_V 0x1 +#define GPIO_PIN22_PAD_DRIVER_S 2 + +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x00e4) +/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN23_INT_ENA 0x0000001F +#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) +#define GPIO_PIN23_INT_ENA_V 0x1F +#define GPIO_PIN23_INT_ENA_S 13 +/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) +#define GPIO_PIN23_CONFIG_V 0x3 +#define GPIO_PIN23_CONFIG_S 11 +/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) +#define GPIO_PIN23_INT_TYPE_V 0x7 +#define GPIO_PIN23_INT_TYPE_S 7 +/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_V 0x1 +#define GPIO_PIN23_PAD_DRIVER_S 2 + +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x00e8) +/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN24_INT_ENA 0x0000001F +#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) +#define GPIO_PIN24_INT_ENA_V 0x1F +#define GPIO_PIN24_INT_ENA_S 13 +/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) +#define GPIO_PIN24_CONFIG_V 0x3 +#define GPIO_PIN24_CONFIG_S 11 +/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) +#define GPIO_PIN24_INT_TYPE_V 0x7 +#define GPIO_PIN24_INT_TYPE_S 7 +/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_V 0x1 +#define GPIO_PIN24_PAD_DRIVER_S 2 + +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x00ec) +/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN25_INT_ENA 0x0000001F +#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) +#define GPIO_PIN25_INT_ENA_V 0x1F +#define GPIO_PIN25_INT_ENA_S 13 +/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) +#define GPIO_PIN25_CONFIG_V 0x3 +#define GPIO_PIN25_CONFIG_S 11 +/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) +#define GPIO_PIN25_INT_TYPE_V 0x7 +#define GPIO_PIN25_INT_TYPE_S 7 +/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_V 0x1 +#define GPIO_PIN25_PAD_DRIVER_S 2 + +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x00f0) +/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN26_INT_ENA 0x0000001F +#define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) +#define GPIO_PIN26_INT_ENA_V 0x1F +#define GPIO_PIN26_INT_ENA_S 13 +/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN26_CONFIG 0x00000003 +#define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) +#define GPIO_PIN26_CONFIG_V 0x3 +#define GPIO_PIN26_CONFIG_S 11 +/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN26_INT_TYPE 0x00000007 +#define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) +#define GPIO_PIN26_INT_TYPE_V 0x7 +#define GPIO_PIN26_INT_TYPE_S 7 +/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_V 0x1 +#define GPIO_PIN26_PAD_DRIVER_S 2 + +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x00f4) +/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN27_INT_ENA 0x0000001F +#define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) +#define GPIO_PIN27_INT_ENA_V 0x1F +#define GPIO_PIN27_INT_ENA_S 13 +/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN27_CONFIG 0x00000003 +#define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) +#define GPIO_PIN27_CONFIG_V 0x3 +#define GPIO_PIN27_CONFIG_S 11 +/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN27_INT_TYPE 0x00000007 +#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) +#define GPIO_PIN27_INT_TYPE_V 0x7 +#define GPIO_PIN27_INT_TYPE_S 7 +/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_V 0x1 +#define GPIO_PIN27_PAD_DRIVER_S 2 + +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x00f8) +/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN28_INT_ENA 0x0000001F +#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) +#define GPIO_PIN28_INT_ENA_V 0x1F +#define GPIO_PIN28_INT_ENA_S 13 +/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN28_CONFIG 0x00000003 +#define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) +#define GPIO_PIN28_CONFIG_V 0x3 +#define GPIO_PIN28_CONFIG_S 11 +/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN28_INT_TYPE 0x00000007 +#define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) +#define GPIO_PIN28_INT_TYPE_V 0x7 +#define GPIO_PIN28_INT_TYPE_S 7 +/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_V 0x1 +#define GPIO_PIN28_PAD_DRIVER_S 2 + +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x00fc) +/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN29_INT_ENA 0x0000001F +#define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) +#define GPIO_PIN29_INT_ENA_V 0x1F +#define GPIO_PIN29_INT_ENA_S 13 +/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN29_CONFIG 0x00000003 +#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) +#define GPIO_PIN29_CONFIG_V 0x3 +#define GPIO_PIN29_CONFIG_S 11 +/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN29_INT_TYPE 0x00000007 +#define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) +#define GPIO_PIN29_INT_TYPE_V 0x7 +#define GPIO_PIN29_INT_TYPE_S 7 +/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_V 0x1 +#define GPIO_PIN29_PAD_DRIVER_S 2 + +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x0100) +/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN30_INT_ENA 0x0000001F +#define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S)) +#define GPIO_PIN30_INT_ENA_V 0x1F +#define GPIO_PIN30_INT_ENA_S 13 +/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN30_CONFIG 0x00000003 +#define GPIO_PIN30_CONFIG_M ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S)) +#define GPIO_PIN30_CONFIG_V 0x3 +#define GPIO_PIN30_CONFIG_S 11 +/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN30_INT_TYPE 0x00000007 +#define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S)) +#define GPIO_PIN30_INT_TYPE_V 0x7 +#define GPIO_PIN30_INT_TYPE_S 7 +/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_V 0x1 +#define GPIO_PIN30_PAD_DRIVER_S 2 + +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x0104) +/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN31_INT_ENA 0x0000001F +#define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S)) +#define GPIO_PIN31_INT_ENA_V 0x1F +#define GPIO_PIN31_INT_ENA_S 13 +/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN31_CONFIG 0x00000003 +#define GPIO_PIN31_CONFIG_M ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S)) +#define GPIO_PIN31_CONFIG_V 0x3 +#define GPIO_PIN31_CONFIG_S 11 +/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 +/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN31_INT_TYPE 0x00000007 +#define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S)) +#define GPIO_PIN31_INT_TYPE_V 0x7 +#define GPIO_PIN31_INT_TYPE_S 7 +/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_V 0x1 +#define GPIO_PIN31_PAD_DRIVER_S 2 + +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x0108) +/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN32_INT_ENA 0x0000001F +#define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S)) +#define GPIO_PIN32_INT_ENA_V 0x1F +#define GPIO_PIN32_INT_ENA_S 13 +/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN32_CONFIG 0x00000003 +#define GPIO_PIN32_CONFIG_M ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S)) +#define GPIO_PIN32_CONFIG_V 0x3 +#define GPIO_PIN32_CONFIG_S 11 +/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 +/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN32_INT_TYPE 0x00000007 +#define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S)) +#define GPIO_PIN32_INT_TYPE_V 0x7 +#define GPIO_PIN32_INT_TYPE_S 7 +/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_V 0x1 +#define GPIO_PIN32_PAD_DRIVER_S 2 + +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0x010c) +/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN33_INT_ENA 0x0000001F +#define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S)) +#define GPIO_PIN33_INT_ENA_V 0x1F +#define GPIO_PIN33_INT_ENA_S 13 +/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN33_CONFIG 0x00000003 +#define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S)) +#define GPIO_PIN33_CONFIG_V 0x3 +#define GPIO_PIN33_CONFIG_S 11 +/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 +/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN33_INT_TYPE 0x00000007 +#define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S)) +#define GPIO_PIN33_INT_TYPE_V 0x7 +#define GPIO_PIN33_INT_TYPE_S 7 +/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_V 0x1 +#define GPIO_PIN33_PAD_DRIVER_S 2 + +#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0x0110) +/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN34_INT_ENA 0x0000001F +#define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S)) +#define GPIO_PIN34_INT_ENA_V 0x1F +#define GPIO_PIN34_INT_ENA_S 13 +/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN34_CONFIG 0x00000003 +#define GPIO_PIN34_CONFIG_M ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S)) +#define GPIO_PIN34_CONFIG_V 0x3 +#define GPIO_PIN34_CONFIG_S 11 +/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN34_WAKEUP_ENABLE_S 10 +/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN34_INT_TYPE 0x00000007 +#define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S)) +#define GPIO_PIN34_INT_TYPE_V 0x7 +#define GPIO_PIN34_INT_TYPE_S 7 +/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_V 0x1 +#define GPIO_PIN34_PAD_DRIVER_S 2 + +#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x0114) +/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN35_INT_ENA 0x0000001F +#define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S)) +#define GPIO_PIN35_INT_ENA_V 0x1F +#define GPIO_PIN35_INT_ENA_S 13 +/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN35_CONFIG 0x00000003 +#define GPIO_PIN35_CONFIG_M ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S)) +#define GPIO_PIN35_CONFIG_V 0x3 +#define GPIO_PIN35_CONFIG_S 11 +/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN35_WAKEUP_ENABLE_S 10 +/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN35_INT_TYPE 0x00000007 +#define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S)) +#define GPIO_PIN35_INT_TYPE_V 0x7 +#define GPIO_PIN35_INT_TYPE_S 7 +/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN35_PAD_DRIVER (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_V 0x1 +#define GPIO_PIN35_PAD_DRIVER_S 2 + +#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x0118) +/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN36_INT_ENA 0x0000001F +#define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S)) +#define GPIO_PIN36_INT_ENA_V 0x1F +#define GPIO_PIN36_INT_ENA_S 13 +/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN36_CONFIG 0x00000003 +#define GPIO_PIN36_CONFIG_M ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S)) +#define GPIO_PIN36_CONFIG_V 0x3 +#define GPIO_PIN36_CONFIG_S 11 +/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN36_WAKEUP_ENABLE_S 10 +/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN36_INT_TYPE 0x00000007 +#define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S)) +#define GPIO_PIN36_INT_TYPE_V 0x7 +#define GPIO_PIN36_INT_TYPE_S 7 +/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN36_PAD_DRIVER (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_V 0x1 +#define GPIO_PIN36_PAD_DRIVER_S 2 + +#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x011c) +/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN37_INT_ENA 0x0000001F +#define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S)) +#define GPIO_PIN37_INT_ENA_V 0x1F +#define GPIO_PIN37_INT_ENA_S 13 +/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN37_CONFIG 0x00000003 +#define GPIO_PIN37_CONFIG_M ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S)) +#define GPIO_PIN37_CONFIG_V 0x3 +#define GPIO_PIN37_CONFIG_S 11 +/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN37_WAKEUP_ENABLE_S 10 +/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN37_INT_TYPE 0x00000007 +#define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S)) +#define GPIO_PIN37_INT_TYPE_V 0x7 +#define GPIO_PIN37_INT_TYPE_S 7 +/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN37_PAD_DRIVER (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_V 0x1 +#define GPIO_PIN37_PAD_DRIVER_S 2 + +#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x0120) +/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN38_INT_ENA 0x0000001F +#define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S)) +#define GPIO_PIN38_INT_ENA_V 0x1F +#define GPIO_PIN38_INT_ENA_S 13 +/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN38_CONFIG 0x00000003 +#define GPIO_PIN38_CONFIG_M ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S)) +#define GPIO_PIN38_CONFIG_V 0x3 +#define GPIO_PIN38_CONFIG_S 11 +/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN38_WAKEUP_ENABLE_S 10 +/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN38_INT_TYPE 0x00000007 +#define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S)) +#define GPIO_PIN38_INT_TYPE_V 0x7 +#define GPIO_PIN38_INT_TYPE_S 7 +/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN38_PAD_DRIVER (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_V 0x1 +#define GPIO_PIN38_PAD_DRIVER_S 2 + +#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x0124) +/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN39_INT_ENA 0x0000001F +#define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S)) +#define GPIO_PIN39_INT_ENA_V 0x1F +#define GPIO_PIN39_INT_ENA_S 13 +/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN39_CONFIG 0x00000003 +#define GPIO_PIN39_CONFIG_M ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S)) +#define GPIO_PIN39_CONFIG_V 0x3 +#define GPIO_PIN39_CONFIG_S 11 +/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN39_WAKEUP_ENABLE_S 10 +/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN39_INT_TYPE 0x00000007 +#define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S)) +#define GPIO_PIN39_INT_TYPE_V 0x7 +#define GPIO_PIN39_INT_TYPE_S 7 +/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN39_PAD_DRIVER (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_V 0x1 +#define GPIO_PIN39_PAD_DRIVER_S 2 + +#define GPIO_cali_conf_REG (DR_REG_GPIO_BASE + 0x0128) +/* GPIO_CALI_START : R/W ;bitpos:[31] ;default: x ; */ +/*description: */ +#define GPIO_CALI_START (BIT(31)) +#define GPIO_CALI_START_M (BIT(31)) +#define GPIO_CALI_START_V 0x1 +#define GPIO_CALI_START_S 31 +/* GPIO_CALI_RTC_MAX : R/W ;bitpos:[9:0] ;default: x ; */ +/*description: */ +#define GPIO_CALI_RTC_MAX 0x000003FF +#define GPIO_CALI_RTC_MAX_M ((GPIO_CALI_RTC_MAX_V)<<(GPIO_CALI_RTC_MAX_S)) +#define GPIO_CALI_RTC_MAX_V 0x3FF +#define GPIO_CALI_RTC_MAX_S 0 + +#define GPIO_cali_data_REG (DR_REG_GPIO_BASE + 0x012c) +/* GPIO_CALI_RDY_SYNC2 : RO ;bitpos:[31] ;default: ; */ +/*description: */ +#define GPIO_CALI_RDY_SYNC2 (BIT(31)) +#define GPIO_CALI_RDY_SYNC2_M (BIT(31)) +#define GPIO_CALI_RDY_SYNC2_V 0x1 +#define GPIO_CALI_RDY_SYNC2_S 31 +/* GPIO_CALI_RDY_REAL : RO ;bitpos:[30] ;default: ; */ +/*description: */ +#define GPIO_CALI_RDY_REAL (BIT(30)) +#define GPIO_CALI_RDY_REAL_M (BIT(30)) +#define GPIO_CALI_RDY_REAL_V 0x1 +#define GPIO_CALI_RDY_REAL_S 30 +/* GPIO_CALI_VALUE_SYNC2 : RO ;bitpos:[19:0] ;default: ; */ +/*description: */ +#define GPIO_CALI_VALUE_SYNC2 0x000FFFFF +#define GPIO_CALI_VALUE_SYNC2_M ((GPIO_CALI_VALUE_SYNC2_V)<<(GPIO_CALI_VALUE_SYNC2_S)) +#define GPIO_CALI_VALUE_SYNC2_V 0xFFFFF +#define GPIO_CALI_VALUE_SYNC2_S 0 + +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0130) +/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (BIT(7)) +#define GPIO_SIG0_IN_SEL_V 0x1 +#define GPIO_SIG0_IN_SEL_S 7 +/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_V 0x1 +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC0_IN_SEL 0x0000003F +#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) +#define GPIO_FUNC0_IN_SEL_V 0x3F +#define GPIO_FUNC0_IN_SEL_S 0 + +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0134) +/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG1_IN_SEL (BIT(7)) +#define GPIO_SIG1_IN_SEL_M (BIT(7)) +#define GPIO_SIG1_IN_SEL_V 0x1 +#define GPIO_SIG1_IN_SEL_S 7 +/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_V 0x1 +#define GPIO_FUNC1_IN_INV_SEL_S 6 +/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC1_IN_SEL 0x0000003F +#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) +#define GPIO_FUNC1_IN_SEL_V 0x3F +#define GPIO_FUNC1_IN_SEL_S 0 + +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0138) +/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG2_IN_SEL (BIT(7)) +#define GPIO_SIG2_IN_SEL_M (BIT(7)) +#define GPIO_SIG2_IN_SEL_V 0x1 +#define GPIO_SIG2_IN_SEL_S 7 +/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_V 0x1 +#define GPIO_FUNC2_IN_INV_SEL_S 6 +/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC2_IN_SEL 0x0000003F +#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) +#define GPIO_FUNC2_IN_SEL_V 0x3F +#define GPIO_FUNC2_IN_SEL_S 0 + +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x013c) +/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG3_IN_SEL (BIT(7)) +#define GPIO_SIG3_IN_SEL_M (BIT(7)) +#define GPIO_SIG3_IN_SEL_V 0x1 +#define GPIO_SIG3_IN_SEL_S 7 +/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_V 0x1 +#define GPIO_FUNC3_IN_INV_SEL_S 6 +/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC3_IN_SEL 0x0000003F +#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) +#define GPIO_FUNC3_IN_SEL_V 0x3F +#define GPIO_FUNC3_IN_SEL_S 0 + +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0140) +/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG4_IN_SEL (BIT(7)) +#define GPIO_SIG4_IN_SEL_M (BIT(7)) +#define GPIO_SIG4_IN_SEL_V 0x1 +#define GPIO_SIG4_IN_SEL_S 7 +/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_V 0x1 +#define GPIO_FUNC4_IN_INV_SEL_S 6 +/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC4_IN_SEL 0x0000003F +#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) +#define GPIO_FUNC4_IN_SEL_V 0x3F +#define GPIO_FUNC4_IN_SEL_S 0 + +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0144) +/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG5_IN_SEL (BIT(7)) +#define GPIO_SIG5_IN_SEL_M (BIT(7)) +#define GPIO_SIG5_IN_SEL_V 0x1 +#define GPIO_SIG5_IN_SEL_S 7 +/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_V 0x1 +#define GPIO_FUNC5_IN_INV_SEL_S 6 +/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC5_IN_SEL 0x0000003F +#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) +#define GPIO_FUNC5_IN_SEL_V 0x3F +#define GPIO_FUNC5_IN_SEL_S 0 + +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0148) +/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (BIT(7)) +#define GPIO_SIG6_IN_SEL_V 0x1 +#define GPIO_SIG6_IN_SEL_S 7 +/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_V 0x1 +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC6_IN_SEL 0x0000003F +#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) +#define GPIO_FUNC6_IN_SEL_V 0x3F +#define GPIO_FUNC6_IN_SEL_S 0 + +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x014c) +/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (BIT(7)) +#define GPIO_SIG7_IN_SEL_V 0x1 +#define GPIO_SIG7_IN_SEL_S 7 +/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_V 0x1 +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC7_IN_SEL 0x0000003F +#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) +#define GPIO_FUNC7_IN_SEL_V 0x3F +#define GPIO_FUNC7_IN_SEL_S 0 + +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0150) +/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (BIT(7)) +#define GPIO_SIG8_IN_SEL_V 0x1 +#define GPIO_SIG8_IN_SEL_S 7 +/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_V 0x1 +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC8_IN_SEL 0x0000003F +#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) +#define GPIO_FUNC8_IN_SEL_V 0x3F +#define GPIO_FUNC8_IN_SEL_S 0 + +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0154) +/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (BIT(7)) +#define GPIO_SIG9_IN_SEL_V 0x1 +#define GPIO_SIG9_IN_SEL_S 7 +/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_V 0x1 +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC9_IN_SEL 0x0000003F +#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) +#define GPIO_FUNC9_IN_SEL_V 0x3F +#define GPIO_FUNC9_IN_SEL_S 0 + +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0158) +/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (BIT(7)) +#define GPIO_SIG10_IN_SEL_V 0x1 +#define GPIO_SIG10_IN_SEL_S 7 +/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_V 0x1 +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC10_IN_SEL 0x0000003F +#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) +#define GPIO_FUNC10_IN_SEL_V 0x3F +#define GPIO_FUNC10_IN_SEL_S 0 + +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x015c) +/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (BIT(7)) +#define GPIO_SIG11_IN_SEL_V 0x1 +#define GPIO_SIG11_IN_SEL_S 7 +/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_V 0x1 +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC11_IN_SEL 0x0000003F +#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) +#define GPIO_FUNC11_IN_SEL_V 0x3F +#define GPIO_FUNC11_IN_SEL_S 0 + +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0160) +/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (BIT(7)) +#define GPIO_SIG12_IN_SEL_V 0x1 +#define GPIO_SIG12_IN_SEL_S 7 +/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_V 0x1 +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC12_IN_SEL 0x0000003F +#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) +#define GPIO_FUNC12_IN_SEL_V 0x3F +#define GPIO_FUNC12_IN_SEL_S 0 + +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0164) +/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (BIT(7)) +#define GPIO_SIG13_IN_SEL_V 0x1 +#define GPIO_SIG13_IN_SEL_S 7 +/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_V 0x1 +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC13_IN_SEL 0x0000003F +#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) +#define GPIO_FUNC13_IN_SEL_V 0x3F +#define GPIO_FUNC13_IN_SEL_S 0 + +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0168) +/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (BIT(7)) +#define GPIO_SIG14_IN_SEL_V 0x1 +#define GPIO_SIG14_IN_SEL_S 7 +/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_V 0x1 +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC14_IN_SEL 0x0000003F +#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) +#define GPIO_FUNC14_IN_SEL_V 0x3F +#define GPIO_FUNC14_IN_SEL_S 0 + +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x016c) +/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (BIT(7)) +#define GPIO_SIG15_IN_SEL_V 0x1 +#define GPIO_SIG15_IN_SEL_S 7 +/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_V 0x1 +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC15_IN_SEL 0x0000003F +#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) +#define GPIO_FUNC15_IN_SEL_V 0x3F +#define GPIO_FUNC15_IN_SEL_S 0 + +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0170) +/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (BIT(7)) +#define GPIO_SIG16_IN_SEL_V 0x1 +#define GPIO_SIG16_IN_SEL_S 7 +/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_V 0x1 +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC16_IN_SEL 0x0000003F +#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) +#define GPIO_FUNC16_IN_SEL_V 0x3F +#define GPIO_FUNC16_IN_SEL_S 0 + +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0174) +/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (BIT(7)) +#define GPIO_SIG17_IN_SEL_V 0x1 +#define GPIO_SIG17_IN_SEL_S 7 +/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_V 0x1 +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC17_IN_SEL 0x0000003F +#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) +#define GPIO_FUNC17_IN_SEL_V 0x3F +#define GPIO_FUNC17_IN_SEL_S 0 + +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0178) +/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG18_IN_SEL (BIT(7)) +#define GPIO_SIG18_IN_SEL_M (BIT(7)) +#define GPIO_SIG18_IN_SEL_V 0x1 +#define GPIO_SIG18_IN_SEL_S 7 +/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_V 0x1 +#define GPIO_FUNC18_IN_INV_SEL_S 6 +/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC18_IN_SEL 0x0000003F +#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) +#define GPIO_FUNC18_IN_SEL_V 0x3F +#define GPIO_FUNC18_IN_SEL_S 0 + +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x017c) +/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (BIT(7)) +#define GPIO_SIG19_IN_SEL_V 0x1 +#define GPIO_SIG19_IN_SEL_S 7 +/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_V 0x1 +#define GPIO_FUNC19_IN_INV_SEL_S 6 +/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC19_IN_SEL 0x0000003F +#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) +#define GPIO_FUNC19_IN_SEL_V 0x3F +#define GPIO_FUNC19_IN_SEL_S 0 + +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0180) +/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG20_IN_SEL (BIT(7)) +#define GPIO_SIG20_IN_SEL_M (BIT(7)) +#define GPIO_SIG20_IN_SEL_V 0x1 +#define GPIO_SIG20_IN_SEL_S 7 +/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_V 0x1 +#define GPIO_FUNC20_IN_INV_SEL_S 6 +/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC20_IN_SEL 0x0000003F +#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) +#define GPIO_FUNC20_IN_SEL_V 0x3F +#define GPIO_FUNC20_IN_SEL_S 0 + +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0184) +/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (BIT(7)) +#define GPIO_SIG21_IN_SEL_V 0x1 +#define GPIO_SIG21_IN_SEL_S 7 +/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_V 0x1 +#define GPIO_FUNC21_IN_INV_SEL_S 6 +/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC21_IN_SEL 0x0000003F +#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) +#define GPIO_FUNC21_IN_SEL_V 0x3F +#define GPIO_FUNC21_IN_SEL_S 0 + +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0188) +/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (BIT(7)) +#define GPIO_SIG22_IN_SEL_V 0x1 +#define GPIO_SIG22_IN_SEL_S 7 +/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_V 0x1 +#define GPIO_FUNC22_IN_INV_SEL_S 6 +/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC22_IN_SEL 0x0000003F +#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) +#define GPIO_FUNC22_IN_SEL_V 0x3F +#define GPIO_FUNC22_IN_SEL_S 0 + +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x018c) +/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (BIT(7)) +#define GPIO_SIG23_IN_SEL_V 0x1 +#define GPIO_SIG23_IN_SEL_S 7 +/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_V 0x1 +#define GPIO_FUNC23_IN_INV_SEL_S 6 +/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC23_IN_SEL 0x0000003F +#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) +#define GPIO_FUNC23_IN_SEL_V 0x3F +#define GPIO_FUNC23_IN_SEL_S 0 + +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0190) +/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (BIT(7)) +#define GPIO_SIG24_IN_SEL_V 0x1 +#define GPIO_SIG24_IN_SEL_S 7 +/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_V 0x1 +#define GPIO_FUNC24_IN_INV_SEL_S 6 +/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC24_IN_SEL 0x0000003F +#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) +#define GPIO_FUNC24_IN_SEL_V 0x3F +#define GPIO_FUNC24_IN_SEL_S 0 + +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0194) +/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG25_IN_SEL (BIT(7)) +#define GPIO_SIG25_IN_SEL_M (BIT(7)) +#define GPIO_SIG25_IN_SEL_V 0x1 +#define GPIO_SIG25_IN_SEL_S 7 +/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_V 0x1 +#define GPIO_FUNC25_IN_INV_SEL_S 6 +/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC25_IN_SEL 0x0000003F +#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) +#define GPIO_FUNC25_IN_SEL_V 0x3F +#define GPIO_FUNC25_IN_SEL_S 0 + +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0198) +/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG26_IN_SEL (BIT(7)) +#define GPIO_SIG26_IN_SEL_M (BIT(7)) +#define GPIO_SIG26_IN_SEL_V 0x1 +#define GPIO_SIG26_IN_SEL_S 7 +/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_V 0x1 +#define GPIO_FUNC26_IN_INV_SEL_S 6 +/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC26_IN_SEL 0x0000003F +#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) +#define GPIO_FUNC26_IN_SEL_V 0x3F +#define GPIO_FUNC26_IN_SEL_S 0 + +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x019c) +/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL_M (BIT(7)) +#define GPIO_SIG27_IN_SEL_V 0x1 +#define GPIO_SIG27_IN_SEL_S 7 +/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_V 0x1 +#define GPIO_FUNC27_IN_INV_SEL_S 6 +/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC27_IN_SEL 0x0000003F +#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) +#define GPIO_FUNC27_IN_SEL_V 0x3F +#define GPIO_FUNC27_IN_SEL_S 0 + +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a0) +/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (BIT(7)) +#define GPIO_SIG28_IN_SEL_V 0x1 +#define GPIO_SIG28_IN_SEL_S 7 +/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_V 0x1 +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC28_IN_SEL 0x0000003F +#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) +#define GPIO_FUNC28_IN_SEL_V 0x3F +#define GPIO_FUNC28_IN_SEL_S 0 + +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a4) +/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (BIT(7)) +#define GPIO_SIG29_IN_SEL_V 0x1 +#define GPIO_SIG29_IN_SEL_S 7 +/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_V 0x1 +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC29_IN_SEL 0x0000003F +#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) +#define GPIO_FUNC29_IN_SEL_V 0x3F +#define GPIO_FUNC29_IN_SEL_S 0 + +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a8) +/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (BIT(7)) +#define GPIO_SIG30_IN_SEL_V 0x1 +#define GPIO_SIG30_IN_SEL_S 7 +/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_V 0x1 +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC30_IN_SEL 0x0000003F +#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) +#define GPIO_FUNC30_IN_SEL_V 0x3F +#define GPIO_FUNC30_IN_SEL_S 0 + +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ac) +/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (BIT(7)) +#define GPIO_SIG31_IN_SEL_V 0x1 +#define GPIO_SIG31_IN_SEL_S 7 +/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_V 0x1 +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC31_IN_SEL 0x0000003F +#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) +#define GPIO_FUNC31_IN_SEL_V 0x3F +#define GPIO_FUNC31_IN_SEL_S 0 + +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b0) +/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (BIT(7)) +#define GPIO_SIG32_IN_SEL_V 0x1 +#define GPIO_SIG32_IN_SEL_S 7 +/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_V 0x1 +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC32_IN_SEL 0x0000003F +#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) +#define GPIO_FUNC32_IN_SEL_V 0x3F +#define GPIO_FUNC32_IN_SEL_S 0 + +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b4) +/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (BIT(7)) +#define GPIO_SIG33_IN_SEL_V 0x1 +#define GPIO_SIG33_IN_SEL_S 7 +/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_V 0x1 +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC33_IN_SEL 0x0000003F +#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) +#define GPIO_FUNC33_IN_SEL_V 0x3F +#define GPIO_FUNC33_IN_SEL_S 0 + +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b8) +/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (BIT(7)) +#define GPIO_SIG34_IN_SEL_V 0x1 +#define GPIO_SIG34_IN_SEL_S 7 +/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_V 0x1 +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC34_IN_SEL 0x0000003F +#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) +#define GPIO_FUNC34_IN_SEL_V 0x3F +#define GPIO_FUNC34_IN_SEL_S 0 + +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01bc) +/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (BIT(7)) +#define GPIO_SIG35_IN_SEL_V 0x1 +#define GPIO_SIG35_IN_SEL_S 7 +/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_V 0x1 +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC35_IN_SEL 0x0000003F +#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) +#define GPIO_FUNC35_IN_SEL_V 0x3F +#define GPIO_FUNC35_IN_SEL_S 0 + +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c0) +/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG36_IN_SEL (BIT(7)) +#define GPIO_SIG36_IN_SEL_M (BIT(7)) +#define GPIO_SIG36_IN_SEL_V 0x1 +#define GPIO_SIG36_IN_SEL_S 7 +/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_V 0x1 +#define GPIO_FUNC36_IN_INV_SEL_S 6 +/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC36_IN_SEL 0x0000003F +#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) +#define GPIO_FUNC36_IN_SEL_V 0x3F +#define GPIO_FUNC36_IN_SEL_S 0 + +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c4) +/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG37_IN_SEL (BIT(7)) +#define GPIO_SIG37_IN_SEL_M (BIT(7)) +#define GPIO_SIG37_IN_SEL_V 0x1 +#define GPIO_SIG37_IN_SEL_S 7 +/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_V 0x1 +#define GPIO_FUNC37_IN_INV_SEL_S 6 +/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC37_IN_SEL 0x0000003F +#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) +#define GPIO_FUNC37_IN_SEL_V 0x3F +#define GPIO_FUNC37_IN_SEL_S 0 + +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c8) +/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG38_IN_SEL (BIT(7)) +#define GPIO_SIG38_IN_SEL_M (BIT(7)) +#define GPIO_SIG38_IN_SEL_V 0x1 +#define GPIO_SIG38_IN_SEL_S 7 +/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_V 0x1 +#define GPIO_FUNC38_IN_INV_SEL_S 6 +/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC38_IN_SEL 0x0000003F +#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) +#define GPIO_FUNC38_IN_SEL_V 0x3F +#define GPIO_FUNC38_IN_SEL_S 0 + +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01cc) +/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG39_IN_SEL (BIT(7)) +#define GPIO_SIG39_IN_SEL_M (BIT(7)) +#define GPIO_SIG39_IN_SEL_V 0x1 +#define GPIO_SIG39_IN_SEL_S 7 +/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_V 0x1 +#define GPIO_FUNC39_IN_INV_SEL_S 6 +/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC39_IN_SEL 0x0000003F +#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) +#define GPIO_FUNC39_IN_SEL_V 0x3F +#define GPIO_FUNC39_IN_SEL_S 0 + +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d0) +/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (BIT(7)) +#define GPIO_SIG40_IN_SEL_V 0x1 +#define GPIO_SIG40_IN_SEL_S 7 +/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_V 0x1 +#define GPIO_FUNC40_IN_INV_SEL_S 6 +/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC40_IN_SEL 0x0000003F +#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) +#define GPIO_FUNC40_IN_SEL_V 0x3F +#define GPIO_FUNC40_IN_SEL_S 0 + +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d4) +/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (BIT(7)) +#define GPIO_SIG41_IN_SEL_V 0x1 +#define GPIO_SIG41_IN_SEL_S 7 +/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_V 0x1 +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC41_IN_SEL 0x0000003F +#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) +#define GPIO_FUNC41_IN_SEL_V 0x3F +#define GPIO_FUNC41_IN_SEL_S 0 + +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d8) +/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (BIT(7)) +#define GPIO_SIG42_IN_SEL_V 0x1 +#define GPIO_SIG42_IN_SEL_S 7 +/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_V 0x1 +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC42_IN_SEL 0x0000003F +#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) +#define GPIO_FUNC42_IN_SEL_V 0x3F +#define GPIO_FUNC42_IN_SEL_S 0 + +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01dc) +/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL_M (BIT(7)) +#define GPIO_SIG43_IN_SEL_V 0x1 +#define GPIO_SIG43_IN_SEL_S 7 +/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_V 0x1 +#define GPIO_FUNC43_IN_INV_SEL_S 6 +/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC43_IN_SEL 0x0000003F +#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) +#define GPIO_FUNC43_IN_SEL_V 0x3F +#define GPIO_FUNC43_IN_SEL_S 0 + +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e0) +/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG44_IN_SEL (BIT(7)) +#define GPIO_SIG44_IN_SEL_M (BIT(7)) +#define GPIO_SIG44_IN_SEL_V 0x1 +#define GPIO_SIG44_IN_SEL_S 7 +/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_V 0x1 +#define GPIO_FUNC44_IN_INV_SEL_S 6 +/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC44_IN_SEL 0x0000003F +#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) +#define GPIO_FUNC44_IN_SEL_V 0x3F +#define GPIO_FUNC44_IN_SEL_S 0 + +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e4) +/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (BIT(7)) +#define GPIO_SIG45_IN_SEL_V 0x1 +#define GPIO_SIG45_IN_SEL_S 7 +/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_V 0x1 +#define GPIO_FUNC45_IN_INV_SEL_S 6 +/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC45_IN_SEL 0x0000003F +#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) +#define GPIO_FUNC45_IN_SEL_V 0x3F +#define GPIO_FUNC45_IN_SEL_S 0 + +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e8) +/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (BIT(7)) +#define GPIO_SIG46_IN_SEL_V 0x1 +#define GPIO_SIG46_IN_SEL_S 7 +/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_V 0x1 +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC46_IN_SEL 0x0000003F +#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) +#define GPIO_FUNC46_IN_SEL_V 0x3F +#define GPIO_FUNC46_IN_SEL_S 0 + +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ec) +/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (BIT(7)) +#define GPIO_SIG47_IN_SEL_V 0x1 +#define GPIO_SIG47_IN_SEL_S 7 +/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_V 0x1 +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC47_IN_SEL 0x0000003F +#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) +#define GPIO_FUNC47_IN_SEL_V 0x3F +#define GPIO_FUNC47_IN_SEL_S 0 + +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f0) +/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (BIT(7)) +#define GPIO_SIG48_IN_SEL_V 0x1 +#define GPIO_SIG48_IN_SEL_S 7 +/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_V 0x1 +#define GPIO_FUNC48_IN_INV_SEL_S 6 +/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC48_IN_SEL 0x0000003F +#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) +#define GPIO_FUNC48_IN_SEL_V 0x3F +#define GPIO_FUNC48_IN_SEL_S 0 + +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f4) +/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (BIT(7)) +#define GPIO_SIG49_IN_SEL_V 0x1 +#define GPIO_SIG49_IN_SEL_S 7 +/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_V 0x1 +#define GPIO_FUNC49_IN_INV_SEL_S 6 +/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC49_IN_SEL 0x0000003F +#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) +#define GPIO_FUNC49_IN_SEL_V 0x3F +#define GPIO_FUNC49_IN_SEL_S 0 + +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f8) +/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (BIT(7)) +#define GPIO_SIG50_IN_SEL_V 0x1 +#define GPIO_SIG50_IN_SEL_S 7 +/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_V 0x1 +#define GPIO_FUNC50_IN_INV_SEL_S 6 +/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC50_IN_SEL 0x0000003F +#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) +#define GPIO_FUNC50_IN_SEL_V 0x3F +#define GPIO_FUNC50_IN_SEL_S 0 + +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01fc) +/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (BIT(7)) +#define GPIO_SIG51_IN_SEL_V 0x1 +#define GPIO_SIG51_IN_SEL_S 7 +/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_V 0x1 +#define GPIO_FUNC51_IN_INV_SEL_S 6 +/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC51_IN_SEL 0x0000003F +#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) +#define GPIO_FUNC51_IN_SEL_V 0x3F +#define GPIO_FUNC51_IN_SEL_S 0 + +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0200) +/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (BIT(7)) +#define GPIO_SIG52_IN_SEL_V 0x1 +#define GPIO_SIG52_IN_SEL_S 7 +/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_V 0x1 +#define GPIO_FUNC52_IN_INV_SEL_S 6 +/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC52_IN_SEL 0x0000003F +#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) +#define GPIO_FUNC52_IN_SEL_V 0x3F +#define GPIO_FUNC52_IN_SEL_S 0 + +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0204) +/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (BIT(7)) +#define GPIO_SIG53_IN_SEL_V 0x1 +#define GPIO_SIG53_IN_SEL_S 7 +/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_V 0x1 +#define GPIO_FUNC53_IN_INV_SEL_S 6 +/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC53_IN_SEL 0x0000003F +#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) +#define GPIO_FUNC53_IN_SEL_V 0x3F +#define GPIO_FUNC53_IN_SEL_S 0 + +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0208) +/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (BIT(7)) +#define GPIO_SIG54_IN_SEL_V 0x1 +#define GPIO_SIG54_IN_SEL_S 7 +/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_V 0x1 +#define GPIO_FUNC54_IN_INV_SEL_S 6 +/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC54_IN_SEL 0x0000003F +#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) +#define GPIO_FUNC54_IN_SEL_V 0x3F +#define GPIO_FUNC54_IN_SEL_S 0 + +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x020c) +/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (BIT(7)) +#define GPIO_SIG55_IN_SEL_V 0x1 +#define GPIO_SIG55_IN_SEL_S 7 +/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_V 0x1 +#define GPIO_FUNC55_IN_INV_SEL_S 6 +/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC55_IN_SEL 0x0000003F +#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) +#define GPIO_FUNC55_IN_SEL_V 0x3F +#define GPIO_FUNC55_IN_SEL_S 0 + +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0210) +/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (BIT(7)) +#define GPIO_SIG56_IN_SEL_V 0x1 +#define GPIO_SIG56_IN_SEL_S 7 +/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_V 0x1 +#define GPIO_FUNC56_IN_INV_SEL_S 6 +/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC56_IN_SEL 0x0000003F +#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) +#define GPIO_FUNC56_IN_SEL_V 0x3F +#define GPIO_FUNC56_IN_SEL_S 0 + +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0214) +/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL_M (BIT(7)) +#define GPIO_SIG57_IN_SEL_V 0x1 +#define GPIO_SIG57_IN_SEL_S 7 +/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_V 0x1 +#define GPIO_FUNC57_IN_INV_SEL_S 6 +/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC57_IN_SEL 0x0000003F +#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) +#define GPIO_FUNC57_IN_SEL_V 0x3F +#define GPIO_FUNC57_IN_SEL_S 0 + +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0218) +/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL_M (BIT(7)) +#define GPIO_SIG58_IN_SEL_V 0x1 +#define GPIO_SIG58_IN_SEL_S 7 +/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_V 0x1 +#define GPIO_FUNC58_IN_INV_SEL_S 6 +/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC58_IN_SEL 0x0000003F +#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) +#define GPIO_FUNC58_IN_SEL_V 0x3F +#define GPIO_FUNC58_IN_SEL_S 0 + +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x021c) +/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL_M (BIT(7)) +#define GPIO_SIG59_IN_SEL_V 0x1 +#define GPIO_SIG59_IN_SEL_S 7 +/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_V 0x1 +#define GPIO_FUNC59_IN_INV_SEL_S 6 +/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC59_IN_SEL 0x0000003F +#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) +#define GPIO_FUNC59_IN_SEL_V 0x3F +#define GPIO_FUNC59_IN_SEL_S 0 + +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0220) +/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL_M (BIT(7)) +#define GPIO_SIG60_IN_SEL_V 0x1 +#define GPIO_SIG60_IN_SEL_S 7 +/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_V 0x1 +#define GPIO_FUNC60_IN_INV_SEL_S 6 +/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC60_IN_SEL 0x0000003F +#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) +#define GPIO_FUNC60_IN_SEL_V 0x3F +#define GPIO_FUNC60_IN_SEL_S 0 + +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0224) +/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL_M (BIT(7)) +#define GPIO_SIG61_IN_SEL_V 0x1 +#define GPIO_SIG61_IN_SEL_S 7 +/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_V 0x1 +#define GPIO_FUNC61_IN_INV_SEL_S 6 +/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC61_IN_SEL 0x0000003F +#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) +#define GPIO_FUNC61_IN_SEL_V 0x3F +#define GPIO_FUNC61_IN_SEL_S 0 + +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0228) +/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL_M (BIT(7)) +#define GPIO_SIG62_IN_SEL_V 0x1 +#define GPIO_SIG62_IN_SEL_S 7 +/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_V 0x1 +#define GPIO_FUNC62_IN_INV_SEL_S 6 +/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC62_IN_SEL 0x0000003F +#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) +#define GPIO_FUNC62_IN_SEL_V 0x3F +#define GPIO_FUNC62_IN_SEL_S 0 + +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x022c) +/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (BIT(7)) +#define GPIO_SIG63_IN_SEL_V 0x1 +#define GPIO_SIG63_IN_SEL_S 7 +/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_V 0x1 +#define GPIO_FUNC63_IN_INV_SEL_S 6 +/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC63_IN_SEL 0x0000003F +#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) +#define GPIO_FUNC63_IN_SEL_V 0x3F +#define GPIO_FUNC63_IN_SEL_S 0 + +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0230) +/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (BIT(7)) +#define GPIO_SIG64_IN_SEL_V 0x1 +#define GPIO_SIG64_IN_SEL_S 7 +/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_V 0x1 +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC64_IN_SEL 0x0000003F +#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) +#define GPIO_FUNC64_IN_SEL_V 0x3F +#define GPIO_FUNC64_IN_SEL_S 0 + +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0234) +/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (BIT(7)) +#define GPIO_SIG65_IN_SEL_V 0x1 +#define GPIO_SIG65_IN_SEL_S 7 +/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_V 0x1 +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC65_IN_SEL 0x0000003F +#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) +#define GPIO_FUNC65_IN_SEL_V 0x3F +#define GPIO_FUNC65_IN_SEL_S 0 + +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0238) +/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (BIT(7)) +#define GPIO_SIG66_IN_SEL_V 0x1 +#define GPIO_SIG66_IN_SEL_S 7 +/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_V 0x1 +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC66_IN_SEL 0x0000003F +#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) +#define GPIO_FUNC66_IN_SEL_V 0x3F +#define GPIO_FUNC66_IN_SEL_S 0 + +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x023c) +/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (BIT(7)) +#define GPIO_SIG67_IN_SEL_V 0x1 +#define GPIO_SIG67_IN_SEL_S 7 +/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_V 0x1 +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC67_IN_SEL 0x0000003F +#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) +#define GPIO_FUNC67_IN_SEL_V 0x3F +#define GPIO_FUNC67_IN_SEL_S 0 + +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0240) +/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (BIT(7)) +#define GPIO_SIG68_IN_SEL_V 0x1 +#define GPIO_SIG68_IN_SEL_S 7 +/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_V 0x1 +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC68_IN_SEL 0x0000003F +#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) +#define GPIO_FUNC68_IN_SEL_V 0x3F +#define GPIO_FUNC68_IN_SEL_S 0 + +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0244) +/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (BIT(7)) +#define GPIO_SIG69_IN_SEL_V 0x1 +#define GPIO_SIG69_IN_SEL_S 7 +/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_V 0x1 +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC69_IN_SEL 0x0000003F +#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) +#define GPIO_FUNC69_IN_SEL_V 0x3F +#define GPIO_FUNC69_IN_SEL_S 0 + +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0248) +/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (BIT(7)) +#define GPIO_SIG70_IN_SEL_V 0x1 +#define GPIO_SIG70_IN_SEL_S 7 +/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_V 0x1 +#define GPIO_FUNC70_IN_INV_SEL_S 6 +/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC70_IN_SEL 0x0000003F +#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) +#define GPIO_FUNC70_IN_SEL_V 0x3F +#define GPIO_FUNC70_IN_SEL_S 0 + +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x024c) +/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (BIT(7)) +#define GPIO_SIG71_IN_SEL_V 0x1 +#define GPIO_SIG71_IN_SEL_S 7 +/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_V 0x1 +#define GPIO_FUNC71_IN_INV_SEL_S 6 +/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC71_IN_SEL 0x0000003F +#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) +#define GPIO_FUNC71_IN_SEL_V 0x3F +#define GPIO_FUNC71_IN_SEL_S 0 + +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0250) +/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (BIT(7)) +#define GPIO_SIG72_IN_SEL_V 0x1 +#define GPIO_SIG72_IN_SEL_S 7 +/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_V 0x1 +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC72_IN_SEL 0x0000003F +#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) +#define GPIO_FUNC72_IN_SEL_V 0x3F +#define GPIO_FUNC72_IN_SEL_S 0 + +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0254) +/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (BIT(7)) +#define GPIO_SIG73_IN_SEL_V 0x1 +#define GPIO_SIG73_IN_SEL_S 7 +/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_V 0x1 +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC73_IN_SEL 0x0000003F +#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) +#define GPIO_FUNC73_IN_SEL_V 0x3F +#define GPIO_FUNC73_IN_SEL_S 0 + +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0258) +/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL_M (BIT(7)) +#define GPIO_SIG74_IN_SEL_V 0x1 +#define GPIO_SIG74_IN_SEL_S 7 +/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_V 0x1 +#define GPIO_FUNC74_IN_INV_SEL_S 6 +/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC74_IN_SEL 0x0000003F +#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) +#define GPIO_FUNC74_IN_SEL_V 0x3F +#define GPIO_FUNC74_IN_SEL_S 0 + +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x025c) +/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG75_IN_SEL (BIT(7)) +#define GPIO_SIG75_IN_SEL_M (BIT(7)) +#define GPIO_SIG75_IN_SEL_V 0x1 +#define GPIO_SIG75_IN_SEL_S 7 +/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_V 0x1 +#define GPIO_FUNC75_IN_INV_SEL_S 6 +/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC75_IN_SEL 0x0000003F +#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) +#define GPIO_FUNC75_IN_SEL_V 0x3F +#define GPIO_FUNC75_IN_SEL_S 0 + +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0260) +/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG76_IN_SEL (BIT(7)) +#define GPIO_SIG76_IN_SEL_M (BIT(7)) +#define GPIO_SIG76_IN_SEL_V 0x1 +#define GPIO_SIG76_IN_SEL_S 7 +/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_V 0x1 +#define GPIO_FUNC76_IN_INV_SEL_S 6 +/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC76_IN_SEL 0x0000003F +#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) +#define GPIO_FUNC76_IN_SEL_V 0x3F +#define GPIO_FUNC76_IN_SEL_S 0 + +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0264) +/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (BIT(7)) +#define GPIO_SIG77_IN_SEL_V 0x1 +#define GPIO_SIG77_IN_SEL_S 7 +/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_V 0x1 +#define GPIO_FUNC77_IN_INV_SEL_S 6 +/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC77_IN_SEL 0x0000003F +#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) +#define GPIO_FUNC77_IN_SEL_V 0x3F +#define GPIO_FUNC77_IN_SEL_S 0 + +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0268) +/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG78_IN_SEL (BIT(7)) +#define GPIO_SIG78_IN_SEL_M (BIT(7)) +#define GPIO_SIG78_IN_SEL_V 0x1 +#define GPIO_SIG78_IN_SEL_S 7 +/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_V 0x1 +#define GPIO_FUNC78_IN_INV_SEL_S 6 +/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC78_IN_SEL 0x0000003F +#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) +#define GPIO_FUNC78_IN_SEL_V 0x3F +#define GPIO_FUNC78_IN_SEL_S 0 + +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x026c) +/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG79_IN_SEL (BIT(7)) +#define GPIO_SIG79_IN_SEL_M (BIT(7)) +#define GPIO_SIG79_IN_SEL_V 0x1 +#define GPIO_SIG79_IN_SEL_S 7 +/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_V 0x1 +#define GPIO_FUNC79_IN_INV_SEL_S 6 +/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC79_IN_SEL 0x0000003F +#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) +#define GPIO_FUNC79_IN_SEL_V 0x3F +#define GPIO_FUNC79_IN_SEL_S 0 + +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0270) +/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG80_IN_SEL (BIT(7)) +#define GPIO_SIG80_IN_SEL_M (BIT(7)) +#define GPIO_SIG80_IN_SEL_V 0x1 +#define GPIO_SIG80_IN_SEL_S 7 +/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_V 0x1 +#define GPIO_FUNC80_IN_INV_SEL_S 6 +/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC80_IN_SEL 0x0000003F +#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) +#define GPIO_FUNC80_IN_SEL_V 0x3F +#define GPIO_FUNC80_IN_SEL_S 0 + +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0274) +/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (BIT(7)) +#define GPIO_SIG81_IN_SEL_V 0x1 +#define GPIO_SIG81_IN_SEL_S 7 +/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_V 0x1 +#define GPIO_FUNC81_IN_INV_SEL_S 6 +/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC81_IN_SEL 0x0000003F +#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) +#define GPIO_FUNC81_IN_SEL_V 0x3F +#define GPIO_FUNC81_IN_SEL_S 0 + +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0278) +/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (BIT(7)) +#define GPIO_SIG82_IN_SEL_V 0x1 +#define GPIO_SIG82_IN_SEL_S 7 +/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_V 0x1 +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC82_IN_SEL 0x0000003F +#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) +#define GPIO_FUNC82_IN_SEL_V 0x3F +#define GPIO_FUNC82_IN_SEL_S 0 + +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x027c) +/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (BIT(7)) +#define GPIO_SIG83_IN_SEL_V 0x1 +#define GPIO_SIG83_IN_SEL_S 7 +/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_V 0x1 +#define GPIO_FUNC83_IN_INV_SEL_S 6 +/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC83_IN_SEL 0x0000003F +#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) +#define GPIO_FUNC83_IN_SEL_V 0x3F +#define GPIO_FUNC83_IN_SEL_S 0 + +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0280) +/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (BIT(7)) +#define GPIO_SIG84_IN_SEL_V 0x1 +#define GPIO_SIG84_IN_SEL_S 7 +/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_V 0x1 +#define GPIO_FUNC84_IN_INV_SEL_S 6 +/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC84_IN_SEL 0x0000003F +#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) +#define GPIO_FUNC84_IN_SEL_V 0x3F +#define GPIO_FUNC84_IN_SEL_S 0 + +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0284) +/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (BIT(7)) +#define GPIO_SIG85_IN_SEL_V 0x1 +#define GPIO_SIG85_IN_SEL_S 7 +/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_V 0x1 +#define GPIO_FUNC85_IN_INV_SEL_S 6 +/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC85_IN_SEL 0x0000003F +#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) +#define GPIO_FUNC85_IN_SEL_V 0x3F +#define GPIO_FUNC85_IN_SEL_S 0 + +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0288) +/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (BIT(7)) +#define GPIO_SIG86_IN_SEL_V 0x1 +#define GPIO_SIG86_IN_SEL_S 7 +/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_V 0x1 +#define GPIO_FUNC86_IN_INV_SEL_S 6 +/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC86_IN_SEL 0x0000003F +#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) +#define GPIO_FUNC86_IN_SEL_V 0x3F +#define GPIO_FUNC86_IN_SEL_S 0 + +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x028c) +/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (BIT(7)) +#define GPIO_SIG87_IN_SEL_V 0x1 +#define GPIO_SIG87_IN_SEL_S 7 +/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_V 0x1 +#define GPIO_FUNC87_IN_INV_SEL_S 6 +/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC87_IN_SEL 0x0000003F +#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) +#define GPIO_FUNC87_IN_SEL_V 0x3F +#define GPIO_FUNC87_IN_SEL_S 0 + +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0290) +/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (BIT(7)) +#define GPIO_SIG88_IN_SEL_V 0x1 +#define GPIO_SIG88_IN_SEL_S 7 +/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_V 0x1 +#define GPIO_FUNC88_IN_INV_SEL_S 6 +/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC88_IN_SEL 0x0000003F +#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) +#define GPIO_FUNC88_IN_SEL_V 0x3F +#define GPIO_FUNC88_IN_SEL_S 0 + +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0294) +/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (BIT(7)) +#define GPIO_SIG89_IN_SEL_V 0x1 +#define GPIO_SIG89_IN_SEL_S 7 +/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_V 0x1 +#define GPIO_FUNC89_IN_INV_SEL_S 6 +/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC89_IN_SEL 0x0000003F +#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) +#define GPIO_FUNC89_IN_SEL_V 0x3F +#define GPIO_FUNC89_IN_SEL_S 0 + +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0298) +/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (BIT(7)) +#define GPIO_SIG90_IN_SEL_V 0x1 +#define GPIO_SIG90_IN_SEL_S 7 +/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_V 0x1 +#define GPIO_FUNC90_IN_INV_SEL_S 6 +/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC90_IN_SEL 0x0000003F +#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) +#define GPIO_FUNC90_IN_SEL_V 0x3F +#define GPIO_FUNC90_IN_SEL_S 0 + +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x029c) +/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (BIT(7)) +#define GPIO_SIG91_IN_SEL_V 0x1 +#define GPIO_SIG91_IN_SEL_S 7 +/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_V 0x1 +#define GPIO_FUNC91_IN_INV_SEL_S 6 +/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC91_IN_SEL 0x0000003F +#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) +#define GPIO_FUNC91_IN_SEL_V 0x3F +#define GPIO_FUNC91_IN_SEL_S 0 + +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a0) +/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (BIT(7)) +#define GPIO_SIG92_IN_SEL_V 0x1 +#define GPIO_SIG92_IN_SEL_S 7 +/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_V 0x1 +#define GPIO_FUNC92_IN_INV_SEL_S 6 +/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC92_IN_SEL 0x0000003F +#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) +#define GPIO_FUNC92_IN_SEL_V 0x3F +#define GPIO_FUNC92_IN_SEL_S 0 + +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a4) +/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (BIT(7)) +#define GPIO_SIG93_IN_SEL_V 0x1 +#define GPIO_SIG93_IN_SEL_S 7 +/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_V 0x1 +#define GPIO_FUNC93_IN_INV_SEL_S 6 +/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC93_IN_SEL 0x0000003F +#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) +#define GPIO_FUNC93_IN_SEL_V 0x3F +#define GPIO_FUNC93_IN_SEL_S 0 + +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a8) +/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (BIT(7)) +#define GPIO_SIG94_IN_SEL_V 0x1 +#define GPIO_SIG94_IN_SEL_S 7 +/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_V 0x1 +#define GPIO_FUNC94_IN_INV_SEL_S 6 +/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC94_IN_SEL 0x0000003F +#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) +#define GPIO_FUNC94_IN_SEL_V 0x3F +#define GPIO_FUNC94_IN_SEL_S 0 + +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ac) +/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (BIT(7)) +#define GPIO_SIG95_IN_SEL_V 0x1 +#define GPIO_SIG95_IN_SEL_S 7 +/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_V 0x1 +#define GPIO_FUNC95_IN_INV_SEL_S 6 +/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC95_IN_SEL 0x0000003F +#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) +#define GPIO_FUNC95_IN_SEL_V 0x3F +#define GPIO_FUNC95_IN_SEL_S 0 + +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b0) +/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG96_IN_SEL (BIT(7)) +#define GPIO_SIG96_IN_SEL_M (BIT(7)) +#define GPIO_SIG96_IN_SEL_V 0x1 +#define GPIO_SIG96_IN_SEL_S 7 +/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_V 0x1 +#define GPIO_FUNC96_IN_INV_SEL_S 6 +/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC96_IN_SEL 0x0000003F +#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) +#define GPIO_FUNC96_IN_SEL_V 0x3F +#define GPIO_FUNC96_IN_SEL_S 0 + +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b4) +/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (BIT(7)) +#define GPIO_SIG97_IN_SEL_V 0x1 +#define GPIO_SIG97_IN_SEL_S 7 +/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_V 0x1 +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC97_IN_SEL 0x0000003F +#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) +#define GPIO_FUNC97_IN_SEL_V 0x3F +#define GPIO_FUNC97_IN_SEL_S 0 + +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b8) +/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (BIT(7)) +#define GPIO_SIG98_IN_SEL_V 0x1 +#define GPIO_SIG98_IN_SEL_S 7 +/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_V 0x1 +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC98_IN_SEL 0x0000003F +#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) +#define GPIO_FUNC98_IN_SEL_V 0x3F +#define GPIO_FUNC98_IN_SEL_S 0 + +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02bc) +/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (BIT(7)) +#define GPIO_SIG99_IN_SEL_V 0x1 +#define GPIO_SIG99_IN_SEL_S 7 +/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_V 0x1 +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC99_IN_SEL 0x0000003F +#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) +#define GPIO_FUNC99_IN_SEL_V 0x3F +#define GPIO_FUNC99_IN_SEL_S 0 + +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c0) +/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (BIT(7)) +#define GPIO_SIG100_IN_SEL_V 0x1 +#define GPIO_SIG100_IN_SEL_S 7 +/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_V 0x1 +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC100_IN_SEL 0x0000003F +#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) +#define GPIO_FUNC100_IN_SEL_V 0x3F +#define GPIO_FUNC100_IN_SEL_S 0 + +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c4) +/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (BIT(7)) +#define GPIO_SIG101_IN_SEL_V 0x1 +#define GPIO_SIG101_IN_SEL_S 7 +/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_V 0x1 +#define GPIO_FUNC101_IN_INV_SEL_S 6 +/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC101_IN_SEL 0x0000003F +#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) +#define GPIO_FUNC101_IN_SEL_V 0x3F +#define GPIO_FUNC101_IN_SEL_S 0 + +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c8) +/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (BIT(7)) +#define GPIO_SIG102_IN_SEL_V 0x1 +#define GPIO_SIG102_IN_SEL_S 7 +/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_V 0x1 +#define GPIO_FUNC102_IN_INV_SEL_S 6 +/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC102_IN_SEL 0x0000003F +#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) +#define GPIO_FUNC102_IN_SEL_V 0x3F +#define GPIO_FUNC102_IN_SEL_S 0 + +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02cc) +/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (BIT(7)) +#define GPIO_SIG103_IN_SEL_V 0x1 +#define GPIO_SIG103_IN_SEL_S 7 +/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_V 0x1 +#define GPIO_FUNC103_IN_INV_SEL_S 6 +/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC103_IN_SEL 0x0000003F +#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) +#define GPIO_FUNC103_IN_SEL_V 0x3F +#define GPIO_FUNC103_IN_SEL_S 0 + +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d0) +/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (BIT(7)) +#define GPIO_SIG104_IN_SEL_V 0x1 +#define GPIO_SIG104_IN_SEL_S 7 +/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_V 0x1 +#define GPIO_FUNC104_IN_INV_SEL_S 6 +/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC104_IN_SEL 0x0000003F +#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) +#define GPIO_FUNC104_IN_SEL_V 0x3F +#define GPIO_FUNC104_IN_SEL_S 0 + +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d4) +/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (BIT(7)) +#define GPIO_SIG105_IN_SEL_V 0x1 +#define GPIO_SIG105_IN_SEL_S 7 +/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_V 0x1 +#define GPIO_FUNC105_IN_INV_SEL_S 6 +/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC105_IN_SEL 0x0000003F +#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) +#define GPIO_FUNC105_IN_SEL_V 0x3F +#define GPIO_FUNC105_IN_SEL_S 0 + +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d8) +/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (BIT(7)) +#define GPIO_SIG106_IN_SEL_V 0x1 +#define GPIO_SIG106_IN_SEL_S 7 +/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_V 0x1 +#define GPIO_FUNC106_IN_INV_SEL_S 6 +/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC106_IN_SEL 0x0000003F +#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) +#define GPIO_FUNC106_IN_SEL_V 0x3F +#define GPIO_FUNC106_IN_SEL_S 0 + +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02dc) +/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (BIT(7)) +#define GPIO_SIG107_IN_SEL_V 0x1 +#define GPIO_SIG107_IN_SEL_S 7 +/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_V 0x1 +#define GPIO_FUNC107_IN_INV_SEL_S 6 +/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC107_IN_SEL 0x0000003F +#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) +#define GPIO_FUNC107_IN_SEL_V 0x3F +#define GPIO_FUNC107_IN_SEL_S 0 + +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e0) +/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (BIT(7)) +#define GPIO_SIG108_IN_SEL_V 0x1 +#define GPIO_SIG108_IN_SEL_S 7 +/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_V 0x1 +#define GPIO_FUNC108_IN_INV_SEL_S 6 +/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC108_IN_SEL 0x0000003F +#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) +#define GPIO_FUNC108_IN_SEL_V 0x3F +#define GPIO_FUNC108_IN_SEL_S 0 + +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e4) +/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (BIT(7)) +#define GPIO_SIG109_IN_SEL_V 0x1 +#define GPIO_SIG109_IN_SEL_S 7 +/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_V 0x1 +#define GPIO_FUNC109_IN_INV_SEL_S 6 +/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC109_IN_SEL 0x0000003F +#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) +#define GPIO_FUNC109_IN_SEL_V 0x3F +#define GPIO_FUNC109_IN_SEL_S 0 + +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e8) +/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (BIT(7)) +#define GPIO_SIG110_IN_SEL_V 0x1 +#define GPIO_SIG110_IN_SEL_S 7 +/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_V 0x1 +#define GPIO_FUNC110_IN_INV_SEL_S 6 +/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC110_IN_SEL 0x0000003F +#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) +#define GPIO_FUNC110_IN_SEL_V 0x3F +#define GPIO_FUNC110_IN_SEL_S 0 + +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ec) +/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (BIT(7)) +#define GPIO_SIG111_IN_SEL_V 0x1 +#define GPIO_SIG111_IN_SEL_S 7 +/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_V 0x1 +#define GPIO_FUNC111_IN_INV_SEL_S 6 +/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC111_IN_SEL 0x0000003F +#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) +#define GPIO_FUNC111_IN_SEL_V 0x3F +#define GPIO_FUNC111_IN_SEL_S 0 + +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f0) +/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (BIT(7)) +#define GPIO_SIG112_IN_SEL_V 0x1 +#define GPIO_SIG112_IN_SEL_S 7 +/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_V 0x1 +#define GPIO_FUNC112_IN_INV_SEL_S 6 +/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC112_IN_SEL 0x0000003F +#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) +#define GPIO_FUNC112_IN_SEL_V 0x3F +#define GPIO_FUNC112_IN_SEL_S 0 + +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f4) +/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (BIT(7)) +#define GPIO_SIG113_IN_SEL_V 0x1 +#define GPIO_SIG113_IN_SEL_S 7 +/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_V 0x1 +#define GPIO_FUNC113_IN_INV_SEL_S 6 +/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC113_IN_SEL 0x0000003F +#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) +#define GPIO_FUNC113_IN_SEL_V 0x3F +#define GPIO_FUNC113_IN_SEL_S 0 + +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f8) +/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (BIT(7)) +#define GPIO_SIG114_IN_SEL_V 0x1 +#define GPIO_SIG114_IN_SEL_S 7 +/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_V 0x1 +#define GPIO_FUNC114_IN_INV_SEL_S 6 +/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC114_IN_SEL 0x0000003F +#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) +#define GPIO_FUNC114_IN_SEL_V 0x3F +#define GPIO_FUNC114_IN_SEL_S 0 + +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02fc) +/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (BIT(7)) +#define GPIO_SIG115_IN_SEL_V 0x1 +#define GPIO_SIG115_IN_SEL_S 7 +/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_V 0x1 +#define GPIO_FUNC115_IN_INV_SEL_S 6 +/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC115_IN_SEL 0x0000003F +#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) +#define GPIO_FUNC115_IN_SEL_V 0x3F +#define GPIO_FUNC115_IN_SEL_S 0 + +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0300) +/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (BIT(7)) +#define GPIO_SIG116_IN_SEL_V 0x1 +#define GPIO_SIG116_IN_SEL_S 7 +/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_V 0x1 +#define GPIO_FUNC116_IN_INV_SEL_S 6 +/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC116_IN_SEL 0x0000003F +#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) +#define GPIO_FUNC116_IN_SEL_V 0x3F +#define GPIO_FUNC116_IN_SEL_S 0 + +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0304) +/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (BIT(7)) +#define GPIO_SIG117_IN_SEL_V 0x1 +#define GPIO_SIG117_IN_SEL_S 7 +/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_V 0x1 +#define GPIO_FUNC117_IN_INV_SEL_S 6 +/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC117_IN_SEL 0x0000003F +#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) +#define GPIO_FUNC117_IN_SEL_V 0x3F +#define GPIO_FUNC117_IN_SEL_S 0 + +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0308) +/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (BIT(7)) +#define GPIO_SIG118_IN_SEL_V 0x1 +#define GPIO_SIG118_IN_SEL_S 7 +/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_V 0x1 +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC118_IN_SEL 0x0000003F +#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) +#define GPIO_FUNC118_IN_SEL_V 0x3F +#define GPIO_FUNC118_IN_SEL_S 0 + +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x030c) +/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (BIT(7)) +#define GPIO_SIG119_IN_SEL_V 0x1 +#define GPIO_SIG119_IN_SEL_S 7 +/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_V 0x1 +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC119_IN_SEL 0x0000003F +#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) +#define GPIO_FUNC119_IN_SEL_V 0x3F +#define GPIO_FUNC119_IN_SEL_S 0 + +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0310) +/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (BIT(7)) +#define GPIO_SIG120_IN_SEL_V 0x1 +#define GPIO_SIG120_IN_SEL_S 7 +/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_V 0x1 +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC120_IN_SEL 0x0000003F +#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) +#define GPIO_FUNC120_IN_SEL_V 0x3F +#define GPIO_FUNC120_IN_SEL_S 0 + +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0314) +/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (BIT(7)) +#define GPIO_SIG121_IN_SEL_V 0x1 +#define GPIO_SIG121_IN_SEL_S 7 +/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_V 0x1 +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC121_IN_SEL 0x0000003F +#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) +#define GPIO_FUNC121_IN_SEL_V 0x3F +#define GPIO_FUNC121_IN_SEL_S 0 + +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0318) +/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (BIT(7)) +#define GPIO_SIG122_IN_SEL_V 0x1 +#define GPIO_SIG122_IN_SEL_S 7 +/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_V 0x1 +#define GPIO_FUNC122_IN_INV_SEL_S 6 +/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC122_IN_SEL 0x0000003F +#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) +#define GPIO_FUNC122_IN_SEL_V 0x3F +#define GPIO_FUNC122_IN_SEL_S 0 + +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x031c) +/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (BIT(7)) +#define GPIO_SIG123_IN_SEL_V 0x1 +#define GPIO_SIG123_IN_SEL_S 7 +/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_V 0x1 +#define GPIO_FUNC123_IN_INV_SEL_S 6 +/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC123_IN_SEL 0x0000003F +#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) +#define GPIO_FUNC123_IN_SEL_V 0x3F +#define GPIO_FUNC123_IN_SEL_S 0 + +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0320) +/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (BIT(7)) +#define GPIO_SIG124_IN_SEL_V 0x1 +#define GPIO_SIG124_IN_SEL_S 7 +/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_V 0x1 +#define GPIO_FUNC124_IN_INV_SEL_S 6 +/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC124_IN_SEL 0x0000003F +#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) +#define GPIO_FUNC124_IN_SEL_V 0x3F +#define GPIO_FUNC124_IN_SEL_S 0 + +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0324) +/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG125_IN_SEL (BIT(7)) +#define GPIO_SIG125_IN_SEL_M (BIT(7)) +#define GPIO_SIG125_IN_SEL_V 0x1 +#define GPIO_SIG125_IN_SEL_S 7 +/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_V 0x1 +#define GPIO_FUNC125_IN_INV_SEL_S 6 +/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC125_IN_SEL 0x0000003F +#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) +#define GPIO_FUNC125_IN_SEL_V 0x3F +#define GPIO_FUNC125_IN_SEL_S 0 + +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0328) +/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG126_IN_SEL (BIT(7)) +#define GPIO_SIG126_IN_SEL_M (BIT(7)) +#define GPIO_SIG126_IN_SEL_V 0x1 +#define GPIO_SIG126_IN_SEL_S 7 +/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_V 0x1 +#define GPIO_FUNC126_IN_INV_SEL_S 6 +/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC126_IN_SEL 0x0000003F +#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) +#define GPIO_FUNC126_IN_SEL_V 0x3F +#define GPIO_FUNC126_IN_SEL_S 0 + +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x032c) +/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG127_IN_SEL (BIT(7)) +#define GPIO_SIG127_IN_SEL_M (BIT(7)) +#define GPIO_SIG127_IN_SEL_V 0x1 +#define GPIO_SIG127_IN_SEL_S 7 +/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_V 0x1 +#define GPIO_FUNC127_IN_INV_SEL_S 6 +/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC127_IN_SEL 0x0000003F +#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) +#define GPIO_FUNC127_IN_SEL_V 0x3F +#define GPIO_FUNC127_IN_SEL_S 0 + +#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0330) +/* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG128_IN_SEL (BIT(7)) +#define GPIO_SIG128_IN_SEL_M (BIT(7)) +#define GPIO_SIG128_IN_SEL_V 0x1 +#define GPIO_SIG128_IN_SEL_S 7 +/* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC128_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_V 0x1 +#define GPIO_FUNC128_IN_INV_SEL_S 6 +/* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC128_IN_SEL 0x0000003F +#define GPIO_FUNC128_IN_SEL_M ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S)) +#define GPIO_FUNC128_IN_SEL_V 0x3F +#define GPIO_FUNC128_IN_SEL_S 0 + +#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0334) +/* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG129_IN_SEL (BIT(7)) +#define GPIO_SIG129_IN_SEL_M (BIT(7)) +#define GPIO_SIG129_IN_SEL_V 0x1 +#define GPIO_SIG129_IN_SEL_S 7 +/* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC129_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_V 0x1 +#define GPIO_FUNC129_IN_INV_SEL_S 6 +/* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC129_IN_SEL 0x0000003F +#define GPIO_FUNC129_IN_SEL_M ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S)) +#define GPIO_FUNC129_IN_SEL_V 0x3F +#define GPIO_FUNC129_IN_SEL_S 0 + +#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0338) +/* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG130_IN_SEL (BIT(7)) +#define GPIO_SIG130_IN_SEL_M (BIT(7)) +#define GPIO_SIG130_IN_SEL_V 0x1 +#define GPIO_SIG130_IN_SEL_S 7 +/* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC130_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_V 0x1 +#define GPIO_FUNC130_IN_INV_SEL_S 6 +/* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC130_IN_SEL 0x0000003F +#define GPIO_FUNC130_IN_SEL_M ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S)) +#define GPIO_FUNC130_IN_SEL_V 0x3F +#define GPIO_FUNC130_IN_SEL_S 0 + +#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x033c) +/* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG131_IN_SEL (BIT(7)) +#define GPIO_SIG131_IN_SEL_M (BIT(7)) +#define GPIO_SIG131_IN_SEL_V 0x1 +#define GPIO_SIG131_IN_SEL_S 7 +/* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC131_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_V 0x1 +#define GPIO_FUNC131_IN_INV_SEL_S 6 +/* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC131_IN_SEL 0x0000003F +#define GPIO_FUNC131_IN_SEL_M ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S)) +#define GPIO_FUNC131_IN_SEL_V 0x3F +#define GPIO_FUNC131_IN_SEL_S 0 + +#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0340) +/* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG132_IN_SEL (BIT(7)) +#define GPIO_SIG132_IN_SEL_M (BIT(7)) +#define GPIO_SIG132_IN_SEL_V 0x1 +#define GPIO_SIG132_IN_SEL_S 7 +/* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC132_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_V 0x1 +#define GPIO_FUNC132_IN_INV_SEL_S 6 +/* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC132_IN_SEL 0x0000003F +#define GPIO_FUNC132_IN_SEL_M ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S)) +#define GPIO_FUNC132_IN_SEL_V 0x3F +#define GPIO_FUNC132_IN_SEL_S 0 + +#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0344) +/* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG133_IN_SEL (BIT(7)) +#define GPIO_SIG133_IN_SEL_M (BIT(7)) +#define GPIO_SIG133_IN_SEL_V 0x1 +#define GPIO_SIG133_IN_SEL_S 7 +/* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC133_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_V 0x1 +#define GPIO_FUNC133_IN_INV_SEL_S 6 +/* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC133_IN_SEL 0x0000003F +#define GPIO_FUNC133_IN_SEL_M ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S)) +#define GPIO_FUNC133_IN_SEL_V 0x3F +#define GPIO_FUNC133_IN_SEL_S 0 + +#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0348) +/* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG134_IN_SEL (BIT(7)) +#define GPIO_SIG134_IN_SEL_M (BIT(7)) +#define GPIO_SIG134_IN_SEL_V 0x1 +#define GPIO_SIG134_IN_SEL_S 7 +/* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC134_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_V 0x1 +#define GPIO_FUNC134_IN_INV_SEL_S 6 +/* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC134_IN_SEL 0x0000003F +#define GPIO_FUNC134_IN_SEL_M ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S)) +#define GPIO_FUNC134_IN_SEL_V 0x3F +#define GPIO_FUNC134_IN_SEL_S 0 + +#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x034c) +/* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG135_IN_SEL (BIT(7)) +#define GPIO_SIG135_IN_SEL_M (BIT(7)) +#define GPIO_SIG135_IN_SEL_V 0x1 +#define GPIO_SIG135_IN_SEL_S 7 +/* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC135_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_V 0x1 +#define GPIO_FUNC135_IN_INV_SEL_S 6 +/* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC135_IN_SEL 0x0000003F +#define GPIO_FUNC135_IN_SEL_M ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S)) +#define GPIO_FUNC135_IN_SEL_V 0x3F +#define GPIO_FUNC135_IN_SEL_S 0 + +#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0350) +/* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG136_IN_SEL (BIT(7)) +#define GPIO_SIG136_IN_SEL_M (BIT(7)) +#define GPIO_SIG136_IN_SEL_V 0x1 +#define GPIO_SIG136_IN_SEL_S 7 +/* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC136_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_V 0x1 +#define GPIO_FUNC136_IN_INV_SEL_S 6 +/* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC136_IN_SEL 0x0000003F +#define GPIO_FUNC136_IN_SEL_M ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S)) +#define GPIO_FUNC136_IN_SEL_V 0x3F +#define GPIO_FUNC136_IN_SEL_S 0 + +#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0354) +/* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG137_IN_SEL (BIT(7)) +#define GPIO_SIG137_IN_SEL_M (BIT(7)) +#define GPIO_SIG137_IN_SEL_V 0x1 +#define GPIO_SIG137_IN_SEL_S 7 +/* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC137_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_V 0x1 +#define GPIO_FUNC137_IN_INV_SEL_S 6 +/* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC137_IN_SEL 0x0000003F +#define GPIO_FUNC137_IN_SEL_M ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S)) +#define GPIO_FUNC137_IN_SEL_V 0x3F +#define GPIO_FUNC137_IN_SEL_S 0 + +#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0358) +/* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG138_IN_SEL (BIT(7)) +#define GPIO_SIG138_IN_SEL_M (BIT(7)) +#define GPIO_SIG138_IN_SEL_V 0x1 +#define GPIO_SIG138_IN_SEL_S 7 +/* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC138_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_V 0x1 +#define GPIO_FUNC138_IN_INV_SEL_S 6 +/* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC138_IN_SEL 0x0000003F +#define GPIO_FUNC138_IN_SEL_M ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S)) +#define GPIO_FUNC138_IN_SEL_V 0x3F +#define GPIO_FUNC138_IN_SEL_S 0 + +#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x035c) +/* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG139_IN_SEL (BIT(7)) +#define GPIO_SIG139_IN_SEL_M (BIT(7)) +#define GPIO_SIG139_IN_SEL_V 0x1 +#define GPIO_SIG139_IN_SEL_S 7 +/* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC139_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_V 0x1 +#define GPIO_FUNC139_IN_INV_SEL_S 6 +/* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC139_IN_SEL 0x0000003F +#define GPIO_FUNC139_IN_SEL_M ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S)) +#define GPIO_FUNC139_IN_SEL_V 0x3F +#define GPIO_FUNC139_IN_SEL_S 0 + +#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0360) +/* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG140_IN_SEL (BIT(7)) +#define GPIO_SIG140_IN_SEL_M (BIT(7)) +#define GPIO_SIG140_IN_SEL_V 0x1 +#define GPIO_SIG140_IN_SEL_S 7 +/* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC140_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_V 0x1 +#define GPIO_FUNC140_IN_INV_SEL_S 6 +/* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC140_IN_SEL 0x0000003F +#define GPIO_FUNC140_IN_SEL_M ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S)) +#define GPIO_FUNC140_IN_SEL_V 0x3F +#define GPIO_FUNC140_IN_SEL_S 0 + +#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0364) +/* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG141_IN_SEL (BIT(7)) +#define GPIO_SIG141_IN_SEL_M (BIT(7)) +#define GPIO_SIG141_IN_SEL_V 0x1 +#define GPIO_SIG141_IN_SEL_S 7 +/* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC141_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_V 0x1 +#define GPIO_FUNC141_IN_INV_SEL_S 6 +/* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC141_IN_SEL 0x0000003F +#define GPIO_FUNC141_IN_SEL_M ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S)) +#define GPIO_FUNC141_IN_SEL_V 0x3F +#define GPIO_FUNC141_IN_SEL_S 0 + +#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0368) +/* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG142_IN_SEL (BIT(7)) +#define GPIO_SIG142_IN_SEL_M (BIT(7)) +#define GPIO_SIG142_IN_SEL_V 0x1 +#define GPIO_SIG142_IN_SEL_S 7 +/* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC142_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_V 0x1 +#define GPIO_FUNC142_IN_INV_SEL_S 6 +/* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC142_IN_SEL 0x0000003F +#define GPIO_FUNC142_IN_SEL_M ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S)) +#define GPIO_FUNC142_IN_SEL_V 0x3F +#define GPIO_FUNC142_IN_SEL_S 0 + +#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x036c) +/* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG143_IN_SEL (BIT(7)) +#define GPIO_SIG143_IN_SEL_M (BIT(7)) +#define GPIO_SIG143_IN_SEL_V 0x1 +#define GPIO_SIG143_IN_SEL_S 7 +/* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC143_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_V 0x1 +#define GPIO_FUNC143_IN_INV_SEL_S 6 +/* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC143_IN_SEL 0x0000003F +#define GPIO_FUNC143_IN_SEL_M ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S)) +#define GPIO_FUNC143_IN_SEL_V 0x3F +#define GPIO_FUNC143_IN_SEL_S 0 + +#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0370) +/* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG144_IN_SEL (BIT(7)) +#define GPIO_SIG144_IN_SEL_M (BIT(7)) +#define GPIO_SIG144_IN_SEL_V 0x1 +#define GPIO_SIG144_IN_SEL_S 7 +/* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC144_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_V 0x1 +#define GPIO_FUNC144_IN_INV_SEL_S 6 +/* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC144_IN_SEL 0x0000003F +#define GPIO_FUNC144_IN_SEL_M ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S)) +#define GPIO_FUNC144_IN_SEL_V 0x3F +#define GPIO_FUNC144_IN_SEL_S 0 + +#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0374) +/* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG145_IN_SEL (BIT(7)) +#define GPIO_SIG145_IN_SEL_M (BIT(7)) +#define GPIO_SIG145_IN_SEL_V 0x1 +#define GPIO_SIG145_IN_SEL_S 7 +/* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC145_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_V 0x1 +#define GPIO_FUNC145_IN_INV_SEL_S 6 +/* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC145_IN_SEL 0x0000003F +#define GPIO_FUNC145_IN_SEL_M ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S)) +#define GPIO_FUNC145_IN_SEL_V 0x3F +#define GPIO_FUNC145_IN_SEL_S 0 + +#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0378) +/* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG146_IN_SEL (BIT(7)) +#define GPIO_SIG146_IN_SEL_M (BIT(7)) +#define GPIO_SIG146_IN_SEL_V 0x1 +#define GPIO_SIG146_IN_SEL_S 7 +/* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC146_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_V 0x1 +#define GPIO_FUNC146_IN_INV_SEL_S 6 +/* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC146_IN_SEL 0x0000003F +#define GPIO_FUNC146_IN_SEL_M ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S)) +#define GPIO_FUNC146_IN_SEL_V 0x3F +#define GPIO_FUNC146_IN_SEL_S 0 + +#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x037c) +/* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG147_IN_SEL (BIT(7)) +#define GPIO_SIG147_IN_SEL_M (BIT(7)) +#define GPIO_SIG147_IN_SEL_V 0x1 +#define GPIO_SIG147_IN_SEL_S 7 +/* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC147_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_V 0x1 +#define GPIO_FUNC147_IN_INV_SEL_S 6 +/* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC147_IN_SEL 0x0000003F +#define GPIO_FUNC147_IN_SEL_M ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S)) +#define GPIO_FUNC147_IN_SEL_V 0x3F +#define GPIO_FUNC147_IN_SEL_S 0 + +#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0380) +/* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG148_IN_SEL (BIT(7)) +#define GPIO_SIG148_IN_SEL_M (BIT(7)) +#define GPIO_SIG148_IN_SEL_V 0x1 +#define GPIO_SIG148_IN_SEL_S 7 +/* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC148_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_V 0x1 +#define GPIO_FUNC148_IN_INV_SEL_S 6 +/* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC148_IN_SEL 0x0000003F +#define GPIO_FUNC148_IN_SEL_M ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S)) +#define GPIO_FUNC148_IN_SEL_V 0x3F +#define GPIO_FUNC148_IN_SEL_S 0 + +#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0384) +/* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG149_IN_SEL (BIT(7)) +#define GPIO_SIG149_IN_SEL_M (BIT(7)) +#define GPIO_SIG149_IN_SEL_V 0x1 +#define GPIO_SIG149_IN_SEL_S 7 +/* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC149_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_V 0x1 +#define GPIO_FUNC149_IN_INV_SEL_S 6 +/* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC149_IN_SEL 0x0000003F +#define GPIO_FUNC149_IN_SEL_M ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S)) +#define GPIO_FUNC149_IN_SEL_V 0x3F +#define GPIO_FUNC149_IN_SEL_S 0 + +#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0388) +/* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG150_IN_SEL (BIT(7)) +#define GPIO_SIG150_IN_SEL_M (BIT(7)) +#define GPIO_SIG150_IN_SEL_V 0x1 +#define GPIO_SIG150_IN_SEL_S 7 +/* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC150_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_V 0x1 +#define GPIO_FUNC150_IN_INV_SEL_S 6 +/* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC150_IN_SEL 0x0000003F +#define GPIO_FUNC150_IN_SEL_M ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S)) +#define GPIO_FUNC150_IN_SEL_V 0x3F +#define GPIO_FUNC150_IN_SEL_S 0 + +#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x038c) +/* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG151_IN_SEL (BIT(7)) +#define GPIO_SIG151_IN_SEL_M (BIT(7)) +#define GPIO_SIG151_IN_SEL_V 0x1 +#define GPIO_SIG151_IN_SEL_S 7 +/* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC151_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_V 0x1 +#define GPIO_FUNC151_IN_INV_SEL_S 6 +/* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC151_IN_SEL 0x0000003F +#define GPIO_FUNC151_IN_SEL_M ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S)) +#define GPIO_FUNC151_IN_SEL_V 0x3F +#define GPIO_FUNC151_IN_SEL_S 0 + +#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0390) +/* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG152_IN_SEL (BIT(7)) +#define GPIO_SIG152_IN_SEL_M (BIT(7)) +#define GPIO_SIG152_IN_SEL_V 0x1 +#define GPIO_SIG152_IN_SEL_S 7 +/* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC152_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_V 0x1 +#define GPIO_FUNC152_IN_INV_SEL_S 6 +/* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC152_IN_SEL 0x0000003F +#define GPIO_FUNC152_IN_SEL_M ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S)) +#define GPIO_FUNC152_IN_SEL_V 0x3F +#define GPIO_FUNC152_IN_SEL_S 0 + +#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0394) +/* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG153_IN_SEL (BIT(7)) +#define GPIO_SIG153_IN_SEL_M (BIT(7)) +#define GPIO_SIG153_IN_SEL_V 0x1 +#define GPIO_SIG153_IN_SEL_S 7 +/* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC153_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_V 0x1 +#define GPIO_FUNC153_IN_INV_SEL_S 6 +/* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC153_IN_SEL 0x0000003F +#define GPIO_FUNC153_IN_SEL_M ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S)) +#define GPIO_FUNC153_IN_SEL_V 0x3F +#define GPIO_FUNC153_IN_SEL_S 0 + +#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0398) +/* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG154_IN_SEL (BIT(7)) +#define GPIO_SIG154_IN_SEL_M (BIT(7)) +#define GPIO_SIG154_IN_SEL_V 0x1 +#define GPIO_SIG154_IN_SEL_S 7 +/* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC154_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_V 0x1 +#define GPIO_FUNC154_IN_INV_SEL_S 6 +/* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC154_IN_SEL 0x0000003F +#define GPIO_FUNC154_IN_SEL_M ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S)) +#define GPIO_FUNC154_IN_SEL_V 0x3F +#define GPIO_FUNC154_IN_SEL_S 0 + +#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x039c) +/* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG155_IN_SEL (BIT(7)) +#define GPIO_SIG155_IN_SEL_M (BIT(7)) +#define GPIO_SIG155_IN_SEL_V 0x1 +#define GPIO_SIG155_IN_SEL_S 7 +/* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC155_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_V 0x1 +#define GPIO_FUNC155_IN_INV_SEL_S 6 +/* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC155_IN_SEL 0x0000003F +#define GPIO_FUNC155_IN_SEL_M ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S)) +#define GPIO_FUNC155_IN_SEL_V 0x3F +#define GPIO_FUNC155_IN_SEL_S 0 + +#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a0) +/* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG156_IN_SEL (BIT(7)) +#define GPIO_SIG156_IN_SEL_M (BIT(7)) +#define GPIO_SIG156_IN_SEL_V 0x1 +#define GPIO_SIG156_IN_SEL_S 7 +/* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC156_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_V 0x1 +#define GPIO_FUNC156_IN_INV_SEL_S 6 +/* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC156_IN_SEL 0x0000003F +#define GPIO_FUNC156_IN_SEL_M ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S)) +#define GPIO_FUNC156_IN_SEL_V 0x3F +#define GPIO_FUNC156_IN_SEL_S 0 + +#define GPIO_FUNC157_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a4) +/* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG157_IN_SEL (BIT(7)) +#define GPIO_SIG157_IN_SEL_M (BIT(7)) +#define GPIO_SIG157_IN_SEL_V 0x1 +#define GPIO_SIG157_IN_SEL_S 7 +/* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC157_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_V 0x1 +#define GPIO_FUNC157_IN_INV_SEL_S 6 +/* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC157_IN_SEL 0x0000003F +#define GPIO_FUNC157_IN_SEL_M ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S)) +#define GPIO_FUNC157_IN_SEL_V 0x3F +#define GPIO_FUNC157_IN_SEL_S 0 + +#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a8) +/* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG158_IN_SEL (BIT(7)) +#define GPIO_SIG158_IN_SEL_M (BIT(7)) +#define GPIO_SIG158_IN_SEL_V 0x1 +#define GPIO_SIG158_IN_SEL_S 7 +/* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC158_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_V 0x1 +#define GPIO_FUNC158_IN_INV_SEL_S 6 +/* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC158_IN_SEL 0x0000003F +#define GPIO_FUNC158_IN_SEL_M ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S)) +#define GPIO_FUNC158_IN_SEL_V 0x3F +#define GPIO_FUNC158_IN_SEL_S 0 + +#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ac) +/* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG159_IN_SEL (BIT(7)) +#define GPIO_SIG159_IN_SEL_M (BIT(7)) +#define GPIO_SIG159_IN_SEL_V 0x1 +#define GPIO_SIG159_IN_SEL_S 7 +/* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC159_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_V 0x1 +#define GPIO_FUNC159_IN_INV_SEL_S 6 +/* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC159_IN_SEL 0x0000003F +#define GPIO_FUNC159_IN_SEL_M ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S)) +#define GPIO_FUNC159_IN_SEL_V 0x3F +#define GPIO_FUNC159_IN_SEL_S 0 + +#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b0) +/* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG160_IN_SEL (BIT(7)) +#define GPIO_SIG160_IN_SEL_M (BIT(7)) +#define GPIO_SIG160_IN_SEL_V 0x1 +#define GPIO_SIG160_IN_SEL_S 7 +/* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC160_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_V 0x1 +#define GPIO_FUNC160_IN_INV_SEL_S 6 +/* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC160_IN_SEL 0x0000003F +#define GPIO_FUNC160_IN_SEL_M ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S)) +#define GPIO_FUNC160_IN_SEL_V 0x3F +#define GPIO_FUNC160_IN_SEL_S 0 + +#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b4) +/* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG161_IN_SEL (BIT(7)) +#define GPIO_SIG161_IN_SEL_M (BIT(7)) +#define GPIO_SIG161_IN_SEL_V 0x1 +#define GPIO_SIG161_IN_SEL_S 7 +/* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC161_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_V 0x1 +#define GPIO_FUNC161_IN_INV_SEL_S 6 +/* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC161_IN_SEL 0x0000003F +#define GPIO_FUNC161_IN_SEL_M ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S)) +#define GPIO_FUNC161_IN_SEL_V 0x3F +#define GPIO_FUNC161_IN_SEL_S 0 + +#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b8) +/* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG162_IN_SEL (BIT(7)) +#define GPIO_SIG162_IN_SEL_M (BIT(7)) +#define GPIO_SIG162_IN_SEL_V 0x1 +#define GPIO_SIG162_IN_SEL_S 7 +/* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC162_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_V 0x1 +#define GPIO_FUNC162_IN_INV_SEL_S 6 +/* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC162_IN_SEL 0x0000003F +#define GPIO_FUNC162_IN_SEL_M ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S)) +#define GPIO_FUNC162_IN_SEL_V 0x3F +#define GPIO_FUNC162_IN_SEL_S 0 + +#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03bc) +/* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG163_IN_SEL (BIT(7)) +#define GPIO_SIG163_IN_SEL_M (BIT(7)) +#define GPIO_SIG163_IN_SEL_V 0x1 +#define GPIO_SIG163_IN_SEL_S 7 +/* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC163_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_V 0x1 +#define GPIO_FUNC163_IN_INV_SEL_S 6 +/* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC163_IN_SEL 0x0000003F +#define GPIO_FUNC163_IN_SEL_M ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S)) +#define GPIO_FUNC163_IN_SEL_V 0x3F +#define GPIO_FUNC163_IN_SEL_S 0 + +#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c0) +/* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG164_IN_SEL (BIT(7)) +#define GPIO_SIG164_IN_SEL_M (BIT(7)) +#define GPIO_SIG164_IN_SEL_V 0x1 +#define GPIO_SIG164_IN_SEL_S 7 +/* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC164_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_V 0x1 +#define GPIO_FUNC164_IN_INV_SEL_S 6 +/* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC164_IN_SEL 0x0000003F +#define GPIO_FUNC164_IN_SEL_M ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S)) +#define GPIO_FUNC164_IN_SEL_V 0x3F +#define GPIO_FUNC164_IN_SEL_S 0 + +#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c4) +/* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG165_IN_SEL (BIT(7)) +#define GPIO_SIG165_IN_SEL_M (BIT(7)) +#define GPIO_SIG165_IN_SEL_V 0x1 +#define GPIO_SIG165_IN_SEL_S 7 +/* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC165_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_V 0x1 +#define GPIO_FUNC165_IN_INV_SEL_S 6 +/* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC165_IN_SEL 0x0000003F +#define GPIO_FUNC165_IN_SEL_M ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S)) +#define GPIO_FUNC165_IN_SEL_V 0x3F +#define GPIO_FUNC165_IN_SEL_S 0 + +#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c8) +/* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG166_IN_SEL (BIT(7)) +#define GPIO_SIG166_IN_SEL_M (BIT(7)) +#define GPIO_SIG166_IN_SEL_V 0x1 +#define GPIO_SIG166_IN_SEL_S 7 +/* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC166_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_V 0x1 +#define GPIO_FUNC166_IN_INV_SEL_S 6 +/* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC166_IN_SEL 0x0000003F +#define GPIO_FUNC166_IN_SEL_M ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S)) +#define GPIO_FUNC166_IN_SEL_V 0x3F +#define GPIO_FUNC166_IN_SEL_S 0 + +#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03cc) +/* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG167_IN_SEL (BIT(7)) +#define GPIO_SIG167_IN_SEL_M (BIT(7)) +#define GPIO_SIG167_IN_SEL_V 0x1 +#define GPIO_SIG167_IN_SEL_S 7 +/* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC167_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_V 0x1 +#define GPIO_FUNC167_IN_INV_SEL_S 6 +/* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC167_IN_SEL 0x0000003F +#define GPIO_FUNC167_IN_SEL_M ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S)) +#define GPIO_FUNC167_IN_SEL_V 0x3F +#define GPIO_FUNC167_IN_SEL_S 0 + +#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d0) +/* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG168_IN_SEL (BIT(7)) +#define GPIO_SIG168_IN_SEL_M (BIT(7)) +#define GPIO_SIG168_IN_SEL_V 0x1 +#define GPIO_SIG168_IN_SEL_S 7 +/* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC168_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_V 0x1 +#define GPIO_FUNC168_IN_INV_SEL_S 6 +/* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC168_IN_SEL 0x0000003F +#define GPIO_FUNC168_IN_SEL_M ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S)) +#define GPIO_FUNC168_IN_SEL_V 0x3F +#define GPIO_FUNC168_IN_SEL_S 0 + +#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d4) +/* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG169_IN_SEL (BIT(7)) +#define GPIO_SIG169_IN_SEL_M (BIT(7)) +#define GPIO_SIG169_IN_SEL_V 0x1 +#define GPIO_SIG169_IN_SEL_S 7 +/* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC169_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_V 0x1 +#define GPIO_FUNC169_IN_INV_SEL_S 6 +/* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC169_IN_SEL 0x0000003F +#define GPIO_FUNC169_IN_SEL_M ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S)) +#define GPIO_FUNC169_IN_SEL_V 0x3F +#define GPIO_FUNC169_IN_SEL_S 0 + +#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d8) +/* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG170_IN_SEL (BIT(7)) +#define GPIO_SIG170_IN_SEL_M (BIT(7)) +#define GPIO_SIG170_IN_SEL_V 0x1 +#define GPIO_SIG170_IN_SEL_S 7 +/* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC170_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_V 0x1 +#define GPIO_FUNC170_IN_INV_SEL_S 6 +/* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC170_IN_SEL 0x0000003F +#define GPIO_FUNC170_IN_SEL_M ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S)) +#define GPIO_FUNC170_IN_SEL_V 0x3F +#define GPIO_FUNC170_IN_SEL_S 0 + +#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03dc) +/* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG171_IN_SEL (BIT(7)) +#define GPIO_SIG171_IN_SEL_M (BIT(7)) +#define GPIO_SIG171_IN_SEL_V 0x1 +#define GPIO_SIG171_IN_SEL_S 7 +/* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC171_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_V 0x1 +#define GPIO_FUNC171_IN_INV_SEL_S 6 +/* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC171_IN_SEL 0x0000003F +#define GPIO_FUNC171_IN_SEL_M ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S)) +#define GPIO_FUNC171_IN_SEL_V 0x3F +#define GPIO_FUNC171_IN_SEL_S 0 + +#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e0) +/* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG172_IN_SEL (BIT(7)) +#define GPIO_SIG172_IN_SEL_M (BIT(7)) +#define GPIO_SIG172_IN_SEL_V 0x1 +#define GPIO_SIG172_IN_SEL_S 7 +/* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC172_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_V 0x1 +#define GPIO_FUNC172_IN_INV_SEL_S 6 +/* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC172_IN_SEL 0x0000003F +#define GPIO_FUNC172_IN_SEL_M ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S)) +#define GPIO_FUNC172_IN_SEL_V 0x3F +#define GPIO_FUNC172_IN_SEL_S 0 + +#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e4) +/* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG173_IN_SEL (BIT(7)) +#define GPIO_SIG173_IN_SEL_M (BIT(7)) +#define GPIO_SIG173_IN_SEL_V 0x1 +#define GPIO_SIG173_IN_SEL_S 7 +/* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC173_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_V 0x1 +#define GPIO_FUNC173_IN_INV_SEL_S 6 +/* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC173_IN_SEL 0x0000003F +#define GPIO_FUNC173_IN_SEL_M ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S)) +#define GPIO_FUNC173_IN_SEL_V 0x3F +#define GPIO_FUNC173_IN_SEL_S 0 + +#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e8) +/* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG174_IN_SEL (BIT(7)) +#define GPIO_SIG174_IN_SEL_M (BIT(7)) +#define GPIO_SIG174_IN_SEL_V 0x1 +#define GPIO_SIG174_IN_SEL_S 7 +/* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC174_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_V 0x1 +#define GPIO_FUNC174_IN_INV_SEL_S 6 +/* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC174_IN_SEL 0x0000003F +#define GPIO_FUNC174_IN_SEL_M ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S)) +#define GPIO_FUNC174_IN_SEL_V 0x3F +#define GPIO_FUNC174_IN_SEL_S 0 + +#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ec) +/* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG175_IN_SEL (BIT(7)) +#define GPIO_SIG175_IN_SEL_M (BIT(7)) +#define GPIO_SIG175_IN_SEL_V 0x1 +#define GPIO_SIG175_IN_SEL_S 7 +/* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC175_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_V 0x1 +#define GPIO_FUNC175_IN_INV_SEL_S 6 +/* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC175_IN_SEL 0x0000003F +#define GPIO_FUNC175_IN_SEL_M ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S)) +#define GPIO_FUNC175_IN_SEL_V 0x3F +#define GPIO_FUNC175_IN_SEL_S 0 + +#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f0) +/* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG176_IN_SEL (BIT(7)) +#define GPIO_SIG176_IN_SEL_M (BIT(7)) +#define GPIO_SIG176_IN_SEL_V 0x1 +#define GPIO_SIG176_IN_SEL_S 7 +/* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC176_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_V 0x1 +#define GPIO_FUNC176_IN_INV_SEL_S 6 +/* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC176_IN_SEL 0x0000003F +#define GPIO_FUNC176_IN_SEL_M ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S)) +#define GPIO_FUNC176_IN_SEL_V 0x3F +#define GPIO_FUNC176_IN_SEL_S 0 + +#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f4) +/* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG177_IN_SEL (BIT(7)) +#define GPIO_SIG177_IN_SEL_M (BIT(7)) +#define GPIO_SIG177_IN_SEL_V 0x1 +#define GPIO_SIG177_IN_SEL_S 7 +/* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC177_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_V 0x1 +#define GPIO_FUNC177_IN_INV_SEL_S 6 +/* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC177_IN_SEL 0x0000003F +#define GPIO_FUNC177_IN_SEL_M ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S)) +#define GPIO_FUNC177_IN_SEL_V 0x3F +#define GPIO_FUNC177_IN_SEL_S 0 + +#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f8) +/* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG178_IN_SEL (BIT(7)) +#define GPIO_SIG178_IN_SEL_M (BIT(7)) +#define GPIO_SIG178_IN_SEL_V 0x1 +#define GPIO_SIG178_IN_SEL_S 7 +/* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC178_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_V 0x1 +#define GPIO_FUNC178_IN_INV_SEL_S 6 +/* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC178_IN_SEL 0x0000003F +#define GPIO_FUNC178_IN_SEL_M ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S)) +#define GPIO_FUNC178_IN_SEL_V 0x3F +#define GPIO_FUNC178_IN_SEL_S 0 + +#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03fc) +/* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG179_IN_SEL (BIT(7)) +#define GPIO_SIG179_IN_SEL_M (BIT(7)) +#define GPIO_SIG179_IN_SEL_V 0x1 +#define GPIO_SIG179_IN_SEL_S 7 +/* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC179_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_V 0x1 +#define GPIO_FUNC179_IN_INV_SEL_S 6 +/* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC179_IN_SEL 0x0000003F +#define GPIO_FUNC179_IN_SEL_M ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S)) +#define GPIO_FUNC179_IN_SEL_V 0x3F +#define GPIO_FUNC179_IN_SEL_S 0 + +#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0400) +/* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG180_IN_SEL (BIT(7)) +#define GPIO_SIG180_IN_SEL_M (BIT(7)) +#define GPIO_SIG180_IN_SEL_V 0x1 +#define GPIO_SIG180_IN_SEL_S 7 +/* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC180_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_V 0x1 +#define GPIO_FUNC180_IN_INV_SEL_S 6 +/* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC180_IN_SEL 0x0000003F +#define GPIO_FUNC180_IN_SEL_M ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S)) +#define GPIO_FUNC180_IN_SEL_V 0x3F +#define GPIO_FUNC180_IN_SEL_S 0 + +#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0404) +/* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG181_IN_SEL (BIT(7)) +#define GPIO_SIG181_IN_SEL_M (BIT(7)) +#define GPIO_SIG181_IN_SEL_V 0x1 +#define GPIO_SIG181_IN_SEL_S 7 +/* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC181_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_V 0x1 +#define GPIO_FUNC181_IN_INV_SEL_S 6 +/* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC181_IN_SEL 0x0000003F +#define GPIO_FUNC181_IN_SEL_M ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S)) +#define GPIO_FUNC181_IN_SEL_V 0x3F +#define GPIO_FUNC181_IN_SEL_S 0 + +#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0408) +/* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG182_IN_SEL (BIT(7)) +#define GPIO_SIG182_IN_SEL_M (BIT(7)) +#define GPIO_SIG182_IN_SEL_V 0x1 +#define GPIO_SIG182_IN_SEL_S 7 +/* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC182_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_V 0x1 +#define GPIO_FUNC182_IN_INV_SEL_S 6 +/* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC182_IN_SEL 0x0000003F +#define GPIO_FUNC182_IN_SEL_M ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S)) +#define GPIO_FUNC182_IN_SEL_V 0x3F +#define GPIO_FUNC182_IN_SEL_S 0 + +#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x040c) +/* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG183_IN_SEL (BIT(7)) +#define GPIO_SIG183_IN_SEL_M (BIT(7)) +#define GPIO_SIG183_IN_SEL_V 0x1 +#define GPIO_SIG183_IN_SEL_S 7 +/* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC183_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_V 0x1 +#define GPIO_FUNC183_IN_INV_SEL_S 6 +/* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC183_IN_SEL 0x0000003F +#define GPIO_FUNC183_IN_SEL_M ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S)) +#define GPIO_FUNC183_IN_SEL_V 0x3F +#define GPIO_FUNC183_IN_SEL_S 0 + +#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0410) +/* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG184_IN_SEL (BIT(7)) +#define GPIO_SIG184_IN_SEL_M (BIT(7)) +#define GPIO_SIG184_IN_SEL_V 0x1 +#define GPIO_SIG184_IN_SEL_S 7 +/* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC184_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_V 0x1 +#define GPIO_FUNC184_IN_INV_SEL_S 6 +/* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC184_IN_SEL 0x0000003F +#define GPIO_FUNC184_IN_SEL_M ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S)) +#define GPIO_FUNC184_IN_SEL_V 0x3F +#define GPIO_FUNC184_IN_SEL_S 0 + +#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0414) +/* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG185_IN_SEL (BIT(7)) +#define GPIO_SIG185_IN_SEL_M (BIT(7)) +#define GPIO_SIG185_IN_SEL_V 0x1 +#define GPIO_SIG185_IN_SEL_S 7 +/* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC185_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_V 0x1 +#define GPIO_FUNC185_IN_INV_SEL_S 6 +/* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC185_IN_SEL 0x0000003F +#define GPIO_FUNC185_IN_SEL_M ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S)) +#define GPIO_FUNC185_IN_SEL_V 0x3F +#define GPIO_FUNC185_IN_SEL_S 0 + +#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0418) +/* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG186_IN_SEL (BIT(7)) +#define GPIO_SIG186_IN_SEL_M (BIT(7)) +#define GPIO_SIG186_IN_SEL_V 0x1 +#define GPIO_SIG186_IN_SEL_S 7 +/* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC186_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_V 0x1 +#define GPIO_FUNC186_IN_INV_SEL_S 6 +/* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC186_IN_SEL 0x0000003F +#define GPIO_FUNC186_IN_SEL_M ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S)) +#define GPIO_FUNC186_IN_SEL_V 0x3F +#define GPIO_FUNC186_IN_SEL_S 0 + +#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x041c) +/* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG187_IN_SEL (BIT(7)) +#define GPIO_SIG187_IN_SEL_M (BIT(7)) +#define GPIO_SIG187_IN_SEL_V 0x1 +#define GPIO_SIG187_IN_SEL_S 7 +/* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC187_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_V 0x1 +#define GPIO_FUNC187_IN_INV_SEL_S 6 +/* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC187_IN_SEL 0x0000003F +#define GPIO_FUNC187_IN_SEL_M ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S)) +#define GPIO_FUNC187_IN_SEL_V 0x3F +#define GPIO_FUNC187_IN_SEL_S 0 + +#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0420) +/* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG188_IN_SEL (BIT(7)) +#define GPIO_SIG188_IN_SEL_M (BIT(7)) +#define GPIO_SIG188_IN_SEL_V 0x1 +#define GPIO_SIG188_IN_SEL_S 7 +/* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC188_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_V 0x1 +#define GPIO_FUNC188_IN_INV_SEL_S 6 +/* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC188_IN_SEL 0x0000003F +#define GPIO_FUNC188_IN_SEL_M ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S)) +#define GPIO_FUNC188_IN_SEL_V 0x3F +#define GPIO_FUNC188_IN_SEL_S 0 + +#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0424) +/* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG189_IN_SEL (BIT(7)) +#define GPIO_SIG189_IN_SEL_M (BIT(7)) +#define GPIO_SIG189_IN_SEL_V 0x1 +#define GPIO_SIG189_IN_SEL_S 7 +/* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC189_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_V 0x1 +#define GPIO_FUNC189_IN_INV_SEL_S 6 +/* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC189_IN_SEL 0x0000003F +#define GPIO_FUNC189_IN_SEL_M ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S)) +#define GPIO_FUNC189_IN_SEL_V 0x3F +#define GPIO_FUNC189_IN_SEL_S 0 + +#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0428) +/* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG190_IN_SEL (BIT(7)) +#define GPIO_SIG190_IN_SEL_M (BIT(7)) +#define GPIO_SIG190_IN_SEL_V 0x1 +#define GPIO_SIG190_IN_SEL_S 7 +/* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC190_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_V 0x1 +#define GPIO_FUNC190_IN_INV_SEL_S 6 +/* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC190_IN_SEL 0x0000003F +#define GPIO_FUNC190_IN_SEL_M ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S)) +#define GPIO_FUNC190_IN_SEL_V 0x3F +#define GPIO_FUNC190_IN_SEL_S 0 + +#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x042c) +/* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG191_IN_SEL (BIT(7)) +#define GPIO_SIG191_IN_SEL_M (BIT(7)) +#define GPIO_SIG191_IN_SEL_V 0x1 +#define GPIO_SIG191_IN_SEL_S 7 +/* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC191_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_V 0x1 +#define GPIO_FUNC191_IN_INV_SEL_S 6 +/* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC191_IN_SEL 0x0000003F +#define GPIO_FUNC191_IN_SEL_M ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S)) +#define GPIO_FUNC191_IN_SEL_V 0x3F +#define GPIO_FUNC191_IN_SEL_S 0 + +#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0430) +/* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG192_IN_SEL (BIT(7)) +#define GPIO_SIG192_IN_SEL_M (BIT(7)) +#define GPIO_SIG192_IN_SEL_V 0x1 +#define GPIO_SIG192_IN_SEL_S 7 +/* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC192_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_V 0x1 +#define GPIO_FUNC192_IN_INV_SEL_S 6 +/* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC192_IN_SEL 0x0000003F +#define GPIO_FUNC192_IN_SEL_M ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S)) +#define GPIO_FUNC192_IN_SEL_V 0x3F +#define GPIO_FUNC192_IN_SEL_S 0 + +#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0434) +/* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG193_IN_SEL (BIT(7)) +#define GPIO_SIG193_IN_SEL_M (BIT(7)) +#define GPIO_SIG193_IN_SEL_V 0x1 +#define GPIO_SIG193_IN_SEL_S 7 +/* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC193_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_V 0x1 +#define GPIO_FUNC193_IN_INV_SEL_S 6 +/* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC193_IN_SEL 0x0000003F +#define GPIO_FUNC193_IN_SEL_M ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S)) +#define GPIO_FUNC193_IN_SEL_V 0x3F +#define GPIO_FUNC193_IN_SEL_S 0 + +#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0438) +/* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG194_IN_SEL (BIT(7)) +#define GPIO_SIG194_IN_SEL_M (BIT(7)) +#define GPIO_SIG194_IN_SEL_V 0x1 +#define GPIO_SIG194_IN_SEL_S 7 +/* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC194_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_V 0x1 +#define GPIO_FUNC194_IN_INV_SEL_S 6 +/* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC194_IN_SEL 0x0000003F +#define GPIO_FUNC194_IN_SEL_M ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S)) +#define GPIO_FUNC194_IN_SEL_V 0x3F +#define GPIO_FUNC194_IN_SEL_S 0 + +#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x043c) +/* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG195_IN_SEL (BIT(7)) +#define GPIO_SIG195_IN_SEL_M (BIT(7)) +#define GPIO_SIG195_IN_SEL_V 0x1 +#define GPIO_SIG195_IN_SEL_S 7 +/* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC195_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_V 0x1 +#define GPIO_FUNC195_IN_INV_SEL_S 6 +/* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC195_IN_SEL 0x0000003F +#define GPIO_FUNC195_IN_SEL_M ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S)) +#define GPIO_FUNC195_IN_SEL_V 0x3F +#define GPIO_FUNC195_IN_SEL_S 0 + +#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0440) +/* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG196_IN_SEL (BIT(7)) +#define GPIO_SIG196_IN_SEL_M (BIT(7)) +#define GPIO_SIG196_IN_SEL_V 0x1 +#define GPIO_SIG196_IN_SEL_S 7 +/* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC196_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_V 0x1 +#define GPIO_FUNC196_IN_INV_SEL_S 6 +/* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC196_IN_SEL 0x0000003F +#define GPIO_FUNC196_IN_SEL_M ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S)) +#define GPIO_FUNC196_IN_SEL_V 0x3F +#define GPIO_FUNC196_IN_SEL_S 0 + +#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0444) +/* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG197_IN_SEL (BIT(7)) +#define GPIO_SIG197_IN_SEL_M (BIT(7)) +#define GPIO_SIG197_IN_SEL_V 0x1 +#define GPIO_SIG197_IN_SEL_S 7 +/* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC197_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_V 0x1 +#define GPIO_FUNC197_IN_INV_SEL_S 6 +/* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC197_IN_SEL 0x0000003F +#define GPIO_FUNC197_IN_SEL_M ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S)) +#define GPIO_FUNC197_IN_SEL_V 0x3F +#define GPIO_FUNC197_IN_SEL_S 0 + +#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0448) +/* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG198_IN_SEL (BIT(7)) +#define GPIO_SIG198_IN_SEL_M (BIT(7)) +#define GPIO_SIG198_IN_SEL_V 0x1 +#define GPIO_SIG198_IN_SEL_S 7 +/* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC198_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_V 0x1 +#define GPIO_FUNC198_IN_INV_SEL_S 6 +/* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC198_IN_SEL 0x0000003F +#define GPIO_FUNC198_IN_SEL_M ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S)) +#define GPIO_FUNC198_IN_SEL_V 0x3F +#define GPIO_FUNC198_IN_SEL_S 0 + +#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x044c) +/* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG199_IN_SEL (BIT(7)) +#define GPIO_SIG199_IN_SEL_M (BIT(7)) +#define GPIO_SIG199_IN_SEL_V 0x1 +#define GPIO_SIG199_IN_SEL_S 7 +/* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC199_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_V 0x1 +#define GPIO_FUNC199_IN_INV_SEL_S 6 +/* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC199_IN_SEL 0x0000003F +#define GPIO_FUNC199_IN_SEL_M ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S)) +#define GPIO_FUNC199_IN_SEL_V 0x3F +#define GPIO_FUNC199_IN_SEL_S 0 + +#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0450) +/* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG200_IN_SEL (BIT(7)) +#define GPIO_SIG200_IN_SEL_M (BIT(7)) +#define GPIO_SIG200_IN_SEL_V 0x1 +#define GPIO_SIG200_IN_SEL_S 7 +/* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC200_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_V 0x1 +#define GPIO_FUNC200_IN_INV_SEL_S 6 +/* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC200_IN_SEL 0x0000003F +#define GPIO_FUNC200_IN_SEL_M ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S)) +#define GPIO_FUNC200_IN_SEL_V 0x3F +#define GPIO_FUNC200_IN_SEL_S 0 + +#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0454) +/* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG201_IN_SEL (BIT(7)) +#define GPIO_SIG201_IN_SEL_M (BIT(7)) +#define GPIO_SIG201_IN_SEL_V 0x1 +#define GPIO_SIG201_IN_SEL_S 7 +/* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC201_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_V 0x1 +#define GPIO_FUNC201_IN_INV_SEL_S 6 +/* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC201_IN_SEL 0x0000003F +#define GPIO_FUNC201_IN_SEL_M ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S)) +#define GPIO_FUNC201_IN_SEL_V 0x3F +#define GPIO_FUNC201_IN_SEL_S 0 + +#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0458) +/* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG202_IN_SEL (BIT(7)) +#define GPIO_SIG202_IN_SEL_M (BIT(7)) +#define GPIO_SIG202_IN_SEL_V 0x1 +#define GPIO_SIG202_IN_SEL_S 7 +/* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC202_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_V 0x1 +#define GPIO_FUNC202_IN_INV_SEL_S 6 +/* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC202_IN_SEL 0x0000003F +#define GPIO_FUNC202_IN_SEL_M ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S)) +#define GPIO_FUNC202_IN_SEL_V 0x3F +#define GPIO_FUNC202_IN_SEL_S 0 + +#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x045c) +/* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG203_IN_SEL (BIT(7)) +#define GPIO_SIG203_IN_SEL_M (BIT(7)) +#define GPIO_SIG203_IN_SEL_V 0x1 +#define GPIO_SIG203_IN_SEL_S 7 +/* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC203_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_V 0x1 +#define GPIO_FUNC203_IN_INV_SEL_S 6 +/* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC203_IN_SEL 0x0000003F +#define GPIO_FUNC203_IN_SEL_M ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S)) +#define GPIO_FUNC203_IN_SEL_V 0x3F +#define GPIO_FUNC203_IN_SEL_S 0 + +#define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0460) +/* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG204_IN_SEL (BIT(7)) +#define GPIO_SIG204_IN_SEL_M (BIT(7)) +#define GPIO_SIG204_IN_SEL_V 0x1 +#define GPIO_SIG204_IN_SEL_S 7 +/* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC204_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_V 0x1 +#define GPIO_FUNC204_IN_INV_SEL_S 6 +/* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC204_IN_SEL 0x0000003F +#define GPIO_FUNC204_IN_SEL_M ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S)) +#define GPIO_FUNC204_IN_SEL_V 0x3F +#define GPIO_FUNC204_IN_SEL_S 0 + +#define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0464) +/* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG205_IN_SEL (BIT(7)) +#define GPIO_SIG205_IN_SEL_M (BIT(7)) +#define GPIO_SIG205_IN_SEL_V 0x1 +#define GPIO_SIG205_IN_SEL_S 7 +/* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC205_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_V 0x1 +#define GPIO_FUNC205_IN_INV_SEL_S 6 +/* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC205_IN_SEL 0x0000003F +#define GPIO_FUNC205_IN_SEL_M ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S)) +#define GPIO_FUNC205_IN_SEL_V 0x3F +#define GPIO_FUNC205_IN_SEL_S 0 + +#define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0468) +/* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG206_IN_SEL (BIT(7)) +#define GPIO_SIG206_IN_SEL_M (BIT(7)) +#define GPIO_SIG206_IN_SEL_V 0x1 +#define GPIO_SIG206_IN_SEL_S 7 +/* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC206_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_V 0x1 +#define GPIO_FUNC206_IN_INV_SEL_S 6 +/* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC206_IN_SEL 0x0000003F +#define GPIO_FUNC206_IN_SEL_M ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S)) +#define GPIO_FUNC206_IN_SEL_V 0x3F +#define GPIO_FUNC206_IN_SEL_S 0 + +#define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x046c) +/* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG207_IN_SEL (BIT(7)) +#define GPIO_SIG207_IN_SEL_M (BIT(7)) +#define GPIO_SIG207_IN_SEL_V 0x1 +#define GPIO_SIG207_IN_SEL_S 7 +/* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC207_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_V 0x1 +#define GPIO_FUNC207_IN_INV_SEL_S 6 +/* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC207_IN_SEL 0x0000003F +#define GPIO_FUNC207_IN_SEL_M ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S)) +#define GPIO_FUNC207_IN_SEL_V 0x3F +#define GPIO_FUNC207_IN_SEL_S 0 + +#define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0470) +/* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG208_IN_SEL (BIT(7)) +#define GPIO_SIG208_IN_SEL_M (BIT(7)) +#define GPIO_SIG208_IN_SEL_V 0x1 +#define GPIO_SIG208_IN_SEL_S 7 +/* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC208_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_V 0x1 +#define GPIO_FUNC208_IN_INV_SEL_S 6 +/* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC208_IN_SEL 0x0000003F +#define GPIO_FUNC208_IN_SEL_M ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S)) +#define GPIO_FUNC208_IN_SEL_V 0x3F +#define GPIO_FUNC208_IN_SEL_S 0 + +#define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0474) +/* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG209_IN_SEL (BIT(7)) +#define GPIO_SIG209_IN_SEL_M (BIT(7)) +#define GPIO_SIG209_IN_SEL_V 0x1 +#define GPIO_SIG209_IN_SEL_S 7 +/* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC209_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_V 0x1 +#define GPIO_FUNC209_IN_INV_SEL_S 6 +/* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC209_IN_SEL 0x0000003F +#define GPIO_FUNC209_IN_SEL_M ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S)) +#define GPIO_FUNC209_IN_SEL_V 0x3F +#define GPIO_FUNC209_IN_SEL_S 0 + +#define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0478) +/* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG210_IN_SEL (BIT(7)) +#define GPIO_SIG210_IN_SEL_M (BIT(7)) +#define GPIO_SIG210_IN_SEL_V 0x1 +#define GPIO_SIG210_IN_SEL_S 7 +/* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC210_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_V 0x1 +#define GPIO_FUNC210_IN_INV_SEL_S 6 +/* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC210_IN_SEL 0x0000003F +#define GPIO_FUNC210_IN_SEL_M ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S)) +#define GPIO_FUNC210_IN_SEL_V 0x3F +#define GPIO_FUNC210_IN_SEL_S 0 + +#define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x047c) +/* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG211_IN_SEL (BIT(7)) +#define GPIO_SIG211_IN_SEL_M (BIT(7)) +#define GPIO_SIG211_IN_SEL_V 0x1 +#define GPIO_SIG211_IN_SEL_S 7 +/* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC211_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_V 0x1 +#define GPIO_FUNC211_IN_INV_SEL_S 6 +/* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC211_IN_SEL 0x0000003F +#define GPIO_FUNC211_IN_SEL_M ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S)) +#define GPIO_FUNC211_IN_SEL_V 0x3F +#define GPIO_FUNC211_IN_SEL_S 0 + +#define GPIO_FUNC212_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0480) +/* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG212_IN_SEL (BIT(7)) +#define GPIO_SIG212_IN_SEL_M (BIT(7)) +#define GPIO_SIG212_IN_SEL_V 0x1 +#define GPIO_SIG212_IN_SEL_S 7 +/* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC212_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_V 0x1 +#define GPIO_FUNC212_IN_INV_SEL_S 6 +/* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC212_IN_SEL 0x0000003F +#define GPIO_FUNC212_IN_SEL_M ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S)) +#define GPIO_FUNC212_IN_SEL_V 0x3F +#define GPIO_FUNC212_IN_SEL_S 0 + +#define GPIO_FUNC213_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0484) +/* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG213_IN_SEL (BIT(7)) +#define GPIO_SIG213_IN_SEL_M (BIT(7)) +#define GPIO_SIG213_IN_SEL_V 0x1 +#define GPIO_SIG213_IN_SEL_S 7 +/* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC213_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_V 0x1 +#define GPIO_FUNC213_IN_INV_SEL_S 6 +/* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC213_IN_SEL 0x0000003F +#define GPIO_FUNC213_IN_SEL_M ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S)) +#define GPIO_FUNC213_IN_SEL_V 0x3F +#define GPIO_FUNC213_IN_SEL_S 0 + +#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0488) +/* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG214_IN_SEL (BIT(7)) +#define GPIO_SIG214_IN_SEL_M (BIT(7)) +#define GPIO_SIG214_IN_SEL_V 0x1 +#define GPIO_SIG214_IN_SEL_S 7 +/* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC214_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_V 0x1 +#define GPIO_FUNC214_IN_INV_SEL_S 6 +/* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC214_IN_SEL 0x0000003F +#define GPIO_FUNC214_IN_SEL_M ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S)) +#define GPIO_FUNC214_IN_SEL_V 0x3F +#define GPIO_FUNC214_IN_SEL_S 0 + +#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x048c) +/* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG215_IN_SEL (BIT(7)) +#define GPIO_SIG215_IN_SEL_M (BIT(7)) +#define GPIO_SIG215_IN_SEL_V 0x1 +#define GPIO_SIG215_IN_SEL_S 7 +/* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC215_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_V 0x1 +#define GPIO_FUNC215_IN_INV_SEL_S 6 +/* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC215_IN_SEL 0x0000003F +#define GPIO_FUNC215_IN_SEL_M ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S)) +#define GPIO_FUNC215_IN_SEL_V 0x3F +#define GPIO_FUNC215_IN_SEL_S 0 + +#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0490) +/* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG216_IN_SEL (BIT(7)) +#define GPIO_SIG216_IN_SEL_M (BIT(7)) +#define GPIO_SIG216_IN_SEL_V 0x1 +#define GPIO_SIG216_IN_SEL_S 7 +/* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC216_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_V 0x1 +#define GPIO_FUNC216_IN_INV_SEL_S 6 +/* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC216_IN_SEL 0x0000003F +#define GPIO_FUNC216_IN_SEL_M ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S)) +#define GPIO_FUNC216_IN_SEL_V 0x3F +#define GPIO_FUNC216_IN_SEL_S 0 + +#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0494) +/* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG217_IN_SEL (BIT(7)) +#define GPIO_SIG217_IN_SEL_M (BIT(7)) +#define GPIO_SIG217_IN_SEL_V 0x1 +#define GPIO_SIG217_IN_SEL_S 7 +/* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC217_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_V 0x1 +#define GPIO_FUNC217_IN_INV_SEL_S 6 +/* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC217_IN_SEL 0x0000003F +#define GPIO_FUNC217_IN_SEL_M ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S)) +#define GPIO_FUNC217_IN_SEL_V 0x3F +#define GPIO_FUNC217_IN_SEL_S 0 + +#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0498) +/* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG218_IN_SEL (BIT(7)) +#define GPIO_SIG218_IN_SEL_M (BIT(7)) +#define GPIO_SIG218_IN_SEL_V 0x1 +#define GPIO_SIG218_IN_SEL_S 7 +/* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC218_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_V 0x1 +#define GPIO_FUNC218_IN_INV_SEL_S 6 +/* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC218_IN_SEL 0x0000003F +#define GPIO_FUNC218_IN_SEL_M ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S)) +#define GPIO_FUNC218_IN_SEL_V 0x3F +#define GPIO_FUNC218_IN_SEL_S 0 + +#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x049c) +/* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG219_IN_SEL (BIT(7)) +#define GPIO_SIG219_IN_SEL_M (BIT(7)) +#define GPIO_SIG219_IN_SEL_V 0x1 +#define GPIO_SIG219_IN_SEL_S 7 +/* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC219_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_V 0x1 +#define GPIO_FUNC219_IN_INV_SEL_S 6 +/* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC219_IN_SEL 0x0000003F +#define GPIO_FUNC219_IN_SEL_M ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S)) +#define GPIO_FUNC219_IN_SEL_V 0x3F +#define GPIO_FUNC219_IN_SEL_S 0 + +#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a0) +/* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG220_IN_SEL (BIT(7)) +#define GPIO_SIG220_IN_SEL_M (BIT(7)) +#define GPIO_SIG220_IN_SEL_V 0x1 +#define GPIO_SIG220_IN_SEL_S 7 +/* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC220_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_V 0x1 +#define GPIO_FUNC220_IN_INV_SEL_S 6 +/* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC220_IN_SEL 0x0000003F +#define GPIO_FUNC220_IN_SEL_M ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S)) +#define GPIO_FUNC220_IN_SEL_V 0x3F +#define GPIO_FUNC220_IN_SEL_S 0 + +#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a4) +/* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG221_IN_SEL (BIT(7)) +#define GPIO_SIG221_IN_SEL_M (BIT(7)) +#define GPIO_SIG221_IN_SEL_V 0x1 +#define GPIO_SIG221_IN_SEL_S 7 +/* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC221_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_V 0x1 +#define GPIO_FUNC221_IN_INV_SEL_S 6 +/* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC221_IN_SEL 0x0000003F +#define GPIO_FUNC221_IN_SEL_M ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S)) +#define GPIO_FUNC221_IN_SEL_V 0x3F +#define GPIO_FUNC221_IN_SEL_S 0 + +#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a8) +/* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG222_IN_SEL (BIT(7)) +#define GPIO_SIG222_IN_SEL_M (BIT(7)) +#define GPIO_SIG222_IN_SEL_V 0x1 +#define GPIO_SIG222_IN_SEL_S 7 +/* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC222_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_V 0x1 +#define GPIO_FUNC222_IN_INV_SEL_S 6 +/* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC222_IN_SEL 0x0000003F +#define GPIO_FUNC222_IN_SEL_M ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S)) +#define GPIO_FUNC222_IN_SEL_V 0x3F +#define GPIO_FUNC222_IN_SEL_S 0 + +#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ac) +/* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG223_IN_SEL (BIT(7)) +#define GPIO_SIG223_IN_SEL_M (BIT(7)) +#define GPIO_SIG223_IN_SEL_V 0x1 +#define GPIO_SIG223_IN_SEL_S 7 +/* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC223_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_V 0x1 +#define GPIO_FUNC223_IN_INV_SEL_S 6 +/* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC223_IN_SEL 0x0000003F +#define GPIO_FUNC223_IN_SEL_M ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S)) +#define GPIO_FUNC223_IN_SEL_V 0x3F +#define GPIO_FUNC223_IN_SEL_S 0 + +#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b0) +/* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG224_IN_SEL (BIT(7)) +#define GPIO_SIG224_IN_SEL_M (BIT(7)) +#define GPIO_SIG224_IN_SEL_V 0x1 +#define GPIO_SIG224_IN_SEL_S 7 +/* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC224_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_V 0x1 +#define GPIO_FUNC224_IN_INV_SEL_S 6 +/* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC224_IN_SEL 0x0000003F +#define GPIO_FUNC224_IN_SEL_M ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S)) +#define GPIO_FUNC224_IN_SEL_V 0x3F +#define GPIO_FUNC224_IN_SEL_S 0 + +#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b4) +/* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG225_IN_SEL (BIT(7)) +#define GPIO_SIG225_IN_SEL_M (BIT(7)) +#define GPIO_SIG225_IN_SEL_V 0x1 +#define GPIO_SIG225_IN_SEL_S 7 +/* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC225_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_V 0x1 +#define GPIO_FUNC225_IN_INV_SEL_S 6 +/* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC225_IN_SEL 0x0000003F +#define GPIO_FUNC225_IN_SEL_M ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S)) +#define GPIO_FUNC225_IN_SEL_V 0x3F +#define GPIO_FUNC225_IN_SEL_S 0 + +#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b8) +/* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG226_IN_SEL (BIT(7)) +#define GPIO_SIG226_IN_SEL_M (BIT(7)) +#define GPIO_SIG226_IN_SEL_V 0x1 +#define GPIO_SIG226_IN_SEL_S 7 +/* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC226_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_V 0x1 +#define GPIO_FUNC226_IN_INV_SEL_S 6 +/* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC226_IN_SEL 0x0000003F +#define GPIO_FUNC226_IN_SEL_M ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S)) +#define GPIO_FUNC226_IN_SEL_V 0x3F +#define GPIO_FUNC226_IN_SEL_S 0 + +#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04bc) +/* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG227_IN_SEL (BIT(7)) +#define GPIO_SIG227_IN_SEL_M (BIT(7)) +#define GPIO_SIG227_IN_SEL_V 0x1 +#define GPIO_SIG227_IN_SEL_S 7 +/* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC227_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_V 0x1 +#define GPIO_FUNC227_IN_INV_SEL_S 6 +/* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC227_IN_SEL 0x0000003F +#define GPIO_FUNC227_IN_SEL_M ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S)) +#define GPIO_FUNC227_IN_SEL_V 0x3F +#define GPIO_FUNC227_IN_SEL_S 0 + +#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c0) +/* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG228_IN_SEL (BIT(7)) +#define GPIO_SIG228_IN_SEL_M (BIT(7)) +#define GPIO_SIG228_IN_SEL_V 0x1 +#define GPIO_SIG228_IN_SEL_S 7 +/* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC228_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_V 0x1 +#define GPIO_FUNC228_IN_INV_SEL_S 6 +/* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC228_IN_SEL 0x0000003F +#define GPIO_FUNC228_IN_SEL_M ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S)) +#define GPIO_FUNC228_IN_SEL_V 0x3F +#define GPIO_FUNC228_IN_SEL_S 0 + +#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c4) +/* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG229_IN_SEL (BIT(7)) +#define GPIO_SIG229_IN_SEL_M (BIT(7)) +#define GPIO_SIG229_IN_SEL_V 0x1 +#define GPIO_SIG229_IN_SEL_S 7 +/* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC229_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_V 0x1 +#define GPIO_FUNC229_IN_INV_SEL_S 6 +/* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC229_IN_SEL 0x0000003F +#define GPIO_FUNC229_IN_SEL_M ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S)) +#define GPIO_FUNC229_IN_SEL_V 0x3F +#define GPIO_FUNC229_IN_SEL_S 0 + +#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c8) +/* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG230_IN_SEL (BIT(7)) +#define GPIO_SIG230_IN_SEL_M (BIT(7)) +#define GPIO_SIG230_IN_SEL_V 0x1 +#define GPIO_SIG230_IN_SEL_S 7 +/* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC230_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_V 0x1 +#define GPIO_FUNC230_IN_INV_SEL_S 6 +/* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC230_IN_SEL 0x0000003F +#define GPIO_FUNC230_IN_SEL_M ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S)) +#define GPIO_FUNC230_IN_SEL_V 0x3F +#define GPIO_FUNC230_IN_SEL_S 0 + +#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04cc) +/* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG231_IN_SEL (BIT(7)) +#define GPIO_SIG231_IN_SEL_M (BIT(7)) +#define GPIO_SIG231_IN_SEL_V 0x1 +#define GPIO_SIG231_IN_SEL_S 7 +/* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC231_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_V 0x1 +#define GPIO_FUNC231_IN_INV_SEL_S 6 +/* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC231_IN_SEL 0x0000003F +#define GPIO_FUNC231_IN_SEL_M ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S)) +#define GPIO_FUNC231_IN_SEL_V 0x3F +#define GPIO_FUNC231_IN_SEL_S 0 + +#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d0) +/* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG232_IN_SEL (BIT(7)) +#define GPIO_SIG232_IN_SEL_M (BIT(7)) +#define GPIO_SIG232_IN_SEL_V 0x1 +#define GPIO_SIG232_IN_SEL_S 7 +/* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC232_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_V 0x1 +#define GPIO_FUNC232_IN_INV_SEL_S 6 +/* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC232_IN_SEL 0x0000003F +#define GPIO_FUNC232_IN_SEL_M ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S)) +#define GPIO_FUNC232_IN_SEL_V 0x3F +#define GPIO_FUNC232_IN_SEL_S 0 + +#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d4) +/* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG233_IN_SEL (BIT(7)) +#define GPIO_SIG233_IN_SEL_M (BIT(7)) +#define GPIO_SIG233_IN_SEL_V 0x1 +#define GPIO_SIG233_IN_SEL_S 7 +/* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC233_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_V 0x1 +#define GPIO_FUNC233_IN_INV_SEL_S 6 +/* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC233_IN_SEL 0x0000003F +#define GPIO_FUNC233_IN_SEL_M ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S)) +#define GPIO_FUNC233_IN_SEL_V 0x3F +#define GPIO_FUNC233_IN_SEL_S 0 + +#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d8) +/* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG234_IN_SEL (BIT(7)) +#define GPIO_SIG234_IN_SEL_M (BIT(7)) +#define GPIO_SIG234_IN_SEL_V 0x1 +#define GPIO_SIG234_IN_SEL_S 7 +/* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC234_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_V 0x1 +#define GPIO_FUNC234_IN_INV_SEL_S 6 +/* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC234_IN_SEL 0x0000003F +#define GPIO_FUNC234_IN_SEL_M ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S)) +#define GPIO_FUNC234_IN_SEL_V 0x3F +#define GPIO_FUNC234_IN_SEL_S 0 + +#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04dc) +/* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG235_IN_SEL (BIT(7)) +#define GPIO_SIG235_IN_SEL_M (BIT(7)) +#define GPIO_SIG235_IN_SEL_V 0x1 +#define GPIO_SIG235_IN_SEL_S 7 +/* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC235_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_V 0x1 +#define GPIO_FUNC235_IN_INV_SEL_S 6 +/* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC235_IN_SEL 0x0000003F +#define GPIO_FUNC235_IN_SEL_M ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S)) +#define GPIO_FUNC235_IN_SEL_V 0x3F +#define GPIO_FUNC235_IN_SEL_S 0 + +#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e0) +/* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG236_IN_SEL (BIT(7)) +#define GPIO_SIG236_IN_SEL_M (BIT(7)) +#define GPIO_SIG236_IN_SEL_V 0x1 +#define GPIO_SIG236_IN_SEL_S 7 +/* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC236_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_V 0x1 +#define GPIO_FUNC236_IN_INV_SEL_S 6 +/* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC236_IN_SEL 0x0000003F +#define GPIO_FUNC236_IN_SEL_M ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S)) +#define GPIO_FUNC236_IN_SEL_V 0x3F +#define GPIO_FUNC236_IN_SEL_S 0 + +#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e4) +/* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG237_IN_SEL (BIT(7)) +#define GPIO_SIG237_IN_SEL_M (BIT(7)) +#define GPIO_SIG237_IN_SEL_V 0x1 +#define GPIO_SIG237_IN_SEL_S 7 +/* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC237_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_V 0x1 +#define GPIO_FUNC237_IN_INV_SEL_S 6 +/* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC237_IN_SEL 0x0000003F +#define GPIO_FUNC237_IN_SEL_M ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S)) +#define GPIO_FUNC237_IN_SEL_V 0x3F +#define GPIO_FUNC237_IN_SEL_S 0 + +#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e8) +/* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG238_IN_SEL (BIT(7)) +#define GPIO_SIG238_IN_SEL_M (BIT(7)) +#define GPIO_SIG238_IN_SEL_V 0x1 +#define GPIO_SIG238_IN_SEL_S 7 +/* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC238_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_V 0x1 +#define GPIO_FUNC238_IN_INV_SEL_S 6 +/* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC238_IN_SEL 0x0000003F +#define GPIO_FUNC238_IN_SEL_M ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S)) +#define GPIO_FUNC238_IN_SEL_V 0x3F +#define GPIO_FUNC238_IN_SEL_S 0 + +#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ec) +/* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG239_IN_SEL (BIT(7)) +#define GPIO_SIG239_IN_SEL_M (BIT(7)) +#define GPIO_SIG239_IN_SEL_V 0x1 +#define GPIO_SIG239_IN_SEL_S 7 +/* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC239_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_V 0x1 +#define GPIO_FUNC239_IN_INV_SEL_S 6 +/* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC239_IN_SEL 0x0000003F +#define GPIO_FUNC239_IN_SEL_M ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S)) +#define GPIO_FUNC239_IN_SEL_V 0x3F +#define GPIO_FUNC239_IN_SEL_S 0 + +#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f0) +/* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG240_IN_SEL (BIT(7)) +#define GPIO_SIG240_IN_SEL_M (BIT(7)) +#define GPIO_SIG240_IN_SEL_V 0x1 +#define GPIO_SIG240_IN_SEL_S 7 +/* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC240_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_V 0x1 +#define GPIO_FUNC240_IN_INV_SEL_S 6 +/* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC240_IN_SEL 0x0000003F +#define GPIO_FUNC240_IN_SEL_M ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S)) +#define GPIO_FUNC240_IN_SEL_V 0x3F +#define GPIO_FUNC240_IN_SEL_S 0 + +#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f4) +/* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG241_IN_SEL (BIT(7)) +#define GPIO_SIG241_IN_SEL_M (BIT(7)) +#define GPIO_SIG241_IN_SEL_V 0x1 +#define GPIO_SIG241_IN_SEL_S 7 +/* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC241_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_V 0x1 +#define GPIO_FUNC241_IN_INV_SEL_S 6 +/* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC241_IN_SEL 0x0000003F +#define GPIO_FUNC241_IN_SEL_M ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S)) +#define GPIO_FUNC241_IN_SEL_V 0x3F +#define GPIO_FUNC241_IN_SEL_S 0 + +#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f8) +/* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG242_IN_SEL (BIT(7)) +#define GPIO_SIG242_IN_SEL_M (BIT(7)) +#define GPIO_SIG242_IN_SEL_V 0x1 +#define GPIO_SIG242_IN_SEL_S 7 +/* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC242_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_V 0x1 +#define GPIO_FUNC242_IN_INV_SEL_S 6 +/* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC242_IN_SEL 0x0000003F +#define GPIO_FUNC242_IN_SEL_M ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S)) +#define GPIO_FUNC242_IN_SEL_V 0x3F +#define GPIO_FUNC242_IN_SEL_S 0 + +#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04fc) +/* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG243_IN_SEL (BIT(7)) +#define GPIO_SIG243_IN_SEL_M (BIT(7)) +#define GPIO_SIG243_IN_SEL_V 0x1 +#define GPIO_SIG243_IN_SEL_S 7 +/* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC243_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_V 0x1 +#define GPIO_FUNC243_IN_INV_SEL_S 6 +/* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC243_IN_SEL 0x0000003F +#define GPIO_FUNC243_IN_SEL_M ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S)) +#define GPIO_FUNC243_IN_SEL_V 0x3F +#define GPIO_FUNC243_IN_SEL_S 0 + +#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0500) +/* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG244_IN_SEL (BIT(7)) +#define GPIO_SIG244_IN_SEL_M (BIT(7)) +#define GPIO_SIG244_IN_SEL_V 0x1 +#define GPIO_SIG244_IN_SEL_S 7 +/* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC244_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_V 0x1 +#define GPIO_FUNC244_IN_INV_SEL_S 6 +/* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC244_IN_SEL 0x0000003F +#define GPIO_FUNC244_IN_SEL_M ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S)) +#define GPIO_FUNC244_IN_SEL_V 0x3F +#define GPIO_FUNC244_IN_SEL_S 0 + +#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0504) +/* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG245_IN_SEL (BIT(7)) +#define GPIO_SIG245_IN_SEL_M (BIT(7)) +#define GPIO_SIG245_IN_SEL_V 0x1 +#define GPIO_SIG245_IN_SEL_S 7 +/* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC245_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_V 0x1 +#define GPIO_FUNC245_IN_INV_SEL_S 6 +/* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC245_IN_SEL 0x0000003F +#define GPIO_FUNC245_IN_SEL_M ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S)) +#define GPIO_FUNC245_IN_SEL_V 0x3F +#define GPIO_FUNC245_IN_SEL_S 0 + +#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0508) +/* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG246_IN_SEL (BIT(7)) +#define GPIO_SIG246_IN_SEL_M (BIT(7)) +#define GPIO_SIG246_IN_SEL_V 0x1 +#define GPIO_SIG246_IN_SEL_S 7 +/* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC246_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_V 0x1 +#define GPIO_FUNC246_IN_INV_SEL_S 6 +/* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC246_IN_SEL 0x0000003F +#define GPIO_FUNC246_IN_SEL_M ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S)) +#define GPIO_FUNC246_IN_SEL_V 0x3F +#define GPIO_FUNC246_IN_SEL_S 0 + +#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x050c) +/* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG247_IN_SEL (BIT(7)) +#define GPIO_SIG247_IN_SEL_M (BIT(7)) +#define GPIO_SIG247_IN_SEL_V 0x1 +#define GPIO_SIG247_IN_SEL_S 7 +/* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC247_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_V 0x1 +#define GPIO_FUNC247_IN_INV_SEL_S 6 +/* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC247_IN_SEL 0x0000003F +#define GPIO_FUNC247_IN_SEL_M ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S)) +#define GPIO_FUNC247_IN_SEL_V 0x3F +#define GPIO_FUNC247_IN_SEL_S 0 + +#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0510) +/* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG248_IN_SEL (BIT(7)) +#define GPIO_SIG248_IN_SEL_M (BIT(7)) +#define GPIO_SIG248_IN_SEL_V 0x1 +#define GPIO_SIG248_IN_SEL_S 7 +/* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC248_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_V 0x1 +#define GPIO_FUNC248_IN_INV_SEL_S 6 +/* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC248_IN_SEL 0x0000003F +#define GPIO_FUNC248_IN_SEL_M ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S)) +#define GPIO_FUNC248_IN_SEL_V 0x3F +#define GPIO_FUNC248_IN_SEL_S 0 + +#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0514) +/* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG249_IN_SEL (BIT(7)) +#define GPIO_SIG249_IN_SEL_M (BIT(7)) +#define GPIO_SIG249_IN_SEL_V 0x1 +#define GPIO_SIG249_IN_SEL_S 7 +/* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC249_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_V 0x1 +#define GPIO_FUNC249_IN_INV_SEL_S 6 +/* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC249_IN_SEL 0x0000003F +#define GPIO_FUNC249_IN_SEL_M ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S)) +#define GPIO_FUNC249_IN_SEL_V 0x3F +#define GPIO_FUNC249_IN_SEL_S 0 + +#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0518) +/* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG250_IN_SEL (BIT(7)) +#define GPIO_SIG250_IN_SEL_M (BIT(7)) +#define GPIO_SIG250_IN_SEL_V 0x1 +#define GPIO_SIG250_IN_SEL_S 7 +/* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC250_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_V 0x1 +#define GPIO_FUNC250_IN_INV_SEL_S 6 +/* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC250_IN_SEL 0x0000003F +#define GPIO_FUNC250_IN_SEL_M ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S)) +#define GPIO_FUNC250_IN_SEL_V 0x3F +#define GPIO_FUNC250_IN_SEL_S 0 + +#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x051c) +/* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG251_IN_SEL (BIT(7)) +#define GPIO_SIG251_IN_SEL_M (BIT(7)) +#define GPIO_SIG251_IN_SEL_V 0x1 +#define GPIO_SIG251_IN_SEL_S 7 +/* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC251_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_V 0x1 +#define GPIO_FUNC251_IN_INV_SEL_S 6 +/* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC251_IN_SEL 0x0000003F +#define GPIO_FUNC251_IN_SEL_M ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S)) +#define GPIO_FUNC251_IN_SEL_V 0x3F +#define GPIO_FUNC251_IN_SEL_S 0 + +#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0520) +/* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG252_IN_SEL (BIT(7)) +#define GPIO_SIG252_IN_SEL_M (BIT(7)) +#define GPIO_SIG252_IN_SEL_V 0x1 +#define GPIO_SIG252_IN_SEL_S 7 +/* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC252_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_V 0x1 +#define GPIO_FUNC252_IN_INV_SEL_S 6 +/* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC252_IN_SEL 0x0000003F +#define GPIO_FUNC252_IN_SEL_M ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S)) +#define GPIO_FUNC252_IN_SEL_V 0x3F +#define GPIO_FUNC252_IN_SEL_S 0 + +#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0524) +/* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG253_IN_SEL (BIT(7)) +#define GPIO_SIG253_IN_SEL_M (BIT(7)) +#define GPIO_SIG253_IN_SEL_V 0x1 +#define GPIO_SIG253_IN_SEL_S 7 +/* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC253_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_V 0x1 +#define GPIO_FUNC253_IN_INV_SEL_S 6 +/* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC253_IN_SEL 0x0000003F +#define GPIO_FUNC253_IN_SEL_M ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S)) +#define GPIO_FUNC253_IN_SEL_V 0x3F +#define GPIO_FUNC253_IN_SEL_S 0 + +#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0528) +/* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG254_IN_SEL (BIT(7)) +#define GPIO_SIG254_IN_SEL_M (BIT(7)) +#define GPIO_SIG254_IN_SEL_V 0x1 +#define GPIO_SIG254_IN_SEL_S 7 +/* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC254_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_V 0x1 +#define GPIO_FUNC254_IN_INV_SEL_S 6 +/* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC254_IN_SEL 0x0000003F +#define GPIO_FUNC254_IN_SEL_M ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S)) +#define GPIO_FUNC254_IN_SEL_V 0x3F +#define GPIO_FUNC254_IN_SEL_S 0 + +#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x052c) +/* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG255_IN_SEL (BIT(7)) +#define GPIO_SIG255_IN_SEL_M (BIT(7)) +#define GPIO_SIG255_IN_SEL_V 0x1 +#define GPIO_SIG255_IN_SEL_S 7 +/* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC255_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_V 0x1 +#define GPIO_FUNC255_IN_INV_SEL_S 6 +/* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC255_IN_SEL 0x0000003F +#define GPIO_FUNC255_IN_SEL_M ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S)) +#define GPIO_FUNC255_IN_SEL_V 0x3F +#define GPIO_FUNC255_IN_SEL_S 0 + +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0530) +/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC0_OEN_INV_SEL_S 11 +/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC0_OEN_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_V 0x1 +#define GPIO_FUNC0_OEN_SEL_S 10 +/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC0_OUT_INV_SEL_S 9 +/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC0_OUT_SEL 0x000001FF +#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) +#define GPIO_FUNC0_OUT_SEL_V 0x1FF +#define GPIO_FUNC0_OUT_SEL_S 0 + +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0534) +/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC1_OEN_INV_SEL_S 11 +/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC1_OEN_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_V 0x1 +#define GPIO_FUNC1_OEN_SEL_S 10 +/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC1_OUT_INV_SEL_S 9 +/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC1_OUT_SEL 0x000001FF +#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) +#define GPIO_FUNC1_OUT_SEL_V 0x1FF +#define GPIO_FUNC1_OUT_SEL_S 0 + +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0538) +/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC2_OEN_INV_SEL_S 11 +/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC2_OEN_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_V 0x1 +#define GPIO_FUNC2_OEN_SEL_S 10 +/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC2_OUT_INV_SEL_S 9 +/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC2_OUT_SEL 0x000001FF +#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) +#define GPIO_FUNC2_OUT_SEL_V 0x1FF +#define GPIO_FUNC2_OUT_SEL_S 0 + +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x053c) +/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC3_OEN_INV_SEL_S 11 +/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC3_OEN_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_V 0x1 +#define GPIO_FUNC3_OEN_SEL_S 10 +/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC3_OUT_INV_SEL_S 9 +/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC3_OUT_SEL 0x000001FF +#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) +#define GPIO_FUNC3_OUT_SEL_V 0x1FF +#define GPIO_FUNC3_OUT_SEL_S 0 + +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0540) +/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC4_OEN_INV_SEL_S 11 +/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC4_OEN_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_V 0x1 +#define GPIO_FUNC4_OEN_SEL_S 10 +/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC4_OUT_INV_SEL_S 9 +/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC4_OUT_SEL 0x000001FF +#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) +#define GPIO_FUNC4_OUT_SEL_V 0x1FF +#define GPIO_FUNC4_OUT_SEL_S 0 + +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0544) +/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC5_OEN_INV_SEL_S 11 +/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC5_OEN_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_V 0x1 +#define GPIO_FUNC5_OEN_SEL_S 10 +/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC5_OUT_INV_SEL_S 9 +/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC5_OUT_SEL 0x000001FF +#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) +#define GPIO_FUNC5_OUT_SEL_V 0x1FF +#define GPIO_FUNC5_OUT_SEL_S 0 + +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0548) +/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC6_OEN_INV_SEL_S 11 +/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC6_OEN_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_V 0x1 +#define GPIO_FUNC6_OEN_SEL_S 10 +/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC6_OUT_INV_SEL_S 9 +/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC6_OUT_SEL 0x000001FF +#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) +#define GPIO_FUNC6_OUT_SEL_V 0x1FF +#define GPIO_FUNC6_OUT_SEL_S 0 + +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x054c) +/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC7_OEN_INV_SEL_S 11 +/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC7_OEN_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_V 0x1 +#define GPIO_FUNC7_OEN_SEL_S 10 +/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC7_OUT_INV_SEL_S 9 +/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC7_OUT_SEL 0x000001FF +#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) +#define GPIO_FUNC7_OUT_SEL_V 0x1FF +#define GPIO_FUNC7_OUT_SEL_S 0 + +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0550) +/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC8_OEN_INV_SEL_S 11 +/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC8_OEN_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_V 0x1 +#define GPIO_FUNC8_OEN_SEL_S 10 +/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC8_OUT_INV_SEL_S 9 +/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC8_OUT_SEL 0x000001FF +#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) +#define GPIO_FUNC8_OUT_SEL_V 0x1FF +#define GPIO_FUNC8_OUT_SEL_S 0 + +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0554) +/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC9_OEN_INV_SEL_S 11 +/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC9_OEN_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_V 0x1 +#define GPIO_FUNC9_OEN_SEL_S 10 +/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC9_OUT_INV_SEL_S 9 +/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC9_OUT_SEL 0x000001FF +#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) +#define GPIO_FUNC9_OUT_SEL_V 0x1FF +#define GPIO_FUNC9_OUT_SEL_S 0 + +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0558) +/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC10_OEN_INV_SEL_S 11 +/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC10_OEN_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_V 0x1 +#define GPIO_FUNC10_OEN_SEL_S 10 +/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC10_OUT_INV_SEL_S 9 +/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC10_OUT_SEL 0x000001FF +#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) +#define GPIO_FUNC10_OUT_SEL_V 0x1FF +#define GPIO_FUNC10_OUT_SEL_S 0 + +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x055c) +/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC11_OEN_INV_SEL_S 11 +/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC11_OEN_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_V 0x1 +#define GPIO_FUNC11_OEN_SEL_S 10 +/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC11_OUT_INV_SEL_S 9 +/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC11_OUT_SEL 0x000001FF +#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) +#define GPIO_FUNC11_OUT_SEL_V 0x1FF +#define GPIO_FUNC11_OUT_SEL_S 0 + +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0560) +/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC12_OEN_INV_SEL_S 11 +/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC12_OEN_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_V 0x1 +#define GPIO_FUNC12_OEN_SEL_S 10 +/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC12_OUT_INV_SEL_S 9 +/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC12_OUT_SEL 0x000001FF +#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) +#define GPIO_FUNC12_OUT_SEL_V 0x1FF +#define GPIO_FUNC12_OUT_SEL_S 0 + +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0564) +/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC13_OEN_INV_SEL_S 11 +/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC13_OEN_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_V 0x1 +#define GPIO_FUNC13_OEN_SEL_S 10 +/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC13_OUT_INV_SEL_S 9 +/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC13_OUT_SEL 0x000001FF +#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) +#define GPIO_FUNC13_OUT_SEL_V 0x1FF +#define GPIO_FUNC13_OUT_SEL_S 0 + +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0568) +/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC14_OEN_INV_SEL_S 11 +/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC14_OEN_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_V 0x1 +#define GPIO_FUNC14_OEN_SEL_S 10 +/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC14_OUT_INV_SEL_S 9 +/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC14_OUT_SEL 0x000001FF +#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) +#define GPIO_FUNC14_OUT_SEL_V 0x1FF +#define GPIO_FUNC14_OUT_SEL_S 0 + +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x056c) +/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC15_OEN_INV_SEL_S 11 +/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC15_OEN_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_V 0x1 +#define GPIO_FUNC15_OEN_SEL_S 10 +/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC15_OUT_INV_SEL_S 9 +/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC15_OUT_SEL 0x000001FF +#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) +#define GPIO_FUNC15_OUT_SEL_V 0x1FF +#define GPIO_FUNC15_OUT_SEL_S 0 + +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0570) +/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC16_OEN_INV_SEL_S 11 +/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC16_OEN_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_V 0x1 +#define GPIO_FUNC16_OEN_SEL_S 10 +/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC16_OUT_INV_SEL_S 9 +/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC16_OUT_SEL 0x000001FF +#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) +#define GPIO_FUNC16_OUT_SEL_V 0x1FF +#define GPIO_FUNC16_OUT_SEL_S 0 + +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0574) +/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC17_OEN_INV_SEL_S 11 +/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC17_OEN_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_V 0x1 +#define GPIO_FUNC17_OEN_SEL_S 10 +/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC17_OUT_INV_SEL_S 9 +/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC17_OUT_SEL 0x000001FF +#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) +#define GPIO_FUNC17_OUT_SEL_V 0x1FF +#define GPIO_FUNC17_OUT_SEL_S 0 + +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0578) +/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC18_OEN_INV_SEL_S 11 +/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC18_OEN_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_V 0x1 +#define GPIO_FUNC18_OEN_SEL_S 10 +/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC18_OUT_INV_SEL_S 9 +/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC18_OUT_SEL 0x000001FF +#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) +#define GPIO_FUNC18_OUT_SEL_V 0x1FF +#define GPIO_FUNC18_OUT_SEL_S 0 + +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x057c) +/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC19_OEN_INV_SEL_S 11 +/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC19_OEN_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_V 0x1 +#define GPIO_FUNC19_OEN_SEL_S 10 +/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC19_OUT_INV_SEL_S 9 +/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC19_OUT_SEL 0x000001FF +#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) +#define GPIO_FUNC19_OUT_SEL_V 0x1FF +#define GPIO_FUNC19_OUT_SEL_S 0 + +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0580) +/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC20_OEN_INV_SEL_S 11 +/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC20_OEN_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_V 0x1 +#define GPIO_FUNC20_OEN_SEL_S 10 +/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC20_OUT_INV_SEL_S 9 +/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC20_OUT_SEL 0x000001FF +#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) +#define GPIO_FUNC20_OUT_SEL_V 0x1FF +#define GPIO_FUNC20_OUT_SEL_S 0 + +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0584) +/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC21_OEN_INV_SEL_S 11 +/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC21_OEN_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_V 0x1 +#define GPIO_FUNC21_OEN_SEL_S 10 +/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC21_OUT_INV_SEL_S 9 +/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC21_OUT_SEL 0x000001FF +#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) +#define GPIO_FUNC21_OUT_SEL_V 0x1FF +#define GPIO_FUNC21_OUT_SEL_S 0 + +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0588) +/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC22_OEN_INV_SEL_S 11 +/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC22_OEN_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_V 0x1 +#define GPIO_FUNC22_OEN_SEL_S 10 +/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC22_OUT_INV_SEL_S 9 +/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC22_OUT_SEL 0x000001FF +#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) +#define GPIO_FUNC22_OUT_SEL_V 0x1FF +#define GPIO_FUNC22_OUT_SEL_S 0 + +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x058c) +/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC23_OEN_INV_SEL_S 11 +/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC23_OEN_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_V 0x1 +#define GPIO_FUNC23_OEN_SEL_S 10 +/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC23_OUT_INV_SEL_S 9 +/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC23_OUT_SEL 0x000001FF +#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) +#define GPIO_FUNC23_OUT_SEL_V 0x1FF +#define GPIO_FUNC23_OUT_SEL_S 0 + +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0590) +/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC24_OEN_INV_SEL_S 11 +/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC24_OEN_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_V 0x1 +#define GPIO_FUNC24_OEN_SEL_S 10 +/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC24_OUT_INV_SEL_S 9 +/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC24_OUT_SEL 0x000001FF +#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) +#define GPIO_FUNC24_OUT_SEL_V 0x1FF +#define GPIO_FUNC24_OUT_SEL_S 0 + +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0594) +/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC25_OEN_INV_SEL_S 11 +/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC25_OEN_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_V 0x1 +#define GPIO_FUNC25_OEN_SEL_S 10 +/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC25_OUT_INV_SEL_S 9 +/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC25_OUT_SEL 0x000001FF +#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) +#define GPIO_FUNC25_OUT_SEL_V 0x1FF +#define GPIO_FUNC25_OUT_SEL_S 0 + +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0598) +/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC26_OEN_INV_SEL_S 11 +/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC26_OEN_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_V 0x1 +#define GPIO_FUNC26_OEN_SEL_S 10 +/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC26_OUT_INV_SEL_S 9 +/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC26_OUT_SEL 0x000001FF +#define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) +#define GPIO_FUNC26_OUT_SEL_V 0x1FF +#define GPIO_FUNC26_OUT_SEL_S 0 + +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x059c) +/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC27_OEN_INV_SEL_S 11 +/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC27_OEN_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_V 0x1 +#define GPIO_FUNC27_OEN_SEL_S 10 +/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC27_OUT_INV_SEL_S 9 +/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC27_OUT_SEL 0x000001FF +#define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) +#define GPIO_FUNC27_OUT_SEL_V 0x1FF +#define GPIO_FUNC27_OUT_SEL_S 0 + +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a0) +/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC28_OEN_INV_SEL_S 11 +/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC28_OEN_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_V 0x1 +#define GPIO_FUNC28_OEN_SEL_S 10 +/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC28_OUT_INV_SEL_S 9 +/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC28_OUT_SEL 0x000001FF +#define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) +#define GPIO_FUNC28_OUT_SEL_V 0x1FF +#define GPIO_FUNC28_OUT_SEL_S 0 + +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a4) +/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC29_OEN_INV_SEL_S 11 +/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC29_OEN_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_V 0x1 +#define GPIO_FUNC29_OEN_SEL_S 10 +/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC29_OUT_INV_SEL_S 9 +/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC29_OUT_SEL 0x000001FF +#define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) +#define GPIO_FUNC29_OUT_SEL_V 0x1FF +#define GPIO_FUNC29_OUT_SEL_S 0 + +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a8) +/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC30_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC30_OEN_INV_SEL_S 11 +/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC30_OEN_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_V 0x1 +#define GPIO_FUNC30_OEN_SEL_S 10 +/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC30_OUT_INV_SEL_S 9 +/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC30_OUT_SEL 0x000001FF +#define GPIO_FUNC30_OUT_SEL_M ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S)) +#define GPIO_FUNC30_OUT_SEL_V 0x1FF +#define GPIO_FUNC30_OUT_SEL_S 0 + +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05ac) +/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC31_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC31_OEN_INV_SEL_S 11 +/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC31_OEN_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_V 0x1 +#define GPIO_FUNC31_OEN_SEL_S 10 +/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC31_OUT_INV_SEL_S 9 +/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC31_OUT_SEL 0x000001FF +#define GPIO_FUNC31_OUT_SEL_M ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S)) +#define GPIO_FUNC31_OUT_SEL_V 0x1FF +#define GPIO_FUNC31_OUT_SEL_S 0 + +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b0) +/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC32_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC32_OEN_INV_SEL_S 11 +/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC32_OEN_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_V 0x1 +#define GPIO_FUNC32_OEN_SEL_S 10 +/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC32_OUT_INV_SEL_S 9 +/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC32_OUT_SEL 0x000001FF +#define GPIO_FUNC32_OUT_SEL_M ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S)) +#define GPIO_FUNC32_OUT_SEL_V 0x1FF +#define GPIO_FUNC32_OUT_SEL_S 0 + +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b4) +/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC33_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC33_OEN_INV_SEL_S 11 +/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC33_OEN_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_V 0x1 +#define GPIO_FUNC33_OEN_SEL_S 10 +/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC33_OUT_INV_SEL_S 9 +/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC33_OUT_SEL 0x000001FF +#define GPIO_FUNC33_OUT_SEL_M ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S)) +#define GPIO_FUNC33_OUT_SEL_V 0x1FF +#define GPIO_FUNC33_OUT_SEL_S 0 + +#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b8) +/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC34_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC34_OEN_INV_SEL_S 11 +/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC34_OEN_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_V 0x1 +#define GPIO_FUNC34_OEN_SEL_S 10 +/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC34_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC34_OUT_INV_SEL_S 9 +/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC34_OUT_SEL 0x000001FF +#define GPIO_FUNC34_OUT_SEL_M ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S)) +#define GPIO_FUNC34_OUT_SEL_V 0x1FF +#define GPIO_FUNC34_OUT_SEL_S 0 + +#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05bc) +/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC35_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC35_OEN_INV_SEL_S 11 +/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC35_OEN_SEL (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_V 0x1 +#define GPIO_FUNC35_OEN_SEL_S 10 +/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC35_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC35_OUT_INV_SEL_S 9 +/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC35_OUT_SEL 0x000001FF +#define GPIO_FUNC35_OUT_SEL_M ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S)) +#define GPIO_FUNC35_OUT_SEL_V 0x1FF +#define GPIO_FUNC35_OUT_SEL_S 0 + +#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c0) +/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC36_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC36_OEN_INV_SEL_S 11 +/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC36_OEN_SEL (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_V 0x1 +#define GPIO_FUNC36_OEN_SEL_S 10 +/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC36_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC36_OUT_INV_SEL_S 9 +/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC36_OUT_SEL 0x000001FF +#define GPIO_FUNC36_OUT_SEL_M ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S)) +#define GPIO_FUNC36_OUT_SEL_V 0x1FF +#define GPIO_FUNC36_OUT_SEL_S 0 + +#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c4) +/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC37_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC37_OEN_INV_SEL_S 11 +/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC37_OEN_SEL (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_V 0x1 +#define GPIO_FUNC37_OEN_SEL_S 10 +/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC37_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC37_OUT_INV_SEL_S 9 +/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC37_OUT_SEL 0x000001FF +#define GPIO_FUNC37_OUT_SEL_M ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S)) +#define GPIO_FUNC37_OUT_SEL_V 0x1FF +#define GPIO_FUNC37_OUT_SEL_S 0 + +#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c8) +/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC38_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC38_OEN_INV_SEL_S 11 +/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC38_OEN_SEL (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_V 0x1 +#define GPIO_FUNC38_OEN_SEL_S 10 +/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC38_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC38_OUT_INV_SEL_S 9 +/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC38_OUT_SEL 0x000001FF +#define GPIO_FUNC38_OUT_SEL_M ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S)) +#define GPIO_FUNC38_OUT_SEL_V 0x1FF +#define GPIO_FUNC38_OUT_SEL_S 0 + +#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05cc) +/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC39_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC39_OEN_INV_SEL_S 11 +/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC39_OEN_SEL (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_V 0x1 +#define GPIO_FUNC39_OEN_SEL_S 10 +/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC39_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC39_OUT_INV_SEL_S 9 +/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC39_OUT_SEL 0x000001FF +#define GPIO_FUNC39_OUT_SEL_M ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S)) +#define GPIO_FUNC39_OUT_SEL_V 0x1FF +#define GPIO_FUNC39_OUT_SEL_S 0 + + + + +#endif /*_SOC_GPIO_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/gpio_sd_reg.h b/tools/sdk/include/soc/include/soc/gpio_sd_reg.h new file mode 100644 index 00000000000..be39fcf2c20 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/gpio_sd_reg.h @@ -0,0 +1,160 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SD_REG_H_ +#define _SOC_GPIO_SD_REG_H_ + +#include "soc.h" +#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000) +/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD0_PRESCALE 0x000000FF +#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S)) +#define GPIO_SD0_PRESCALE_V 0xFF +#define GPIO_SD0_PRESCALE_S 8 +/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD0_IN 0x000000FF +#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S)) +#define GPIO_SD0_IN_V 0xFF +#define GPIO_SD0_IN_S 0 + +#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004) +/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD1_PRESCALE 0x000000FF +#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S)) +#define GPIO_SD1_PRESCALE_V 0xFF +#define GPIO_SD1_PRESCALE_S 8 +/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD1_IN 0x000000FF +#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S)) +#define GPIO_SD1_IN_V 0xFF +#define GPIO_SD1_IN_S 0 + +#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008) +/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD2_PRESCALE 0x000000FF +#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S)) +#define GPIO_SD2_PRESCALE_V 0xFF +#define GPIO_SD2_PRESCALE_S 8 +/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD2_IN 0x000000FF +#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S)) +#define GPIO_SD2_IN_V 0xFF +#define GPIO_SD2_IN_S 0 + +#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c) +/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD3_PRESCALE 0x000000FF +#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S)) +#define GPIO_SD3_PRESCALE_V 0xFF +#define GPIO_SD3_PRESCALE_S 8 +/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD3_IN 0x000000FF +#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S)) +#define GPIO_SD3_IN_V 0xFF +#define GPIO_SD3_IN_S 0 + +#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010) +/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD4_PRESCALE 0x000000FF +#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S)) +#define GPIO_SD4_PRESCALE_V 0xFF +#define GPIO_SD4_PRESCALE_S 8 +/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD4_IN 0x000000FF +#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S)) +#define GPIO_SD4_IN_V 0xFF +#define GPIO_SD4_IN_S 0 + +#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014) +/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD5_PRESCALE 0x000000FF +#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S)) +#define GPIO_SD5_PRESCALE_V 0xFF +#define GPIO_SD5_PRESCALE_S 8 +/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD5_IN 0x000000FF +#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S)) +#define GPIO_SD5_IN_V 0xFF +#define GPIO_SD5_IN_S 0 + +#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018) +/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD6_PRESCALE 0x000000FF +#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S)) +#define GPIO_SD6_PRESCALE_V 0xFF +#define GPIO_SD6_PRESCALE_S 8 +/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD6_IN 0x000000FF +#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S)) +#define GPIO_SD6_IN_V 0xFF +#define GPIO_SD6_IN_S 0 + +#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c) +/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD7_PRESCALE 0x000000FF +#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S)) +#define GPIO_SD7_PRESCALE_V 0xFF +#define GPIO_SD7_PRESCALE_S 8 +/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD7_IN 0x000000FF +#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S)) +#define GPIO_SD7_IN_V 0xFF +#define GPIO_SD7_IN_S 0 + +#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020) +/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SD_CLK_EN (BIT(31)) +#define GPIO_SD_CLK_EN_M (BIT(31)) +#define GPIO_SD_CLK_EN_V 0x1 +#define GPIO_SD_CLK_EN_S 31 + +#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024) +/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SPI_SWAP (BIT(31)) +#define GPIO_SPI_SWAP_M (BIT(31)) +#define GPIO_SPI_SWAP_V 0x1 +#define GPIO_SPI_SWAP_S 31 + +#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028) +/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1506190 ; */ +/*description: */ +#define GPIO_SD_DATE 0x0FFFFFFF +#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S)) +#define GPIO_SD_DATE_V 0xFFFFFFF +#define GPIO_SD_DATE_S 0 +#define SIGMADELTA_GPIO_SD_DATE_VERSION 0x1506190 + + + + +#endif /*_SOC_GPIO_SD_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/gpio_sd_struct.h b/tools/sdk/include/soc/include/soc/gpio_sd_struct.h new file mode 100644 index 00000000000..4b82be052ca --- /dev/null +++ b/tools/sdk/include/soc/include/soc/gpio_sd_struct.h @@ -0,0 +1,60 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SD_STRUCT_H_ +#define _SOC_GPIO_SD_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t duty: 8; + uint32_t prescale: 8; + uint32_t reserved16: 16; + }; + uint32_t val; + } channel[8]; + union { + struct { + uint32_t reserved0: 31; + uint32_t clk_en: 1; + }; + uint32_t val; + } cg; + union { + struct { + uint32_t reserved0: 31; + uint32_t spi_swap: 1; + }; + uint32_t val; + } misc; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } version; +} gpio_sd_dev_t; +extern gpio_sd_dev_t SIGMADELTA; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_GPIO_SD_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/gpio_sig_map.h b/tools/sdk/include/soc/include/soc/gpio_sig_map.h new file mode 100644 index 00000000000..1d3dc5b04ce --- /dev/null +++ b/tools/sdk/include/soc/include/soc/gpio_sig_map.h @@ -0,0 +1,422 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SIG_MAP_H_ +#define _SOC_GPIO_SIG_MAP_H_ + +#define SPICLK_IN_IDX 0 +#define SPICLK_OUT_IDX 0 +#define SPIQ_IN_IDX 1 +#define SPIQ_OUT_IDX 1 +#define SPID_IN_IDX 2 +#define SPID_OUT_IDX 2 +#define SPIHD_IN_IDX 3 +#define SPIHD_OUT_IDX 3 +#define SPIWP_IN_IDX 4 +#define SPIWP_OUT_IDX 4 +#define SPICS0_IN_IDX 5 +#define SPICS0_OUT_IDX 5 +#define SPICS1_IN_IDX 6 +#define SPICS1_OUT_IDX 6 +#define SPICS2_IN_IDX 7 +#define SPICS2_OUT_IDX 7 +#define HSPICLK_IN_IDX 8 +#define HSPICLK_OUT_IDX 8 +#define HSPIQ_IN_IDX 9 +#define HSPIQ_OUT_IDX 9 +#define HSPID_IN_IDX 10 +#define HSPID_OUT_IDX 10 +#define HSPICS0_IN_IDX 11 +#define HSPICS0_OUT_IDX 11 +#define HSPIHD_IN_IDX 12 +#define HSPIHD_OUT_IDX 12 +#define HSPIWP_IN_IDX 13 +#define HSPIWP_OUT_IDX 13 +#define U0RXD_IN_IDX 14 +#define U0TXD_OUT_IDX 14 +#define U0CTS_IN_IDX 15 +#define U0RTS_OUT_IDX 15 +#define U0DSR_IN_IDX 16 +#define U0DTR_OUT_IDX 16 +#define U1RXD_IN_IDX 17 +#define U1TXD_OUT_IDX 17 +#define U1CTS_IN_IDX 18 +#define U1RTS_OUT_IDX 18 +#define I2CM_SCL_O_IDX 19 +#define I2CM_SDA_I_IDX 20 +#define I2CM_SDA_O_IDX 20 +#define EXT_I2C_SCL_O_IDX 21 +#define EXT_I2C_SDA_O_IDX 22 +#define EXT_I2C_SDA_I_IDX 22 +#define I2S0O_BCK_IN_IDX 23 +#define I2S0O_BCK_OUT_IDX 23 +#define I2S1O_BCK_IN_IDX 24 +#define I2S1O_BCK_OUT_IDX 24 +#define I2S0O_WS_IN_IDX 25 +#define I2S0O_WS_OUT_IDX 25 +#define I2S1O_WS_IN_IDX 26 +#define I2S1O_WS_OUT_IDX 26 +#define I2S0I_BCK_IN_IDX 27 +#define I2S0I_BCK_OUT_IDX 27 +#define I2S0I_WS_IN_IDX 28 +#define I2S0I_WS_OUT_IDX 28 +#define I2CEXT0_SCL_IN_IDX 29 +#define I2CEXT0_SCL_OUT_IDX 29 +#define I2CEXT0_SDA_IN_IDX 30 +#define I2CEXT0_SDA_OUT_IDX 30 +#define PWM0_SYNC0_IN_IDX 31 +#define SDIO_TOHOST_INT_OUT_IDX 31 +#define PWM0_SYNC1_IN_IDX 32 +#define PWM0_OUT0A_IDX 32 +#define PWM0_SYNC2_IN_IDX 33 +#define PWM0_OUT0B_IDX 33 +#define PWM0_F0_IN_IDX 34 +#define PWM0_OUT1A_IDX 34 +#define PWM0_F1_IN_IDX 35 +#define PWM0_OUT1B_IDX 35 +#define PWM0_F2_IN_IDX 36 +#define PWM0_OUT2A_IDX 36 +#define GPIO_BT_ACTIVE_IDX 37 +#define PWM0_OUT2B_IDX 37 +#define GPIO_BT_PRIORITY_IDX 38 +#define PCNT_SIG_CH0_IN0_IDX 39 +#define PCNT_SIG_CH1_IN0_IDX 40 +#define GPIO_WLAN_ACTIVE_IDX 40 +#define PCNT_CTRL_CH0_IN0_IDX 41 +#define BB_DIAG0_IDX 41 +#define PCNT_CTRL_CH1_IN0_IDX 42 +#define BB_DIAG1_IDX 42 +#define PCNT_SIG_CH0_IN1_IDX 43 +#define BB_DIAG2_IDX 43 +#define PCNT_SIG_CH1_IN1_IDX 44 +#define BB_DIAG3_IDX 44 +#define PCNT_CTRL_CH0_IN1_IDX 45 +#define BB_DIAG4_IDX 45 +#define PCNT_CTRL_CH1_IN1_IDX 46 +#define BB_DIAG5_IDX 46 +#define PCNT_SIG_CH0_IN2_IDX 47 +#define BB_DIAG6_IDX 47 +#define PCNT_SIG_CH1_IN2_IDX 48 +#define BB_DIAG7_IDX 48 +#define PCNT_CTRL_CH0_IN2_IDX 49 +#define BB_DIAG8_IDX 49 +#define PCNT_CTRL_CH1_IN2_IDX 50 +#define BB_DIAG9_IDX 50 +#define PCNT_SIG_CH0_IN3_IDX 51 +#define BB_DIAG10_IDX 51 +#define PCNT_SIG_CH1_IN3_IDX 52 +#define BB_DIAG11_IDX 52 +#define PCNT_CTRL_CH0_IN3_IDX 53 +#define BB_DIAG12_IDX 53 +#define PCNT_CTRL_CH1_IN3_IDX 54 +#define BB_DIAG13_IDX 54 +#define PCNT_SIG_CH0_IN4_IDX 55 +#define BB_DIAG14_IDX 55 +#define PCNT_SIG_CH1_IN4_IDX 56 +#define BB_DIAG15_IDX 56 +#define PCNT_CTRL_CH0_IN4_IDX 57 +#define BB_DIAG16_IDX 57 +#define PCNT_CTRL_CH1_IN4_IDX 58 +#define BB_DIAG17_IDX 58 +#define BB_DIAG18_IDX 59 +#define BB_DIAG19_IDX 60 +#define HSPICS1_IN_IDX 61 +#define HSPICS1_OUT_IDX 61 +#define HSPICS2_IN_IDX 62 +#define HSPICS2_OUT_IDX 62 +#define VSPICLK_IN_IDX 63 +#define VSPICLK_OUT_IDX 63 +#define VSPIQ_IN_IDX 64 +#define VSPIQ_OUT_IDX 64 +#define VSPID_IN_IDX 65 +#define VSPID_OUT_IDX 65 +#define VSPIHD_IN_IDX 66 +#define VSPIHD_OUT_IDX 66 +#define VSPIWP_IN_IDX 67 +#define VSPIWP_OUT_IDX 67 +#define VSPICS0_IN_IDX 68 +#define VSPICS0_OUT_IDX 68 +#define VSPICS1_IN_IDX 69 +#define VSPICS1_OUT_IDX 69 +#define VSPICS2_IN_IDX 70 +#define VSPICS2_OUT_IDX 70 +#define PCNT_SIG_CH0_IN5_IDX 71 +#define LEDC_HS_SIG_OUT0_IDX 71 +#define PCNT_SIG_CH1_IN5_IDX 72 +#define LEDC_HS_SIG_OUT1_IDX 72 +#define PCNT_CTRL_CH0_IN5_IDX 73 +#define LEDC_HS_SIG_OUT2_IDX 73 +#define PCNT_CTRL_CH1_IN5_IDX 74 +#define LEDC_HS_SIG_OUT3_IDX 74 +#define PCNT_SIG_CH0_IN6_IDX 75 +#define LEDC_HS_SIG_OUT4_IDX 75 +#define PCNT_SIG_CH1_IN6_IDX 76 +#define LEDC_HS_SIG_OUT5_IDX 76 +#define PCNT_CTRL_CH0_IN6_IDX 77 +#define LEDC_HS_SIG_OUT6_IDX 77 +#define PCNT_CTRL_CH1_IN6_IDX 78 +#define LEDC_HS_SIG_OUT7_IDX 78 +#define PCNT_SIG_CH0_IN7_IDX 79 +#define LEDC_LS_SIG_OUT0_IDX 79 +#define PCNT_SIG_CH1_IN7_IDX 80 +#define LEDC_LS_SIG_OUT1_IDX 80 +#define PCNT_CTRL_CH0_IN7_IDX 81 +#define LEDC_LS_SIG_OUT2_IDX 81 +#define PCNT_CTRL_CH1_IN7_IDX 82 +#define LEDC_LS_SIG_OUT3_IDX 82 +#define RMT_SIG_IN0_IDX 83 +#define LEDC_LS_SIG_OUT4_IDX 83 +#define RMT_SIG_IN1_IDX 84 +#define LEDC_LS_SIG_OUT5_IDX 84 +#define RMT_SIG_IN2_IDX 85 +#define LEDC_LS_SIG_OUT6_IDX 85 +#define RMT_SIG_IN3_IDX 86 +#define LEDC_LS_SIG_OUT7_IDX 86 +#define RMT_SIG_IN4_IDX 87 +#define RMT_SIG_OUT0_IDX 87 +#define RMT_SIG_IN5_IDX 88 +#define RMT_SIG_OUT1_IDX 88 +#define RMT_SIG_IN6_IDX 89 +#define RMT_SIG_OUT2_IDX 89 +#define RMT_SIG_IN7_IDX 90 +#define RMT_SIG_OUT3_IDX 90 +#define RMT_SIG_OUT4_IDX 91 +#define RMT_SIG_OUT5_IDX 92 +#define EXT_ADC_START_IDX 93 +#define RMT_SIG_OUT6_IDX 93 +#define CAN_RX_IDX 94 +#define RMT_SIG_OUT7_IDX 94 +#define I2CEXT1_SCL_IN_IDX 95 +#define I2CEXT1_SCL_OUT_IDX 95 +#define I2CEXT1_SDA_IN_IDX 96 +#define I2CEXT1_SDA_OUT_IDX 96 +#define HOST_CARD_DETECT_N_1_IDX 97 +#define HOST_CCMD_OD_PULLUP_EN_N_IDX 97 +#define HOST_CARD_DETECT_N_2_IDX 98 +#define HOST_RST_N_1_IDX 98 +#define HOST_CARD_WRITE_PRT_1_IDX 99 +#define HOST_RST_N_2_IDX 99 +#define HOST_CARD_WRITE_PRT_2_IDX 100 +#define GPIO_SD0_OUT_IDX 100 +#define HOST_CARD_INT_N_1_IDX 101 +#define GPIO_SD1_OUT_IDX 101 +#define HOST_CARD_INT_N_2_IDX 102 +#define GPIO_SD2_OUT_IDX 102 +#define PWM1_SYNC0_IN_IDX 103 +#define GPIO_SD3_OUT_IDX 103 +#define PWM1_SYNC1_IN_IDX 104 +#define GPIO_SD4_OUT_IDX 104 +#define PWM1_SYNC2_IN_IDX 105 +#define GPIO_SD5_OUT_IDX 105 +#define PWM1_F0_IN_IDX 106 +#define GPIO_SD6_OUT_IDX 106 +#define PWM1_F1_IN_IDX 107 +#define GPIO_SD7_OUT_IDX 107 +#define PWM1_F2_IN_IDX 108 +#define PWM1_OUT0A_IDX 108 +#define PWM0_CAP0_IN_IDX 109 +#define PWM1_OUT0B_IDX 109 +#define PWM0_CAP1_IN_IDX 110 +#define PWM1_OUT1A_IDX 110 +#define PWM0_CAP2_IN_IDX 111 +#define PWM1_OUT1B_IDX 111 +#define PWM1_CAP0_IN_IDX 112 +#define PWM1_OUT2A_IDX 112 +#define PWM1_CAP1_IN_IDX 113 +#define PWM1_OUT2B_IDX 113 +#define PWM1_CAP2_IN_IDX 114 +#define PWM2_OUT1H_IDX 114 +#define PWM2_FLTA_IDX 115 +#define PWM2_OUT1L_IDX 115 +#define PWM2_FLTB_IDX 116 +#define PWM2_OUT2H_IDX 116 +#define PWM2_CAP1_IN_IDX 117 +#define PWM2_OUT2L_IDX 117 +#define PWM2_CAP2_IN_IDX 118 +#define PWM2_OUT3H_IDX 118 +#define PWM2_CAP3_IN_IDX 119 +#define PWM2_OUT3L_IDX 119 +#define PWM3_FLTA_IDX 120 +#define PWM2_OUT4H_IDX 120 +#define PWM3_FLTB_IDX 121 +#define PWM2_OUT4L_IDX 121 +#define PWM3_CAP1_IN_IDX 122 +#define PWM3_CAP2_IN_IDX 123 +#define CAN_TX_IDX 123 +#define PWM3_CAP3_IN_IDX 124 +#define CAN_BUS_OFF_ON_IDX 124 +#define CAN_CLKOUT_IDX 125 +#define SPID4_IN_IDX 128 +#define SPID4_OUT_IDX 128 +#define SPID5_IN_IDX 129 +#define SPID5_OUT_IDX 129 +#define SPID6_IN_IDX 130 +#define SPID6_OUT_IDX 130 +#define SPID7_IN_IDX 131 +#define SPID7_OUT_IDX 131 +#define HSPID4_IN_IDX 132 +#define HSPID4_OUT_IDX 132 +#define HSPID5_IN_IDX 133 +#define HSPID5_OUT_IDX 133 +#define HSPID6_IN_IDX 134 +#define HSPID6_OUT_IDX 134 +#define HSPID7_IN_IDX 135 +#define HSPID7_OUT_IDX 135 +#define VSPID4_IN_IDX 136 +#define VSPID4_OUT_IDX 136 +#define VSPID5_IN_IDX 137 +#define VSPID5_OUT_IDX 137 +#define VSPID6_IN_IDX 138 +#define VSPID6_OUT_IDX 138 +#define VSPID7_IN_IDX 139 +#define VSPID7_OUT_IDX 139 +#define I2S0I_DATA_IN0_IDX 140 +#define I2S0O_DATA_OUT0_IDX 140 +#define I2S0I_DATA_IN1_IDX 141 +#define I2S0O_DATA_OUT1_IDX 141 +#define I2S0I_DATA_IN2_IDX 142 +#define I2S0O_DATA_OUT2_IDX 142 +#define I2S0I_DATA_IN3_IDX 143 +#define I2S0O_DATA_OUT3_IDX 143 +#define I2S0I_DATA_IN4_IDX 144 +#define I2S0O_DATA_OUT4_IDX 144 +#define I2S0I_DATA_IN5_IDX 145 +#define I2S0O_DATA_OUT5_IDX 145 +#define I2S0I_DATA_IN6_IDX 146 +#define I2S0O_DATA_OUT6_IDX 146 +#define I2S0I_DATA_IN7_IDX 147 +#define I2S0O_DATA_OUT7_IDX 147 +#define I2S0I_DATA_IN8_IDX 148 +#define I2S0O_DATA_OUT8_IDX 148 +#define I2S0I_DATA_IN9_IDX 149 +#define I2S0O_DATA_OUT9_IDX 149 +#define I2S0I_DATA_IN10_IDX 150 +#define I2S0O_DATA_OUT10_IDX 150 +#define I2S0I_DATA_IN11_IDX 151 +#define I2S0O_DATA_OUT11_IDX 151 +#define I2S0I_DATA_IN12_IDX 152 +#define I2S0O_DATA_OUT12_IDX 152 +#define I2S0I_DATA_IN13_IDX 153 +#define I2S0O_DATA_OUT13_IDX 153 +#define I2S0I_DATA_IN14_IDX 154 +#define I2S0O_DATA_OUT14_IDX 154 +#define I2S0I_DATA_IN15_IDX 155 +#define I2S0O_DATA_OUT15_IDX 155 +#define I2S0O_DATA_OUT16_IDX 156 +#define I2S0O_DATA_OUT17_IDX 157 +#define I2S0O_DATA_OUT18_IDX 158 +#define I2S0O_DATA_OUT19_IDX 159 +#define I2S0O_DATA_OUT20_IDX 160 +#define I2S0O_DATA_OUT21_IDX 161 +#define I2S0O_DATA_OUT22_IDX 162 +#define I2S0O_DATA_OUT23_IDX 163 +#define I2S1I_BCK_IN_IDX 164 +#define I2S1I_BCK_OUT_IDX 164 +#define I2S1I_WS_IN_IDX 165 +#define I2S1I_WS_OUT_IDX 165 +#define I2S1I_DATA_IN0_IDX 166 +#define I2S1O_DATA_OUT0_IDX 166 +#define I2S1I_DATA_IN1_IDX 167 +#define I2S1O_DATA_OUT1_IDX 167 +#define I2S1I_DATA_IN2_IDX 168 +#define I2S1O_DATA_OUT2_IDX 168 +#define I2S1I_DATA_IN3_IDX 169 +#define I2S1O_DATA_OUT3_IDX 169 +#define I2S1I_DATA_IN4_IDX 170 +#define I2S1O_DATA_OUT4_IDX 170 +#define I2S1I_DATA_IN5_IDX 171 +#define I2S1O_DATA_OUT5_IDX 171 +#define I2S1I_DATA_IN6_IDX 172 +#define I2S1O_DATA_OUT6_IDX 172 +#define I2S1I_DATA_IN7_IDX 173 +#define I2S1O_DATA_OUT7_IDX 173 +#define I2S1I_DATA_IN8_IDX 174 +#define I2S1O_DATA_OUT8_IDX 174 +#define I2S1I_DATA_IN9_IDX 175 +#define I2S1O_DATA_OUT9_IDX 175 +#define I2S1I_DATA_IN10_IDX 176 +#define I2S1O_DATA_OUT10_IDX 176 +#define I2S1I_DATA_IN11_IDX 177 +#define I2S1O_DATA_OUT11_IDX 177 +#define I2S1I_DATA_IN12_IDX 178 +#define I2S1O_DATA_OUT12_IDX 178 +#define I2S1I_DATA_IN13_IDX 179 +#define I2S1O_DATA_OUT13_IDX 179 +#define I2S1I_DATA_IN14_IDX 180 +#define I2S1O_DATA_OUT14_IDX 180 +#define I2S1I_DATA_IN15_IDX 181 +#define I2S1O_DATA_OUT15_IDX 181 +#define I2S1O_DATA_OUT16_IDX 182 +#define I2S1O_DATA_OUT17_IDX 183 +#define I2S1O_DATA_OUT18_IDX 184 +#define I2S1O_DATA_OUT19_IDX 185 +#define I2S1O_DATA_OUT20_IDX 186 +#define I2S1O_DATA_OUT21_IDX 187 +#define I2S1O_DATA_OUT22_IDX 188 +#define I2S1O_DATA_OUT23_IDX 189 +#define I2S0I_H_SYNC_IDX 190 +#define PWM3_OUT1H_IDX 190 +#define I2S0I_V_SYNC_IDX 191 +#define PWM3_OUT1L_IDX 191 +#define I2S0I_H_ENABLE_IDX 192 +#define PWM3_OUT2H_IDX 192 +#define I2S1I_H_SYNC_IDX 193 +#define PWM3_OUT2L_IDX 193 +#define I2S1I_V_SYNC_IDX 194 +#define PWM3_OUT3H_IDX 194 +#define I2S1I_H_ENABLE_IDX 195 +#define PWM3_OUT3L_IDX 195 +#define PWM3_OUT4H_IDX 196 +#define PWM3_OUT4L_IDX 197 +#define U2RXD_IN_IDX 198 +#define U2TXD_OUT_IDX 198 +#define U2CTS_IN_IDX 199 +#define U2RTS_OUT_IDX 199 +#define EMAC_MDC_I_IDX 200 +#define EMAC_MDC_O_IDX 200 +#define EMAC_MDI_I_IDX 201 +#define EMAC_MDO_O_IDX 201 +#define EMAC_CRS_I_IDX 202 +#define EMAC_CRS_O_IDX 202 +#define EMAC_COL_I_IDX 203 +#define EMAC_COL_O_IDX 203 +#define PCMFSYNC_IN_IDX 204 +#define BT_AUDIO0_IRQ_IDX 204 +#define PCMCLK_IN_IDX 205 +#define BT_AUDIO1_IRQ_IDX 205 +#define PCMDIN_IDX 206 +#define BT_AUDIO2_IRQ_IDX 206 +#define BLE_AUDIO0_IRQ_IDX 207 +#define BLE_AUDIO1_IRQ_IDX 208 +#define BLE_AUDIO2_IRQ_IDX 209 +#define PCMFSYNC_OUT_IDX 210 +#define PCMCLK_OUT_IDX 211 +#define PCMDOUT_IDX 212 +#define BLE_AUDIO_SYNC0_P_IDX 213 +#define BLE_AUDIO_SYNC1_P_IDX 214 +#define BLE_AUDIO_SYNC2_P_IDX 215 +#define ANT_SEL0_IDX 216 +#define ANT_SEL1_IDX 217 +#define ANT_SEL2_IDX 218 +#define ANT_SEL3_IDX 219 +#define ANT_SEL4_IDX 220 +#define ANT_SEL5_IDX 221 +#define ANT_SEL6_IDX 222 +#define ANT_SEL7_IDX 223 +#define SIG_IN_FUNC224_IDX 224 +#define SIG_IN_FUNC225_IDX 225 +#define SIG_IN_FUNC226_IDX 226 +#define SIG_IN_FUNC227_IDX 227 +#define SIG_IN_FUNC228_IDX 228 +#define SIG_GPIO_OUT_IDX 256 +#endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/tools/sdk/include/soc/include/soc/gpio_struct.h b/tools/sdk/include/soc/include/soc/gpio_struct.h new file mode 100644 index 00000000000..15038fed3ff --- /dev/null +++ b/tools/sdk/include/soc/include/soc/gpio_struct.h @@ -0,0 +1,216 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_STRUCT_H_ +#define _SOC_GPIO_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + uint32_t bt_select; /*NA*/ + uint32_t out; /*GPIO0~31 output value*/ + uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/ + uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/ + union { + struct { + uint32_t data: 8; /*GPIO32~39 output value*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } out1; + union { + struct { + uint32_t data: 8; /*GPIO32~39 output value write 1 to set*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } out1_w1ts; + union { + struct { + uint32_t data: 8; /*GPIO32~39 output value write 1 to clear*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } out1_w1tc; + union { + struct { + uint32_t sel: 8; /*SDIO PADS on/off control from outside*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } sdio_select; + uint32_t enable; /*GPIO0~31 output enable*/ + uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/ + uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/ + union { + struct { + uint32_t data: 8; /*GPIO32~39 output enable*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } enable1; + union { + struct { + uint32_t data: 8; /*GPIO32~39 output enable write 1 to set*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } enable1_w1ts; + union { + struct { + uint32_t data: 8; /*GPIO32~39 output enable write 1 to clear*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } enable1_w1tc; + union { + struct { + uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]} . Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3} . vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */ + uint32_t reserved16:16; + }; + uint32_t val; + } strap; + uint32_t in; /*GPIO0~31 input value*/ + union { + struct { + uint32_t data: 8; /*GPIO32~39 input value*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } in1; + uint32_t status; /*GPIO0~31 interrupt status*/ + uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/ + uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/ + union { + struct { + uint32_t intr_st: 8; /*GPIO32~39 interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } status1; + union { + struct { + uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to set*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } status1_w1ts; + union { + struct { + uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to clear*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } status1_w1tc; + uint32_t reserved_5c; + uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/ + uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/ + uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/ + uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/ + uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/ + union { + struct { + uint32_t intr: 8; /*GPIO32~39 APP CPU interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } acpu_int1; + union { + struct { + uint32_t intr: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } acpu_nmi_int1; + union { + struct { + uint32_t intr: 8; /*GPIO32~39 PRO CPU interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } pcpu_int1; + union { + struct { + uint32_t intr: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } pcpu_nmi_int1; + union { + struct { + uint32_t intr: 8; /*SDIO's extent GPIO32~39 interrupt*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } cpusdio_int1; + union { + struct { + uint32_t reserved0: 2; + uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + uint32_t reserved3: 4; + uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + uint32_t config: 2; /*NA*/ + uint32_t int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ + uint32_t reserved18: 14; + }; + uint32_t val; + } pin[40]; + union { + struct { + uint32_t rtc_max: 10; + uint32_t reserved10: 21; + uint32_t start: 1; + }; + uint32_t val; + } cali_conf; + union { + struct { + uint32_t value_sync2: 20; + uint32_t reserved20: 10; + uint32_t rdy_real: 1; + uint32_t rdy_sync2: 1; + }; + uint32_t val; + } cali_data; + union { + struct { + uint32_t func_sel: 6; /*select one of the 256 inputs*/ + uint32_t sig_in_inv: 1; /*revert the value of the input if you want to revert please set the value to 1*/ + uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/ + uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/ + }; + uint32_t val; + } func_in_sel_cfg[256]; + union { + struct { + uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/ + uint32_t inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/ + uint32_t oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/ + uint32_t oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/ + uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/ + }; + uint32_t val; + } func_out_sel_cfg[40]; +} gpio_dev_t; +extern gpio_dev_t GPIO; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_GPIO_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/hinf_reg.h b/tools/sdk/include/soc/include/soc/hinf_reg.h new file mode 100644 index 00000000000..aad357864eb --- /dev/null +++ b/tools/sdk/include/soc/include/soc/hinf_reg.h @@ -0,0 +1,248 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_HINF_REG_H_ +#define _SOC_HINF_REG_H_ + + +#include "soc.h" +#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) +/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */ +/*description: */ +#define HINF_DEVICE_ID_FN1 0x0000FFFF +#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V)<<(HINF_DEVICE_ID_FN1_S)) +#define HINF_DEVICE_ID_FN1_V 0xFFFF +#define HINF_DEVICE_ID_FN1_S 16 +/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */ +/*description: */ +#define HINF_USER_ID_FN1 0x0000FFFF +#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V)<<(HINF_USER_ID_FN1_S)) +#define HINF_USER_ID_FN1_V 0xFFFF +#define HINF_USER_ID_FN1_S 0 + +#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4) +/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */ +/*description: */ +#define HINF_SDIO20_CONF1 0x00000007 +#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V)<<(HINF_SDIO20_CONF1_S)) +#define HINF_SDIO20_CONF1_V 0x7 +#define HINF_SDIO20_CONF1_S 29 +/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define HINF_FUNC2_EPS (BIT(28)) +#define HINF_FUNC2_EPS_M (BIT(28)) +#define HINF_FUNC2_EPS_V 0x1 +#define HINF_FUNC2_EPS_S 28 +/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */ +/*description: */ +#define HINF_SDIO_VER 0x00000FFF +#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V)<<(HINF_SDIO_VER_S)) +#define HINF_SDIO_VER_V 0xFFF +#define HINF_SDIO_VER_S 16 +/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */ +/*description: */ +#define HINF_SDIO20_CONF0 0x0000000F +#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V)<<(HINF_SDIO20_CONF0_S)) +#define HINF_SDIO20_CONF0_V 0xF +#define HINF_SDIO20_CONF0_S 12 +/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HINF_IOENABLE1 (BIT(11)) +#define HINF_IOENABLE1_M (BIT(11)) +#define HINF_IOENABLE1_V 0x1 +#define HINF_IOENABLE1_S 11 +/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HINF_EMP (BIT(10)) +#define HINF_EMP_M (BIT(10)) +#define HINF_EMP_V 0x1 +#define HINF_EMP_S 10 +/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HINF_FUNC1_EPS (BIT(9)) +#define HINF_FUNC1_EPS_M (BIT(9)) +#define HINF_FUNC1_EPS_V 0x1 +#define HINF_FUNC1_EPS_S 9 +/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HINF_CD_DISABLE (BIT(8)) +#define HINF_CD_DISABLE_M (BIT(8)) +#define HINF_CD_DISABLE_V 0x1 +#define HINF_CD_DISABLE_S 8 +/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HINF_IOENABLE2 (BIT(7)) +#define HINF_IOENABLE2_M (BIT(7)) +#define HINF_IOENABLE2_V 0x1 +#define HINF_IOENABLE2_S 7 +/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HINF_SDIO_INT_MASK (BIT(6)) +#define HINF_SDIO_INT_MASK_M (BIT(6)) +#define HINF_SDIO_INT_MASK_V 0x1 +#define HINF_SDIO_INT_MASK_S 6 +/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HINF_SDIO_IOREADY2 (BIT(5)) +#define HINF_SDIO_IOREADY2_M (BIT(5)) +#define HINF_SDIO_IOREADY2_V 0x1 +#define HINF_SDIO_IOREADY2_S 5 +/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define HINF_SDIO_CD_ENABLE (BIT(4)) +#define HINF_SDIO_CD_ENABLE_M (BIT(4)) +#define HINF_SDIO_CD_ENABLE_V 0x1 +#define HINF_SDIO_CD_ENABLE_S 4 +/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HINF_HIGHSPEED_MODE (BIT(3)) +#define HINF_HIGHSPEED_MODE_M (BIT(3)) +#define HINF_HIGHSPEED_MODE_V 0x1 +#define HINF_HIGHSPEED_MODE_S 3 +/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HINF_HIGHSPEED_ENABLE (BIT(2)) +#define HINF_HIGHSPEED_ENABLE_M (BIT(2)) +#define HINF_HIGHSPEED_ENABLE_V 0x1 +#define HINF_HIGHSPEED_ENABLE_S 2 +/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HINF_SDIO_IOREADY1 (BIT(1)) +#define HINF_SDIO_IOREADY1_M (BIT(1)) +#define HINF_SDIO_IOREADY1_V 0x1 +#define HINF_SDIO_IOREADY1_S 1 +/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define HINF_SDIO_ENABLE (BIT(0)) +#define HINF_SDIO_ENABLE_M (BIT(0)) +#define HINF_SDIO_ENABLE_V 0x1 +#define HINF_SDIO_ENABLE_S 0 + +#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C) +/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */ +/*description: */ +#define HINF_SDIO_IOREADY0 (BIT(17)) +#define HINF_SDIO_IOREADY0_M (BIT(17)) +#define HINF_SDIO_IOREADY0_V 0x1 +#define HINF_SDIO_IOREADY0_S 17 +/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HINF_SDIO_RST (BIT(16)) +#define HINF_SDIO_RST_M (BIT(16)) +#define HINF_SDIO_RST_V 0x1 +#define HINF_SDIO_RST_S 16 +/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: */ +#define HINF_CHIP_STATE 0x000000FF +#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V)<<(HINF_CHIP_STATE_S)) +#define HINF_CHIP_STATE_V 0xFF +#define HINF_CHIP_STATE_S 8 +/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define HINF_PIN_STATE 0x000000FF +#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V)<<(HINF_PIN_STATE_S)) +#define HINF_PIN_STATE_V 0xFF +#define HINF_PIN_STATE_S 0 + +#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20) +/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W0 0xFFFFFFFF +#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V)<<(HINF_CIS_CONF_W0_S)) +#define HINF_CIS_CONF_W0_V 0xFFFFFFFF +#define HINF_CIS_CONF_W0_S 0 + +#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24) +/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W1 0xFFFFFFFF +#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V)<<(HINF_CIS_CONF_W1_S)) +#define HINF_CIS_CONF_W1_V 0xFFFFFFFF +#define HINF_CIS_CONF_W1_S 0 + +#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28) +/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W2 0xFFFFFFFF +#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V)<<(HINF_CIS_CONF_W2_S)) +#define HINF_CIS_CONF_W2_V 0xFFFFFFFF +#define HINF_CIS_CONF_W2_S 0 + +#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C) +/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W3 0xFFFFFFFF +#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V)<<(HINF_CIS_CONF_W3_S)) +#define HINF_CIS_CONF_W3_V 0xFFFFFFFF +#define HINF_CIS_CONF_W3_S 0 + +#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30) +/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W4 0xFFFFFFFF +#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V)<<(HINF_CIS_CONF_W4_S)) +#define HINF_CIS_CONF_W4_V 0xFFFFFFFF +#define HINF_CIS_CONF_W4_S 0 + +#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34) +/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W5 0xFFFFFFFF +#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V)<<(HINF_CIS_CONF_W5_S)) +#define HINF_CIS_CONF_W5_V 0xFFFFFFFF +#define HINF_CIS_CONF_W5_S 0 + +#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38) +/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W6 0xFFFFFFFF +#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V)<<(HINF_CIS_CONF_W6_S)) +#define HINF_CIS_CONF_W6_V 0xFFFFFFFF +#define HINF_CIS_CONF_W6_S 0 + +#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C) +/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W7 0xFFFFFFFF +#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V)<<(HINF_CIS_CONF_W7_S)) +#define HINF_CIS_CONF_W7_V 0xFFFFFFFF +#define HINF_CIS_CONF_W7_S 0 + +#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40) +/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */ +/*description: */ +#define HINF_DEVICE_ID_FN2 0x0000FFFF +#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V)<<(HINF_DEVICE_ID_FN2_S)) +#define HINF_DEVICE_ID_FN2_V 0xFFFF +#define HINF_DEVICE_ID_FN2_S 16 +/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */ +/*description: */ +#define HINF_USER_ID_FN2 0x0000FFFF +#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V)<<(HINF_USER_ID_FN2_S)) +#define HINF_USER_ID_FN2_V 0xFFFF +#define HINF_USER_ID_FN2_S 0 + +#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC) +/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */ +/*description: */ +#define HINF_SDIO_DATE 0xFFFFFFFF +#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V)<<(HINF_SDIO_DATE_S)) +#define HINF_SDIO_DATE_V 0xFFFFFFFF +#define HINF_SDIO_DATE_S 0 + + + + +#endif /*_SOC_HINF_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/hinf_struct.h b/tools/sdk/include/soc/include/soc/hinf_struct.h new file mode 100644 index 00000000000..8e46f5397d0 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/hinf_struct.h @@ -0,0 +1,136 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_HINF_STRUCT_H_ +#define _SOC_HINF_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t user_id_fn1: 16; + uint32_t device_id_fn1:16; + }; + uint32_t val; + } cfg_data0; + union { + struct { + uint32_t sdio_enable: 1; + uint32_t sdio_ioready1: 1; + uint32_t highspeed_enable: 1; + uint32_t highspeed_mode: 1; + uint32_t sdio_cd_enable: 1; + uint32_t sdio_ioready2: 1; + uint32_t sdio_int_mask: 1; + uint32_t ioenable2: 1; + uint32_t cd_disable: 1; + uint32_t func1_eps: 1; + uint32_t emp: 1; + uint32_t ioenable1: 1; + uint32_t sdio20_conf0: 4; + uint32_t sdio_ver: 12; + uint32_t func2_eps: 1; + uint32_t sdio20_conf1: 3; + }; + uint32_t val; + } cfg_data1; + uint32_t reserved_8; + uint32_t reserved_c; + uint32_t reserved_10; + uint32_t reserved_14; + uint32_t reserved_18; + union { + struct { + uint32_t pin_state: 8; + uint32_t chip_state: 8; + uint32_t sdio_rst: 1; + uint32_t sdio_ioready0: 1; + uint32_t reserved18: 14; + }; + uint32_t val; + } cfg_data7; + uint32_t cis_conf0; /**/ + uint32_t cis_conf1; /**/ + uint32_t cis_conf2; /**/ + uint32_t cis_conf3; /**/ + uint32_t cis_conf4; /**/ + uint32_t cis_conf5; /**/ + uint32_t cis_conf6; /**/ + uint32_t cis_conf7; /**/ + union { + struct { + uint32_t user_id_fn2: 16; + uint32_t device_id_fn2:16; + }; + uint32_t val; + } cfg_data16; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ +} hinf_dev_t; +extern hinf_dev_t HINF; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_HINF_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/host_reg.h b/tools/sdk/include/soc/include/soc/host_reg.h new file mode 100644 index 00000000000..ef556e21cdc --- /dev/null +++ b/tools/sdk/include/soc/include/soc/host_reg.h @@ -0,0 +1,3144 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_HOST_REG_H_ +#define _SOC_HOST_REG_H_ + + +#include "soc.h" +#define HOST_SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10) +/* HOST_SLC_FUNC2_INT : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC_FUNC2_INT (BIT(24)) +#define HOST_SLC_FUNC2_INT_M (BIT(24)) +#define HOST_SLC_FUNC2_INT_V 0x1 +#define HOST_SLC_FUNC2_INT_S 24 + +#define HOST_SLCHOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14) +/* HOST_SLC_FUNC2_INT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC_FUNC2_INT_EN (BIT(0)) +#define HOST_SLC_FUNC2_INT_EN_M (BIT(0)) +#define HOST_SLC_FUNC2_INT_EN_V 0x1 +#define HOST_SLC_FUNC2_INT_EN_S 0 + +#define HOST_SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20) +/* HOST_SLC_FUNC1_MDSTAT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define HOST_SLC_FUNC1_MDSTAT (BIT(0)) +#define HOST_SLC_FUNC1_MDSTAT_M (BIT(0)) +#define HOST_SLC_FUNC1_MDSTAT_V 0x1 +#define HOST_SLC_FUNC1_MDSTAT_S 0 + +#define HOST_SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34) +/* HOST_GPIO_SDIO_INT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT0 0xFFFFFFFF +#define HOST_GPIO_SDIO_INT0_M ((HOST_GPIO_SDIO_INT0_V)<<(HOST_GPIO_SDIO_INT0_S)) +#define HOST_GPIO_SDIO_INT0_V 0xFFFFFFFF +#define HOST_GPIO_SDIO_INT0_S 0 + +#define HOST_SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38) +/* HOST_GPIO_SDIO_INT1 : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT1 0x000000FF +#define HOST_GPIO_SDIO_INT1_M ((HOST_GPIO_SDIO_INT1_V)<<(HOST_GPIO_SDIO_INT1_S)) +#define HOST_GPIO_SDIO_INT1_V 0xFF +#define HOST_GPIO_SDIO_INT1_S 0 + +#define HOST_SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3C) +/* HOST_GPIO_SDIO_IN0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_IN0 0xFFFFFFFF +#define HOST_GPIO_SDIO_IN0_M ((HOST_GPIO_SDIO_IN0_V)<<(HOST_GPIO_SDIO_IN0_S)) +#define HOST_GPIO_SDIO_IN0_V 0xFFFFFFFF +#define HOST_GPIO_SDIO_IN0_S 0 + +#define HOST_SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40) +/* HOST_GPIO_SDIO_IN1 : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_IN1 0x000000FF +#define HOST_GPIO_SDIO_IN1_M ((HOST_GPIO_SDIO_IN1_V)<<(HOST_GPIO_SDIO_IN1_S)) +#define HOST_GPIO_SDIO_IN1_V 0xFF +#define HOST_GPIO_SDIO_IN1_S 0 + +#define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44) +/* HOST_SLC0_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_EOF 0x0000000F +#define HOST_SLC0_RX_PF_EOF_M ((HOST_SLC0_RX_PF_EOF_V)<<(HOST_SLC0_RX_PF_EOF_S)) +#define HOST_SLC0_RX_PF_EOF_V 0xF +#define HOST_SLC0_RX_PF_EOF_S 28 +/* HOST_HOSTSLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_TOKEN1 0x00000FFF +#define HOST_HOSTSLC0_TOKEN1_M ((HOST_HOSTSLC0_TOKEN1_V)<<(HOST_HOSTSLC0_TOKEN1_S)) +#define HOST_HOSTSLC0_TOKEN1_V 0xFFF +#define HOST_HOSTSLC0_TOKEN1_S 16 +/* HOST_SLC0_RX_PF_VALID : RO ;bitpos:[12] ;default: 4'h0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID (BIT(12)) +#define HOST_SLC0_RX_PF_VALID_M (BIT(12)) +#define HOST_SLC0_RX_PF_VALID_V 0x1 +#define HOST_SLC0_RX_PF_VALID_S 12 +/* HOST_SLC0_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0 0x00000FFF +#define HOST_SLC0_TOKEN0_M ((HOST_SLC0_TOKEN0_V)<<(HOST_SLC0_TOKEN0_S)) +#define HOST_SLC0_TOKEN0_V 0xFFF +#define HOST_SLC0_TOKEN0_S 0 + +#define HOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48) +/* HOST_SLC0_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define HOST_SLC0_PF_DATA 0xFFFFFFFF +#define HOST_SLC0_PF_DATA_M ((HOST_SLC0_PF_DATA_V)<<(HOST_SLC0_PF_DATA_S)) +#define HOST_SLC0_PF_DATA_V 0xFFFFFFFF +#define HOST_SLC0_PF_DATA_S 0 + +#define HOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4C) +/* HOST_SLC1_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define HOST_SLC1_PF_DATA 0xFFFFFFFF +#define HOST_SLC1_PF_DATA_M ((HOST_SLC1_PF_DATA_V)<<(HOST_SLC1_PF_DATA_S)) +#define HOST_SLC1_PF_DATA_V 0xFFFFFFFF +#define HOST_SLC1_PF_DATA_S 0 + +#define HOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50) +/* HOST_GPIO_SDIO_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_RAW (BIT(25)) +#define HOST_GPIO_SDIO_INT_RAW_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_RAW_V 0x1 +#define HOST_GPIO_SDIO_INT_RAW_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23 +/* HOST_SLC0_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_RAW (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_RAW_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_RAW_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_RAW_S 22 +/* HOST_SLC0_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_RAW (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_RAW_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_RAW_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_RAW_S 21 +/* HOST_SLC0_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_RAW (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_RAW_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_RAW_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_RAW_S 20 +/* HOST_SLC0_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_RAW (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_RAW_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_RAW_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_RAW_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_RAW_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_RAW_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_RAW_S 18 +/* HOST_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_RAW (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_RAW_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_RAW_V 0x1 +#define HOST_SLC0_TX_OVF_INT_RAW_S 17 +/* HOST_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_RAW (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_RAW_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_RAW_V 0x1 +#define HOST_SLC0_RX_UDF_INT_RAW_S 16 +/* HOST_SLC0HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_RAW (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_RAW_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_RAW_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_RAW_S 15 +/* HOST_SLC0HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_RAW (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_RAW_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_RAW_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_RAW_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_RAW_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_RAW_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_RAW_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_RAW_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_RAW_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_RAW_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_RAW_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_RAW_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_RAW_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_RAW_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_RAW_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_RAW_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_RAW_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_RAW_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_RAW_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_RAW_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_RAW_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_RAW_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_RAW_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_RAW_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_RAW_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_RAW_S 0 + +#define HOST_SLC1HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x54) +/* HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V 0x1 +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S 25 +/* HOST_SLC1_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_RAW_M (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_RAW_V 0x1 +#define HOST_SLC1_HOST_RD_RETRY_INT_RAW_S 24 +/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V 0x1 +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S 23 +/* HOST_SLC1_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT3_INT_RAW (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_RAW_M (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_RAW_V 0x1 +#define HOST_SLC1_EXT_BIT3_INT_RAW_S 22 +/* HOST_SLC1_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT2_INT_RAW (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_RAW_M (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_RAW_V 0x1 +#define HOST_SLC1_EXT_BIT2_INT_RAW_S 21 +/* HOST_SLC1_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT1_INT_RAW (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_RAW_M (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_RAW_V 0x1 +#define HOST_SLC1_EXT_BIT1_INT_RAW_S 20 +/* HOST_SLC1_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT0_INT_RAW (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_RAW_M (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_RAW_V 0x1 +#define HOST_SLC1_EXT_BIT0_INT_RAW_S 19 +/* HOST_SLC1_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_PF_VALID_INT_RAW (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_RAW_M (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_RAW_V 0x1 +#define HOST_SLC1_RX_PF_VALID_INT_RAW_S 18 +/* HOST_SLC1_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TX_OVF_INT_RAW (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_RAW_M (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_RAW_V 0x1 +#define HOST_SLC1_TX_OVF_INT_RAW_S 17 +/* HOST_SLC1_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_UDF_INT_RAW (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_RAW_M (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_RAW_V 0x1 +#define HOST_SLC1_RX_UDF_INT_RAW_S 16 +/* HOST_SLC1HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_TX_START_INT_RAW (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_RAW_M (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_RAW_V 0x1 +#define HOST_SLC1HOST_TX_START_INT_RAW_S 15 +/* HOST_SLC1HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_START_INT_RAW (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_RAW_M (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_RAW_V 0x1 +#define HOST_SLC1HOST_RX_START_INT_RAW_S 14 +/* HOST_SLC1HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_EOF_INT_RAW (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_RAW_M (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_RAW_V 0x1 +#define HOST_SLC1HOST_RX_EOF_INT_RAW_S 13 +/* HOST_SLC1HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_SOF_INT_RAW (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_RAW_M (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_RAW_V 0x1 +#define HOST_SLC1HOST_RX_SOF_INT_RAW_S 12 +/* HOST_SLC1_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_RAW_M (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_RAW_V 0x1 +#define HOST_SLC1_TOKEN1_0TO1_INT_RAW_S 11 +/* HOST_SLC1_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_RAW_M (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_RAW_V 0x1 +#define HOST_SLC1_TOKEN0_0TO1_INT_RAW_S 10 +/* HOST_SLC1_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_RAW_M (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_RAW_V 0x1 +#define HOST_SLC1_TOKEN1_1TO0_INT_RAW_S 9 +/* HOST_SLC1_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_RAW_M (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_RAW_V 0x1 +#define HOST_SLC1_TOKEN0_1TO0_INT_RAW_S 8 +/* HOST_SLC1_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT7_INT_RAW (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_RAW_M (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_RAW_V 0x1 +#define HOST_SLC1_TOHOST_BIT7_INT_RAW_S 7 +/* HOST_SLC1_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT6_INT_RAW (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_RAW_M (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_RAW_V 0x1 +#define HOST_SLC1_TOHOST_BIT6_INT_RAW_S 6 +/* HOST_SLC1_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT5_INT_RAW (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_RAW_M (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_RAW_V 0x1 +#define HOST_SLC1_TOHOST_BIT5_INT_RAW_S 5 +/* HOST_SLC1_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT4_INT_RAW (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_RAW_M (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_RAW_V 0x1 +#define HOST_SLC1_TOHOST_BIT4_INT_RAW_S 4 +/* HOST_SLC1_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT3_INT_RAW (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_RAW_M (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_RAW_V 0x1 +#define HOST_SLC1_TOHOST_BIT3_INT_RAW_S 3 +/* HOST_SLC1_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT2_INT_RAW (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_RAW_M (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_RAW_V 0x1 +#define HOST_SLC1_TOHOST_BIT2_INT_RAW_S 2 +/* HOST_SLC1_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT1_INT_RAW (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_RAW_M (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_RAW_V 0x1 +#define HOST_SLC1_TOHOST_BIT1_INT_RAW_S 1 +/* HOST_SLC1_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT0_INT_RAW (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_RAW_M (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_RAW_V 0x1 +#define HOST_SLC1_TOHOST_BIT0_INT_RAW_S 0 + +#define HOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58) +/* HOST_GPIO_SDIO_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_ST (BIT(25)) +#define HOST_GPIO_SDIO_INT_ST_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_ST_V 0x1 +#define HOST_GPIO_SDIO_INT_ST_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ST_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_ST_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ST_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_ST_S 23 +/* HOST_SLC0_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_ST (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ST_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ST_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_ST_S 22 +/* HOST_SLC0_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_ST (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ST_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ST_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_ST_S 21 +/* HOST_SLC0_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_ST (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ST_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ST_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_ST_S 20 +/* HOST_SLC0_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_ST (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ST_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ST_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_ST_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_ST (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ST_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ST_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_ST_S 18 +/* HOST_SLC0_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_ST (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ST_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ST_V 0x1 +#define HOST_SLC0_TX_OVF_INT_ST_S 17 +/* HOST_SLC0_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_ST (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ST_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ST_V 0x1 +#define HOST_SLC0_RX_UDF_INT_ST_S 16 +/* HOST_SLC0HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_ST (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ST_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ST_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_ST_S 15 +/* HOST_SLC0HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_ST (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ST_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ST_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_ST_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_ST (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ST_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ST_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_ST_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_ST (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ST_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ST_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_ST_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ST_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_ST_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ST_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_ST_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_ST_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_ST_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ST_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_ST_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ST_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_ST_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ST_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_ST_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ST_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_ST_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ST_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_ST_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ST_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_ST_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ST_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_ST_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ST_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_ST_S 0 + +#define HOST_SLC1HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x5C) +/* HOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V 0x1 +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S 25 +/* HOST_SLC1_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_HOST_RD_RETRY_INT_ST (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_ST_M (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_ST_V 0x1 +#define HOST_SLC1_HOST_RD_RETRY_INT_ST_S 24 +/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V 0x1 +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S 23 +/* HOST_SLC1_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT3_INT_ST (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_ST_M (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_ST_V 0x1 +#define HOST_SLC1_EXT_BIT3_INT_ST_S 22 +/* HOST_SLC1_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT2_INT_ST (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_ST_M (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_ST_V 0x1 +#define HOST_SLC1_EXT_BIT2_INT_ST_S 21 +/* HOST_SLC1_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT1_INT_ST (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_ST_M (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_ST_V 0x1 +#define HOST_SLC1_EXT_BIT1_INT_ST_S 20 +/* HOST_SLC1_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT0_INT_ST (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_ST_M (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_ST_V 0x1 +#define HOST_SLC1_EXT_BIT0_INT_ST_S 19 +/* HOST_SLC1_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_PF_VALID_INT_ST (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_ST_M (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_ST_V 0x1 +#define HOST_SLC1_RX_PF_VALID_INT_ST_S 18 +/* HOST_SLC1_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TX_OVF_INT_ST (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_ST_M (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_ST_V 0x1 +#define HOST_SLC1_TX_OVF_INT_ST_S 17 +/* HOST_SLC1_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_UDF_INT_ST (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_ST_M (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_ST_V 0x1 +#define HOST_SLC1_RX_UDF_INT_ST_S 16 +/* HOST_SLC1HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_TX_START_INT_ST (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_ST_M (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_ST_V 0x1 +#define HOST_SLC1HOST_TX_START_INT_ST_S 15 +/* HOST_SLC1HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_START_INT_ST (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_ST_M (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_ST_V 0x1 +#define HOST_SLC1HOST_RX_START_INT_ST_S 14 +/* HOST_SLC1HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_EOF_INT_ST (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_ST_M (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_ST_V 0x1 +#define HOST_SLC1HOST_RX_EOF_INT_ST_S 13 +/* HOST_SLC1HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_SOF_INT_ST (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_ST_M (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_ST_V 0x1 +#define HOST_SLC1HOST_RX_SOF_INT_ST_S 12 +/* HOST_SLC1_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_0TO1_INT_ST (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_ST_M (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_ST_V 0x1 +#define HOST_SLC1_TOKEN1_0TO1_INT_ST_S 11 +/* HOST_SLC1_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_0TO1_INT_ST (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_ST_M (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_ST_V 0x1 +#define HOST_SLC1_TOKEN0_0TO1_INT_ST_S 10 +/* HOST_SLC1_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_1TO0_INT_ST (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_ST_M (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_ST_V 0x1 +#define HOST_SLC1_TOKEN1_1TO0_INT_ST_S 9 +/* HOST_SLC1_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_1TO0_INT_ST (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_ST_M (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_ST_V 0x1 +#define HOST_SLC1_TOKEN0_1TO0_INT_ST_S 8 +/* HOST_SLC1_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT7_INT_ST (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_ST_M (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_ST_V 0x1 +#define HOST_SLC1_TOHOST_BIT7_INT_ST_S 7 +/* HOST_SLC1_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT6_INT_ST (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_ST_M (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_ST_V 0x1 +#define HOST_SLC1_TOHOST_BIT6_INT_ST_S 6 +/* HOST_SLC1_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT5_INT_ST (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_ST_M (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_ST_V 0x1 +#define HOST_SLC1_TOHOST_BIT5_INT_ST_S 5 +/* HOST_SLC1_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT4_INT_ST (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_ST_M (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_ST_V 0x1 +#define HOST_SLC1_TOHOST_BIT4_INT_ST_S 4 +/* HOST_SLC1_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT3_INT_ST (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_ST_M (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_ST_V 0x1 +#define HOST_SLC1_TOHOST_BIT3_INT_ST_S 3 +/* HOST_SLC1_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT2_INT_ST (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_ST_M (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_ST_V 0x1 +#define HOST_SLC1_TOHOST_BIT2_INT_ST_S 2 +/* HOST_SLC1_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT1_INT_ST (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_ST_M (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_ST_V 0x1 +#define HOST_SLC1_TOHOST_BIT1_INT_ST_S 1 +/* HOST_SLC1_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT0_INT_ST (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_ST_M (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_ST_V 0x1 +#define HOST_SLC1_TOHOST_BIT0_INT_ST_S 0 + +#define HOST_SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60) +/* HOST_HOSTSLC0_LEN_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN_CHECK 0x00000FFF +#define HOST_HOSTSLC0_LEN_CHECK_M ((HOST_HOSTSLC0_LEN_CHECK_V)<<(HOST_HOSTSLC0_LEN_CHECK_S)) +#define HOST_HOSTSLC0_LEN_CHECK_V 0xFFF +#define HOST_HOSTSLC0_LEN_CHECK_S 20 +/* HOST_HOSTSLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN 0x000FFFFF +#define HOST_HOSTSLC0_LEN_M ((HOST_HOSTSLC0_LEN_V)<<(HOST_HOSTSLC0_LEN_S)) +#define HOST_HOSTSLC0_LEN_V 0xFFFFF +#define HOST_HOSTSLC0_LEN_S 0 + +#define HOST_SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64) +/* HOST_SLCHOST_STATE3 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE3 0x000000FF +#define HOST_SLCHOST_STATE3_M ((HOST_SLCHOST_STATE3_V)<<(HOST_SLCHOST_STATE3_S)) +#define HOST_SLCHOST_STATE3_V 0xFF +#define HOST_SLCHOST_STATE3_S 24 +/* HOST_SLCHOST_STATE2 : RO ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE2 0x000000FF +#define HOST_SLCHOST_STATE2_M ((HOST_SLCHOST_STATE2_V)<<(HOST_SLCHOST_STATE2_S)) +#define HOST_SLCHOST_STATE2_V 0xFF +#define HOST_SLCHOST_STATE2_S 16 +/* HOST_SLCHOST_STATE1 : RO ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE1 0x000000FF +#define HOST_SLCHOST_STATE1_M ((HOST_SLCHOST_STATE1_V)<<(HOST_SLCHOST_STATE1_S)) +#define HOST_SLCHOST_STATE1_V 0xFF +#define HOST_SLCHOST_STATE1_S 8 +/* HOST_SLCHOST_STATE0 : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE0 0x000000FF +#define HOST_SLCHOST_STATE0_M ((HOST_SLCHOST_STATE0_V)<<(HOST_SLCHOST_STATE0_S)) +#define HOST_SLCHOST_STATE0_V 0xFF +#define HOST_SLCHOST_STATE0_S 0 + +#define HOST_SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68) +/* HOST_SLCHOST_STATE7 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE7 0x000000FF +#define HOST_SLCHOST_STATE7_M ((HOST_SLCHOST_STATE7_V)<<(HOST_SLCHOST_STATE7_S)) +#define HOST_SLCHOST_STATE7_V 0xFF +#define HOST_SLCHOST_STATE7_S 24 +/* HOST_SLCHOST_STATE6 : RO ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE6 0x000000FF +#define HOST_SLCHOST_STATE6_M ((HOST_SLCHOST_STATE6_V)<<(HOST_SLCHOST_STATE6_S)) +#define HOST_SLCHOST_STATE6_V 0xFF +#define HOST_SLCHOST_STATE6_S 16 +/* HOST_SLCHOST_STATE5 : RO ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE5 0x000000FF +#define HOST_SLCHOST_STATE5_M ((HOST_SLCHOST_STATE5_V)<<(HOST_SLCHOST_STATE5_S)) +#define HOST_SLCHOST_STATE5_V 0xFF +#define HOST_SLCHOST_STATE5_S 8 +/* HOST_SLCHOST_STATE4 : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE4 0x000000FF +#define HOST_SLCHOST_STATE4_M ((HOST_SLCHOST_STATE4_V)<<(HOST_SLCHOST_STATE4_S)) +#define HOST_SLCHOST_STATE4_V 0xFF +#define HOST_SLCHOST_STATE4_S 0 + +#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0)) + +#define HOST_SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6C) +/* HOST_SLCHOST_CONF3 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF3 0x000000FF +#define HOST_SLCHOST_CONF3_M ((HOST_SLCHOST_CONF3_V)<<(HOST_SLCHOST_CONF3_S)) +#define HOST_SLCHOST_CONF3_V 0xFF +#define HOST_SLCHOST_CONF3_S 24 +/* HOST_SLCHOST_CONF2 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF2 0x000000FF +#define HOST_SLCHOST_CONF2_M ((HOST_SLCHOST_CONF2_V)<<(HOST_SLCHOST_CONF2_S)) +#define HOST_SLCHOST_CONF2_V 0xFF +#define HOST_SLCHOST_CONF2_S 16 +/* HOST_SLCHOST_CONF1 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF1 0x000000FF +#define HOST_SLCHOST_CONF1_M ((HOST_SLCHOST_CONF1_V)<<(HOST_SLCHOST_CONF1_S)) +#define HOST_SLCHOST_CONF1_V 0xFF +#define HOST_SLCHOST_CONF1_S 8 +/* HOST_SLCHOST_CONF0 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF0 0x000000FF +#define HOST_SLCHOST_CONF0_M ((HOST_SLCHOST_CONF0_V)<<(HOST_SLCHOST_CONF0_S)) +#define HOST_SLCHOST_CONF0_V 0xFF +#define HOST_SLCHOST_CONF0_S 0 + +#define HOST_SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70) +/* HOST_SLCHOST_CONF7 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF7 0x000000FF +#define HOST_SLCHOST_CONF7_M ((HOST_SLCHOST_CONF7_V)<<(HOST_SLCHOST_CONF7_S)) +#define HOST_SLCHOST_CONF7_V 0xFF +#define HOST_SLCHOST_CONF7_S 24 +/* HOST_SLCHOST_CONF6 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF6 0x000000FF +#define HOST_SLCHOST_CONF6_M ((HOST_SLCHOST_CONF6_V)<<(HOST_SLCHOST_CONF6_S)) +#define HOST_SLCHOST_CONF6_V 0xFF +#define HOST_SLCHOST_CONF6_S 16 +/* HOST_SLCHOST_CONF5 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF5 0x000000FF +#define HOST_SLCHOST_CONF5_M ((HOST_SLCHOST_CONF5_V)<<(HOST_SLCHOST_CONF5_S)) +#define HOST_SLCHOST_CONF5_V 0xFF +#define HOST_SLCHOST_CONF5_S 8 +/* HOST_SLCHOST_CONF4 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF4 0x000000FF +#define HOST_SLCHOST_CONF4_M ((HOST_SLCHOST_CONF4_V)<<(HOST_SLCHOST_CONF4_S)) +#define HOST_SLCHOST_CONF4_V 0xFF +#define HOST_SLCHOST_CONF4_S 0 + +#define HOST_SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74) +/* HOST_SLCHOST_CONF11 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF11 0x000000FF +#define HOST_SLCHOST_CONF11_M ((HOST_SLCHOST_CONF11_V)<<(HOST_SLCHOST_CONF11_S)) +#define HOST_SLCHOST_CONF11_V 0xFF +#define HOST_SLCHOST_CONF11_S 24 +/* HOST_SLCHOST_CONF10 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF10 0x000000FF +#define HOST_SLCHOST_CONF10_M ((HOST_SLCHOST_CONF10_V)<<(HOST_SLCHOST_CONF10_S)) +#define HOST_SLCHOST_CONF10_V 0xFF +#define HOST_SLCHOST_CONF10_S 16 +/* HOST_SLCHOST_CONF9 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF9 0x000000FF +#define HOST_SLCHOST_CONF9_M ((HOST_SLCHOST_CONF9_V)<<(HOST_SLCHOST_CONF9_S)) +#define HOST_SLCHOST_CONF9_V 0xFF +#define HOST_SLCHOST_CONF9_S 8 +/* HOST_SLCHOST_CONF8 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF8 0x000000FF +#define HOST_SLCHOST_CONF8_M ((HOST_SLCHOST_CONF8_V)<<(HOST_SLCHOST_CONF8_S)) +#define HOST_SLCHOST_CONF8_V 0xFF +#define HOST_SLCHOST_CONF8_S 0 + +#define HOST_SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78) +/* HOST_SLCHOST_CONF15 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF15 0x000000FF +#define HOST_SLCHOST_CONF15_M ((HOST_SLCHOST_CONF15_V)<<(HOST_SLCHOST_CONF15_S)) +#define HOST_SLCHOST_CONF15_V 0xFF +#define HOST_SLCHOST_CONF15_S 24 +/* HOST_SLCHOST_CONF14 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF14 0x000000FF +#define HOST_SLCHOST_CONF14_M ((HOST_SLCHOST_CONF14_V)<<(HOST_SLCHOST_CONF14_S)) +#define HOST_SLCHOST_CONF14_V 0xFF +#define HOST_SLCHOST_CONF14_S 16 +/* HOST_SLCHOST_CONF13 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF13 0x000000FF +#define HOST_SLCHOST_CONF13_M ((HOST_SLCHOST_CONF13_V)<<(HOST_SLCHOST_CONF13_S)) +#define HOST_SLCHOST_CONF13_V 0xFF +#define HOST_SLCHOST_CONF13_S 8 +/* HOST_SLCHOST_CONF12 : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF12 0x000000FF +#define HOST_SLCHOST_CONF12_M ((HOST_SLCHOST_CONF12_V)<<(HOST_SLCHOST_CONF12_S)) +#define HOST_SLCHOST_CONF12_V 0xFF +#define HOST_SLCHOST_CONF12_S 0 + +#define HOST_SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7C) +/* HOST_SLCHOST_CONF19 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: Interrupt to target CPU*/ +#define HOST_SLCHOST_CONF19 0x000000FF +#define HOST_SLCHOST_CONF19_M ((HOST_SLCHOST_CONF19_V)<<(HOST_SLCHOST_CONF19_S)) +#define HOST_SLCHOST_CONF19_V 0xFF +#define HOST_SLCHOST_CONF19_S 24 +/* HOST_SLCHOST_CONF18 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF18 0x000000FF +#define HOST_SLCHOST_CONF18_M ((HOST_SLCHOST_CONF18_V)<<(HOST_SLCHOST_CONF18_S)) +#define HOST_SLCHOST_CONF18_V 0xFF +#define HOST_SLCHOST_CONF18_S 16 +/* HOST_SLCHOST_CONF17 : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: SLC timeout enable*/ +#define HOST_SLCHOST_CONF17 0x000000FF +#define HOST_SLCHOST_CONF17_M ((HOST_SLCHOST_CONF17_V)<<(HOST_SLCHOST_CONF17_S)) +#define HOST_SLCHOST_CONF17_V 0xFF +#define HOST_SLCHOST_CONF17_S 8 +/* HOST_SLCHOST_CONF16 : R/W ;bitpos:[7:0] ;default: 8'hFF ; */ +/*description: SLC timeout value*/ +#define HOST_SLCHOST_CONF16 0x000000FF +#define HOST_SLCHOST_CONF16_M ((HOST_SLCHOST_CONF16_V)<<(HOST_SLCHOST_CONF16_S)) +#define HOST_SLCHOST_CONF16_V 0xFF +#define HOST_SLCHOST_CONF16_S 0 + +#define HOST_SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80) +/* HOST_SLCHOST_CONF23 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF23 0x000000FF +#define HOST_SLCHOST_CONF23_M ((HOST_SLCHOST_CONF23_V)<<(HOST_SLCHOST_CONF23_S)) +#define HOST_SLCHOST_CONF23_V 0xFF +#define HOST_SLCHOST_CONF23_S 24 +/* HOST_SLCHOST_CONF22 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF22 0x000000FF +#define HOST_SLCHOST_CONF22_M ((HOST_SLCHOST_CONF22_V)<<(HOST_SLCHOST_CONF22_S)) +#define HOST_SLCHOST_CONF22_V 0xFF +#define HOST_SLCHOST_CONF22_S 16 +/* HOST_SLCHOST_CONF21 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF21 0x000000FF +#define HOST_SLCHOST_CONF21_M ((HOST_SLCHOST_CONF21_V)<<(HOST_SLCHOST_CONF21_S)) +#define HOST_SLCHOST_CONF21_V 0xFF +#define HOST_SLCHOST_CONF21_S 8 +/* HOST_SLCHOST_CONF20 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF20 0x000000FF +#define HOST_SLCHOST_CONF20_M ((HOST_SLCHOST_CONF20_V)<<(HOST_SLCHOST_CONF20_S)) +#define HOST_SLCHOST_CONF20_V 0xFF +#define HOST_SLCHOST_CONF20_S 0 + +#define HOST_SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84) + +#define HOST_SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88) +/* HOST_SLCHOST_CONF27 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF27 0x000000FF +#define HOST_SLCHOST_CONF27_M ((HOST_SLCHOST_CONF27_V)<<(HOST_SLCHOST_CONF27_S)) +#define HOST_SLCHOST_CONF27_V 0xFF +#define HOST_SLCHOST_CONF27_S 24 +/* HOST_SLCHOST_CONF26 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF26 0x000000FF +#define HOST_SLCHOST_CONF26_M ((HOST_SLCHOST_CONF26_V)<<(HOST_SLCHOST_CONF26_S)) +#define HOST_SLCHOST_CONF26_V 0xFF +#define HOST_SLCHOST_CONF26_S 16 +/* HOST_SLCHOST_CONF25 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF25 0x000000FF +#define HOST_SLCHOST_CONF25_M ((HOST_SLCHOST_CONF25_V)<<(HOST_SLCHOST_CONF25_S)) +#define HOST_SLCHOST_CONF25_V 0xFF +#define HOST_SLCHOST_CONF25_S 8 +/* HOST_SLCHOST_CONF24 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF24 0x000000FF +#define HOST_SLCHOST_CONF24_M ((HOST_SLCHOST_CONF24_V)<<(HOST_SLCHOST_CONF24_S)) +#define HOST_SLCHOST_CONF24_V 0xFF +#define HOST_SLCHOST_CONF24_S 0 + +#define HOST_SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8C) +/* HOST_SLCHOST_CONF31 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF31 0x000000FF +#define HOST_SLCHOST_CONF31_M ((HOST_SLCHOST_CONF31_V)<<(HOST_SLCHOST_CONF31_S)) +#define HOST_SLCHOST_CONF31_V 0xFF +#define HOST_SLCHOST_CONF31_S 24 +/* HOST_SLCHOST_CONF30 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF30 0x000000FF +#define HOST_SLCHOST_CONF30_M ((HOST_SLCHOST_CONF30_V)<<(HOST_SLCHOST_CONF30_S)) +#define HOST_SLCHOST_CONF30_V 0xFF +#define HOST_SLCHOST_CONF30_S 16 +/* HOST_SLCHOST_CONF29 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF29 0x000000FF +#define HOST_SLCHOST_CONF29_M ((HOST_SLCHOST_CONF29_V)<<(HOST_SLCHOST_CONF29_S)) +#define HOST_SLCHOST_CONF29_V 0xFF +#define HOST_SLCHOST_CONF29_S 8 +/* HOST_SLCHOST_CONF28 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF28 0x000000FF +#define HOST_SLCHOST_CONF28_M ((HOST_SLCHOST_CONF28_V)<<(HOST_SLCHOST_CONF28_S)) +#define HOST_SLCHOST_CONF28_V 0xFF +#define HOST_SLCHOST_CONF28_S 0 + +#define HOST_SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90) +/* HOST_HOSTSLC0_LEN0 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN0 0x000FFFFF +#define HOST_HOSTSLC0_LEN0_M ((HOST_HOSTSLC0_LEN0_V)<<(HOST_HOSTSLC0_LEN0_S)) +#define HOST_HOSTSLC0_LEN0_V 0xFFFFF +#define HOST_HOSTSLC0_LEN0_S 0 + +#define HOST_SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94) +/* HOST_HOSTSLC0_LEN1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN1 0x000FFFFF +#define HOST_HOSTSLC0_LEN1_M ((HOST_HOSTSLC0_LEN1_V)<<(HOST_HOSTSLC0_LEN1_S)) +#define HOST_HOSTSLC0_LEN1_V 0xFFFFF +#define HOST_HOSTSLC0_LEN1_S 0 + +#define HOST_SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98) +/* HOST_HOSTSLC0_LEN2 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN2 0x000FFFFF +#define HOST_HOSTSLC0_LEN2_M ((HOST_HOSTSLC0_LEN2_V)<<(HOST_HOSTSLC0_LEN2_S)) +#define HOST_HOSTSLC0_LEN2_V 0xFFFFF +#define HOST_HOSTSLC0_LEN2_S 0 + +#define HOST_SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9C) +/* HOST_SLCHOST_CONF35 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF35 0x000000FF +#define HOST_SLCHOST_CONF35_M ((HOST_SLCHOST_CONF35_V)<<(HOST_SLCHOST_CONF35_S)) +#define HOST_SLCHOST_CONF35_V 0xFF +#define HOST_SLCHOST_CONF35_S 24 +/* HOST_SLCHOST_CONF34 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF34 0x000000FF +#define HOST_SLCHOST_CONF34_M ((HOST_SLCHOST_CONF34_V)<<(HOST_SLCHOST_CONF34_S)) +#define HOST_SLCHOST_CONF34_V 0xFF +#define HOST_SLCHOST_CONF34_S 16 +/* HOST_SLCHOST_CONF33 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF33 0x000000FF +#define HOST_SLCHOST_CONF33_M ((HOST_SLCHOST_CONF33_V)<<(HOST_SLCHOST_CONF33_S)) +#define HOST_SLCHOST_CONF33_V 0xFF +#define HOST_SLCHOST_CONF33_S 8 +/* HOST_SLCHOST_CONF32 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF32 0x000000FF +#define HOST_SLCHOST_CONF32_M ((HOST_SLCHOST_CONF32_V)<<(HOST_SLCHOST_CONF32_S)) +#define HOST_SLCHOST_CONF32_V 0xFF +#define HOST_SLCHOST_CONF32_S 0 + +#define HOST_SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xA0) +/* HOST_SLCHOST_CONF39 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF39 0x000000FF +#define HOST_SLCHOST_CONF39_M ((HOST_SLCHOST_CONF39_V)<<(HOST_SLCHOST_CONF39_S)) +#define HOST_SLCHOST_CONF39_V 0xFF +#define HOST_SLCHOST_CONF39_S 24 +/* HOST_SLCHOST_CONF38 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF38 0x000000FF +#define HOST_SLCHOST_CONF38_M ((HOST_SLCHOST_CONF38_V)<<(HOST_SLCHOST_CONF38_S)) +#define HOST_SLCHOST_CONF38_V 0xFF +#define HOST_SLCHOST_CONF38_S 16 +/* HOST_SLCHOST_CONF37 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF37 0x000000FF +#define HOST_SLCHOST_CONF37_M ((HOST_SLCHOST_CONF37_V)<<(HOST_SLCHOST_CONF37_S)) +#define HOST_SLCHOST_CONF37_V 0xFF +#define HOST_SLCHOST_CONF37_S 8 +/* HOST_SLCHOST_CONF36 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF36 0x000000FF +#define HOST_SLCHOST_CONF36_M ((HOST_SLCHOST_CONF36_V)<<(HOST_SLCHOST_CONF36_S)) +#define HOST_SLCHOST_CONF36_V 0xFF +#define HOST_SLCHOST_CONF36_S 0 + +#define HOST_SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xA4) +/* HOST_SLCHOST_CONF43 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF43 0x000000FF +#define HOST_SLCHOST_CONF43_M ((HOST_SLCHOST_CONF43_V)<<(HOST_SLCHOST_CONF43_S)) +#define HOST_SLCHOST_CONF43_V 0xFF +#define HOST_SLCHOST_CONF43_S 24 +/* HOST_SLCHOST_CONF42 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF42 0x000000FF +#define HOST_SLCHOST_CONF42_M ((HOST_SLCHOST_CONF42_V)<<(HOST_SLCHOST_CONF42_S)) +#define HOST_SLCHOST_CONF42_V 0xFF +#define HOST_SLCHOST_CONF42_S 16 +/* HOST_SLCHOST_CONF41 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF41 0x000000FF +#define HOST_SLCHOST_CONF41_M ((HOST_SLCHOST_CONF41_V)<<(HOST_SLCHOST_CONF41_S)) +#define HOST_SLCHOST_CONF41_V 0xFF +#define HOST_SLCHOST_CONF41_S 8 +/* HOST_SLCHOST_CONF40 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF40 0x000000FF +#define HOST_SLCHOST_CONF40_M ((HOST_SLCHOST_CONF40_V)<<(HOST_SLCHOST_CONF40_S)) +#define HOST_SLCHOST_CONF40_V 0xFF +#define HOST_SLCHOST_CONF40_S 0 + +#define HOST_SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xA8) +/* HOST_SLCHOST_CONF47 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF47 0x000000FF +#define HOST_SLCHOST_CONF47_M ((HOST_SLCHOST_CONF47_V)<<(HOST_SLCHOST_CONF47_S)) +#define HOST_SLCHOST_CONF47_V 0xFF +#define HOST_SLCHOST_CONF47_S 24 +/* HOST_SLCHOST_CONF46 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF46 0x000000FF +#define HOST_SLCHOST_CONF46_M ((HOST_SLCHOST_CONF46_V)<<(HOST_SLCHOST_CONF46_S)) +#define HOST_SLCHOST_CONF46_V 0xFF +#define HOST_SLCHOST_CONF46_S 16 +/* HOST_SLCHOST_CONF45 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF45 0x000000FF +#define HOST_SLCHOST_CONF45_M ((HOST_SLCHOST_CONF45_V)<<(HOST_SLCHOST_CONF45_S)) +#define HOST_SLCHOST_CONF45_V 0xFF +#define HOST_SLCHOST_CONF45_S 8 +/* HOST_SLCHOST_CONF44 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF44 0x000000FF +#define HOST_SLCHOST_CONF44_M ((HOST_SLCHOST_CONF44_V)<<(HOST_SLCHOST_CONF44_S)) +#define HOST_SLCHOST_CONF44_V 0xFF +#define HOST_SLCHOST_CONF44_S 0 + +#define HOST_SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xAC) +/* HOST_SLCHOST_CONF51 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF51 0x000000FF +#define HOST_SLCHOST_CONF51_M ((HOST_SLCHOST_CONF51_V)<<(HOST_SLCHOST_CONF51_S)) +#define HOST_SLCHOST_CONF51_V 0xFF +#define HOST_SLCHOST_CONF51_S 24 +/* HOST_SLCHOST_CONF50 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF50 0x000000FF +#define HOST_SLCHOST_CONF50_M ((HOST_SLCHOST_CONF50_V)<<(HOST_SLCHOST_CONF50_S)) +#define HOST_SLCHOST_CONF50_V 0xFF +#define HOST_SLCHOST_CONF50_S 16 +/* HOST_SLCHOST_CONF49 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF49 0x000000FF +#define HOST_SLCHOST_CONF49_M ((HOST_SLCHOST_CONF49_V)<<(HOST_SLCHOST_CONF49_S)) +#define HOST_SLCHOST_CONF49_V 0xFF +#define HOST_SLCHOST_CONF49_S 8 +/* HOST_SLCHOST_CONF48 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF48 0x000000FF +#define HOST_SLCHOST_CONF48_M ((HOST_SLCHOST_CONF48_V)<<(HOST_SLCHOST_CONF48_S)) +#define HOST_SLCHOST_CONF48_V 0xFF +#define HOST_SLCHOST_CONF48_S 0 + +#define HOST_SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xB0) +/* HOST_SLCHOST_CONF55 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF55 0x000000FF +#define HOST_SLCHOST_CONF55_M ((HOST_SLCHOST_CONF55_V)<<(HOST_SLCHOST_CONF55_S)) +#define HOST_SLCHOST_CONF55_V 0xFF +#define HOST_SLCHOST_CONF55_S 24 +/* HOST_SLCHOST_CONF54 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF54 0x000000FF +#define HOST_SLCHOST_CONF54_M ((HOST_SLCHOST_CONF54_V)<<(HOST_SLCHOST_CONF54_S)) +#define HOST_SLCHOST_CONF54_V 0xFF +#define HOST_SLCHOST_CONF54_S 16 +/* HOST_SLCHOST_CONF53 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF53 0x000000FF +#define HOST_SLCHOST_CONF53_M ((HOST_SLCHOST_CONF53_V)<<(HOST_SLCHOST_CONF53_S)) +#define HOST_SLCHOST_CONF53_V 0xFF +#define HOST_SLCHOST_CONF53_S 8 +/* HOST_SLCHOST_CONF52 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF52 0x000000FF +#define HOST_SLCHOST_CONF52_M ((HOST_SLCHOST_CONF52_V)<<(HOST_SLCHOST_CONF52_S)) +#define HOST_SLCHOST_CONF52_V 0xFF +#define HOST_SLCHOST_CONF52_S 0 + +#define HOST_SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xB4) +/* HOST_SLCHOST_CONF59 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF59 0x000000FF +#define HOST_SLCHOST_CONF59_M ((HOST_SLCHOST_CONF59_V)<<(HOST_SLCHOST_CONF59_S)) +#define HOST_SLCHOST_CONF59_V 0xFF +#define HOST_SLCHOST_CONF59_S 24 +/* HOST_SLCHOST_CONF58 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF58 0x000000FF +#define HOST_SLCHOST_CONF58_M ((HOST_SLCHOST_CONF58_V)<<(HOST_SLCHOST_CONF58_S)) +#define HOST_SLCHOST_CONF58_V 0xFF +#define HOST_SLCHOST_CONF58_S 16 +/* HOST_SLCHOST_CONF57 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF57 0x000000FF +#define HOST_SLCHOST_CONF57_M ((HOST_SLCHOST_CONF57_V)<<(HOST_SLCHOST_CONF57_S)) +#define HOST_SLCHOST_CONF57_V 0xFF +#define HOST_SLCHOST_CONF57_S 8 +/* HOST_SLCHOST_CONF56 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF56 0x000000FF +#define HOST_SLCHOST_CONF56_M ((HOST_SLCHOST_CONF56_V)<<(HOST_SLCHOST_CONF56_S)) +#define HOST_SLCHOST_CONF56_V 0xFF +#define HOST_SLCHOST_CONF56_S 0 + +#define HOST_SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xB8) +/* HOST_SLCHOST_CONF63 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF63 0x000000FF +#define HOST_SLCHOST_CONF63_M ((HOST_SLCHOST_CONF63_V)<<(HOST_SLCHOST_CONF63_S)) +#define HOST_SLCHOST_CONF63_V 0xFF +#define HOST_SLCHOST_CONF63_S 24 +/* HOST_SLCHOST_CONF62 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF62 0x000000FF +#define HOST_SLCHOST_CONF62_M ((HOST_SLCHOST_CONF62_V)<<(HOST_SLCHOST_CONF62_S)) +#define HOST_SLCHOST_CONF62_V 0xFF +#define HOST_SLCHOST_CONF62_S 16 +/* HOST_SLCHOST_CONF61 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF61 0x000000FF +#define HOST_SLCHOST_CONF61_M ((HOST_SLCHOST_CONF61_V)<<(HOST_SLCHOST_CONF61_S)) +#define HOST_SLCHOST_CONF61_V 0xFF +#define HOST_SLCHOST_CONF61_S 8 +/* HOST_SLCHOST_CONF60 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF60 0x000000FF +#define HOST_SLCHOST_CONF60_M ((HOST_SLCHOST_CONF60_V)<<(HOST_SLCHOST_CONF60_S)) +#define HOST_SLCHOST_CONF60_V 0xFF +#define HOST_SLCHOST_CONF60_S 0 + +#define HOST_SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xBC) +/* HOST_SLCHOST_CHECK_SUM0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLCHOST_CHECK_SUM0 0xFFFFFFFF +#define HOST_SLCHOST_CHECK_SUM0_M ((HOST_SLCHOST_CHECK_SUM0_V)<<(HOST_SLCHOST_CHECK_SUM0_S)) +#define HOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFF +#define HOST_SLCHOST_CHECK_SUM0_S 0 + +#define HOST_SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xC0) +/* HOST_SLCHOST_CHECK_SUM1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLCHOST_CHECK_SUM1 0xFFFFFFFF +#define HOST_SLCHOST_CHECK_SUM1_M ((HOST_SLCHOST_CHECK_SUM1_V)<<(HOST_SLCHOST_CHECK_SUM1_S)) +#define HOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFF +#define HOST_SLCHOST_CHECK_SUM1_S 0 + +#define HOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0xC4) +/* HOST_SLC1_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: */ +#define HOST_SLC1_RX_PF_EOF 0x0000000F +#define HOST_SLC1_RX_PF_EOF_M ((HOST_SLC1_RX_PF_EOF_V)<<(HOST_SLC1_RX_PF_EOF_S)) +#define HOST_SLC1_RX_PF_EOF_V 0xF +#define HOST_SLC1_RX_PF_EOF_S 28 +/* HOST_HOSTSLC1_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define HOST_HOSTSLC1_TOKEN1 0x00000FFF +#define HOST_HOSTSLC1_TOKEN1_M ((HOST_HOSTSLC1_TOKEN1_V)<<(HOST_HOSTSLC1_TOKEN1_S)) +#define HOST_HOSTSLC1_TOKEN1_V 0xFFF +#define HOST_HOSTSLC1_TOKEN1_S 16 +/* HOST_SLC1_RX_PF_VALID : RO ;bitpos:[12] ;default: 1'h0 ; */ +/*description: */ +#define HOST_SLC1_RX_PF_VALID (BIT(12)) +#define HOST_SLC1_RX_PF_VALID_M (BIT(12)) +#define HOST_SLC1_RX_PF_VALID_V 0x1 +#define HOST_SLC1_RX_PF_VALID_S 12 +/* HOST_SLC1_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0 0x00000FFF +#define HOST_SLC1_TOKEN0_M ((HOST_SLC1_TOKEN0_V)<<(HOST_SLC1_TOKEN0_S)) +#define HOST_SLC1_TOKEN0_V 0xFFF +#define HOST_SLC1_TOKEN0_S 0 + +#define HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xC8) +/* HOST_SLC0HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN1_WD 0x00000FFF +#define HOST_SLC0HOST_TOKEN1_WD_M ((HOST_SLC0HOST_TOKEN1_WD_V)<<(HOST_SLC0HOST_TOKEN1_WD_S)) +#define HOST_SLC0HOST_TOKEN1_WD_V 0xFFF +#define HOST_SLC0HOST_TOKEN1_WD_S 16 +/* HOST_SLC0HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN0_WD 0x00000FFF +#define HOST_SLC0HOST_TOKEN0_WD_M ((HOST_SLC0HOST_TOKEN0_WD_V)<<(HOST_SLC0HOST_TOKEN0_WD_S)) +#define HOST_SLC0HOST_TOKEN0_WD_V 0xFFF +#define HOST_SLC0HOST_TOKEN0_WD_S 0 + +#define HOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xCC) +/* HOST_SLC1HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define HOST_SLC1HOST_TOKEN1_WD 0x00000FFF +#define HOST_SLC1HOST_TOKEN1_WD_M ((HOST_SLC1HOST_TOKEN1_WD_V)<<(HOST_SLC1HOST_TOKEN1_WD_S)) +#define HOST_SLC1HOST_TOKEN1_WD_V 0xFFF +#define HOST_SLC1HOST_TOKEN1_WD_S 16 +/* HOST_SLC1HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define HOST_SLC1HOST_TOKEN0_WD 0x00000FFF +#define HOST_SLC1HOST_TOKEN0_WD_M ((HOST_SLC1HOST_TOKEN0_WD_V)<<(HOST_SLC1HOST_TOKEN0_WD_S)) +#define HOST_SLC1HOST_TOKEN0_WD_V 0xFFF +#define HOST_SLC1HOST_TOKEN0_WD_S 0 + +#define HOST_SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xD0) +/* HOST_SLC0HOST_LEN_WR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_LEN_WR (BIT(8)) +#define HOST_SLC0HOST_LEN_WR_M (BIT(8)) +#define HOST_SLC0HOST_LEN_WR_V 0x1 +#define HOST_SLC0HOST_LEN_WR_S 8 +/* HOST_SLC1HOST_TOKEN1_WR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_TOKEN1_WR (BIT(7)) +#define HOST_SLC1HOST_TOKEN1_WR_M (BIT(7)) +#define HOST_SLC1HOST_TOKEN1_WR_V 0x1 +#define HOST_SLC1HOST_TOKEN1_WR_S 7 +/* HOST_SLC1HOST_TOKEN0_WR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_TOKEN0_WR (BIT(6)) +#define HOST_SLC1HOST_TOKEN0_WR_M (BIT(6)) +#define HOST_SLC1HOST_TOKEN0_WR_V 0x1 +#define HOST_SLC1HOST_TOKEN0_WR_S 6 +/* HOST_SLC1HOST_TOKEN1_DEC : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_TOKEN1_DEC (BIT(5)) +#define HOST_SLC1HOST_TOKEN1_DEC_M (BIT(5)) +#define HOST_SLC1HOST_TOKEN1_DEC_V 0x1 +#define HOST_SLC1HOST_TOKEN1_DEC_S 5 +/* HOST_SLC1HOST_TOKEN0_DEC : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_TOKEN0_DEC (BIT(4)) +#define HOST_SLC1HOST_TOKEN0_DEC_M (BIT(4)) +#define HOST_SLC1HOST_TOKEN0_DEC_V 0x1 +#define HOST_SLC1HOST_TOKEN0_DEC_S 4 +/* HOST_SLC0HOST_TOKEN1_WR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN1_WR (BIT(3)) +#define HOST_SLC0HOST_TOKEN1_WR_M (BIT(3)) +#define HOST_SLC0HOST_TOKEN1_WR_V 0x1 +#define HOST_SLC0HOST_TOKEN1_WR_S 3 +/* HOST_SLC0HOST_TOKEN0_WR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN0_WR (BIT(2)) +#define HOST_SLC0HOST_TOKEN0_WR_M (BIT(2)) +#define HOST_SLC0HOST_TOKEN0_WR_V 0x1 +#define HOST_SLC0HOST_TOKEN0_WR_S 2 +/* HOST_SLC0HOST_TOKEN1_DEC : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN1_DEC (BIT(1)) +#define HOST_SLC0HOST_TOKEN1_DEC_M (BIT(1)) +#define HOST_SLC0HOST_TOKEN1_DEC_V 0x1 +#define HOST_SLC0HOST_TOKEN1_DEC_S 1 +/* HOST_SLC0HOST_TOKEN0_DEC : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN0_DEC (BIT(0)) +#define HOST_SLC0HOST_TOKEN0_DEC_M (BIT(0)) +#define HOST_SLC0HOST_TOKEN0_DEC_V 0x1 +#define HOST_SLC0HOST_TOKEN0_DEC_S 0 + +#define HOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD4) +/* HOST_GPIO_SDIO_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_CLR (BIT(25)) +#define HOST_GPIO_SDIO_INT_CLR_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_CLR_V 0x1 +#define HOST_GPIO_SDIO_INT_CLR_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23 +/* HOST_SLC0_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_CLR (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_CLR_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_CLR_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_CLR_S 22 +/* HOST_SLC0_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_CLR (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_CLR_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_CLR_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_CLR_S 21 +/* HOST_SLC0_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_CLR (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_CLR_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_CLR_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_CLR_S 20 +/* HOST_SLC0_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_CLR (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_CLR_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_CLR_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_CLR_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_CLR_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_CLR_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_CLR_S 18 +/* HOST_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_CLR (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_CLR_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_CLR_V 0x1 +#define HOST_SLC0_TX_OVF_INT_CLR_S 17 +/* HOST_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_CLR (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_CLR_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_CLR_V 0x1 +#define HOST_SLC0_RX_UDF_INT_CLR_S 16 +/* HOST_SLC0HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_CLR (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_CLR_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_CLR_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_CLR_S 15 +/* HOST_SLC0HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_CLR (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_CLR_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_CLR_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_CLR_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_CLR_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_CLR_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_CLR_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_CLR_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_CLR_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_CLR_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_CLR_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_CLR_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_CLR_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_CLR_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_CLR_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_CLR_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_CLR_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_CLR_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_CLR_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_CLR_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_CLR_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_CLR_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_CLR_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_CLR_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_CLR_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_CLR_S 0 + +#define HOST_SLC1HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD8) +/* HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V 0x1 +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S 25 +/* HOST_SLC1_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_CLR_M (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_CLR_V 0x1 +#define HOST_SLC1_HOST_RD_RETRY_INT_CLR_S 24 +/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V 0x1 +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S 23 +/* HOST_SLC1_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT3_INT_CLR (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_CLR_M (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_CLR_V 0x1 +#define HOST_SLC1_EXT_BIT3_INT_CLR_S 22 +/* HOST_SLC1_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT2_INT_CLR (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_CLR_M (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_CLR_V 0x1 +#define HOST_SLC1_EXT_BIT2_INT_CLR_S 21 +/* HOST_SLC1_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT1_INT_CLR (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_CLR_M (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_CLR_V 0x1 +#define HOST_SLC1_EXT_BIT1_INT_CLR_S 20 +/* HOST_SLC1_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT0_INT_CLR (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_CLR_M (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_CLR_V 0x1 +#define HOST_SLC1_EXT_BIT0_INT_CLR_S 19 +/* HOST_SLC1_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_PF_VALID_INT_CLR (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_CLR_M (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_CLR_V 0x1 +#define HOST_SLC1_RX_PF_VALID_INT_CLR_S 18 +/* HOST_SLC1_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TX_OVF_INT_CLR (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_CLR_M (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_CLR_V 0x1 +#define HOST_SLC1_TX_OVF_INT_CLR_S 17 +/* HOST_SLC1_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_UDF_INT_CLR (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_CLR_M (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_CLR_V 0x1 +#define HOST_SLC1_RX_UDF_INT_CLR_S 16 +/* HOST_SLC1HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_TX_START_INT_CLR (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_CLR_M (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_CLR_V 0x1 +#define HOST_SLC1HOST_TX_START_INT_CLR_S 15 +/* HOST_SLC1HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_START_INT_CLR (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_CLR_M (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_CLR_V 0x1 +#define HOST_SLC1HOST_RX_START_INT_CLR_S 14 +/* HOST_SLC1HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_EOF_INT_CLR (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_CLR_M (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_CLR_V 0x1 +#define HOST_SLC1HOST_RX_EOF_INT_CLR_S 13 +/* HOST_SLC1HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_SOF_INT_CLR (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_CLR_M (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_CLR_V 0x1 +#define HOST_SLC1HOST_RX_SOF_INT_CLR_S 12 +/* HOST_SLC1_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_CLR_M (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_CLR_V 0x1 +#define HOST_SLC1_TOKEN1_0TO1_INT_CLR_S 11 +/* HOST_SLC1_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_CLR_M (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_CLR_V 0x1 +#define HOST_SLC1_TOKEN0_0TO1_INT_CLR_S 10 +/* HOST_SLC1_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_CLR_M (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_CLR_V 0x1 +#define HOST_SLC1_TOKEN1_1TO0_INT_CLR_S 9 +/* HOST_SLC1_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_CLR_M (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_CLR_V 0x1 +#define HOST_SLC1_TOKEN0_1TO0_INT_CLR_S 8 +/* HOST_SLC1_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT7_INT_CLR (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_CLR_M (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_CLR_V 0x1 +#define HOST_SLC1_TOHOST_BIT7_INT_CLR_S 7 +/* HOST_SLC1_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT6_INT_CLR (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_CLR_M (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_CLR_V 0x1 +#define HOST_SLC1_TOHOST_BIT6_INT_CLR_S 6 +/* HOST_SLC1_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT5_INT_CLR (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_CLR_M (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_CLR_V 0x1 +#define HOST_SLC1_TOHOST_BIT5_INT_CLR_S 5 +/* HOST_SLC1_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT4_INT_CLR (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_CLR_M (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_CLR_V 0x1 +#define HOST_SLC1_TOHOST_BIT4_INT_CLR_S 4 +/* HOST_SLC1_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT3_INT_CLR (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_CLR_M (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_CLR_V 0x1 +#define HOST_SLC1_TOHOST_BIT3_INT_CLR_S 3 +/* HOST_SLC1_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT2_INT_CLR (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_CLR_M (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_CLR_V 0x1 +#define HOST_SLC1_TOHOST_BIT2_INT_CLR_S 2 +/* HOST_SLC1_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT1_INT_CLR (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_CLR_M (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_CLR_V 0x1 +#define HOST_SLC1_TOHOST_BIT1_INT_CLR_S 1 +/* HOST_SLC1_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT0_INT_CLR (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_CLR_M (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_CLR_V 0x1 +#define HOST_SLC1_TOHOST_BIT0_INT_CLR_S 0 + +#define HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xDC) +/* HOST_FN1_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_GPIO_SDIO_INT_ENA (BIT(25)) +#define HOST_FN1_GPIO_SDIO_INT_ENA_M (BIT(25)) +#define HOST_FN1_GPIO_SDIO_INT_ENA_V 0x1 +#define HOST_FN1_GPIO_SDIO_INT_ENA_S 25 +/* HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24)) +#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/* HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23)) +#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/* HOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (BIT(22)) +#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22 +/* HOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (BIT(21)) +#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21 +/* HOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (BIT(20)) +#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20 +/* HOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (BIT(19)) +#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19 +/* HOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18)) +#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18 +/* HOST_FN1_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define HOST_FN1_SLC0_TX_OVF_INT_ENA_M (BIT(17)) +#define HOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TX_OVF_INT_ENA_S 17 +/* HOST_FN1_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define HOST_FN1_SLC0_RX_UDF_INT_ENA_M (BIT(16)) +#define HOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_RX_UDF_INT_ENA_S 16 +/* HOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_M (BIT(15)) +#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x1 +#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15 +/* HOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_M (BIT(14)) +#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x1 +#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14 +/* HOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13)) +#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x1 +#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13 +/* HOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12)) +#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x1 +#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12 +/* HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11)) +#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/* HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10)) +#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/* HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9)) +#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/* HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8)) +#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/* HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7)) +#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/* HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6)) +#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/* HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5)) +#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/* HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4)) +#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/* HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3)) +#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/* HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2)) +#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/* HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1)) +#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/* HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0)) +#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0 + +#define HOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xE0) +/* HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (BIT(25)) +#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 +/* HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M (BIT(24)) +#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/* HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (BIT(23)) +#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/* HOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA_M (BIT(22)) +#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA_S 22 +/* HOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA_M (BIT(21)) +#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA_S 21 +/* HOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA_M (BIT(20)) +#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA_S 20 +/* HOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA_M (BIT(19)) +#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA_S 19 +/* HOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M (BIT(18)) +#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S 18 +/* HOST_FN1_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define HOST_FN1_SLC1_TX_OVF_INT_ENA_M (BIT(17)) +#define HOST_FN1_SLC1_TX_OVF_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TX_OVF_INT_ENA_S 17 +/* HOST_FN1_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define HOST_FN1_SLC1_RX_UDF_INT_ENA_M (BIT(16)) +#define HOST_FN1_SLC1_RX_UDF_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_RX_UDF_INT_ENA_S 16 +/* HOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define HOST_FN1_SLC1HOST_TX_START_INT_ENA_M (BIT(15)) +#define HOST_FN1_SLC1HOST_TX_START_INT_ENA_V 0x1 +#define HOST_FN1_SLC1HOST_TX_START_INT_ENA_S 15 +/* HOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define HOST_FN1_SLC1HOST_RX_START_INT_ENA_M (BIT(14)) +#define HOST_FN1_SLC1HOST_RX_START_INT_ENA_V 0x1 +#define HOST_FN1_SLC1HOST_RX_START_INT_ENA_S 14 +/* HOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M (BIT(13)) +#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V 0x1 +#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S 13 +/* HOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M (BIT(12)) +#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V 0x1 +#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S 12 +/* HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M (BIT(11)) +#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/* HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M (BIT(10)) +#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/* HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M (BIT(9)) +#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/* HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M (BIT(8)) +#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/* HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M (BIT(7)) +#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/* HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M (BIT(6)) +#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/* HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M (BIT(5)) +#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/* HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M (BIT(4)) +#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/* HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M (BIT(3)) +#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/* HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M (BIT(2)) +#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/* HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M (BIT(1)) +#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/* HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M (BIT(0)) +#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V 0x1 +#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S 0 + +#define HOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xE4) +/* HOST_FN2_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_GPIO_SDIO_INT_ENA (BIT(25)) +#define HOST_FN2_GPIO_SDIO_INT_ENA_M (BIT(25)) +#define HOST_FN2_GPIO_SDIO_INT_ENA_V 0x1 +#define HOST_FN2_GPIO_SDIO_INT_ENA_S 25 +/* HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24)) +#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/* HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23)) +#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/* HOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA_M (BIT(22)) +#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA_S 22 +/* HOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA_M (BIT(21)) +#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA_S 21 +/* HOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA_M (BIT(20)) +#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA_S 20 +/* HOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA_M (BIT(19)) +#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA_S 19 +/* HOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18)) +#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S 18 +/* HOST_FN2_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define HOST_FN2_SLC0_TX_OVF_INT_ENA_M (BIT(17)) +#define HOST_FN2_SLC0_TX_OVF_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TX_OVF_INT_ENA_S 17 +/* HOST_FN2_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define HOST_FN2_SLC0_RX_UDF_INT_ENA_M (BIT(16)) +#define HOST_FN2_SLC0_RX_UDF_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_RX_UDF_INT_ENA_S 16 +/* HOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define HOST_FN2_SLC0HOST_TX_START_INT_ENA_M (BIT(15)) +#define HOST_FN2_SLC0HOST_TX_START_INT_ENA_V 0x1 +#define HOST_FN2_SLC0HOST_TX_START_INT_ENA_S 15 +/* HOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define HOST_FN2_SLC0HOST_RX_START_INT_ENA_M (BIT(14)) +#define HOST_FN2_SLC0HOST_RX_START_INT_ENA_V 0x1 +#define HOST_FN2_SLC0HOST_RX_START_INT_ENA_S 14 +/* HOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13)) +#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V 0x1 +#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S 13 +/* HOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12)) +#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V 0x1 +#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S 12 +/* HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11)) +#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/* HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10)) +#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/* HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9)) +#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/* HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8)) +#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/* HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7)) +#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/* HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6)) +#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/* HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5)) +#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/* HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4)) +#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/* HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3)) +#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/* HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2)) +#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/* HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1)) +#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/* HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0)) +#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V 0x1 +#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S 0 + +#define HOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xE8) +/* HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (BIT(25)) +#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 +/* HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M (BIT(24)) +#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/* HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (BIT(23)) +#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/* HOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA_M (BIT(22)) +#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA_S 22 +/* HOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA_M (BIT(21)) +#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA_S 21 +/* HOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA_M (BIT(20)) +#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA_S 20 +/* HOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA_M (BIT(19)) +#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA_S 19 +/* HOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M (BIT(18)) +#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S 18 +/* HOST_FN2_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define HOST_FN2_SLC1_TX_OVF_INT_ENA_M (BIT(17)) +#define HOST_FN2_SLC1_TX_OVF_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TX_OVF_INT_ENA_S 17 +/* HOST_FN2_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define HOST_FN2_SLC1_RX_UDF_INT_ENA_M (BIT(16)) +#define HOST_FN2_SLC1_RX_UDF_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_RX_UDF_INT_ENA_S 16 +/* HOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define HOST_FN2_SLC1HOST_TX_START_INT_ENA_M (BIT(15)) +#define HOST_FN2_SLC1HOST_TX_START_INT_ENA_V 0x1 +#define HOST_FN2_SLC1HOST_TX_START_INT_ENA_S 15 +/* HOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define HOST_FN2_SLC1HOST_RX_START_INT_ENA_M (BIT(14)) +#define HOST_FN2_SLC1HOST_RX_START_INT_ENA_V 0x1 +#define HOST_FN2_SLC1HOST_RX_START_INT_ENA_S 14 +/* HOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M (BIT(13)) +#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V 0x1 +#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S 13 +/* HOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M (BIT(12)) +#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V 0x1 +#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S 12 +/* HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M (BIT(11)) +#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/* HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M (BIT(10)) +#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/* HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M (BIT(9)) +#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/* HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M (BIT(8)) +#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/* HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M (BIT(7)) +#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/* HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M (BIT(6)) +#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/* HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M (BIT(5)) +#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/* HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M (BIT(4)) +#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/* HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M (BIT(3)) +#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/* HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M (BIT(2)) +#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/* HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M (BIT(1)) +#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/* HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M (BIT(0)) +#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V 0x1 +#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S 0 + +#define HOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xEC) +/* HOST_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_ENA (BIT(25)) +#define HOST_GPIO_SDIO_INT_ENA_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_ENA_V 0x1 +#define HOST_GPIO_SDIO_INT_ENA_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/* HOST_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ENA_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ENA_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_ENA_S 22 +/* HOST_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ENA_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ENA_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_ENA_S 21 +/* HOST_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ENA_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ENA_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_ENA_S 20 +/* HOST_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ENA_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ENA_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_ENA_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ENA_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_ENA_S 18 +/* HOST_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ENA_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ENA_V 0x1 +#define HOST_SLC0_TX_OVF_INT_ENA_S 17 +/* HOST_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ENA_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ENA_V 0x1 +#define HOST_SLC0_RX_UDF_INT_ENA_S 16 +/* HOST_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ENA_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ENA_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_ENA_S 15 +/* HOST_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ENA_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ENA_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_ENA_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ENA_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_ENA_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ENA_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_ENA_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_ENA_S 0 + +#define HOST_SLC1HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xF0) +/* HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 +/* HOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_ENA_M (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_ENA_V 0x1 +#define HOST_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/* HOST_SLC1_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_ENA_M (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_ENA_V 0x1 +#define HOST_SLC1_EXT_BIT3_INT_ENA_S 22 +/* HOST_SLC1_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_ENA_M (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_ENA_V 0x1 +#define HOST_SLC1_EXT_BIT2_INT_ENA_S 21 +/* HOST_SLC1_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_ENA_M (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_ENA_V 0x1 +#define HOST_SLC1_EXT_BIT1_INT_ENA_S 20 +/* HOST_SLC1_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_ENA_M (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_ENA_V 0x1 +#define HOST_SLC1_EXT_BIT0_INT_ENA_S 19 +/* HOST_SLC1_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_ENA_M (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_ENA_V 0x1 +#define HOST_SLC1_RX_PF_VALID_INT_ENA_S 18 +/* HOST_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_ENA_M (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_ENA_V 0x1 +#define HOST_SLC1_TX_OVF_INT_ENA_S 17 +/* HOST_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_ENA_M (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_ENA_V 0x1 +#define HOST_SLC1_RX_UDF_INT_ENA_S 16 +/* HOST_SLC1HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_ENA_M (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_ENA_V 0x1 +#define HOST_SLC1HOST_TX_START_INT_ENA_S 15 +/* HOST_SLC1HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_ENA_M (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_ENA_V 0x1 +#define HOST_SLC1HOST_RX_START_INT_ENA_S 14 +/* HOST_SLC1HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_ENA_M (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_ENA_V 0x1 +#define HOST_SLC1HOST_RX_EOF_INT_ENA_S 13 +/* HOST_SLC1HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_ENA_M (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_ENA_V 0x1 +#define HOST_SLC1HOST_RX_SOF_INT_ENA_S 12 +/* HOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_ENA_M (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_ENA_V 0x1 +#define HOST_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/* HOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_ENA_M (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_ENA_V 0x1 +#define HOST_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/* HOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_ENA_M (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_ENA_V 0x1 +#define HOST_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/* HOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_ENA_M (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_ENA_V 0x1 +#define HOST_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/* HOST_SLC1_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_ENA_M (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_ENA_V 0x1 +#define HOST_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/* HOST_SLC1_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_ENA_M (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_ENA_V 0x1 +#define HOST_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/* HOST_SLC1_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_ENA_M (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_ENA_V 0x1 +#define HOST_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/* HOST_SLC1_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_ENA_M (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_ENA_V 0x1 +#define HOST_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/* HOST_SLC1_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_ENA_M (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_ENA_V 0x1 +#define HOST_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/* HOST_SLC1_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_ENA_M (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_ENA_V 0x1 +#define HOST_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/* HOST_SLC1_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_ENA_M (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_ENA_V 0x1 +#define HOST_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/* HOST_SLC1_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_ENA_M (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_ENA_V 0x1 +#define HOST_SLC1_TOHOST_BIT0_INT_ENA_S 0 + +#define HOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xF4) +/* HOST_SLC0HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_INFOR 0x000FFFFF +#define HOST_SLC0HOST_RX_INFOR_M ((HOST_SLC0HOST_RX_INFOR_V)<<(HOST_SLC0HOST_RX_INFOR_S)) +#define HOST_SLC0HOST_RX_INFOR_V 0xFFFFF +#define HOST_SLC0HOST_RX_INFOR_S 0 + +#define HOST_SLC1HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xF8) +/* HOST_SLC1HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_INFOR 0x000FFFFF +#define HOST_SLC1HOST_RX_INFOR_M ((HOST_SLC1HOST_RX_INFOR_V)<<(HOST_SLC1HOST_RX_INFOR_S)) +#define HOST_SLC1HOST_RX_INFOR_V 0xFFFFF +#define HOST_SLC1HOST_RX_INFOR_S 0 + +#define HOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xFC) +/* HOST_SLC0HOST_LEN_WD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_LEN_WD 0xFFFFFFFF +#define HOST_SLC0HOST_LEN_WD_M ((HOST_SLC0HOST_LEN_WD_V)<<(HOST_SLC0HOST_LEN_WD_S)) +#define HOST_SLC0HOST_LEN_WD_V 0xFFFFFFFF +#define HOST_SLC0HOST_LEN_WD_S 0 + +#define HOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100) +/* HOST_SLC_APBWIN_WDATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_WDATA 0xFFFFFFFF +#define HOST_SLC_APBWIN_WDATA_M ((HOST_SLC_APBWIN_WDATA_V)<<(HOST_SLC_APBWIN_WDATA_S)) +#define HOST_SLC_APBWIN_WDATA_V 0xFFFFFFFF +#define HOST_SLC_APBWIN_WDATA_S 0 + +#define HOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104) +/* HOST_SLC_APBWIN_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_START (BIT(29)) +#define HOST_SLC_APBWIN_START_M (BIT(29)) +#define HOST_SLC_APBWIN_START_V 0x1 +#define HOST_SLC_APBWIN_START_S 29 +/* HOST_SLC_APBWIN_WR : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_WR (BIT(28)) +#define HOST_SLC_APBWIN_WR_M (BIT(28)) +#define HOST_SLC_APBWIN_WR_V 0x1 +#define HOST_SLC_APBWIN_WR_S 28 +/* HOST_SLC_APBWIN_ADDR : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_ADDR 0x0FFFFFFF +#define HOST_SLC_APBWIN_ADDR_M ((HOST_SLC_APBWIN_ADDR_V)<<(HOST_SLC_APBWIN_ADDR_S)) +#define HOST_SLC_APBWIN_ADDR_V 0xFFFFFFF +#define HOST_SLC_APBWIN_ADDR_S 0 + +#define HOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108) +/* HOST_SLC_APBWIN_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_RDATA 0xFFFFFFFF +#define HOST_SLC_APBWIN_RDATA_M ((HOST_SLC_APBWIN_RDATA_V)<<(HOST_SLC_APBWIN_RDATA_S)) +#define HOST_SLC_APBWIN_RDATA_V 0xFFFFFFFF +#define HOST_SLC_APBWIN_RDATA_S 0 + +#define HOST_SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10C) +/* HOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */ +/*description: */ +#define HOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FF +#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT6_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT6_CLRADDR_S)) +#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x1FF +#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9 +/* HOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h44 ; */ +/*description: */ +#define HOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FF +#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT7_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT7_CLRADDR_S)) +#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x1FF +#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0 + +#define HOST_SLCHOST_RDCLR1_REG (DR_REG_SLCHOST_BASE + 0x110) +/* HOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */ +/*description: */ +#define HOST_SLCHOST_SLC1_BIT6_CLRADDR 0x000001FF +#define HOST_SLCHOST_SLC1_BIT6_CLRADDR_M ((HOST_SLCHOST_SLC1_BIT6_CLRADDR_V)<<(HOST_SLCHOST_SLC1_BIT6_CLRADDR_S)) +#define HOST_SLCHOST_SLC1_BIT6_CLRADDR_V 0x1FF +#define HOST_SLCHOST_SLC1_BIT6_CLRADDR_S 9 +/* HOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h1e0 ; */ +/*description: */ +#define HOST_SLCHOST_SLC1_BIT7_CLRADDR 0x000001FF +#define HOST_SLCHOST_SLC1_BIT7_CLRADDR_M ((HOST_SLCHOST_SLC1_BIT7_CLRADDR_V)<<(HOST_SLCHOST_SLC1_BIT7_CLRADDR_S)) +#define HOST_SLCHOST_SLC1_BIT7_CLRADDR_V 0x1FF +#define HOST_SLCHOST_SLC1_BIT7_CLRADDR_S 0 + +#define HOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114) +/* HOST_GPIO_SDIO_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_ENA1 (BIT(25)) +#define HOST_GPIO_SDIO_INT_ENA1_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_ENA1_V 0x1 +#define HOST_GPIO_SDIO_INT_ENA1_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23 +/* HOST_SLC0_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ENA1_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ENA1_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_ENA1_S 22 +/* HOST_SLC0_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ENA1_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ENA1_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_ENA1_S 21 +/* HOST_SLC0_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ENA1_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ENA1_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_ENA1_S 20 +/* HOST_SLC0_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ENA1_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ENA1_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_ENA1_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ENA1_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_ENA1_S 18 +/* HOST_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_ENA1 (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ENA1_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ENA1_V 0x1 +#define HOST_SLC0_TX_OVF_INT_ENA1_S 17 +/* HOST_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_ENA1 (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ENA1_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ENA1_V 0x1 +#define HOST_SLC0_RX_UDF_INT_ENA1_S 16 +/* HOST_SLC0HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ENA1_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ENA1_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_ENA1_S 15 +/* HOST_SLC0HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ENA1_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ENA1_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_ENA1_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ENA1_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_ENA1_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ENA1_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_ENA1_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0 + +#define HOST_SLC1HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x118) +/* HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M (BIT(25)) +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V 0x1 +#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S 25 +/* HOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1_M (BIT(24)) +#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1_V 0x1 +#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1_S 24 +/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M (BIT(23)) +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V 0x1 +#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S 23 +/* HOST_SLC1_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT3_INT_ENA1 (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_ENA1_M (BIT(22)) +#define HOST_SLC1_EXT_BIT3_INT_ENA1_V 0x1 +#define HOST_SLC1_EXT_BIT3_INT_ENA1_S 22 +/* HOST_SLC1_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT2_INT_ENA1 (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_ENA1_M (BIT(21)) +#define HOST_SLC1_EXT_BIT2_INT_ENA1_V 0x1 +#define HOST_SLC1_EXT_BIT2_INT_ENA1_S 21 +/* HOST_SLC1_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT1_INT_ENA1 (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_ENA1_M (BIT(20)) +#define HOST_SLC1_EXT_BIT1_INT_ENA1_V 0x1 +#define HOST_SLC1_EXT_BIT1_INT_ENA1_S 20 +/* HOST_SLC1_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_EXT_BIT0_INT_ENA1 (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_ENA1_M (BIT(19)) +#define HOST_SLC1_EXT_BIT0_INT_ENA1_V 0x1 +#define HOST_SLC1_EXT_BIT0_INT_ENA1_S 19 +/* HOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_ENA1_M (BIT(18)) +#define HOST_SLC1_RX_PF_VALID_INT_ENA1_V 0x1 +#define HOST_SLC1_RX_PF_VALID_INT_ENA1_S 18 +/* HOST_SLC1_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TX_OVF_INT_ENA1 (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_ENA1_M (BIT(17)) +#define HOST_SLC1_TX_OVF_INT_ENA1_V 0x1 +#define HOST_SLC1_TX_OVF_INT_ENA1_S 17 +/* HOST_SLC1_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_RX_UDF_INT_ENA1 (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_ENA1_M (BIT(16)) +#define HOST_SLC1_RX_UDF_INT_ENA1_V 0x1 +#define HOST_SLC1_RX_UDF_INT_ENA1_S 16 +/* HOST_SLC1HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_TX_START_INT_ENA1 (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_ENA1_M (BIT(15)) +#define HOST_SLC1HOST_TX_START_INT_ENA1_V 0x1 +#define HOST_SLC1HOST_TX_START_INT_ENA1_S 15 +/* HOST_SLC1HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_START_INT_ENA1 (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_ENA1_M (BIT(14)) +#define HOST_SLC1HOST_RX_START_INT_ENA1_V 0x1 +#define HOST_SLC1HOST_RX_START_INT_ENA1_S 14 +/* HOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_ENA1_M (BIT(13)) +#define HOST_SLC1HOST_RX_EOF_INT_ENA1_V 0x1 +#define HOST_SLC1HOST_RX_EOF_INT_ENA1_S 13 +/* HOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_ENA1_M (BIT(12)) +#define HOST_SLC1HOST_RX_SOF_INT_ENA1_V 0x1 +#define HOST_SLC1HOST_RX_SOF_INT_ENA1_S 12 +/* HOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1_M (BIT(11)) +#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1_V 0x1 +#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1_S 11 +/* HOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1_M (BIT(10)) +#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1_V 0x1 +#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1_S 10 +/* HOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1_M (BIT(9)) +#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x1 +#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1_S 9 +/* HOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1_M (BIT(8)) +#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x1 +#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1_S 8 +/* HOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_ENA1_M (BIT(7)) +#define HOST_SLC1_TOHOST_BIT7_INT_ENA1_V 0x1 +#define HOST_SLC1_TOHOST_BIT7_INT_ENA1_S 7 +/* HOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_ENA1_M (BIT(6)) +#define HOST_SLC1_TOHOST_BIT6_INT_ENA1_V 0x1 +#define HOST_SLC1_TOHOST_BIT6_INT_ENA1_S 6 +/* HOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_ENA1_M (BIT(5)) +#define HOST_SLC1_TOHOST_BIT5_INT_ENA1_V 0x1 +#define HOST_SLC1_TOHOST_BIT5_INT_ENA1_S 5 +/* HOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_ENA1_M (BIT(4)) +#define HOST_SLC1_TOHOST_BIT4_INT_ENA1_V 0x1 +#define HOST_SLC1_TOHOST_BIT4_INT_ENA1_S 4 +/* HOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_ENA1_M (BIT(3)) +#define HOST_SLC1_TOHOST_BIT3_INT_ENA1_V 0x1 +#define HOST_SLC1_TOHOST_BIT3_INT_ENA1_S 3 +/* HOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_ENA1_M (BIT(2)) +#define HOST_SLC1_TOHOST_BIT2_INT_ENA1_V 0x1 +#define HOST_SLC1_TOHOST_BIT2_INT_ENA1_S 2 +/* HOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_ENA1_M (BIT(1)) +#define HOST_SLC1_TOHOST_BIT1_INT_ENA1_V 0x1 +#define HOST_SLC1_TOHOST_BIT1_INT_ENA1_S 1 +/* HOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC1_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_ENA1_M (BIT(0)) +#define HOST_SLC1_TOHOST_BIT0_INT_ENA1_V 0x1 +#define HOST_SLC1_TOHOST_BIT0_INT_ENA1_S 0 + +#define HOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178) +/* HOST_SLCHOST_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022500 ; */ +/*description: */ +#define HOST_SLCHOST_DATE 0xFFFFFFFF +#define HOST_SLCHOST_DATE_M ((HOST_SLCHOST_DATE_V)<<(HOST_SLCHOST_DATE_S)) +#define HOST_SLCHOST_DATE_V 0xFFFFFFFF +#define HOST_SLCHOST_DATE_S 0 + +#define HOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17C) +/* HOST_SLCHOST_ID : R/W ;bitpos:[31:0] ;default: 32'h0600 ; */ +/*description: */ +#define HOST_SLCHOST_ID 0xFFFFFFFF +#define HOST_SLCHOST_ID_M ((HOST_SLCHOST_ID_V)<<(HOST_SLCHOST_ID_S)) +#define HOST_SLCHOST_ID_V 0xFFFFFFFF +#define HOST_SLCHOST_ID_S 0 + +#define HOST_SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1F0) +/* HOST_HSPEED_CON_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define HOST_HSPEED_CON_EN (BIT(27)) +#define HOST_HSPEED_CON_EN_M (BIT(27)) +#define HOST_HSPEED_CON_EN_V 0x1 +#define HOST_HSPEED_CON_EN_S 27 +/* HOST_SDIO_PAD_PULLUP : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SDIO_PAD_PULLUP (BIT(26)) +#define HOST_SDIO_PAD_PULLUP_M (BIT(26)) +#define HOST_SDIO_PAD_PULLUP_V 0x1 +#define HOST_SDIO_PAD_PULLUP_S 26 +/* HOST_SDIO20_INT_DELAY : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SDIO20_INT_DELAY (BIT(25)) +#define HOST_SDIO20_INT_DELAY_M (BIT(25)) +#define HOST_SDIO20_INT_DELAY_V 0x1 +#define HOST_SDIO20_INT_DELAY_S 25 +/* HOST_FRC_QUICK_IN : R/W ;bitpos:[24:20] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_QUICK_IN 0x0000001F +#define HOST_FRC_QUICK_IN_M ((HOST_FRC_QUICK_IN_V)<<(HOST_FRC_QUICK_IN_S)) +#define HOST_FRC_QUICK_IN_V 0x1F +#define HOST_FRC_QUICK_IN_S 20 +/* HOST_FRC_POS_SAMP : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_POS_SAMP 0x0000001F +#define HOST_FRC_POS_SAMP_M ((HOST_FRC_POS_SAMP_V)<<(HOST_FRC_POS_SAMP_S)) +#define HOST_FRC_POS_SAMP_V 0x1F +#define HOST_FRC_POS_SAMP_S 15 +/* HOST_FRC_NEG_SAMP : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_NEG_SAMP 0x0000001F +#define HOST_FRC_NEG_SAMP_M ((HOST_FRC_NEG_SAMP_V)<<(HOST_FRC_NEG_SAMP_S)) +#define HOST_FRC_NEG_SAMP_V 0x1F +#define HOST_FRC_NEG_SAMP_S 10 +/* HOST_FRC_SDIO20 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_SDIO20 0x0000001F +#define HOST_FRC_SDIO20_M ((HOST_FRC_SDIO20_V)<<(HOST_FRC_SDIO20_S)) +#define HOST_FRC_SDIO20_V 0x1F +#define HOST_FRC_SDIO20_S 5 +/* HOST_FRC_SDIO11 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_SDIO11 0x0000001F +#define HOST_FRC_SDIO11_M ((HOST_FRC_SDIO11_V)<<(HOST_FRC_SDIO11_S)) +#define HOST_FRC_SDIO11_V 0x1F +#define HOST_FRC_SDIO11_S 0 + +#define HOST_SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1F4) +/* HOST_SDIO_QUICK_IN : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: */ +#define HOST_SDIO_QUICK_IN 0x0000001F +#define HOST_SDIO_QUICK_IN_M ((HOST_SDIO_QUICK_IN_V)<<(HOST_SDIO_QUICK_IN_S)) +#define HOST_SDIO_QUICK_IN_V 0x1F +#define HOST_SDIO_QUICK_IN_S 10 +/* HOST_SDIO_NEG_SAMP : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: */ +#define HOST_SDIO_NEG_SAMP 0x0000001F +#define HOST_SDIO_NEG_SAMP_M ((HOST_SDIO_NEG_SAMP_V)<<(HOST_SDIO_NEG_SAMP_S)) +#define HOST_SDIO_NEG_SAMP_V 0x1F +#define HOST_SDIO_NEG_SAMP_S 5 +/* HOST_SDIO20_MODE : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: */ +#define HOST_SDIO20_MODE 0x0000001F +#define HOST_SDIO20_MODE_M ((HOST_SDIO20_MODE_V)<<(HOST_SDIO20_MODE_S)) +#define HOST_SDIO20_MODE_V 0x1F +#define HOST_SDIO20_MODE_S 0 + + + + +#endif /*_SOC_HOST_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/host_struct.h b/tools/sdk/include/soc/include/soc/host_struct.h new file mode 100644 index 00000000000..6c350abfc3a --- /dev/null +++ b/tools/sdk/include/soc/include/soc/host_struct.h @@ -0,0 +1,893 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_HOST_STRUCT_H_ +#define _SOC_HOST_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + uint32_t reserved_0; + uint32_t reserved_4; + uint32_t reserved_8; + uint32_t reserved_c; + union { + struct { + uint32_t reserved0: 24; + uint32_t func2_int: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } func2_0; + union { + struct { + uint32_t func2_int_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } func2_1; + uint32_t reserved_18; + uint32_t reserved_1c; + union { + struct { + uint32_t func1_mdstat: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } func2_2; + uint32_t reserved_24; + uint32_t reserved_28; + uint32_t reserved_2c; + uint32_t reserved_30; + uint32_t gpio_status0; /**/ + union { + struct { + uint32_t sdio_int1: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } gpio_status1; + uint32_t gpio_in0; /**/ + union { + struct { + uint32_t sdio_in1: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } gpio_in1; + union { + struct { + uint32_t token0: 12; + uint32_t rx_pf_valid: 1; + uint32_t reserved13: 3; + uint32_t reg_token1: 12; + uint32_t rx_pf_eof: 4; + }; + uint32_t val; + } slc0_token_rdata; + uint32_t slc0_pf; /**/ + uint32_t slc1_pf; /**/ + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_raw; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t wifi_rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t bt_rx_new_packet: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc1_int_raw; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_st; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t wifi_rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t bt_rx_new_packet: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc1_int_st; + union { + struct { + uint32_t reg_slc0_len: 20; + uint32_t reg_slc0_len_check:12; + }; + uint32_t val; + } pkt_len; + union { + struct { + uint32_t state0: 8; + uint32_t state1: 8; + uint32_t state2: 8; + uint32_t state3: 8; + }; + uint32_t val; + } state_w0; + union { + struct { + uint32_t state4: 8; + uint32_t state5: 8; + uint32_t state6: 8; + uint32_t state7: 8; + }; + uint32_t val; + } state_w1; + union { + struct { + uint32_t conf0: 8; + uint32_t conf1: 8; + uint32_t conf2: 8; + uint32_t conf3: 8; + }; + uint32_t val; + } conf_w0; + union { + struct { + uint32_t conf4: 8; + uint32_t conf5: 8; + uint32_t conf6: 8; + uint32_t conf7: 8; + }; + uint32_t val; + } conf_w1; + union { + struct { + uint32_t conf8: 8; + uint32_t conf9: 8; + uint32_t conf10: 8; + uint32_t conf11: 8; + }; + uint32_t val; + } conf_w2; + union { + struct { + uint32_t conf12: 8; + uint32_t conf13: 8; + uint32_t conf14: 8; + uint32_t conf15: 8; + }; + uint32_t val; + } conf_w3; + union { + struct { + uint32_t conf16: 8; /*SLC timeout value*/ + uint32_t conf17: 8; /*SLC timeout enable*/ + uint32_t conf18: 8; + uint32_t conf19: 8; /*Interrupt to target CPU*/ + }; + uint32_t val; + } conf_w4; + union { + struct { + uint32_t conf20: 8; + uint32_t conf21: 8; + uint32_t conf22: 8; + uint32_t conf23: 8; + }; + uint32_t val; + } conf_w5; + uint32_t win_cmd; /**/ + union { + struct { + uint32_t conf24: 8; + uint32_t conf25: 8; + uint32_t conf26: 8; + uint32_t conf27: 8; + }; + uint32_t val; + } conf_w6; + union { + struct { + uint32_t conf28: 8; + uint32_t conf29: 8; + uint32_t conf30: 8; + uint32_t conf31: 8; + }; + uint32_t val; + } conf_w7; + union { + struct { + uint32_t reg_slc0_len0:20; + uint32_t reserved20: 12; + }; + uint32_t val; + } pkt_len0; + union { + struct { + uint32_t reg_slc0_len1:20; + uint32_t reserved20: 12; + }; + uint32_t val; + } pkt_len1; + union { + struct { + uint32_t reg_slc0_len2:20; + uint32_t reserved20: 12; + }; + uint32_t val; + } pkt_len2; + union { + struct { + uint32_t conf32: 8; + uint32_t conf33: 8; + uint32_t conf34: 8; + uint32_t conf35: 8; + }; + uint32_t val; + } conf_w8; + union { + struct { + uint32_t conf36: 8; + uint32_t conf37: 8; + uint32_t conf38: 8; + uint32_t conf39: 8; + }; + uint32_t val; + } conf_w9; + union { + struct { + uint32_t conf40: 8; + uint32_t conf41: 8; + uint32_t conf42: 8; + uint32_t conf43: 8; + }; + uint32_t val; + } conf_w10; + union { + struct { + uint32_t conf44: 8; + uint32_t conf45: 8; + uint32_t conf46: 8; + uint32_t conf47: 8; + }; + uint32_t val; + } conf_w11; + union { + struct { + uint32_t conf48: 8; + uint32_t conf49: 8; + uint32_t conf50: 8; + uint32_t conf51: 8; + }; + uint32_t val; + } conf_w12; + union { + struct { + uint32_t conf52: 8; + uint32_t conf53: 8; + uint32_t conf54: 8; + uint32_t conf55: 8; + }; + uint32_t val; + } conf_w13; + union { + struct { + uint32_t conf56: 8; + uint32_t conf57: 8; + uint32_t conf58: 8; + uint32_t conf59: 8; + }; + uint32_t val; + } conf_w14; + union { + struct { + uint32_t conf60: 8; + uint32_t conf61: 8; + uint32_t conf62: 8; + uint32_t conf63: 8; + }; + uint32_t val; + } conf_w15; + uint32_t check_sum0; /**/ + uint32_t check_sum1; /**/ + union { + struct { + uint32_t token0: 12; + uint32_t rx_pf_valid: 1; + uint32_t reserved13: 3; + uint32_t reg_token1: 12; + uint32_t rx_pf_eof: 4; + }; + uint32_t val; + } slc1_token_rdata; + union { + struct { + uint32_t token0_wd: 12; + uint32_t reserved12: 4; + uint32_t token1_wd: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_token_wdata; + union { + struct { + uint32_t token0_wd: 12; + uint32_t reserved12: 4; + uint32_t token1_wd: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc1_token_wdata; + union { + struct { + uint32_t slc0_token0_dec: 1; + uint32_t slc0_token1_dec: 1; + uint32_t slc0_token0_wr: 1; + uint32_t slc0_token1_wr: 1; + uint32_t slc1_token0_dec: 1; + uint32_t slc1_token1_dec: 1; + uint32_t slc1_token0_wr: 1; + uint32_t slc1_token1_wr: 1; + uint32_t slc0_len_wr: 1; + uint32_t reserved9: 23; + }; + uint32_t val; + } token_con; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_clr; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t wifi_rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t bt_rx_new_packet: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc1_int_clr; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_func1_int_ena; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t wifi_rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t bt_rx_new_packet: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc1_func1_int_ena; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_func2_int_ena; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t wifi_rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t bt_rx_new_packet: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc1_func2_int_ena; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_ena; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t wifi_rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t bt_rx_new_packet: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc1_int_ena; + union { + struct { + uint32_t infor: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } slc0_rx_infor; + union { + struct { + uint32_t infor: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } slc1_rx_infor; + uint32_t slc0_len_wd; /**/ + uint32_t apbwin_wdata; /**/ + union { + struct { + uint32_t addr: 28; + uint32_t wr: 1; + uint32_t start: 1; + uint32_t reserved30: 2; + }; + uint32_t val; + } apbwin_conf; + uint32_t apbwin_rdata; /**/ + union { + struct { + uint32_t bit7_clraddr: 9; + uint32_t bit6_clraddr: 9; + uint32_t reserved18: 14; + }; + uint32_t val; + } slc0_rdclr; + union { + struct { + uint32_t bit7_clraddr: 9; + uint32_t bit6_clraddr: 9; + uint32_t reserved18: 14; + }; + uint32_t val; + } slc1_rdclr; + union { + struct { + uint32_t tohost_bit01: 1; + uint32_t tohost_bit11: 1; + uint32_t tohost_bit21: 1; + uint32_t tohost_bit31: 1; + uint32_t tohost_bit41: 1; + uint32_t tohost_bit51: 1; + uint32_t tohost_bit61: 1; + uint32_t tohost_bit71: 1; + uint32_t token0_1to01: 1; + uint32_t token1_1to01: 1; + uint32_t token0_0to11: 1; + uint32_t token1_0to11: 1; + uint32_t rx_sof1: 1; + uint32_t rx_eof1: 1; + uint32_t rx_start1: 1; + uint32_t tx_start1: 1; + uint32_t rx_udf1: 1; + uint32_t tx_ovf1: 1; + uint32_t rx_pf_valid1: 1; + uint32_t ext_bit01: 1; + uint32_t ext_bit11: 1; + uint32_t ext_bit21: 1; + uint32_t ext_bit31: 1; + uint32_t rx_new_packet1: 1; + uint32_t rd_retry1: 1; + uint32_t gpio_sdio1: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_ena1; + union { + struct { + uint32_t tohost_bit01: 1; + uint32_t tohost_bit11: 1; + uint32_t tohost_bit21: 1; + uint32_t tohost_bit31: 1; + uint32_t tohost_bit41: 1; + uint32_t tohost_bit51: 1; + uint32_t tohost_bit61: 1; + uint32_t tohost_bit71: 1; + uint32_t token0_1to01: 1; + uint32_t token1_1to01: 1; + uint32_t token0_0to11: 1; + uint32_t token1_0to11: 1; + uint32_t rx_sof1: 1; + uint32_t rx_eof1: 1; + uint32_t rx_start1: 1; + uint32_t tx_start1: 1; + uint32_t rx_udf1: 1; + uint32_t tx_ovf1: 1; + uint32_t rx_pf_valid1: 1; + uint32_t ext_bit01: 1; + uint32_t ext_bit11: 1; + uint32_t ext_bit21: 1; + uint32_t ext_bit31: 1; + uint32_t wifi_rx_new_packet1: 1; + uint32_t rd_retry1: 1; + uint32_t bt_rx_new_packet1: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc1_int_ena1; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t date; /**/ + uint32_t id; /**/ + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + union { + struct { + uint32_t frc_sdio11: 5; + uint32_t frc_sdio20: 5; + uint32_t frc_neg_samp: 5; + uint32_t frc_pos_samp: 5; + uint32_t frc_quick_in: 5; + uint32_t sdio20_int_delay: 1; + uint32_t sdio_pad_pullup: 1; + uint32_t hspeed_con_en: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } conf; + union { + struct { + uint32_t sdio20_mode: 5; + uint32_t sdio_neg_samp: 5; + uint32_t sdio_quick_in: 5; + uint32_t reserved15: 17; + }; + uint32_t val; + } inf_st; +} host_dev_t; +extern host_dev_t HOST; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_HOST_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/hwcrypto_reg.h b/tools/sdk/include/soc/include/soc/hwcrypto_reg.h new file mode 100644 index 00000000000..d0dfa748589 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/hwcrypto_reg.h @@ -0,0 +1,68 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __HWCRYPTO_REG_H__ +#define __HWCRYPTO_REG_H__ + +#include "soc.h" + +/* registers for RSA acceleration via Multiple Precision Integer ops */ +#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) +/* RB & Z use the same memory block, depending on phase of operation */ +#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) +#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) +#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400) +#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600) + +#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800) +#define RSA_MODEXP_MODE_REG (DR_REG_RSA_BASE + 0x804) +#define RSA_START_MODEXP_REG (DR_REG_RSA_BASE + 0x808) +#define RSA_MULT_MODE_REG (DR_REG_RSA_BASE + 0x80c) +#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x810) + +#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x814) + +#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x818) + +/* SHA acceleration registers */ +#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x00) + +#define SHA_1_START_REG ((DR_REG_SHA_BASE) + 0x80) +#define SHA_1_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x84) +#define SHA_1_LOAD_REG ((DR_REG_SHA_BASE) + 0x88) +#define SHA_1_BUSY_REG ((DR_REG_SHA_BASE) + 0x8c) + +#define SHA_256_START_REG ((DR_REG_SHA_BASE) + 0x90) +#define SHA_256_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x94) +#define SHA_256_LOAD_REG ((DR_REG_SHA_BASE) + 0x98) +#define SHA_256_BUSY_REG ((DR_REG_SHA_BASE) + 0x9c) + +#define SHA_384_START_REG ((DR_REG_SHA_BASE) + 0xa0) +#define SHA_384_CONTINUE_REG ((DR_REG_SHA_BASE) + 0xa4) +#define SHA_384_LOAD_REG ((DR_REG_SHA_BASE) + 0xa8) +#define SHA_384_BUSY_REG ((DR_REG_SHA_BASE) + 0xac) + +#define SHA_512_START_REG ((DR_REG_SHA_BASE) + 0xb0) +#define SHA_512_CONTINUE_REG ((DR_REG_SHA_BASE) + 0xb4) +#define SHA_512_LOAD_REG ((DR_REG_SHA_BASE) + 0xb8) +#define SHA_512_BUSY_REG ((DR_REG_SHA_BASE) + 0xbc) + +/* AES acceleration registers */ +#define AES_START_REG ((DR_REG_AES_BASE) + 0x00) +#define AES_IDLE_REG ((DR_REG_AES_BASE) + 0x04) +#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x08) +#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x10) +#define AES_TEXT_BASE ((DR_REG_AES_BASE) + 0x30) +#define AES_ENDIAN ((DR_REG_AES_BASE) + 0x40) + +#endif diff --git a/tools/sdk/include/soc/include/soc/i2c_reg.h b/tools/sdk/include/soc/include/soc/i2c_reg.h new file mode 100644 index 00000000000..292695eb7f3 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/i2c_reg.h @@ -0,0 +1,951 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_REG_H_ +#define _SOC_I2C_REG_H_ + + +#include "soc.h" + +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) + +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) +/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the low level width of SCL clock.*/ +#define I2C_SCL_LOW_PERIOD 0x00003FFF +#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) +#define I2C_SCL_LOW_PERIOD_V 0x3FFF +#define I2C_SCL_LOW_PERIOD_S 0 + +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004) +/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the clock gating control bit for reading or writing registers.*/ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (BIT(8)) +#define I2C_CLK_EN_V 0x1 +#define I2C_CLK_EN_S 8 +/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: This bit is used to control the storage mode for received datas. + 1: receive data from most significant bit 0: receive data from least significant bit*/ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (BIT(7)) +#define I2C_RX_LSB_FIRST_V 0x1 +#define I2C_RX_LSB_FIRST_S 7 +/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This bit is used to control the sending mode for data need to + be send. 1: receive data from most significant bit 0: receive data from least significant bit*/ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (BIT(6)) +#define I2C_TX_LSB_FIRST_V 0x1 +#define I2C_TX_LSB_FIRST_S 6 +/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to start sending data in txfifo.*/ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (BIT(5)) +#define I2C_TRANS_START_V 0x1 +#define I2C_TRANS_START_S 5 +/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to configure the module as i2c master clear this + bit to configure the module as i2c slave.*/ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (BIT(4)) +#define I2C_MS_MODE_V 0x1 +#define I2C_MS_MODE_S 4 +/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to sample data in SCL low level. clear this bit + to sample data in SCL high level.*/ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_V 0x1 +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: 1: normally ouput scl clock 0: exchange the function of scl_o + and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (BIT(1)) +#define I2C_SCL_FORCE_OUT_V 0x1 +#define I2C_SCL_FORCE_OUT_S 1 +/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: normally ouput sda data 0: exchange the function of sda_o + and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (BIT(0)) +#define I2C_SDA_FORCE_OUT_V 0x1 +#define I2C_SDA_FORCE_OUT_S 0 + +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) +/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: This register stores the value of state machine to produce SCL. + 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ +#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) +#define I2C_SCL_STATE_LAST_V 0x7 +#define I2C_SCL_STATE_LAST_S 28 +/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: This register stores the value of state machine for i2c module. + 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) +#define I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ +/*description: This register stores the amount of received data in ram.*/ +#define I2C_TXFIFO_CNT 0x0000003F +#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) +#define I2C_TXFIFO_CNT_V 0x3F +#define I2C_TXFIFO_CNT_S 18 +/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ +/*description: This register represent the amount of data need to send.*/ +#define I2C_RXFIFO_CNT 0x0000003F +#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) +#define I2C_RXFIFO_CNT_V 0x3F +#define I2C_RXFIFO_CNT_S 8 +/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This register changes to high level when one byte is transferred.*/ +#define I2C_BYTE_TRANS (BIT(6)) +#define I2C_BYTE_TRANS_M (BIT(6)) +#define I2C_BYTE_TRANS_V 0x1 +#define I2C_BYTE_TRANS_S 6 +/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: when configured as i2c slave and the address send by master + is equal to slave's address then this bit will be high level.*/ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (BIT(5)) +#define I2C_SLAVE_ADDRESSED_V 0x1 +#define I2C_SLAVE_ADDRESSED_S 5 +/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (BIT(4)) +#define I2C_BUS_BUSY_V 0x1 +#define I2C_BUS_BUSY_S 4 +/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: when I2C lost control of SDA line this register changes to high level.*/ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (BIT(3)) +#define I2C_ARB_LOST_V 0x1 +#define I2C_ARB_LOST_S 3 +/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: when I2C takes more than time_out_reg clocks to receive a data + then this register changes to high level.*/ +#define I2C_TIME_OUT (BIT(2)) +#define I2C_TIME_OUT_M (BIT(2)) +#define I2C_TIME_OUT_V 0x1 +#define I2C_TIME_OUT_S 2 +/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when in slave mode 1: master read slave 0: master write slave.*/ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (BIT(1)) +#define I2C_SLAVE_RW_V 0x1 +#define I2C_SLAVE_RW_S 1 +/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This register stores the value of ACK bit.*/ +#define I2C_ACK_REC (BIT(0)) +#define I2C_ACK_REC_M (BIT(0)) +#define I2C_ACK_REC_V 0x1 +#define I2C_ACK_REC_S 0 + +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) +/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: This register is used to configure the max clock number of receiving a data.*/ +#define I2C_TIME_OUT_REG 0x000FFFFF +#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) +#define I2C_TIME_OUT_REG_V 0xFFFFF +#define I2C_TIME_OUT_REG_S 0 + +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) +/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: This register is used to enable slave 10bit address mode.*/ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (BIT(31)) +#define I2C_ADDR_10BIT_EN_V 0x1 +#define I2C_ADDR_10BIT_EN_S 31 +/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: when configured as i2c slave this register is used to configure + slave's address.*/ +#define I2C_SLAVE_ADDR 0x00007FFF +#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) +#define I2C_SLAVE_ADDR_V 0x7FFF +#define I2C_SLAVE_ADDR_S 0 + +#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) +/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: This is the offset address of the last sending data as described + in nonfifo_tx_thres register.*/ +#define I2C_TXFIFO_END_ADDR 0x0000001F +#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S)) +#define I2C_TXFIFO_END_ADDR_V 0x1F +#define I2C_TXFIFO_END_ADDR_S 15 +/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: This is the offset address of the first sending data as described + in nonfifo_tx_thres register.*/ +#define I2C_TXFIFO_START_ADDR 0x0000001F +#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S)) +#define I2C_TXFIFO_START_ADDR_V 0x1F +#define I2C_TXFIFO_START_ADDR_S 10 +/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: This is the offset address of the first receiving data as described + in nonfifo_rx_thres_register.*/ +#define I2C_RXFIFO_END_ADDR 0x0000001F +#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S)) +#define I2C_RXFIFO_END_ADDR_V 0x1F +#define I2C_RXFIFO_END_ADDR_S 5 +/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: This is the offset address of the last receiving data as described + in nonfifo_rx_thres_register.*/ +#define I2C_RXFIFO_START_ADDR 0x0000001F +#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S)) +#define I2C_RXFIFO_START_ADDR_V 0x1F +#define I2C_RXFIFO_START_ADDR_S 0 + +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) +/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ +/*description: when I2C sends more than nonfifo_tx_thres data it will produce + tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ +#define I2C_NONFIFO_TX_THRES 0x0000003F +#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S)) +#define I2C_NONFIFO_TX_THRES_V 0x3F +#define I2C_NONFIFO_TX_THRES_S 20 +/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */ +/*description: when I2C receives more than nonfifo_rx_thres data it will produce + rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ +#define I2C_NONFIFO_RX_THRES 0x0000003F +#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S)) +#define I2C_NONFIFO_RX_THRES_V 0x3F +#define I2C_NONFIFO_RX_THRES_S 14 +/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to reset tx fifo when using apb fifo access.*/ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (BIT(13)) +#define I2C_TX_FIFO_RST_V 0x1 +#define I2C_TX_FIFO_RST_S 13 +/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to reset rx fifo when using apb fifo access.*/ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (BIT(12)) +#define I2C_RX_FIFO_RST_V 0x1 +#define I2C_RX_FIFO_RST_S 12 +/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: When this bit is set to 1 then the byte after address represent + the offset address of I2C Slave's ram.*/ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_V 0x1 +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to enble apb nonfifo access.*/ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (BIT(10)) +#define I2C_NONFIFO_EN_V 0x1 +#define I2C_NONFIFO_EN_S 10 +/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ +/*description: Config txfifo empty threhd value when using apb fifo access*/ +#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F +#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S)) +#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F +#define I2C_TXFIFO_EMPTY_THRHD_S 5 +/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ +/*description: */ +#define I2C_RXFIFO_FULL_THRHD 0x0000001F +#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S)) +#define I2C_RXFIFO_FULL_THRHD_V 0x1F +#define I2C_RXFIFO_FULL_THRHD_S 0 + +#define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c) + +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) +/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: The register represent the byte data read from rxfifo when use apb fifo access*/ +#define I2C_FIFO_RDATA 0x000000FF +#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) +#define I2C_FIFO_RDATA_V 0xFF +#define I2C_FIFO_RDATA_S 0 + +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) +/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when + I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ +#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_RAW_S 12 +/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when + I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_RAW (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_V 0x1 +#define I2C_RX_REC_FULL_INT_RAW_S 11 +/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for ack_err_int interrupt. when + I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ +#define I2C_ACK_ERR_INT_RAW (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_M (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_V 0x1 +#define I2C_ACK_ERR_INT_RAW_S 10 +/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for trans_start_int interrupt. when + I2C sends the START bit it will produce trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (BIT(9)) +#define I2C_TRANS_START_INT_RAW_V 0x1 +#define I2C_TRANS_START_INT_RAW_S 9 +/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for time_out_int interrupt. when + I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_V 0x1 +#define I2C_TIME_OUT_INT_RAW_S 8 +/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for trans_complete_int interrupt. + when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for master_tra_comp_int interrupt. + when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 +/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when + I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for slave_tran_comp_int interrupt. + when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 +/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for end_detect_int interrupt. when + I2C deals with the END command it will produce end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (BIT(3)) +#define I2C_END_DETECT_INT_RAW_V 0x1 +#define I2C_END_DETECT_INT_RAW_S 3 +/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for receiving data overflow when + use apb fifo access.*/ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/ +#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_RAW_S 1 +/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/ +#define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_V 0x1 +#define I2C_RXFIFO_FULL_INT_RAW_S 0 + +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) +/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_CLR_S 12 +/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_CLR (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_V 0x1 +#define I2C_RX_REC_FULL_INT_CLR_S 11 +/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_CLR (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_M (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_V 0x1 +#define I2C_ACK_ERR_INT_CLR_S 10 +/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (BIT(9)) +#define I2C_TRANS_START_INT_CLR_V 0x1 +#define I2C_TRANS_START_INT_CLR_S 9 +/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_V 0x1 +#define I2C_TIME_OUT_INT_CLR_S 8 +/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the master_tran_comp interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 +/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 +/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (BIT(3)) +#define I2C_END_DETECT_INT_CLR_V 0x1 +#define I2C_END_DETECT_INT_CLR_S 3 +/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_CLR_S 1 +/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_V 0x1 +#define I2C_RXFIFO_FULL_INT_CLR_S 0 + +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) +/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The enable bit for tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ENA_S 12 +/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The enable bit for rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_ENA (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_V 0x1 +#define I2C_RX_REC_FULL_INT_ENA_S 11 +/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_ENA (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_M (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_V 0x1 +#define I2C_ACK_ERR_INT_ENA_S 10 +/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (BIT(9)) +#define I2C_TRANS_START_INT_ENA_V 0x1 +#define I2C_TRANS_START_INT_ENA_S 9 +/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_V 0x1 +#define I2C_TIME_OUT_INT_ENA_S 8 +/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 +/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 +/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (BIT(3)) +#define I2C_END_DETECT_INT_ENA_V 0x1 +#define I2C_END_DETECT_INT_ENA_S 3 +/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ENA_S 1 +/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_V 0x1 +#define I2C_RXFIFO_FULL_INT_ENA_S 0 + +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) +/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The masked interrupt status for tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ST_S 12 +/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_ST (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_V 0x1 +#define I2C_RX_REC_FULL_INT_ST_S 11 +/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The masked interrupt status for ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_ST (BIT(10)) +#define I2C_ACK_ERR_INT_ST_M (BIT(10)) +#define I2C_ACK_ERR_INT_ST_V 0x1 +#define I2C_ACK_ERR_INT_ST_S 10 +/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The masked interrupt status for trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (BIT(9)) +#define I2C_TRANS_START_INT_ST_V 0x1 +#define I2C_TRANS_START_INT_ST_S 9 +/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The masked interrupt status for time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (BIT(8)) +#define I2C_TIME_OUT_INT_ST_V 0x1 +#define I2C_TIME_OUT_INT_ST_S 8 +/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The masked interrupt status for trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The masked interrupt status for master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ST_S 6 +/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The masked interrupt status for arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 +/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The masked interrupt status for end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (BIT(3)) +#define I2C_END_DETECT_INT_ST_V 0x1 +#define I2C_END_DETECT_INT_ST_S 3 +/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_V 0x1 +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The masked interrupt status for txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ST_S 1 +/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_ST (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_V 0x1 +#define I2C_RXFIFO_FULL_INT_ST_S 0 + +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) +/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num I2C used to + hold the data after the negedge of SCL.*/ +#define I2C_SDA_HOLD_TIME 0x000003FF +#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) +#define I2C_SDA_HOLD_TIME_V 0x3FF +#define I2C_SDA_HOLD_TIME_S 0 + +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) +/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num I2C used to + sample data on SDA after the posedge of SCL*/ +#define I2C_SDA_SAMPLE_TIME 0x000003FF +#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) +#define I2C_SDA_SAMPLE_TIME_V 0x3FF +#define I2C_SDA_SAMPLE_TIME_S 0 + +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038) +/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the clock num during SCL is low level.*/ +#define I2C_SCL_HIGH_PERIOD 0x00003FFF +#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) +#define I2C_SCL_HIGH_PERIOD_V 0x3FFF +#define I2C_SCL_HIGH_PERIOD_S 0 + +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) +/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: This register is used to configure the clock num between the + negedge of SDA and negedge of SCL for start mark.*/ +#define I2C_SCL_START_HOLD_TIME 0x000003FF +#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) +#define I2C_SCL_START_HOLD_TIME_V 0x3FF +#define I2C_SCL_START_HOLD_TIME_S 0 + +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) +/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: This register is used to configure the clock num between the + posedge of SCL and the negedge of SDA for restart mark.*/ +#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF +#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) +/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the clock num after the STOP bit's posedge.*/ +#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF +#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) +#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) +/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num between the + posedge of SCL and the posedge of SDA.*/ +#define I2C_SCL_STOP_SETUP_TIME 0x000003FF +#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) +#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: This is the filter enable bit for SCL.*/ +#define I2C_SCL_FILTER_EN (BIT(3)) +#define I2C_SCL_FILTER_EN_M (BIT(3)) +#define I2C_SCL_FILTER_EN_V 0x1 +#define I2C_SCL_FILTER_EN_S 3 +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: When input SCL's pulse width is smaller than this register value + I2C ignores this pulse.*/ +#define I2C_SCL_FILTER_THRES 0x00000007 +#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) +#define I2C_SCL_FILTER_THRES_V 0x7 +#define I2C_SCL_FILTER_THRES_S 0 + +#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: This is the filter enable bit for SDA.*/ +#define I2C_SDA_FILTER_EN (BIT(3)) +#define I2C_SDA_FILTER_EN_M (BIT(3)) +#define I2C_SDA_FILTER_EN_V 0x1 +#define I2C_SDA_FILTER_EN_S 3 +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: When input SCL's pulse width is smaller than this register value + I2C ignores this pulse.*/ +#define I2C_SDA_FILTER_THRES 0x00000007 +#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) +#define I2C_SDA_FILTER_THRES_V 0x7 +#define I2C_SDA_FILTER_THRES_S 0 + +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) +/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command0 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (BIT(31)) +#define I2C_COMMAND0_DONE_V 0x1 +#define I2C_COMMAND0_DONE_S 31 +/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command0. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND0 0x00003FFF +#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) +#define I2C_COMMAND0_V 0x3FFF +#define I2C_COMMAND0_S 0 + +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) +/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command1 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (BIT(31)) +#define I2C_COMMAND1_DONE_V 0x1 +#define I2C_COMMAND1_DONE_S 31 +/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command1. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND1 0x00003FFF +#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) +#define I2C_COMMAND1_V 0x3FFF +#define I2C_COMMAND1_S 0 + +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) +/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command2 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (BIT(31)) +#define I2C_COMMAND2_DONE_V 0x1 +#define I2C_COMMAND2_DONE_S 31 +/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command2. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND2 0x00003FFF +#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) +#define I2C_COMMAND2_V 0x3FFF +#define I2C_COMMAND2_S 0 + +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) +/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command3 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (BIT(31)) +#define I2C_COMMAND3_DONE_V 0x1 +#define I2C_COMMAND3_DONE_S 31 +/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command3. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND3 0x00003FFF +#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) +#define I2C_COMMAND3_V 0x3FFF +#define I2C_COMMAND3_S 0 + +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) +/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command4 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (BIT(31)) +#define I2C_COMMAND4_DONE_V 0x1 +#define I2C_COMMAND4_DONE_S 31 +/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command4. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND4 0x00003FFF +#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) +#define I2C_COMMAND4_V 0x3FFF +#define I2C_COMMAND4_S 0 + +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) +/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command5 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (BIT(31)) +#define I2C_COMMAND5_DONE_V 0x1 +#define I2C_COMMAND5_DONE_S 31 +/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command5. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND5 0x00003FFF +#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) +#define I2C_COMMAND5_V 0x3FFF +#define I2C_COMMAND5_S 0 + +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) +/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command6 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (BIT(31)) +#define I2C_COMMAND6_DONE_V 0x1 +#define I2C_COMMAND6_DONE_S 31 +/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command6. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND6 0x00003FFF +#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) +#define I2C_COMMAND6_V 0x3FFF +#define I2C_COMMAND6_S 0 + +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) +/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command7 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (BIT(31)) +#define I2C_COMMAND7_DONE_V 0x1 +#define I2C_COMMAND7_DONE_S 31 +/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command7. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND7 0x00003FFF +#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) +#define I2C_COMMAND7_V 0x3FFF +#define I2C_COMMAND7_S 0 + +#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078) +/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command8 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND8_DONE (BIT(31)) +#define I2C_COMMAND8_DONE_M (BIT(31)) +#define I2C_COMMAND8_DONE_V 0x1 +#define I2C_COMMAND8_DONE_S 31 +/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command8. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND8 0x00003FFF +#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S)) +#define I2C_COMMAND8_V 0x3FFF +#define I2C_COMMAND8_S 0 + +#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C) +/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command9 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND9_DONE (BIT(31)) +#define I2C_COMMAND9_DONE_M (BIT(31)) +#define I2C_COMMAND9_DONE_V 0x1 +#define I2C_COMMAND9_DONE_S 31 +/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command9. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND9 0x00003FFF +#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S)) +#define I2C_COMMAND9_V 0x3FFF +#define I2C_COMMAND9_S 0 + +#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080) +/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command10 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND10_DONE (BIT(31)) +#define I2C_COMMAND10_DONE_M (BIT(31)) +#define I2C_COMMAND10_DONE_V 0x1 +#define I2C_COMMAND10_DONE_S 31 +/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command10. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND10 0x00003FFF +#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S)) +#define I2C_COMMAND10_V 0x3FFF +#define I2C_COMMAND10_S 0 + +#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084) +/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command11 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND11_DONE (BIT(31)) +#define I2C_COMMAND11_DONE_M (BIT(31)) +#define I2C_COMMAND11_DONE_V 0x1 +#define I2C_COMMAND11_DONE_S 31 +/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command11. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND11 0x00003FFF +#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S)) +#define I2C_COMMAND11_V 0x3FFF +#define I2C_COMMAND11_S 0 + +#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088) +/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command12 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND12_DONE (BIT(31)) +#define I2C_COMMAND12_DONE_M (BIT(31)) +#define I2C_COMMAND12_DONE_V 0x1 +#define I2C_COMMAND12_DONE_S 31 +/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command12. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND12 0x00003FFF +#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S)) +#define I2C_COMMAND12_V 0x3FFF +#define I2C_COMMAND12_S 0 + +#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C) +/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command13 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND13_DONE (BIT(31)) +#define I2C_COMMAND13_DONE_M (BIT(31)) +#define I2C_COMMAND13_DONE_V 0x1 +#define I2C_COMMAND13_DONE_S 31 +/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command13. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND13 0x00003FFF +#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S)) +#define I2C_COMMAND13_V 0x3FFF +#define I2C_COMMAND13_S 0 + +#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090) +/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command14 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND14_DONE (BIT(31)) +#define I2C_COMMAND14_DONE_M (BIT(31)) +#define I2C_COMMAND14_DONE_V 0x1 +#define I2C_COMMAND14_DONE_S 31 +/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command14. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND14 0x00003FFF +#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S)) +#define I2C_COMMAND14_V 0x3FFF +#define I2C_COMMAND14_S 0 + +#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094) +/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command15 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND15_DONE (BIT(31)) +#define I2C_COMMAND15_DONE_M (BIT(31)) +#define I2C_COMMAND15_DONE_V 0x1 +#define I2C_COMMAND15_DONE_S 31 +/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command15. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND15 0x00003FFF +#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S)) +#define I2C_COMMAND15_V 0x3FFF +#define I2C_COMMAND15_S 0 + +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ +/*description: */ +#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) +#define I2C_DATE_V 0xFFFFFFFF +#define I2C_DATE_S 0 + +#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) + + + + +#endif /*_SOC_I2C_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/i2c_struct.h b/tools/sdk/include/soc/include/soc/i2c_struct.h new file mode 100644 index 00000000000..c60bb1e7c18 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/i2c_struct.h @@ -0,0 +1,301 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_STRUCT_H_ +#define _SOC_I2C_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t period:14; /*This register is used to configure the low level width of SCL clock.*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } scl_low_period; + union { + struct { + uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ + uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ + uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/ + uint32_t reserved3: 1; + uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/ + uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/ + uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/ + uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/ + uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } ctr; + union { + struct { + uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ + uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ + uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ + uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ + uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ + uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ + uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ + uint32_t reserved7: 1; + uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ + uint32_t reserved14: 4; + uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ + uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ + uint32_t reserved27: 1; + uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } status_reg; + union { + struct { + uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data, unit: APB clock cycle.*/ + uint32_t reserved20:12; + }; + uint32_t val; + } timeout; + union { + struct { + uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/ + uint32_t reserved15: 16; + uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/ + }; + uint32_t val; + } slave_addr; + union { + struct { + uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ + uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } fifo_st; + union { + struct { + uint32_t rx_fifo_full_thrhd: 5; + uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/ + uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/ + uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/ + uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/ + uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/ + uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ + uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ + uint32_t reserved26: 6; + }; + uint32_t val; + } fifo_conf; + union { + struct { + uint8_t data; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ + uint8_t reserved[3]; + }; + uint32_t val; + } fifo_data; + union { + struct { + uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/ + uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/ + uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/ + uint32_t end_detect: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ + uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ + uint32_t trans_start: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ + uint32_t rx_rec_full: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect: 1; /*Set this bit to clear the end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*Set this bit to clear the master_tran_comp interrupt.*/ + uint32_t trans_complete: 1; /*Set this bit to clear the trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/ + uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.*/ + uint32_t rx_rec_full: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect: 1; /*The enable bit for end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.*/ + uint32_t trans_complete: 1; /*The enable bit for trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*The enable bit for time_out_int interrupt.*/ + uint32_t trans_start: 1; /*The enable bit for trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*The enable bit for ack_err_int interrupt.*/ + uint32_t rx_rec_full: 1; /*The enable bit for rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*The enable bit for tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect: 1; /*The masked interrupt status for end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/ + uint32_t trans_complete: 1; /*The masked interrupt status for trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*The masked interrupt status for time_out_int interrupt.*/ + uint32_t trans_start: 1; /*The masked interrupt status for trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/ + uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } int_status; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sda_hold; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sda_sample; + union { + struct { + uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } scl_high_period; + uint32_t reserved_3c; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } scl_start_hold; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } scl_rstart_setup; + union { + struct { + uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } scl_stop_hold; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } scl_stop_setup; + union { + struct { + uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + uint32_t en: 1; /*This is the filter enable bit for SCL.*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } scl_filter_cfg; + union { + struct { + uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + uint32_t en: 1; /*This is the filter enable bit for SDA.*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } sda_filter_cfg; + union { + struct { + uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + uint32_t reserved14: 17; + uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + }; + uint32_t val; + } command[16]; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t date; /**/ + uint32_t reserved_fc; + uint32_t ram_data[32]; /*This the start address for ram when use apb nonfifo access.*/ +} i2c_dev_t; +extern i2c_dev_t I2C0; +extern i2c_dev_t I2C1; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_I2C_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/i2s_reg.h b/tools/sdk/include/soc/include/soc/i2s_reg.h new file mode 100644 index 00000000000..3473c087cae --- /dev/null +++ b/tools/sdk/include/soc/include/soc/i2s_reg.h @@ -0,0 +1,1527 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2S_REG_H_ +#define _SOC_I2S_REG_H_ + +#include "soc.h" + +#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000)) + + +#define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008) +/* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define I2S_SIG_LOOPBACK (BIT(18)) +#define I2S_SIG_LOOPBACK_M (BIT(18)) +#define I2S_SIG_LOOPBACK_V 0x1 +#define I2S_SIG_LOOPBACK_S 18 +/* I2S_RX_MSB_RIGHT : R/W ;bitpos:[17] ;default: 1'b1 ; */ +/*description: */ +#define I2S_RX_MSB_RIGHT (BIT(17)) +#define I2S_RX_MSB_RIGHT_M (BIT(17)) +#define I2S_RX_MSB_RIGHT_V 0x1 +#define I2S_RX_MSB_RIGHT_S 17 +/* I2S_TX_MSB_RIGHT : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define I2S_TX_MSB_RIGHT (BIT(16)) +#define I2S_TX_MSB_RIGHT_M (BIT(16)) +#define I2S_TX_MSB_RIGHT_V 0x1 +#define I2S_TX_MSB_RIGHT_S 16 +/* I2S_RX_MONO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_MONO (BIT(15)) +#define I2S_RX_MONO_M (BIT(15)) +#define I2S_RX_MONO_V 0x1 +#define I2S_RX_MONO_S 15 +/* I2S_TX_MONO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_MONO (BIT(14)) +#define I2S_TX_MONO_M (BIT(14)) +#define I2S_TX_MONO_V 0x1 +#define I2S_TX_MONO_S 14 +/* I2S_RX_SHORT_SYNC : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_SHORT_SYNC (BIT(13)) +#define I2S_RX_SHORT_SYNC_M (BIT(13)) +#define I2S_RX_SHORT_SYNC_V 0x1 +#define I2S_RX_SHORT_SYNC_S 13 +/* I2S_TX_SHORT_SYNC : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_SHORT_SYNC (BIT(12)) +#define I2S_TX_SHORT_SYNC_M (BIT(12)) +#define I2S_TX_SHORT_SYNC_V 0x1 +#define I2S_TX_SHORT_SYNC_S 12 +/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_MSB_SHIFT (BIT(11)) +#define I2S_RX_MSB_SHIFT_M (BIT(11)) +#define I2S_RX_MSB_SHIFT_V 0x1 +#define I2S_RX_MSB_SHIFT_S 11 +/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_MSB_SHIFT (BIT(10)) +#define I2S_TX_MSB_SHIFT_M (BIT(10)) +#define I2S_TX_MSB_SHIFT_V 0x1 +#define I2S_TX_MSB_SHIFT_S 10 +/* I2S_RX_RIGHT_FIRST : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define I2S_RX_RIGHT_FIRST (BIT(9)) +#define I2S_RX_RIGHT_FIRST_M (BIT(9)) +#define I2S_RX_RIGHT_FIRST_V 0x1 +#define I2S_RX_RIGHT_FIRST_S 9 +/* I2S_TX_RIGHT_FIRST : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define I2S_TX_RIGHT_FIRST (BIT(8)) +#define I2S_TX_RIGHT_FIRST_M (BIT(8)) +#define I2S_TX_RIGHT_FIRST_V 0x1 +#define I2S_TX_RIGHT_FIRST_S 8 +/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_SLAVE_MOD (BIT(7)) +#define I2S_RX_SLAVE_MOD_M (BIT(7)) +#define I2S_RX_SLAVE_MOD_V 0x1 +#define I2S_RX_SLAVE_MOD_S 7 +/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_SLAVE_MOD (BIT(6)) +#define I2S_TX_SLAVE_MOD_M (BIT(6)) +#define I2S_TX_SLAVE_MOD_V 0x1 +#define I2S_TX_SLAVE_MOD_S 6 +/* I2S_RX_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_START (BIT(5)) +#define I2S_RX_START_M (BIT(5)) +#define I2S_RX_START_V 0x1 +#define I2S_RX_START_S 5 +/* I2S_TX_START : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_START (BIT(4)) +#define I2S_TX_START_M (BIT(4)) +#define I2S_TX_START_V 0x1 +#define I2S_TX_START_S 4 +/* I2S_RX_FIFO_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_FIFO_RESET (BIT(3)) +#define I2S_RX_FIFO_RESET_M (BIT(3)) +#define I2S_RX_FIFO_RESET_V 0x1 +#define I2S_RX_FIFO_RESET_S 3 +/* I2S_TX_FIFO_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_FIFO_RESET (BIT(2)) +#define I2S_TX_FIFO_RESET_M (BIT(2)) +#define I2S_TX_FIFO_RESET_V 0x1 +#define I2S_TX_FIFO_RESET_S 2 +/* I2S_RX_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_RESET (BIT(1)) +#define I2S_RX_RESET_M (BIT(1)) +#define I2S_RX_RESET_V 0x1 +#define I2S_RX_RESET_S 1 +/* I2S_TX_RESET : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (BIT(0)) +#define I2S_TX_RESET_V 0x1 +#define I2S_TX_RESET_S 0 + +#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) +/* I2S_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_RAW_M (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_RAW_V 0x1 +#define I2S_OUT_TOTAL_EOF_INT_RAW_S 16 +/* I2S_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_RAW_M (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_RAW_V 0x1 +#define I2S_IN_DSCR_EMPTY_INT_RAW_S 15 +/* I2S_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DSCR_ERR_INT_RAW (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_RAW_M (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_RAW_V 0x1 +#define I2S_OUT_DSCR_ERR_INT_RAW_S 14 +/* I2S_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_ERR_INT_RAW (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_RAW_M (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_RAW_V 0x1 +#define I2S_IN_DSCR_ERR_INT_RAW_S 13 +/* I2S_OUT_EOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_EOF_INT_RAW (BIT(12)) +#define I2S_OUT_EOF_INT_RAW_M (BIT(12)) +#define I2S_OUT_EOF_INT_RAW_V 0x1 +#define I2S_OUT_EOF_INT_RAW_S 12 +/* I2S_OUT_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DONE_INT_RAW (BIT(11)) +#define I2S_OUT_DONE_INT_RAW_M (BIT(11)) +#define I2S_OUT_DONE_INT_RAW_V 0x1 +#define I2S_OUT_DONE_INT_RAW_S 11 +/* I2S_IN_ERR_EOF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_ERR_EOF_INT_RAW (BIT(10)) +#define I2S_IN_ERR_EOF_INT_RAW_M (BIT(10)) +#define I2S_IN_ERR_EOF_INT_RAW_V 0x1 +#define I2S_IN_ERR_EOF_INT_RAW_S 10 +/* I2S_IN_SUC_EOF_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_INT_RAW (BIT(9)) +#define I2S_IN_SUC_EOF_INT_RAW_M (BIT(9)) +#define I2S_IN_SUC_EOF_INT_RAW_V 0x1 +#define I2S_IN_SUC_EOF_INT_RAW_S 9 +/* I2S_IN_DONE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DONE_INT_RAW (BIT(8)) +#define I2S_IN_DONE_INT_RAW_M (BIT(8)) +#define I2S_IN_DONE_INT_RAW_V 0x1 +#define I2S_IN_DONE_INT_RAW_S 8 +/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_HUNG_INT_RAW (BIT(7)) +#define I2S_TX_HUNG_INT_RAW_M (BIT(7)) +#define I2S_TX_HUNG_INT_RAW_V 0x1 +#define I2S_TX_HUNG_INT_RAW_S 7 +/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_HUNG_INT_RAW (BIT(6)) +#define I2S_RX_HUNG_INT_RAW_M (BIT(6)) +#define I2S_RX_HUNG_INT_RAW_V 0x1 +#define I2S_RX_HUNG_INT_RAW_S 6 +/* I2S_TX_REMPTY_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_REMPTY_INT_RAW (BIT(5)) +#define I2S_TX_REMPTY_INT_RAW_M (BIT(5)) +#define I2S_TX_REMPTY_INT_RAW_V 0x1 +#define I2S_TX_REMPTY_INT_RAW_S 5 +/* I2S_TX_WFULL_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_WFULL_INT_RAW (BIT(4)) +#define I2S_TX_WFULL_INT_RAW_M (BIT(4)) +#define I2S_TX_WFULL_INT_RAW_V 0x1 +#define I2S_TX_WFULL_INT_RAW_S 4 +/* I2S_RX_REMPTY_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_REMPTY_INT_RAW (BIT(3)) +#define I2S_RX_REMPTY_INT_RAW_M (BIT(3)) +#define I2S_RX_REMPTY_INT_RAW_V 0x1 +#define I2S_RX_REMPTY_INT_RAW_S 3 +/* I2S_RX_WFULL_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_WFULL_INT_RAW (BIT(2)) +#define I2S_RX_WFULL_INT_RAW_M (BIT(2)) +#define I2S_RX_WFULL_INT_RAW_V 0x1 +#define I2S_RX_WFULL_INT_RAW_S 2 +/* I2S_TX_PUT_DATA_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_PUT_DATA_INT_RAW (BIT(1)) +#define I2S_TX_PUT_DATA_INT_RAW_M (BIT(1)) +#define I2S_TX_PUT_DATA_INT_RAW_V 0x1 +#define I2S_TX_PUT_DATA_INT_RAW_S 1 +/* I2S_RX_TAKE_DATA_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_TAKE_DATA_INT_RAW (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_RAW_M (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_RAW_V 0x1 +#define I2S_RX_TAKE_DATA_INT_RAW_S 0 + +#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) +/* I2S_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_TOTAL_EOF_INT_ST (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ST_M (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ST_V 0x1 +#define I2S_OUT_TOTAL_EOF_INT_ST_S 16 +/* I2S_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_EMPTY_INT_ST (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ST_M (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ST_V 0x1 +#define I2S_IN_DSCR_EMPTY_INT_ST_S 15 +/* I2S_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DSCR_ERR_INT_ST (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ST_M (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ST_V 0x1 +#define I2S_OUT_DSCR_ERR_INT_ST_S 14 +/* I2S_IN_DSCR_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_ERR_INT_ST (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ST_M (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ST_V 0x1 +#define I2S_IN_DSCR_ERR_INT_ST_S 13 +/* I2S_OUT_EOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_EOF_INT_ST (BIT(12)) +#define I2S_OUT_EOF_INT_ST_M (BIT(12)) +#define I2S_OUT_EOF_INT_ST_V 0x1 +#define I2S_OUT_EOF_INT_ST_S 12 +/* I2S_OUT_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DONE_INT_ST (BIT(11)) +#define I2S_OUT_DONE_INT_ST_M (BIT(11)) +#define I2S_OUT_DONE_INT_ST_V 0x1 +#define I2S_OUT_DONE_INT_ST_S 11 +/* I2S_IN_ERR_EOF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_ERR_EOF_INT_ST (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ST_M (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ST_V 0x1 +#define I2S_IN_ERR_EOF_INT_ST_S 10 +/* I2S_IN_SUC_EOF_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_INT_ST (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ST_M (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ST_V 0x1 +#define I2S_IN_SUC_EOF_INT_ST_S 9 +/* I2S_IN_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DONE_INT_ST (BIT(8)) +#define I2S_IN_DONE_INT_ST_M (BIT(8)) +#define I2S_IN_DONE_INT_ST_V 0x1 +#define I2S_IN_DONE_INT_ST_S 8 +/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_HUNG_INT_ST (BIT(7)) +#define I2S_TX_HUNG_INT_ST_M (BIT(7)) +#define I2S_TX_HUNG_INT_ST_V 0x1 +#define I2S_TX_HUNG_INT_ST_S 7 +/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_HUNG_INT_ST (BIT(6)) +#define I2S_RX_HUNG_INT_ST_M (BIT(6)) +#define I2S_RX_HUNG_INT_ST_V 0x1 +#define I2S_RX_HUNG_INT_ST_S 6 +/* I2S_TX_REMPTY_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_REMPTY_INT_ST (BIT(5)) +#define I2S_TX_REMPTY_INT_ST_M (BIT(5)) +#define I2S_TX_REMPTY_INT_ST_V 0x1 +#define I2S_TX_REMPTY_INT_ST_S 5 +/* I2S_TX_WFULL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_WFULL_INT_ST (BIT(4)) +#define I2S_TX_WFULL_INT_ST_M (BIT(4)) +#define I2S_TX_WFULL_INT_ST_V 0x1 +#define I2S_TX_WFULL_INT_ST_S 4 +/* I2S_RX_REMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_REMPTY_INT_ST (BIT(3)) +#define I2S_RX_REMPTY_INT_ST_M (BIT(3)) +#define I2S_RX_REMPTY_INT_ST_V 0x1 +#define I2S_RX_REMPTY_INT_ST_S 3 +/* I2S_RX_WFULL_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_WFULL_INT_ST (BIT(2)) +#define I2S_RX_WFULL_INT_ST_M (BIT(2)) +#define I2S_RX_WFULL_INT_ST_V 0x1 +#define I2S_RX_WFULL_INT_ST_S 2 +/* I2S_TX_PUT_DATA_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_PUT_DATA_INT_ST (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ST_M (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ST_V 0x1 +#define I2S_TX_PUT_DATA_INT_ST_S 1 +/* I2S_RX_TAKE_DATA_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_TAKE_DATA_INT_ST (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ST_M (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ST_V 0x1 +#define I2S_RX_TAKE_DATA_INT_ST_S 0 + +#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) +/* I2S_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ENA_M (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ENA_V 0x1 +#define I2S_OUT_TOTAL_EOF_INT_ENA_S 16 +/* I2S_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ENA_M (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ENA_V 0x1 +#define I2S_IN_DSCR_EMPTY_INT_ENA_S 15 +/* I2S_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DSCR_ERR_INT_ENA (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ENA_M (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ENA_V 0x1 +#define I2S_OUT_DSCR_ERR_INT_ENA_S 14 +/* I2S_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_ERR_INT_ENA (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ENA_M (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ENA_V 0x1 +#define I2S_IN_DSCR_ERR_INT_ENA_S 13 +/* I2S_OUT_EOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_EOF_INT_ENA (BIT(12)) +#define I2S_OUT_EOF_INT_ENA_M (BIT(12)) +#define I2S_OUT_EOF_INT_ENA_V 0x1 +#define I2S_OUT_EOF_INT_ENA_S 12 +/* I2S_OUT_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DONE_INT_ENA (BIT(11)) +#define I2S_OUT_DONE_INT_ENA_M (BIT(11)) +#define I2S_OUT_DONE_INT_ENA_V 0x1 +#define I2S_OUT_DONE_INT_ENA_S 11 +/* I2S_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_ERR_EOF_INT_ENA (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ENA_M (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ENA_V 0x1 +#define I2S_IN_ERR_EOF_INT_ENA_S 10 +/* I2S_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_INT_ENA (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ENA_M (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ENA_V 0x1 +#define I2S_IN_SUC_EOF_INT_ENA_S 9 +/* I2S_IN_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DONE_INT_ENA (BIT(8)) +#define I2S_IN_DONE_INT_ENA_M (BIT(8)) +#define I2S_IN_DONE_INT_ENA_V 0x1 +#define I2S_IN_DONE_INT_ENA_S 8 +/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_HUNG_INT_ENA (BIT(7)) +#define I2S_TX_HUNG_INT_ENA_M (BIT(7)) +#define I2S_TX_HUNG_INT_ENA_V 0x1 +#define I2S_TX_HUNG_INT_ENA_S 7 +/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_HUNG_INT_ENA (BIT(6)) +#define I2S_RX_HUNG_INT_ENA_M (BIT(6)) +#define I2S_RX_HUNG_INT_ENA_V 0x1 +#define I2S_RX_HUNG_INT_ENA_S 6 +/* I2S_TX_REMPTY_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_REMPTY_INT_ENA (BIT(5)) +#define I2S_TX_REMPTY_INT_ENA_M (BIT(5)) +#define I2S_TX_REMPTY_INT_ENA_V 0x1 +#define I2S_TX_REMPTY_INT_ENA_S 5 +/* I2S_TX_WFULL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_WFULL_INT_ENA (BIT(4)) +#define I2S_TX_WFULL_INT_ENA_M (BIT(4)) +#define I2S_TX_WFULL_INT_ENA_V 0x1 +#define I2S_TX_WFULL_INT_ENA_S 4 +/* I2S_RX_REMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_REMPTY_INT_ENA (BIT(3)) +#define I2S_RX_REMPTY_INT_ENA_M (BIT(3)) +#define I2S_RX_REMPTY_INT_ENA_V 0x1 +#define I2S_RX_REMPTY_INT_ENA_S 3 +/* I2S_RX_WFULL_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_WFULL_INT_ENA (BIT(2)) +#define I2S_RX_WFULL_INT_ENA_M (BIT(2)) +#define I2S_RX_WFULL_INT_ENA_V 0x1 +#define I2S_RX_WFULL_INT_ENA_S 2 +/* I2S_TX_PUT_DATA_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_PUT_DATA_INT_ENA (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ENA_M (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ENA_V 0x1 +#define I2S_TX_PUT_DATA_INT_ENA_S 1 +/* I2S_RX_TAKE_DATA_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_TAKE_DATA_INT_ENA (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ENA_M (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ENA_V 0x1 +#define I2S_RX_TAKE_DATA_INT_ENA_S 0 + +#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) +/* I2S_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_CLR_M (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_CLR_V 0x1 +#define I2S_OUT_TOTAL_EOF_INT_CLR_S 16 +/* I2S_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_CLR_M (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_CLR_V 0x1 +#define I2S_IN_DSCR_EMPTY_INT_CLR_S 15 +/* I2S_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DSCR_ERR_INT_CLR (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_CLR_M (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_CLR_V 0x1 +#define I2S_OUT_DSCR_ERR_INT_CLR_S 14 +/* I2S_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_ERR_INT_CLR (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_CLR_M (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_CLR_V 0x1 +#define I2S_IN_DSCR_ERR_INT_CLR_S 13 +/* I2S_OUT_EOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_EOF_INT_CLR (BIT(12)) +#define I2S_OUT_EOF_INT_CLR_M (BIT(12)) +#define I2S_OUT_EOF_INT_CLR_V 0x1 +#define I2S_OUT_EOF_INT_CLR_S 12 +/* I2S_OUT_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DONE_INT_CLR (BIT(11)) +#define I2S_OUT_DONE_INT_CLR_M (BIT(11)) +#define I2S_OUT_DONE_INT_CLR_V 0x1 +#define I2S_OUT_DONE_INT_CLR_S 11 +/* I2S_IN_ERR_EOF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_ERR_EOF_INT_CLR (BIT(10)) +#define I2S_IN_ERR_EOF_INT_CLR_M (BIT(10)) +#define I2S_IN_ERR_EOF_INT_CLR_V 0x1 +#define I2S_IN_ERR_EOF_INT_CLR_S 10 +/* I2S_IN_SUC_EOF_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_INT_CLR (BIT(9)) +#define I2S_IN_SUC_EOF_INT_CLR_M (BIT(9)) +#define I2S_IN_SUC_EOF_INT_CLR_V 0x1 +#define I2S_IN_SUC_EOF_INT_CLR_S 9 +/* I2S_IN_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DONE_INT_CLR (BIT(8)) +#define I2S_IN_DONE_INT_CLR_M (BIT(8)) +#define I2S_IN_DONE_INT_CLR_V 0x1 +#define I2S_IN_DONE_INT_CLR_S 8 +/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_HUNG_INT_CLR (BIT(7)) +#define I2S_TX_HUNG_INT_CLR_M (BIT(7)) +#define I2S_TX_HUNG_INT_CLR_V 0x1 +#define I2S_TX_HUNG_INT_CLR_S 7 +/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_HUNG_INT_CLR (BIT(6)) +#define I2S_RX_HUNG_INT_CLR_M (BIT(6)) +#define I2S_RX_HUNG_INT_CLR_V 0x1 +#define I2S_RX_HUNG_INT_CLR_S 6 +/* I2S_TX_REMPTY_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_REMPTY_INT_CLR (BIT(5)) +#define I2S_TX_REMPTY_INT_CLR_M (BIT(5)) +#define I2S_TX_REMPTY_INT_CLR_V 0x1 +#define I2S_TX_REMPTY_INT_CLR_S 5 +/* I2S_TX_WFULL_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_WFULL_INT_CLR (BIT(4)) +#define I2S_TX_WFULL_INT_CLR_M (BIT(4)) +#define I2S_TX_WFULL_INT_CLR_V 0x1 +#define I2S_TX_WFULL_INT_CLR_S 4 +/* I2S_RX_REMPTY_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_REMPTY_INT_CLR (BIT(3)) +#define I2S_RX_REMPTY_INT_CLR_M (BIT(3)) +#define I2S_RX_REMPTY_INT_CLR_V 0x1 +#define I2S_RX_REMPTY_INT_CLR_S 3 +/* I2S_RX_WFULL_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_WFULL_INT_CLR (BIT(2)) +#define I2S_RX_WFULL_INT_CLR_M (BIT(2)) +#define I2S_RX_WFULL_INT_CLR_V 0x1 +#define I2S_RX_WFULL_INT_CLR_S 2 +/* I2S_PUT_DATA_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_PUT_DATA_INT_CLR (BIT(1)) +#define I2S_PUT_DATA_INT_CLR_M (BIT(1)) +#define I2S_PUT_DATA_INT_CLR_V 0x1 +#define I2S_PUT_DATA_INT_CLR_S 1 +/* I2S_TAKE_DATA_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TAKE_DATA_INT_CLR (BIT(0)) +#define I2S_TAKE_DATA_INT_CLR_M (BIT(0)) +#define I2S_TAKE_DATA_INT_CLR_V 0x1 +#define I2S_TAKE_DATA_INT_CLR_S 0 + +#define I2S_TIMING_REG(i) (REG_I2S_BASE(i) + 0x001c) +/* I2S_TX_BCK_IN_INV : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_BCK_IN_INV (BIT(24)) +#define I2S_TX_BCK_IN_INV_M (BIT(24)) +#define I2S_TX_BCK_IN_INV_V 0x1 +#define I2S_TX_BCK_IN_INV_S 24 +/* I2S_DATA_ENABLE_DELAY : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: */ +#define I2S_DATA_ENABLE_DELAY 0x00000003 +#define I2S_DATA_ENABLE_DELAY_M ((I2S_DATA_ENABLE_DELAY_V)<<(I2S_DATA_ENABLE_DELAY_S)) +#define I2S_DATA_ENABLE_DELAY_V 0x3 +#define I2S_DATA_ENABLE_DELAY_S 22 +/* I2S_RX_DSYNC_SW : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_DSYNC_SW (BIT(21)) +#define I2S_RX_DSYNC_SW_M (BIT(21)) +#define I2S_RX_DSYNC_SW_V 0x1 +#define I2S_RX_DSYNC_SW_S 21 +/* I2S_TX_DSYNC_SW : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_DSYNC_SW (BIT(20)) +#define I2S_TX_DSYNC_SW_M (BIT(20)) +#define I2S_TX_DSYNC_SW_V 0x1 +#define I2S_TX_DSYNC_SW_S 20 +/* I2S_RX_BCK_OUT_DELAY : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_BCK_OUT_DELAY 0x00000003 +#define I2S_RX_BCK_OUT_DELAY_M ((I2S_RX_BCK_OUT_DELAY_V)<<(I2S_RX_BCK_OUT_DELAY_S)) +#define I2S_RX_BCK_OUT_DELAY_V 0x3 +#define I2S_RX_BCK_OUT_DELAY_S 18 +/* I2S_RX_WS_OUT_DELAY : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_WS_OUT_DELAY 0x00000003 +#define I2S_RX_WS_OUT_DELAY_M ((I2S_RX_WS_OUT_DELAY_V)<<(I2S_RX_WS_OUT_DELAY_S)) +#define I2S_RX_WS_OUT_DELAY_V 0x3 +#define I2S_RX_WS_OUT_DELAY_S 16 +/* I2S_TX_SD_OUT_DELAY : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_SD_OUT_DELAY 0x00000003 +#define I2S_TX_SD_OUT_DELAY_M ((I2S_TX_SD_OUT_DELAY_V)<<(I2S_TX_SD_OUT_DELAY_S)) +#define I2S_TX_SD_OUT_DELAY_V 0x3 +#define I2S_TX_SD_OUT_DELAY_S 14 +/* I2S_TX_WS_OUT_DELAY : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_WS_OUT_DELAY 0x00000003 +#define I2S_TX_WS_OUT_DELAY_M ((I2S_TX_WS_OUT_DELAY_V)<<(I2S_TX_WS_OUT_DELAY_S)) +#define I2S_TX_WS_OUT_DELAY_V 0x3 +#define I2S_TX_WS_OUT_DELAY_S 12 +/* I2S_TX_BCK_OUT_DELAY : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_BCK_OUT_DELAY 0x00000003 +#define I2S_TX_BCK_OUT_DELAY_M ((I2S_TX_BCK_OUT_DELAY_V)<<(I2S_TX_BCK_OUT_DELAY_S)) +#define I2S_TX_BCK_OUT_DELAY_V 0x3 +#define I2S_TX_BCK_OUT_DELAY_S 10 +/* I2S_RX_SD_IN_DELAY : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_SD_IN_DELAY 0x00000003 +#define I2S_RX_SD_IN_DELAY_M ((I2S_RX_SD_IN_DELAY_V)<<(I2S_RX_SD_IN_DELAY_S)) +#define I2S_RX_SD_IN_DELAY_V 0x3 +#define I2S_RX_SD_IN_DELAY_S 8 +/* I2S_RX_WS_IN_DELAY : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_WS_IN_DELAY 0x00000003 +#define I2S_RX_WS_IN_DELAY_M ((I2S_RX_WS_IN_DELAY_V)<<(I2S_RX_WS_IN_DELAY_S)) +#define I2S_RX_WS_IN_DELAY_V 0x3 +#define I2S_RX_WS_IN_DELAY_S 6 +/* I2S_RX_BCK_IN_DELAY : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_BCK_IN_DELAY 0x00000003 +#define I2S_RX_BCK_IN_DELAY_M ((I2S_RX_BCK_IN_DELAY_V)<<(I2S_RX_BCK_IN_DELAY_S)) +#define I2S_RX_BCK_IN_DELAY_V 0x3 +#define I2S_RX_BCK_IN_DELAY_S 4 +/* I2S_TX_WS_IN_DELAY : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_WS_IN_DELAY 0x00000003 +#define I2S_TX_WS_IN_DELAY_M ((I2S_TX_WS_IN_DELAY_V)<<(I2S_TX_WS_IN_DELAY_S)) +#define I2S_TX_WS_IN_DELAY_V 0x3 +#define I2S_TX_WS_IN_DELAY_S 2 +/* I2S_TX_BCK_IN_DELAY : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_BCK_IN_DELAY 0x00000003 +#define I2S_TX_BCK_IN_DELAY_M ((I2S_TX_BCK_IN_DELAY_V)<<(I2S_TX_BCK_IN_DELAY_S)) +#define I2S_TX_BCK_IN_DELAY_V 0x3 +#define I2S_TX_BCK_IN_DELAY_S 0 + +#define I2S_FIFO_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) +/* I2S_RX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_FIFO_MOD_FORCE_EN (BIT(20)) +#define I2S_RX_FIFO_MOD_FORCE_EN_M (BIT(20)) +#define I2S_RX_FIFO_MOD_FORCE_EN_V 0x1 +#define I2S_RX_FIFO_MOD_FORCE_EN_S 20 +/* I2S_TX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_FIFO_MOD_FORCE_EN (BIT(19)) +#define I2S_TX_FIFO_MOD_FORCE_EN_M (BIT(19)) +#define I2S_TX_FIFO_MOD_FORCE_EN_V 0x1 +#define I2S_TX_FIFO_MOD_FORCE_EN_S 19 +/* I2S_RX_FIFO_MOD : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ +/*description: */ +#define I2S_RX_FIFO_MOD 0x00000007 +#define I2S_RX_FIFO_MOD_M ((I2S_RX_FIFO_MOD_V)<<(I2S_RX_FIFO_MOD_S)) +#define I2S_RX_FIFO_MOD_V 0x7 +#define I2S_RX_FIFO_MOD_S 16 +/* I2S_TX_FIFO_MOD : R/W ;bitpos:[15:13] ;default: 3'b0 ; */ +/*description: */ +#define I2S_TX_FIFO_MOD 0x00000007 +#define I2S_TX_FIFO_MOD_M ((I2S_TX_FIFO_MOD_V)<<(I2S_TX_FIFO_MOD_S)) +#define I2S_TX_FIFO_MOD_V 0x7 +#define I2S_TX_FIFO_MOD_S 13 +/* I2S_DSCR_EN : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: */ +#define I2S_DSCR_EN (BIT(12)) +#define I2S_DSCR_EN_M (BIT(12)) +#define I2S_DSCR_EN_V 0x1 +#define I2S_DSCR_EN_S 12 +/* I2S_TX_DATA_NUM : R/W ;bitpos:[11:6] ;default: 6'd32 ; */ +/*description: */ +#define I2S_TX_DATA_NUM 0x0000003F +#define I2S_TX_DATA_NUM_M ((I2S_TX_DATA_NUM_V)<<(I2S_TX_DATA_NUM_S)) +#define I2S_TX_DATA_NUM_V 0x3F +#define I2S_TX_DATA_NUM_S 6 +/* I2S_RX_DATA_NUM : R/W ;bitpos:[5:0] ;default: 6'd32 ; */ +/*description: */ +#define I2S_RX_DATA_NUM 0x0000003F +#define I2S_RX_DATA_NUM_M ((I2S_RX_DATA_NUM_V)<<(I2S_RX_DATA_NUM_S)) +#define I2S_RX_DATA_NUM_V 0x3F +#define I2S_RX_DATA_NUM_S 0 + +#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0024) +/* I2S_RX_EOF_NUM : R/W ;bitpos:[31:0] ;default: 32'd64 ; */ +/*description: */ +#define I2S_RX_EOF_NUM 0xFFFFFFFF +#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S)) +#define I2S_RX_EOF_NUM_V 0xFFFFFFFF +#define I2S_RX_EOF_NUM_S 0 + +#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0028) +/* I2S_SIGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define I2S_SIGLE_DATA 0xFFFFFFFF +#define I2S_SIGLE_DATA_M ((I2S_SIGLE_DATA_V)<<(I2S_SIGLE_DATA_S)) +#define I2S_SIGLE_DATA_V 0xFFFFFFFF +#define I2S_SIGLE_DATA_S 0 + +#define I2S_CONF_CHAN_REG(i) (REG_I2S_BASE(i) + 0x002c) +/* I2S_RX_CHAN_MOD : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_CHAN_MOD 0x00000003 +#define I2S_RX_CHAN_MOD_M ((I2S_RX_CHAN_MOD_V)<<(I2S_RX_CHAN_MOD_S)) +#define I2S_RX_CHAN_MOD_V 0x3 +#define I2S_RX_CHAN_MOD_S 3 +/* I2S_TX_CHAN_MOD : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define I2S_TX_CHAN_MOD 0x00000007 +#define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S)) +#define I2S_TX_CHAN_MOD_V 0x7 +#define I2S_TX_CHAN_MOD_S 0 + +#define I2S_OUT_LINK_REG(i) (REG_I2S_BASE(i) + 0x0030) +/* I2S_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define I2S_OUTLINK_PARK (BIT(31)) +#define I2S_OUTLINK_PARK_M (BIT(31)) +#define I2S_OUTLINK_PARK_V 0x1 +#define I2S_OUTLINK_PARK_S 31 +/* I2S_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUTLINK_RESTART (BIT(30)) +#define I2S_OUTLINK_RESTART_M (BIT(30)) +#define I2S_OUTLINK_RESTART_V 0x1 +#define I2S_OUTLINK_RESTART_S 30 +/* I2S_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUTLINK_START (BIT(29)) +#define I2S_OUTLINK_START_M (BIT(29)) +#define I2S_OUTLINK_START_V 0x1 +#define I2S_OUTLINK_START_S 29 +/* I2S_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUTLINK_STOP (BIT(28)) +#define I2S_OUTLINK_STOP_M (BIT(28)) +#define I2S_OUTLINK_STOP_V 0x1 +#define I2S_OUTLINK_STOP_S 28 +/* I2S_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define I2S_OUTLINK_ADDR 0x000FFFFF +#define I2S_OUTLINK_ADDR_M ((I2S_OUTLINK_ADDR_V)<<(I2S_OUTLINK_ADDR_S)) +#define I2S_OUTLINK_ADDR_V 0xFFFFF +#define I2S_OUTLINK_ADDR_S 0 + +#define I2S_IN_LINK_REG(i) (REG_I2S_BASE(i) + 0x0034) +/* I2S_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define I2S_INLINK_PARK (BIT(31)) +#define I2S_INLINK_PARK_M (BIT(31)) +#define I2S_INLINK_PARK_V 0x1 +#define I2S_INLINK_PARK_S 31 +/* I2S_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INLINK_RESTART (BIT(30)) +#define I2S_INLINK_RESTART_M (BIT(30)) +#define I2S_INLINK_RESTART_V 0x1 +#define I2S_INLINK_RESTART_S 30 +/* I2S_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INLINK_START (BIT(29)) +#define I2S_INLINK_START_M (BIT(29)) +#define I2S_INLINK_START_V 0x1 +#define I2S_INLINK_START_S 29 +/* I2S_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INLINK_STOP (BIT(28)) +#define I2S_INLINK_STOP_M (BIT(28)) +#define I2S_INLINK_STOP_V 0x1 +#define I2S_INLINK_STOP_S 28 +/* I2S_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define I2S_INLINK_ADDR 0x000FFFFF +#define I2S_INLINK_ADDR_M ((I2S_INLINK_ADDR_V)<<(I2S_INLINK_ADDR_S)) +#define I2S_INLINK_ADDR_V 0xFFFFF +#define I2S_INLINK_ADDR_S 0 + +#define I2S_OUT_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0038) +/* I2S_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define I2S_OUT_EOF_DES_ADDR_M ((I2S_OUT_EOF_DES_ADDR_V)<<(I2S_OUT_EOF_DES_ADDR_S)) +#define I2S_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define I2S_OUT_EOF_DES_ADDR_S 0 + +#define I2S_IN_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x003c) +/* I2S_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define I2S_IN_SUC_EOF_DES_ADDR_M ((I2S_IN_SUC_EOF_DES_ADDR_V)<<(I2S_IN_SUC_EOF_DES_ADDR_S)) +#define I2S_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define I2S_IN_SUC_EOF_DES_ADDR_S 0 + +#define I2S_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0040) +/* I2S_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define I2S_OUT_EOF_BFR_DES_ADDR_M ((I2S_OUT_EOF_BFR_DES_ADDR_V)<<(I2S_OUT_EOF_BFR_DES_ADDR_S)) +#define I2S_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define I2S_OUT_EOF_BFR_DES_ADDR_S 0 + +#define I2S_AHB_TEST_REG(i) (REG_I2S_BASE(i) + 0x0044) +/* I2S_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define I2S_AHB_TESTADDR 0x00000003 +#define I2S_AHB_TESTADDR_M ((I2S_AHB_TESTADDR_V)<<(I2S_AHB_TESTADDR_S)) +#define I2S_AHB_TESTADDR_V 0x3 +#define I2S_AHB_TESTADDR_S 4 +/* I2S_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define I2S_AHB_TESTMODE 0x00000007 +#define I2S_AHB_TESTMODE_M ((I2S_AHB_TESTMODE_V)<<(I2S_AHB_TESTMODE_S)) +#define I2S_AHB_TESTMODE_V 0x7 +#define I2S_AHB_TESTMODE_S 0 + +#define I2S_INLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0048) +/* I2S_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_INLINK_DSCR 0xFFFFFFFF +#define I2S_INLINK_DSCR_M ((I2S_INLINK_DSCR_V)<<(I2S_INLINK_DSCR_S)) +#define I2S_INLINK_DSCR_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_S 0 + +#define I2S_INLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x004C) +/* I2S_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_INLINK_DSCR_BF0 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF0_M ((I2S_INLINK_DSCR_BF0_V)<<(I2S_INLINK_DSCR_BF0_S)) +#define I2S_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF0_S 0 + +#define I2S_INLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x0050) +/* I2S_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_INLINK_DSCR_BF1 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF1_M ((I2S_INLINK_DSCR_BF1_V)<<(I2S_INLINK_DSCR_BF1_S)) +#define I2S_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF1_S 0 + +#define I2S_OUTLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0054) +/* I2S_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_OUTLINK_DSCR 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_M ((I2S_OUTLINK_DSCR_V)<<(I2S_OUTLINK_DSCR_S)) +#define I2S_OUTLINK_DSCR_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_S 0 + +#define I2S_OUTLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x0058) +/* I2S_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF0_M ((I2S_OUTLINK_DSCR_BF0_V)<<(I2S_OUTLINK_DSCR_BF0_S)) +#define I2S_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF0_S 0 + +#define I2S_OUTLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x005C) +/* I2S_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF1_M ((I2S_OUTLINK_DSCR_BF1_V)<<(I2S_OUTLINK_DSCR_BF1_S)) +#define I2S_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF1_S 0 + +#define I2S_LC_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) +/* I2S_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_MEM_TRANS_EN (BIT(13)) +#define I2S_MEM_TRANS_EN_M (BIT(13)) +#define I2S_MEM_TRANS_EN_V 0x1 +#define I2S_MEM_TRANS_EN_S 13 +/* I2S_CHECK_OWNER : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CHECK_OWNER (BIT(12)) +#define I2S_CHECK_OWNER_M (BIT(12)) +#define I2S_CHECK_OWNER_V 0x1 +#define I2S_CHECK_OWNER_S 12 +/* I2S_OUT_DATA_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DATA_BURST_EN (BIT(11)) +#define I2S_OUT_DATA_BURST_EN_M (BIT(11)) +#define I2S_OUT_DATA_BURST_EN_V 0x1 +#define I2S_OUT_DATA_BURST_EN_S 11 +/* I2S_INDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INDSCR_BURST_EN (BIT(10)) +#define I2S_INDSCR_BURST_EN_M (BIT(10)) +#define I2S_INDSCR_BURST_EN_V 0x1 +#define I2S_INDSCR_BURST_EN_S 10 +/* I2S_OUTDSCR_BURST_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUTDSCR_BURST_EN (BIT(9)) +#define I2S_OUTDSCR_BURST_EN_M (BIT(9)) +#define I2S_OUTDSCR_BURST_EN_V 0x1 +#define I2S_OUTDSCR_BURST_EN_S 9 +/* I2S_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define I2S_OUT_EOF_MODE (BIT(8)) +#define I2S_OUT_EOF_MODE_M (BIT(8)) +#define I2S_OUT_EOF_MODE_V 0x1 +#define I2S_OUT_EOF_MODE_S 8 +/* I2S_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_NO_RESTART_CLR (BIT(7)) +#define I2S_OUT_NO_RESTART_CLR_M (BIT(7)) +#define I2S_OUT_NO_RESTART_CLR_V 0x1 +#define I2S_OUT_NO_RESTART_CLR_S 7 +/* I2S_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_AUTO_WRBACK (BIT(6)) +#define I2S_OUT_AUTO_WRBACK_M (BIT(6)) +#define I2S_OUT_AUTO_WRBACK_V 0x1 +#define I2S_OUT_AUTO_WRBACK_S 6 +/* I2S_IN_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_LOOP_TEST (BIT(5)) +#define I2S_IN_LOOP_TEST_M (BIT(5)) +#define I2S_IN_LOOP_TEST_V 0x1 +#define I2S_IN_LOOP_TEST_S 5 +/* I2S_OUT_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_LOOP_TEST (BIT(4)) +#define I2S_OUT_LOOP_TEST_M (BIT(4)) +#define I2S_OUT_LOOP_TEST_V 0x1 +#define I2S_OUT_LOOP_TEST_S 4 +/* I2S_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_AHBM_RST (BIT(3)) +#define I2S_AHBM_RST_M (BIT(3)) +#define I2S_AHBM_RST_V 0x1 +#define I2S_AHBM_RST_S 3 +/* I2S_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_AHBM_FIFO_RST (BIT(2)) +#define I2S_AHBM_FIFO_RST_M (BIT(2)) +#define I2S_AHBM_FIFO_RST_V 0x1 +#define I2S_AHBM_FIFO_RST_S 2 +/* I2S_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_RST (BIT(1)) +#define I2S_OUT_RST_M (BIT(1)) +#define I2S_OUT_RST_V 0x1 +#define I2S_OUT_RST_S 1 +/* I2S_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define I2S_IN_RST (BIT(0)) +#define I2S_IN_RST_M (BIT(0)) +#define I2S_IN_RST_V 0x1 +#define I2S_IN_RST_S 0 + +#define I2S_OUTFIFO_PUSH_REG(i) (REG_I2S_BASE(i) + 0x0064) +/* I2S_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define I2S_OUTFIFO_PUSH (BIT(16)) +#define I2S_OUTFIFO_PUSH_M (BIT(16)) +#define I2S_OUTFIFO_PUSH_V 0x1 +#define I2S_OUTFIFO_PUSH_S 16 +/* I2S_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define I2S_OUTFIFO_WDATA 0x000001FF +#define I2S_OUTFIFO_WDATA_M ((I2S_OUTFIFO_WDATA_V)<<(I2S_OUTFIFO_WDATA_S)) +#define I2S_OUTFIFO_WDATA_V 0x1FF +#define I2S_OUTFIFO_WDATA_S 0 + +#define I2S_INFIFO_POP_REG(i) (REG_I2S_BASE(i) + 0x0068) +/* I2S_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define I2S_INFIFO_POP (BIT(16)) +#define I2S_INFIFO_POP_M (BIT(16)) +#define I2S_INFIFO_POP_V 0x1 +#define I2S_INFIFO_POP_S 16 +/* I2S_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define I2S_INFIFO_RDATA 0x00000FFF +#define I2S_INFIFO_RDATA_M ((I2S_INFIFO_RDATA_V)<<(I2S_INFIFO_RDATA_S)) +#define I2S_INFIFO_RDATA_V 0xFFF +#define I2S_INFIFO_RDATA_S 0 + +#define I2S_LC_STATE0_REG(i) (REG_I2S_BASE(i) + 0x006C) +/* I2S_LC_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_LC_STATE0 0xFFFFFFFF +#define I2S_LC_STATE0_M ((I2S_LC_STATE0_V)<<(I2S_LC_STATE0_S)) +#define I2S_LC_STATE0_V 0xFFFFFFFF +#define I2S_LC_STATE0_S 0 + +#define I2S_LC_STATE1_REG(i) (REG_I2S_BASE(i) + 0x0070) +/* I2S_LC_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_LC_STATE1 0xFFFFFFFF +#define I2S_LC_STATE1_M ((I2S_LC_STATE1_V)<<(I2S_LC_STATE1_S)) +#define I2S_LC_STATE1_V 0xFFFFFFFF +#define I2S_LC_STATE1_S 0 + +#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0074) +/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 +/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: */ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S)) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ +/*description: */ +#define I2S_LC_FIFO_TIMEOUT 0x000000FF +#define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S)) +#define I2S_LC_FIFO_TIMEOUT_V 0xFF +#define I2S_LC_FIFO_TIMEOUT_S 0 + +#define I2S_CVSD_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0080) +/* I2S_CVSD_Y_MIN : R/W ;bitpos:[31:16] ;default: 16'h8000 ; */ +/*description: */ +#define I2S_CVSD_Y_MIN 0x0000FFFF +#define I2S_CVSD_Y_MIN_M ((I2S_CVSD_Y_MIN_V)<<(I2S_CVSD_Y_MIN_S)) +#define I2S_CVSD_Y_MIN_V 0xFFFF +#define I2S_CVSD_Y_MIN_S 16 +/* I2S_CVSD_Y_MAX : R/W ;bitpos:[15:0] ;default: 16'h7fff ; */ +/*description: */ +#define I2S_CVSD_Y_MAX 0x0000FFFF +#define I2S_CVSD_Y_MAX_M ((I2S_CVSD_Y_MAX_V)<<(I2S_CVSD_Y_MAX_S)) +#define I2S_CVSD_Y_MAX_V 0xFFFF +#define I2S_CVSD_Y_MAX_S 0 + +#define I2S_CVSD_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0084) +/* I2S_CVSD_SIGMA_MIN : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ +/*description: */ +#define I2S_CVSD_SIGMA_MIN 0x0000FFFF +#define I2S_CVSD_SIGMA_MIN_M ((I2S_CVSD_SIGMA_MIN_V)<<(I2S_CVSD_SIGMA_MIN_S)) +#define I2S_CVSD_SIGMA_MIN_V 0xFFFF +#define I2S_CVSD_SIGMA_MIN_S 16 +/* I2S_CVSD_SIGMA_MAX : R/W ;bitpos:[15:0] ;default: 16'd1280 ; */ +/*description: */ +#define I2S_CVSD_SIGMA_MAX 0x0000FFFF +#define I2S_CVSD_SIGMA_MAX_M ((I2S_CVSD_SIGMA_MAX_V)<<(I2S_CVSD_SIGMA_MAX_S)) +#define I2S_CVSD_SIGMA_MAX_V 0xFFFF +#define I2S_CVSD_SIGMA_MAX_S 0 + +#define I2S_CVSD_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0088) +/* I2S_CVSD_H : R/W ;bitpos:[18:16] ;default: 3'd5 ; */ +/*description: */ +#define I2S_CVSD_H 0x00000007 +#define I2S_CVSD_H_M ((I2S_CVSD_H_V)<<(I2S_CVSD_H_S)) +#define I2S_CVSD_H_V 0x7 +#define I2S_CVSD_H_S 16 +/* I2S_CVSD_BETA : R/W ;bitpos:[15:6] ;default: 10'd10 ; */ +/*description: */ +#define I2S_CVSD_BETA 0x000003FF +#define I2S_CVSD_BETA_M ((I2S_CVSD_BETA_V)<<(I2S_CVSD_BETA_S)) +#define I2S_CVSD_BETA_V 0x3FF +#define I2S_CVSD_BETA_S 6 +/* I2S_CVSD_J : R/W ;bitpos:[5:3] ;default: 3'h4 ; */ +/*description: */ +#define I2S_CVSD_J 0x00000007 +#define I2S_CVSD_J_M ((I2S_CVSD_J_V)<<(I2S_CVSD_J_S)) +#define I2S_CVSD_J_V 0x7 +#define I2S_CVSD_J_S 3 +/* I2S_CVSD_K : R/W ;bitpos:[2:0] ;default: 3'h4 ; */ +/*description: */ +#define I2S_CVSD_K 0x00000007 +#define I2S_CVSD_K_M ((I2S_CVSD_K_V)<<(I2S_CVSD_K_S)) +#define I2S_CVSD_K_V 0x7 +#define I2S_CVSD_K_S 0 + +#define I2S_PLC_CONF0_REG(i) (REG_I2S_BASE(i) + 0x008C) +/* I2S_N_MIN_ERR : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ +/*description: */ +#define I2S_N_MIN_ERR 0x00000007 +#define I2S_N_MIN_ERR_M ((I2S_N_MIN_ERR_V)<<(I2S_N_MIN_ERR_S)) +#define I2S_N_MIN_ERR_V 0x7 +#define I2S_N_MIN_ERR_S 25 +/* I2S_PACK_LEN_8K : R/W ;bitpos:[24:20] ;default: 5'd10 ; */ +/*description: */ +#define I2S_PACK_LEN_8K 0x0000001F +#define I2S_PACK_LEN_8K_M ((I2S_PACK_LEN_8K_V)<<(I2S_PACK_LEN_8K_S)) +#define I2S_PACK_LEN_8K_V 0x1F +#define I2S_PACK_LEN_8K_S 20 +/* I2S_MAX_SLIDE_SAMPLE : R/W ;bitpos:[19:12] ;default: 8'd128 ; */ +/*description: */ +#define I2S_MAX_SLIDE_SAMPLE 0x000000FF +#define I2S_MAX_SLIDE_SAMPLE_M ((I2S_MAX_SLIDE_SAMPLE_V)<<(I2S_MAX_SLIDE_SAMPLE_S)) +#define I2S_MAX_SLIDE_SAMPLE_V 0xFF +#define I2S_MAX_SLIDE_SAMPLE_S 12 +/* I2S_SHIFT_RATE : R/W ;bitpos:[11:9] ;default: 3'h1 ; */ +/*description: */ +#define I2S_SHIFT_RATE 0x00000007 +#define I2S_SHIFT_RATE_M ((I2S_SHIFT_RATE_V)<<(I2S_SHIFT_RATE_S)) +#define I2S_SHIFT_RATE_V 0x7 +#define I2S_SHIFT_RATE_S 9 +/* I2S_N_ERR_SEG : R/W ;bitpos:[8:6] ;default: 3'h4 ; */ +/*description: */ +#define I2S_N_ERR_SEG 0x00000007 +#define I2S_N_ERR_SEG_M ((I2S_N_ERR_SEG_V)<<(I2S_N_ERR_SEG_S)) +#define I2S_N_ERR_SEG_V 0x7 +#define I2S_N_ERR_SEG_S 6 +/* I2S_GOOD_PACK_MAX : R/W ;bitpos:[5:0] ;default: 6'h39 ; */ +/*description: */ +#define I2S_GOOD_PACK_MAX 0x0000003F +#define I2S_GOOD_PACK_MAX_M ((I2S_GOOD_PACK_MAX_V)<<(I2S_GOOD_PACK_MAX_S)) +#define I2S_GOOD_PACK_MAX_V 0x3F +#define I2S_GOOD_PACK_MAX_S 0 + +#define I2S_PLC_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0090) +/* I2S_SLIDE_WIN_LEN : R/W ;bitpos:[31:24] ;default: 8'd160 ; */ +/*description: */ +#define I2S_SLIDE_WIN_LEN 0x000000FF +#define I2S_SLIDE_WIN_LEN_M ((I2S_SLIDE_WIN_LEN_V)<<(I2S_SLIDE_WIN_LEN_S)) +#define I2S_SLIDE_WIN_LEN_V 0xFF +#define I2S_SLIDE_WIN_LEN_S 24 +/* I2S_BAD_OLA_WIN2_PARA : R/W ;bitpos:[23:16] ;default: 8'd23 ; */ +/*description: */ +#define I2S_BAD_OLA_WIN2_PARA 0x000000FF +#define I2S_BAD_OLA_WIN2_PARA_M ((I2S_BAD_OLA_WIN2_PARA_V)<<(I2S_BAD_OLA_WIN2_PARA_S)) +#define I2S_BAD_OLA_WIN2_PARA_V 0xFF +#define I2S_BAD_OLA_WIN2_PARA_S 16 +/* I2S_BAD_OLA_WIN2_PARA_SHIFT : R/W ;bitpos:[15:12] ;default: 4'd8 ; */ +/*description: */ +#define I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F +#define I2S_BAD_OLA_WIN2_PARA_SHIFT_M ((I2S_BAD_OLA_WIN2_PARA_SHIFT_V)<<(I2S_BAD_OLA_WIN2_PARA_SHIFT_S)) +#define I2S_BAD_OLA_WIN2_PARA_SHIFT_V 0xF +#define I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12 +/* I2S_BAD_CEF_ATTEN_PARA_SHIFT : R/W ;bitpos:[11:8] ;default: 4'd10 ; */ +/*description: */ +#define I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F +#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_M ((I2S_BAD_CEF_ATTEN_PARA_SHIFT_V)<<(I2S_BAD_CEF_ATTEN_PARA_SHIFT_S)) +#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_V 0xF +#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8 +/* I2S_BAD_CEF_ATTEN_PARA : R/W ;bitpos:[7:0] ;default: 8'd5 ; */ +/*description: */ +#define I2S_BAD_CEF_ATTEN_PARA 0x000000FF +#define I2S_BAD_CEF_ATTEN_PARA_M ((I2S_BAD_CEF_ATTEN_PARA_V)<<(I2S_BAD_CEF_ATTEN_PARA_S)) +#define I2S_BAD_CEF_ATTEN_PARA_V 0xFF +#define I2S_BAD_CEF_ATTEN_PARA_S 0 + +#define I2S_PLC_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0094) +/* I2S_MIN_PERIOD : R/W ;bitpos:[6:2] ;default: 5'd10 ; */ +/*description: */ +#define I2S_MIN_PERIOD 0x0000001F +#define I2S_MIN_PERIOD_M ((I2S_MIN_PERIOD_V)<<(I2S_MIN_PERIOD_S)) +#define I2S_MIN_PERIOD_V 0x1F +#define I2S_MIN_PERIOD_S 2 +/* I2S_CVSD_SEG_MOD : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define I2S_CVSD_SEG_MOD 0x00000003 +#define I2S_CVSD_SEG_MOD_M ((I2S_CVSD_SEG_MOD_V)<<(I2S_CVSD_SEG_MOD_S)) +#define I2S_CVSD_SEG_MOD_V 0x3 +#define I2S_CVSD_SEG_MOD_S 0 + +#define I2S_ESCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0098) +/* I2S_PLC2DMA_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_PLC2DMA_EN (BIT(12)) +#define I2S_PLC2DMA_EN_M (BIT(12)) +#define I2S_PLC2DMA_EN_V 0x1 +#define I2S_PLC2DMA_EN_S 12 +/* I2S_PLC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_PLC_EN (BIT(11)) +#define I2S_PLC_EN_M (BIT(11)) +#define I2S_PLC_EN_V 0x1 +#define I2S_PLC_EN_S 11 +/* I2S_CVSD_DEC_RESET : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CVSD_DEC_RESET (BIT(10)) +#define I2S_CVSD_DEC_RESET_M (BIT(10)) +#define I2S_CVSD_DEC_RESET_V 0x1 +#define I2S_CVSD_DEC_RESET_S 10 +/* I2S_CVSD_DEC_START : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CVSD_DEC_START (BIT(9)) +#define I2S_CVSD_DEC_START_M (BIT(9)) +#define I2S_CVSD_DEC_START_V 0x1 +#define I2S_CVSD_DEC_START_S 9 +/* I2S_ESCO_CVSD_INF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_ESCO_CVSD_INF_EN (BIT(8)) +#define I2S_ESCO_CVSD_INF_EN_M (BIT(8)) +#define I2S_ESCO_CVSD_INF_EN_V 0x1 +#define I2S_ESCO_CVSD_INF_EN_S 8 +/* I2S_ESCO_CVSD_PACK_LEN_8K : R/W ;bitpos:[7:3] ;default: 5'b0 ; */ +/*description: */ +#define I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F +#define I2S_ESCO_CVSD_PACK_LEN_8K_M ((I2S_ESCO_CVSD_PACK_LEN_8K_V)<<(I2S_ESCO_CVSD_PACK_LEN_8K_S)) +#define I2S_ESCO_CVSD_PACK_LEN_8K_V 0x1F +#define I2S_ESCO_CVSD_PACK_LEN_8K_S 3 +/* I2S_ESCO_CVSD_DEC_PACK_ERR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2)) +#define I2S_ESCO_CVSD_DEC_PACK_ERR_M (BIT(2)) +#define I2S_ESCO_CVSD_DEC_PACK_ERR_V 0x1 +#define I2S_ESCO_CVSD_DEC_PACK_ERR_S 2 +/* I2S_ESCO_CHAN_MOD : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define I2S_ESCO_CHAN_MOD (BIT(1)) +#define I2S_ESCO_CHAN_MOD_M (BIT(1)) +#define I2S_ESCO_CHAN_MOD_V 0x1 +#define I2S_ESCO_CHAN_MOD_S 1 +/* I2S_ESCO_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define I2S_ESCO_EN (BIT(0)) +#define I2S_ESCO_EN_M (BIT(0)) +#define I2S_ESCO_EN_V 0x1 +#define I2S_ESCO_EN_S 0 + +#define I2S_SCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x009c) +/* I2S_CVSD_ENC_RESET : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: */ +#define I2S_CVSD_ENC_RESET (BIT(3)) +#define I2S_CVSD_ENC_RESET_M (BIT(3)) +#define I2S_CVSD_ENC_RESET_V 0x1 +#define I2S_CVSD_ENC_RESET_S 3 +/* I2S_CVSD_ENC_START : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: */ +#define I2S_CVSD_ENC_START (BIT(2)) +#define I2S_CVSD_ENC_START_M (BIT(2)) +#define I2S_CVSD_ENC_START_V 0x1 +#define I2S_CVSD_ENC_START_S 2 +/* I2S_SCO_NO_I2S_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define I2S_SCO_NO_I2S_EN (BIT(1)) +#define I2S_SCO_NO_I2S_EN_M (BIT(1)) +#define I2S_SCO_NO_I2S_EN_V 0x1 +#define I2S_SCO_NO_I2S_EN_S 1 +/* I2S_SCO_WITH_I2S_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define I2S_SCO_WITH_I2S_EN (BIT(0)) +#define I2S_SCO_WITH_I2S_EN_M (BIT(0)) +#define I2S_SCO_WITH_I2S_EN_V 0x1 +#define I2S_SCO_WITH_I2S_EN_S 0 + +#define I2S_CONF1_REG(i) (REG_I2S_BASE(i) + 0x00a0) +/* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define I2S_TX_ZEROS_RM_EN (BIT(9)) +#define I2S_TX_ZEROS_RM_EN_M (BIT(9)) +#define I2S_TX_ZEROS_RM_EN_V 0x1 +#define I2S_TX_ZEROS_RM_EN_S 9 +/* I2S_TX_STOP_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define I2S_TX_STOP_EN (BIT(8)) +#define I2S_TX_STOP_EN_M (BIT(8)) +#define I2S_TX_STOP_EN_V 0x1 +#define I2S_TX_STOP_EN_S 8 +/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[7] ;default: 1'h1 ; */ +/*description: */ +#define I2S_RX_PCM_BYPASS (BIT(7)) +#define I2S_RX_PCM_BYPASS_M (BIT(7)) +#define I2S_RX_PCM_BYPASS_V 0x1 +#define I2S_RX_PCM_BYPASS_S 7 +/* I2S_RX_PCM_CONF : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: */ +#define I2S_RX_PCM_CONF 0x00000007 +#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S)) +#define I2S_RX_PCM_CONF_V 0x7 +#define I2S_RX_PCM_CONF_S 4 +/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[3] ;default: 1'h1 ; */ +/*description: */ +#define I2S_TX_PCM_BYPASS (BIT(3)) +#define I2S_TX_PCM_BYPASS_M (BIT(3)) +#define I2S_TX_PCM_BYPASS_V 0x1 +#define I2S_TX_PCM_BYPASS_S 3 +/* I2S_TX_PCM_CONF : R/W ;bitpos:[2:0] ;default: 3'h1 ; */ +/*description: */ +#define I2S_TX_PCM_CONF 0x00000007 +#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S)) +#define I2S_TX_PCM_CONF_V 0x7 +#define I2S_TX_PCM_CONF_S 0 + +#define I2S_PD_CONF_REG(i) (REG_I2S_BASE(i) + 0x00a4) +/* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */ +/*description: */ +#define I2S_PLC_MEM_FORCE_PU (BIT(3)) +#define I2S_PLC_MEM_FORCE_PU_M (BIT(3)) +#define I2S_PLC_MEM_FORCE_PU_V 0x1 +#define I2S_PLC_MEM_FORCE_PU_S 3 +/* I2S_PLC_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define I2S_PLC_MEM_FORCE_PD (BIT(2)) +#define I2S_PLC_MEM_FORCE_PD_M (BIT(2)) +#define I2S_PLC_MEM_FORCE_PD_V 0x1 +#define I2S_PLC_MEM_FORCE_PD_S 2 +/* I2S_FIFO_FORCE_PU : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: */ +#define I2S_FIFO_FORCE_PU (BIT(1)) +#define I2S_FIFO_FORCE_PU_M (BIT(1)) +#define I2S_FIFO_FORCE_PU_V 0x1 +#define I2S_FIFO_FORCE_PU_S 1 +/* I2S_FIFO_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define I2S_FIFO_FORCE_PD (BIT(0)) +#define I2S_FIFO_FORCE_PD_M (BIT(0)) +#define I2S_FIFO_FORCE_PD_V 0x1 +#define I2S_FIFO_FORCE_PD_S 0 + +#define I2S_CONF2_REG(i) (REG_I2S_BASE(i) + 0x00a8) +/* I2S_INTER_VALID_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INTER_VALID_EN (BIT(7)) +#define I2S_INTER_VALID_EN_M (BIT(7)) +#define I2S_INTER_VALID_EN_V 0x1 +#define I2S_INTER_VALID_EN_S 7 +/* I2S_EXT_ADC_START_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_EXT_ADC_START_EN (BIT(6)) +#define I2S_EXT_ADC_START_EN_M (BIT(6)) +#define I2S_EXT_ADC_START_EN_V 0x1 +#define I2S_EXT_ADC_START_EN_S 6 +/* I2S_LCD_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_LCD_EN (BIT(5)) +#define I2S_LCD_EN_M (BIT(5)) +#define I2S_LCD_EN_V 0x1 +#define I2S_LCD_EN_S 5 +/* I2S_DATA_ENABLE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: */ +#define I2S_DATA_ENABLE (BIT(4)) +#define I2S_DATA_ENABLE_M (BIT(4)) +#define I2S_DATA_ENABLE_V 0x1 +#define I2S_DATA_ENABLE_S 4 +/* I2S_DATA_ENABLE_TEST_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define I2S_DATA_ENABLE_TEST_EN (BIT(3)) +#define I2S_DATA_ENABLE_TEST_EN_M (BIT(3)) +#define I2S_DATA_ENABLE_TEST_EN_V 0x1 +#define I2S_DATA_ENABLE_TEST_EN_S 3 +/* I2S_LCD_TX_SDX2_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define I2S_LCD_TX_SDX2_EN (BIT(2)) +#define I2S_LCD_TX_SDX2_EN_M (BIT(2)) +#define I2S_LCD_TX_SDX2_EN_V 0x1 +#define I2S_LCD_TX_SDX2_EN_S 2 +/* I2S_LCD_TX_WRX2_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define I2S_LCD_TX_WRX2_EN (BIT(1)) +#define I2S_LCD_TX_WRX2_EN_M (BIT(1)) +#define I2S_LCD_TX_WRX2_EN_V 0x1 +#define I2S_LCD_TX_WRX2_EN_S 1 +/* I2S_CAMERA_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define I2S_CAMERA_EN (BIT(0)) +#define I2S_CAMERA_EN_M (BIT(0)) +#define I2S_CAMERA_EN_V 0x1 +#define I2S_CAMERA_EN_S 0 + +#define I2S_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00ac) +/* I2S_CLKA_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CLKA_ENA (BIT(21)) +#define I2S_CLKA_ENA_M (BIT(21)) +#define I2S_CLKA_ENA_V 0x1 +#define I2S_CLKA_ENA_S 21 +/* I2S_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CLK_EN (BIT(20)) +#define I2S_CLK_EN_M (BIT(20)) +#define I2S_CLK_EN_V 0x1 +#define I2S_CLK_EN_S 20 +/* I2S_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ +/*description: */ +#define I2S_CLKM_DIV_A 0x0000003F +#define I2S_CLKM_DIV_A_M ((I2S_CLKM_DIV_A_V)<<(I2S_CLKM_DIV_A_S)) +#define I2S_CLKM_DIV_A_V 0x3F +#define I2S_CLKM_DIV_A_S 14 +/* I2S_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ +/*description: */ +#define I2S_CLKM_DIV_B 0x0000003F +#define I2S_CLKM_DIV_B_M ((I2S_CLKM_DIV_B_V)<<(I2S_CLKM_DIV_B_S)) +#define I2S_CLKM_DIV_B_V 0x3F +#define I2S_CLKM_DIV_B_S 8 +/* I2S_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ +/*description: */ +#define I2S_CLKM_DIV_NUM 0x000000FF +#define I2S_CLKM_DIV_NUM_M ((I2S_CLKM_DIV_NUM_V)<<(I2S_CLKM_DIV_NUM_S)) +#define I2S_CLKM_DIV_NUM_V 0xFF +#define I2S_CLKM_DIV_NUM_S 0 + +#define I2S_SAMPLE_RATE_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b0) +/* I2S_RX_BITS_MOD : R/W ;bitpos:[23:18] ;default: 6'd16 ; */ +/*description: */ +#define I2S_RX_BITS_MOD 0x0000003F +#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S)) +#define I2S_RX_BITS_MOD_V 0x3F +#define I2S_RX_BITS_MOD_S 18 +/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:12] ;default: 6'd16 ; */ +/*description: */ +#define I2S_TX_BITS_MOD 0x0000003F +#define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S)) +#define I2S_TX_BITS_MOD_V 0x3F +#define I2S_TX_BITS_MOD_S 12 +/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[11:6] ;default: 6'd6 ; */ +/*description: */ +#define I2S_RX_BCK_DIV_NUM 0x0000003F +#define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S)) +#define I2S_RX_BCK_DIV_NUM_V 0x3F +#define I2S_RX_BCK_DIV_NUM_S 6 +/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[5:0] ;default: 6'd6 ; */ +/*description: */ +#define I2S_TX_BCK_DIV_NUM 0x0000003F +#define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S)) +#define I2S_TX_BCK_DIV_NUM_V 0x3F +#define I2S_TX_BCK_DIV_NUM_S 0 + +#define I2S_PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b4) +/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define I2S_TX_PDM_HP_BYPASS (BIT(25)) +#define I2S_TX_PDM_HP_BYPASS_M (BIT(25)) +#define I2S_TX_PDM_HP_BYPASS_V 0x1 +#define I2S_TX_PDM_HP_BYPASS_S 25 +/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[24] ;default: 1'h1 ; */ +/*description: */ +#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24)) +#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(24)) +#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1 +#define I2S_RX_PDM_SINC_DSR_16_EN_S 24 +/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[23:22] ;default: 2'h1 ; */ +/*description: */ +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)) +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22 +/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[21:20] ;default: 2'h1 ; */ +/*description: */ +#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S)) +#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_SINC_IN_SHIFT_S 20 +/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[19:18] ;default: 2'h1 ; */ +/*description: */ +#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S)) +#define I2S_TX_PDM_LP_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_LP_IN_SHIFT_S 18 +/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[17:16] ;default: 2'h1 ; */ +/*description: */ +#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S)) +#define I2S_TX_PDM_HP_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_HP_IN_SHIFT_S 16 +/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define I2S_TX_PDM_PRESCALE 0x000000FF +#define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S)) +#define I2S_TX_PDM_PRESCALE_V 0xFF +#define I2S_TX_PDM_PRESCALE_S 8 +/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[7:4] ;default: 4'h2 ; */ +/*description: */ +#define I2S_TX_PDM_SINC_OSR2 0x0000000F +#define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S)) +#define I2S_TX_PDM_SINC_OSR2_V 0xF +#define I2S_TX_PDM_SINC_OSR2_S 4 +/* I2S_PDM2PCM_CONV_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define I2S_PDM2PCM_CONV_EN (BIT(3)) +#define I2S_PDM2PCM_CONV_EN_M (BIT(3)) +#define I2S_PDM2PCM_CONV_EN_V 0x1 +#define I2S_PDM2PCM_CONV_EN_S 3 +/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define I2S_PCM2PDM_CONV_EN (BIT(2)) +#define I2S_PCM2PDM_CONV_EN_M (BIT(2)) +#define I2S_PCM2PDM_CONV_EN_V 0x1 +#define I2S_PCM2PDM_CONV_EN_S 2 +/* I2S_RX_PDM_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define I2S_RX_PDM_EN (BIT(1)) +#define I2S_RX_PDM_EN_M (BIT(1)) +#define I2S_RX_PDM_EN_V 0x1 +#define I2S_RX_PDM_EN_S 1 +/* I2S_TX_PDM_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define I2S_TX_PDM_EN (BIT(0)) +#define I2S_TX_PDM_EN_M (BIT(0)) +#define I2S_TX_PDM_EN_V 0x1 +#define I2S_TX_PDM_EN_S 0 + +#define I2S_PDM_FREQ_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b8) +/* I2S_TX_PDM_FP : R/W ;bitpos:[19:10] ;default: 10'd960 ; */ +/*description: */ +#define I2S_TX_PDM_FP 0x000003FF +#define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S)) +#define I2S_TX_PDM_FP_V 0x3FF +#define I2S_TX_PDM_FP_S 10 +/* I2S_TX_PDM_FS : R/W ;bitpos:[9:0] ;default: 10'd480 ; */ +/*description: */ +#define I2S_TX_PDM_FS 0x000003FF +#define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S)) +#define I2S_TX_PDM_FS_V 0x3FF +#define I2S_TX_PDM_FS_S 0 + +#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x00bc) +/* I2S_RX_FIFO_RESET_BACK : RO ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define I2S_RX_FIFO_RESET_BACK (BIT(2)) +#define I2S_RX_FIFO_RESET_BACK_M (BIT(2)) +#define I2S_RX_FIFO_RESET_BACK_V 0x1 +#define I2S_RX_FIFO_RESET_BACK_S 2 +/* I2S_TX_FIFO_RESET_BACK : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define I2S_TX_FIFO_RESET_BACK (BIT(1)) +#define I2S_TX_FIFO_RESET_BACK_M (BIT(1)) +#define I2S_TX_FIFO_RESET_BACK_V 0x1 +#define I2S_TX_FIFO_RESET_BACK_S 1 +/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (BIT(0)) +#define I2S_TX_IDLE_V 0x1 +#define I2S_TX_IDLE_S 0 + +#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x00fc) +/* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h1604201 ; */ +/*description: */ +#define I2S_I2SDATE 0xFFFFFFFF +#define I2S_I2SDATE_M ((I2S_I2SDATE_V)<<(I2S_I2SDATE_S)) +#define I2S_I2SDATE_V 0xFFFFFFFF +#define I2S_I2SDATE_S 0 + + + + +#endif /*_SOC_I2S_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/i2s_struct.h b/tools/sdk/include/soc/include/soc/i2s_struct.h new file mode 100644 index 00000000000..aa92bb75fea --- /dev/null +++ b/tools/sdk/include/soc/include/soc/i2s_struct.h @@ -0,0 +1,472 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2S_STRUCT_H_ +#define _SOC_I2S_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + uint32_t reserved_0; + uint32_t reserved_4; + union { + struct { + uint32_t tx_reset: 1; + uint32_t rx_reset: 1; + uint32_t tx_fifo_reset: 1; + uint32_t rx_fifo_reset: 1; + uint32_t tx_start: 1; + uint32_t rx_start: 1; + uint32_t tx_slave_mod: 1; + uint32_t rx_slave_mod: 1; + uint32_t tx_right_first: 1; + uint32_t rx_right_first: 1; + uint32_t tx_msb_shift: 1; + uint32_t rx_msb_shift: 1; + uint32_t tx_short_sync: 1; + uint32_t rx_short_sync: 1; + uint32_t tx_mono: 1; + uint32_t rx_mono: 1; + uint32_t tx_msb_right: 1; + uint32_t rx_msb_right: 1; + uint32_t sig_loopback: 1; + uint32_t reserved19: 13; + }; + uint32_t val; + } conf; + union { + struct { + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t take_data: 1; + uint32_t put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t tx_bck_in_delay: 2; + uint32_t tx_ws_in_delay: 2; + uint32_t rx_bck_in_delay: 2; + uint32_t rx_ws_in_delay: 2; + uint32_t rx_sd_in_delay: 2; + uint32_t tx_bck_out_delay: 2; + uint32_t tx_ws_out_delay: 2; + uint32_t tx_sd_out_delay: 2; + uint32_t rx_ws_out_delay: 2; + uint32_t rx_bck_out_delay: 2; + uint32_t tx_dsync_sw: 1; + uint32_t rx_dsync_sw: 1; + uint32_t data_enable_delay: 2; + uint32_t tx_bck_in_inv: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } timing; + union { + struct { + uint32_t rx_data_num: 6; + uint32_t tx_data_num: 6; + uint32_t dscr_en: 1; + uint32_t tx_fifo_mod: 3; + uint32_t rx_fifo_mod: 3; + uint32_t tx_fifo_mod_force_en: 1; + uint32_t rx_fifo_mod_force_en: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } fifo_conf; + uint32_t rx_eof_num; + uint32_t conf_single_data; + union { + struct { + uint32_t tx_chan_mod: 3; + uint32_t rx_chan_mod: 2; + uint32_t reserved5: 27; + }; + uint32_t val; + } conf_chan; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } out_link; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } in_link; + uint32_t out_eof_des_addr; + uint32_t in_eof_des_addr; + uint32_t out_eof_bfr_des_addr; + union { + struct { + uint32_t mode: 3; + uint32_t reserved3: 1; + uint32_t addr: 2; + uint32_t reserved6: 26; + }; + uint32_t val; + } ahb_test; + uint32_t in_link_dscr; + uint32_t in_link_dscr_bf0; + uint32_t in_link_dscr_bf1; + uint32_t out_link_dscr; + uint32_t out_link_dscr_bf0; + uint32_t out_link_dscr_bf1; + union { + struct { + uint32_t in_rst: 1; + uint32_t out_rst: 1; + uint32_t ahbm_fifo_rst: 1; + uint32_t ahbm_rst: 1; + uint32_t out_loop_test: 1; + uint32_t in_loop_test: 1; + uint32_t out_auto_wrback: 1; + uint32_t out_no_restart_clr: 1; + uint32_t out_eof_mode: 1; + uint32_t outdscr_burst_en: 1; + uint32_t indscr_burst_en: 1; + uint32_t out_data_burst_en: 1; + uint32_t check_owner: 1; + uint32_t mem_trans_en: 1; + uint32_t reserved14: 18; + }; + uint32_t val; + } lc_conf; + union { + struct { + uint32_t wdata: 9; + uint32_t reserved9: 7; + uint32_t push: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } out_fifo_push; + union { + struct { + uint32_t rdata: 12; + uint32_t reserved12: 4; + uint32_t pop: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } in_fifo_pop; + uint32_t lc_state0; + uint32_t lc_state1; + union { + struct { + uint32_t fifo_timeout: 8; + uint32_t fifo_timeout_shift: 3; + uint32_t fifo_timeout_ena: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } lc_hung_conf; + uint32_t reserved_78; + uint32_t reserved_7c; + union { + struct { + uint32_t y_max:16; + uint32_t y_min:16; + }; + uint32_t val; + } cvsd_conf0; + union { + struct { + uint32_t sigma_max:16; + uint32_t sigma_min:16; + }; + uint32_t val; + } cvsd_conf1; + union { + struct { + uint32_t cvsd_k: 3; + uint32_t cvsd_j: 3; + uint32_t cvsd_beta: 10; + uint32_t cvsd_h: 3; + uint32_t reserved19:13; + }; + uint32_t val; + } cvsd_conf2; + union { + struct { + uint32_t good_pack_max: 6; + uint32_t n_err_seg: 3; + uint32_t shift_rate: 3; + uint32_t max_slide_sample: 8; + uint32_t pack_len_8k: 5; + uint32_t n_min_err: 3; + uint32_t reserved28: 4; + }; + uint32_t val; + } plc_conf0; + union { + struct { + uint32_t bad_cef_atten_para: 8; + uint32_t bad_cef_atten_para_shift: 4; + uint32_t bad_ola_win2_para_shift: 4; + uint32_t bad_ola_win2_para: 8; + uint32_t slide_win_len: 8; + }; + uint32_t val; + } plc_conf1; + union { + struct { + uint32_t cvsd_seg_mod: 2; + uint32_t min_period: 5; + uint32_t reserved7: 25; + }; + uint32_t val; + } plc_conf2; + union { + struct { + uint32_t en: 1; + uint32_t chan_mod: 1; + uint32_t cvsd_dec_pack_err: 1; + uint32_t cvsd_pack_len_8k: 5; + uint32_t cvsd_inf_en: 1; + uint32_t cvsd_dec_start: 1; + uint32_t cvsd_dec_reset: 1; + uint32_t plc_en: 1; + uint32_t plc2dma_en: 1; + uint32_t reserved13: 19; + }; + uint32_t val; + } esco_conf0; + union { + struct { + uint32_t with_en: 1; + uint32_t no_en: 1; + uint32_t cvsd_enc_start: 1; + uint32_t cvsd_enc_reset: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } sco_conf0; + union { + struct { + uint32_t tx_pcm_conf: 3; + uint32_t tx_pcm_bypass: 1; + uint32_t rx_pcm_conf: 3; + uint32_t rx_pcm_bypass: 1; + uint32_t tx_stop_en: 1; + uint32_t tx_zeros_rm_en: 1; + uint32_t reserved10: 22; + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t fifo_force_pd: 1; + uint32_t fifo_force_pu: 1; + uint32_t plc_mem_force_pd: 1; + uint32_t plc_mem_force_pu: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } pd_conf; + union { + struct { + uint32_t camera_en: 1; + uint32_t lcd_tx_wrx2_en: 1; + uint32_t lcd_tx_sdx2_en: 1; + uint32_t data_enable_test_en: 1; + uint32_t data_enable: 1; + uint32_t lcd_en: 1; + uint32_t ext_adc_start_en: 1; + uint32_t inter_valid_en: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } conf2; + union { + struct { + uint32_t clkm_div_num: 8; + uint32_t clkm_div_b: 6; + uint32_t clkm_div_a: 6; + uint32_t clk_en: 1; + uint32_t clka_en: 1; + uint32_t reserved22: 10; + }; + uint32_t val; + } clkm_conf; + union { + struct { + uint32_t tx_bck_div_num: 6; + uint32_t rx_bck_div_num: 6; + uint32_t tx_bits_mod: 6; + uint32_t rx_bits_mod: 6; + uint32_t reserved24: 8; + }; + uint32_t val; + } sample_rate_conf; + union { + struct { + uint32_t tx_pdm_en: 1; + uint32_t rx_pdm_en: 1; + uint32_t pcm2pdm_conv_en: 1; + uint32_t pdm2pcm_conv_en: 1; + uint32_t tx_sinc_osr2: 4; + uint32_t tx_prescale: 8; + uint32_t tx_hp_in_shift: 2; + uint32_t tx_lp_in_shift: 2; + uint32_t tx_sinc_in_shift: 2; + uint32_t tx_sigmadelta_in_shift: 2; + uint32_t rx_sinc_dsr_16_en: 1; + uint32_t txhp_bypass: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } pdm_conf; + union { + struct { + uint32_t tx_pdm_fs: 10; + uint32_t tx_pdm_fp: 10; + uint32_t reserved20:12; + }; + uint32_t val; + } pdm_freq_conf; + union { + struct { + uint32_t tx_idle: 1; + uint32_t tx_fifo_reset_back: 1; + uint32_t rx_fifo_reset_back: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } state; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ +} i2s_dev_t; +extern i2s_dev_t I2S0; +extern i2s_dev_t I2S1; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_I2S_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/io_mux_reg.h b/tools/sdk/include/soc/include/soc/io_mux_reg.h new file mode 100644 index 00000000000..25978b326ff --- /dev/null +++ b/tools/sdk/include/soc/include/soc/io_mux_reg.h @@ -0,0 +1,382 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_IO_MUX_REG_H_ +#define _SOC_IO_MUX_REG_H_ + +#include "soc.h" + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); + +/* + * @attention + * The PIN_PULL[UP|DWN]_[EN|DIS]() functions used to exist as macros in previous SDK versions. + * Unfortunately, however, they do not work for some GPIOs on the ESP32 chip, which needs pullups + * and -downs turned on and off through RTC registers. The functions still exist for compatibility + * with older code, but are marked as deprecated in order to generate a warning. + * Please replace them in this fashion: (make sure to include driver/gpio.h as well) + * PIN_PULLUP_EN(GPIO_PIN_MUX_REG[x]) -> gpio_pullup_en(x) + * PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[x]) -> gpio_pullup_dis(x) + * PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[x]) -> gpio_pulldown_en(x) + * PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[x]) -> gpio_pulldown_dis(x) + * +*/ +static inline void __attribute__ ((deprecated)) PIN_PULLUP_DIS(uint32_t PIN_NAME) +{ + REG_CLR_BIT(PIN_NAME, FUN_PU); +} + +static inline void __attribute__ ((deprecated)) PIN_PULLUP_EN(uint32_t PIN_NAME) +{ + REG_SET_BIT(PIN_NAME, FUN_PU); +} + +static inline void __attribute__ ((deprecated)) PIN_PULLDWN_DIS(uint32_t PIN_NAME) +{ + REG_CLR_BIT(PIN_NAME, FUN_PD); +} + +static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME) +{ + REG_SET_BIT(PIN_NAME, FUN_PD); +} + + +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define PIN_FUNC_GPIO 2 + +#define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00) +#define CLK_OUT3 0xf +#define CLK_OUT3_V CLK_OUT3 +#define CLK_OUT3_S 8 +#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) +#define CLK_OUT2 0xf +#define CLK_OUT2_V CLK_OUT2 +#define CLK_OUT2_S 4 +#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) +#define CLK_OUT1 0xf +#define CLK_OUT1_V CLK_OUT1 +#define CLK_OUT1_S 0 +#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) + +#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U +#define FUNC_GPIO0_EMAC_TX_CLK 5 +#define FUNC_GPIO0_GPIO0 2 +#define FUNC_GPIO0_CLK_OUT1 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U0TXD_U +#define FUNC_U0TXD_EMAC_RXD2 5 +#define FUNC_U0TXD_GPIO1 2 +#define FUNC_U0TXD_CLK_OUT3 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40) +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U +#define FUNC_GPIO2_SD_DATA0 4 +#define FUNC_GPIO2_HS2_DATA0 3 +#define FUNC_GPIO2_GPIO2 2 +#define FUNC_GPIO2_HSPIWP 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U0RXD_U +#define FUNC_U0RXD_GPIO3 2 +#define FUNC_U0RXD_CLK_OUT2 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48) +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U +#define FUNC_GPIO4_EMAC_TX_ER 5 +#define FUNC_GPIO4_SD_DATA1 4 +#define FUNC_GPIO4_HS2_DATA1 3 +#define FUNC_GPIO4_GPIO4 2 +#define FUNC_GPIO4_HSPIHD 1 +#define FUNC_GPIO4_GPIO4_0 0 + +#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c) +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U +#define FUNC_GPIO5_EMAC_RX_CLK 5 +#define FUNC_GPIO5_HS1_DATA6 3 +#define FUNC_GPIO5_GPIO5 2 +#define FUNC_GPIO5_VSPICS0 1 +#define FUNC_GPIO5_GPIO5_0 0 + +#define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60) +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_SD_CLK_U +#define FUNC_SD_CLK_U1CTS 4 +#define FUNC_SD_CLK_HS1_CLK 3 +#define FUNC_SD_CLK_GPIO6 2 +#define FUNC_SD_CLK_SPICLK 1 +#define FUNC_SD_CLK_SD_CLK 0 + +#define PERIPHS_IO_MUX_SD_DATA0_U (DR_REG_IO_MUX_BASE +0x64) +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_SD_DATA0_U +#define FUNC_SD_DATA0_U2RTS 4 +#define FUNC_SD_DATA0_HS1_DATA0 3 +#define FUNC_SD_DATA0_GPIO7 2 +#define FUNC_SD_DATA0_SPIQ 1 +#define FUNC_SD_DATA0_SD_DATA0 0 + +#define PERIPHS_IO_MUX_SD_DATA1_U (DR_REG_IO_MUX_BASE +0x68) +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_SD_DATA1_U +#define FUNC_SD_DATA1_U2CTS 4 +#define FUNC_SD_DATA1_HS1_DATA1 3 +#define FUNC_SD_DATA1_GPIO8 2 +#define FUNC_SD_DATA1_SPID 1 +#define FUNC_SD_DATA1_SD_DATA1 0 + +#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54) +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_SD_DATA2_U +#define FUNC_SD_DATA2_U1RXD 4 +#define FUNC_SD_DATA2_HS1_DATA2 3 +#define FUNC_SD_DATA2_GPIO9 2 +#define FUNC_SD_DATA2_SPIHD 1 +#define FUNC_SD_DATA2_SD_DATA2 0 + +#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58) +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_SD_DATA3_U +#define FUNC_SD_DATA3_U1TXD 4 +#define FUNC_SD_DATA3_HS1_DATA3 3 +#define FUNC_SD_DATA3_GPIO10 2 +#define FUNC_SD_DATA3_SPIWP 1 +#define FUNC_SD_DATA3_SD_DATA3 0 + +#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c) +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_SD_CMD_U +#define FUNC_SD_CMD_U1RTS 4 +#define FUNC_SD_CMD_HS1_CMD 3 +#define FUNC_SD_CMD_GPIO11 2 +#define FUNC_SD_CMD_SPICS0 1 +#define FUNC_SD_CMD_SD_CMD 0 + +#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34) +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_MTDI_U +#define FUNC_MTDI_EMAC_TXD3 5 +#define FUNC_MTDI_SD_DATA2 4 +#define FUNC_MTDI_HS2_DATA2 3 +#define FUNC_MTDI_GPIO12 2 +#define FUNC_MTDI_HSPIQ 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38) +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_MTCK_U +#define FUNC_MTCK_EMAC_RX_ER 5 +#define FUNC_MTCK_SD_DATA3 4 +#define FUNC_MTCK_HS2_DATA3 3 +#define FUNC_MTCK_GPIO13 2 +#define FUNC_MTCK_HSPID 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30) +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_MTMS_U +#define FUNC_MTMS_EMAC_TXD2 5 +#define FUNC_MTMS_SD_CLK 4 +#define FUNC_MTMS_HS2_CLK 3 +#define FUNC_MTMS_GPIO14 2 +#define FUNC_MTMS_HSPICLK 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c) +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_MTDO_U +#define FUNC_MTDO_EMAC_RXD3 5 +#define FUNC_MTDO_SD_CMD 4 +#define FUNC_MTDO_HS2_CMD 3 +#define FUNC_MTDO_GPIO15 2 +#define FUNC_MTDO_HSPICS0 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c) +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_GPIO16_U +#define FUNC_GPIO16_EMAC_CLK_OUT 5 +#define FUNC_GPIO16_U2RXD 4 +#define FUNC_GPIO16_HS1_DATA4 3 +#define FUNC_GPIO16_GPIO16 2 +#define FUNC_GPIO16_GPIO16_0 0 + +#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50) +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_GPIO17_U +#define FUNC_GPIO17_EMAC_CLK_OUT_180 5 +#define FUNC_GPIO17_U2TXD 4 +#define FUNC_GPIO17_HS1_DATA5 3 +#define FUNC_GPIO17_GPIO17 2 +#define FUNC_GPIO17_GPIO17_0 0 + +#define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70) +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U +#define FUNC_GPIO18_HS1_DATA7 3 +#define FUNC_GPIO18_GPIO18 2 +#define FUNC_GPIO18_VSPICLK 1 +#define FUNC_GPIO18_GPIO18_0 0 + +#define PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74) +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U +#define FUNC_GPIO19_EMAC_TXD0 5 +#define FUNC_GPIO19_U0CTS 3 +#define FUNC_GPIO19_GPIO19 2 +#define FUNC_GPIO19_VSPIQ 1 +#define FUNC_GPIO19_GPIO19_0 0 + +#define PERIPHS_IO_MUX_GPIO20_U (DR_REG_IO_MUX_BASE +0x78) +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U +#define FUNC_GPIO20_GPIO20 2 +#define FUNC_GPIO20_GPIO20_0 0 + +#define PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c) +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U +#define FUNC_GPIO21_EMAC_TX_EN 5 +#define FUNC_GPIO21_GPIO21 2 +#define FUNC_GPIO21_VSPIHD 1 +#define FUNC_GPIO21_GPIO21_0 0 + +#define PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80) +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_GPIO22_U +#define FUNC_GPIO22_EMAC_TXD1 5 +#define FUNC_GPIO22_U0RTS 3 +#define FUNC_GPIO22_GPIO22 2 +#define FUNC_GPIO22_VSPIWP 1 +#define FUNC_GPIO22_GPIO22_0 0 + +#define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c) +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U +#define FUNC_GPIO23_HS1_STROBE 3 +#define FUNC_GPIO23_GPIO23 2 +#define FUNC_GPIO23_VSPID 1 +#define FUNC_GPIO23_GPIO23_0 0 + +#define PERIPHS_IO_MUX_GPIO24_U (DR_REG_IO_MUX_BASE +0x90) +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U +#define FUNC_GPIO24_GPIO24 2 +#define FUNC_GPIO24_GPIO24_0 0 + +#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24) +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U +#define FUNC_GPIO25_EMAC_RXD0 5 +#define FUNC_GPIO25_GPIO25 2 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28) +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_GPIO26_U +#define FUNC_GPIO26_EMAC_RXD1 5 +#define FUNC_GPIO26_GPIO26 2 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c) +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_GPIO27_U +#define FUNC_GPIO27_EMAC_RX_DV 5 +#define FUNC_GPIO27_GPIO27 2 +#define FUNC_GPIO27_GPIO27_0 0 + +#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c) +#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_GPIO32_U +#define FUNC_GPIO32_GPIO32 2 +#define FUNC_GPIO32_GPIO32_0 0 + +#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20) +#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U +#define FUNC_GPIO33_GPIO33 2 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14) +#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U +#define FUNC_GPIO34_GPIO34 2 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18) +#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U +#define FUNC_GPIO35_GPIO35 2 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04) +#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U +#define FUNC_GPIO36_GPIO36 2 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08) +#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U +#define FUNC_GPIO37_GPIO37 2 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c) +#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U +#define FUNC_GPIO38_GPIO38 2 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10) +#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_GPIO39_U +#define FUNC_GPIO39_GPIO39 2 +#define FUNC_GPIO39_GPIO39_0 0 + +#endif /* _SOC_IO_MUX_REG_H_ */ diff --git a/tools/sdk/include/soc/include/soc/ledc_reg.h b/tools/sdk/include/soc/include/soc/ledc_reg.h new file mode 100644 index 00000000000..559be87361e --- /dev/null +++ b/tools/sdk/include/soc/include/soc/ledc_reg.h @@ -0,0 +1,2463 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_REG_H_ +#define _SOC_LEDC_REG_H_ + + +#include "soc.h" +#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) +/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: This bit is clock gating control signal. when software config + LED_PWM internal registers it controls the register clock.*/ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (BIT(31)) +#define LEDC_CLK_EN_V 0x1 +#define LEDC_CLK_EN_S 31 +/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel0 is off.*/ +#define LEDC_IDLE_LV_HSCH0 (BIT(3)) +#define LEDC_IDLE_LV_HSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH0_V 0x1 +#define LEDC_IDLE_LV_HSCH0_S 3 +/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel0*/ +#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH0_S 2 +/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH0 0x00000003 +#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S)) +#define LEDC_TIMER_SEL_HSCH0_V 0x3 +#define LEDC_TIMER_SEL_HSCH0_S 0 + +#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) +/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/ +#define LEDC_HPOINT_HSCH0 0x000FFFFF +#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S)) +#define LEDC_HPOINT_HSCH0_V 0xFFFFF +#define LEDC_HPOINT_HSCH0_S 0 + +#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) +/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH0 0x01FFFFFF +#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) +#define LEDC_DUTY_HSCH0_V 0x1FFFFFF +#define LEDC_DUTY_HSCH0_S 0 + +#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) +/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 + has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH0 (BIT(31)) +#define LEDC_DUTY_START_HSCH0_M (BIT(31)) +#define LEDC_DUTY_START_HSCH0_V 0x1 +#define LEDC_DUTY_START_HSCH0_S 31 +/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel0.*/ +#define LEDC_DUTY_INC_HSCH0 (BIT(30)) +#define LEDC_DUTY_INC_HSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH0_V 0x1 +#define LEDC_DUTY_INC_HSCH0_S 30 +/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel0.*/ +#define LEDC_DUTY_NUM_HSCH0 0x000003FF +#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S)) +#define LEDC_DUTY_NUM_HSCH0_V 0x3FF +#define LEDC_DUTY_NUM_HSCH0_S 20 +/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch0 cycles for high speed channel0.*/ +#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S)) +#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH0_S 10 +/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel0.*/ +#define LEDC_DUTY_SCALE_HSCH0 0x000003FF +#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S)) +#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH0_S 0 + +#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) +/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel0.*/ +#define LEDC_DUTY_HSCH0 0x01FFFFFF +#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) +#define LEDC_DUTY_HSCH0_V 0x1FFFFFF +#define LEDC_DUTY_HSCH0_S 0 + +#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) +/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel1 is off.*/ +#define LEDC_IDLE_LV_HSCH1 (BIT(3)) +#define LEDC_IDLE_LV_HSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH1_V 0x1 +#define LEDC_IDLE_LV_HSCH1_S 3 +/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel1*/ +#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH1_S 2 +/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH1 0x00000003 +#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S)) +#define LEDC_TIMER_SEL_HSCH1_V 0x3 +#define LEDC_TIMER_SEL_HSCH1_S 0 + +#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) +/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/ +#define LEDC_HPOINT_HSCH1 0x000FFFFF +#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S)) +#define LEDC_HPOINT_HSCH1_V 0xFFFFF +#define LEDC_HPOINT_HSCH1_S 0 + +#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) +/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH1 0x01FFFFFF +#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) +#define LEDC_DUTY_HSCH1_V 0x1FFFFFF +#define LEDC_DUTY_HSCH1_S 0 + +#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) +/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH1 (BIT(31)) +#define LEDC_DUTY_START_HSCH1_M (BIT(31)) +#define LEDC_DUTY_START_HSCH1_V 0x1 +#define LEDC_DUTY_START_HSCH1_S 31 +/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel1.*/ +#define LEDC_DUTY_INC_HSCH1 (BIT(30)) +#define LEDC_DUTY_INC_HSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH1_V 0x1 +#define LEDC_DUTY_INC_HSCH1_S 30 +/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel1.*/ +#define LEDC_DUTY_NUM_HSCH1 0x000003FF +#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S)) +#define LEDC_DUTY_NUM_HSCH1_V 0x3FF +#define LEDC_DUTY_NUM_HSCH1_S 20 +/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch1 cycles for high speed channel1.*/ +#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S)) +#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH1_S 10 +/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel1.*/ +#define LEDC_DUTY_SCALE_HSCH1 0x000003FF +#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S)) +#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH1_S 0 + +#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) +/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel1.*/ +#define LEDC_DUTY_HSCH1 0x01FFFFFF +#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) +#define LEDC_DUTY_HSCH1_V 0x1FFFFFF +#define LEDC_DUTY_HSCH1_S 0 + +#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) +/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel2 is off.*/ +#define LEDC_IDLE_LV_HSCH2 (BIT(3)) +#define LEDC_IDLE_LV_HSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH2_V 0x1 +#define LEDC_IDLE_LV_HSCH2_S 3 +/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel2*/ +#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH2_S 2 +/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH2 0x00000003 +#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S)) +#define LEDC_TIMER_SEL_HSCH2_V 0x3 +#define LEDC_TIMER_SEL_HSCH2_S 0 + +#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) +/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/ +#define LEDC_HPOINT_HSCH2 0x000FFFFF +#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S)) +#define LEDC_HPOINT_HSCH2_V 0xFFFFF +#define LEDC_HPOINT_HSCH2_S 0 + +#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) +/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH2 0x01FFFFFF +#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) +#define LEDC_DUTY_HSCH2_V 0x1FFFFFF +#define LEDC_DUTY_HSCH2_S 0 + +#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) +/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 + has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH2 (BIT(31)) +#define LEDC_DUTY_START_HSCH2_M (BIT(31)) +#define LEDC_DUTY_START_HSCH2_V 0x1 +#define LEDC_DUTY_START_HSCH2_S 31 +/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel2.*/ +#define LEDC_DUTY_INC_HSCH2 (BIT(30)) +#define LEDC_DUTY_INC_HSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH2_V 0x1 +#define LEDC_DUTY_INC_HSCH2_S 30 +/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel2.*/ +#define LEDC_DUTY_NUM_HSCH2 0x000003FF +#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S)) +#define LEDC_DUTY_NUM_HSCH2_V 0x3FF +#define LEDC_DUTY_NUM_HSCH2_S 20 +/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch2 cycles for high speed channel2.*/ +#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S)) +#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH2_S 10 +/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel2.*/ +#define LEDC_DUTY_SCALE_HSCH2 0x000003FF +#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S)) +#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH2_S 0 + +#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) +/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel2.*/ +#define LEDC_DUTY_HSCH2 0x01FFFFFF +#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) +#define LEDC_DUTY_HSCH2_V 0x1FFFFFF +#define LEDC_DUTY_HSCH2_S 0 + +#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) +/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel3 is off.*/ +#define LEDC_IDLE_LV_HSCH3 (BIT(3)) +#define LEDC_IDLE_LV_HSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH3_V 0x1 +#define LEDC_IDLE_LV_HSCH3_S 3 +/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel3*/ +#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH3_S 2 +/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH3 0x00000003 +#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S)) +#define LEDC_TIMER_SEL_HSCH3_V 0x3 +#define LEDC_TIMER_SEL_HSCH3_S 0 + +#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) +/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/ +#define LEDC_HPOINT_HSCH3 0x000FFFFF +#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S)) +#define LEDC_HPOINT_HSCH3_V 0xFFFFF +#define LEDC_HPOINT_HSCH3_S 0 + +#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) +/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH3 0x01FFFFFF +#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) +#define LEDC_DUTY_HSCH3_V 0x1FFFFFF +#define LEDC_DUTY_HSCH3_S 0 + +#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) +/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 + has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH3 (BIT(31)) +#define LEDC_DUTY_START_HSCH3_M (BIT(31)) +#define LEDC_DUTY_START_HSCH3_V 0x1 +#define LEDC_DUTY_START_HSCH3_S 31 +/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel3.*/ +#define LEDC_DUTY_INC_HSCH3 (BIT(30)) +#define LEDC_DUTY_INC_HSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH3_V 0x1 +#define LEDC_DUTY_INC_HSCH3_S 30 +/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel3.*/ +#define LEDC_DUTY_NUM_HSCH3 0x000003FF +#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S)) +#define LEDC_DUTY_NUM_HSCH3_V 0x3FF +#define LEDC_DUTY_NUM_HSCH3_S 20 +/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch3 cycles for high speed channel3.*/ +#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S)) +#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH3_S 10 +/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel3.*/ +#define LEDC_DUTY_SCALE_HSCH3 0x000003FF +#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S)) +#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH3_S 0 + +#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) +/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel3.*/ +#define LEDC_DUTY_HSCH3 0x01FFFFFF +#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) +#define LEDC_DUTY_HSCH3_V 0x1FFFFFF +#define LEDC_DUTY_HSCH3_S 0 + +#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) +/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel4 is off.*/ +#define LEDC_IDLE_LV_HSCH4 (BIT(3)) +#define LEDC_IDLE_LV_HSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH4_V 0x1 +#define LEDC_IDLE_LV_HSCH4_S 3 +/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel4*/ +#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH4_S 2 +/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH4 0x00000003 +#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S)) +#define LEDC_TIMER_SEL_HSCH4_V 0x3 +#define LEDC_TIMER_SEL_HSCH4_S 0 + +#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) +/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/ +#define LEDC_HPOINT_HSCH4 0x000FFFFF +#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S)) +#define LEDC_HPOINT_HSCH4_V 0xFFFFF +#define LEDC_HPOINT_HSCH4_S 0 + +#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) +/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH4 0x01FFFFFF +#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) +#define LEDC_DUTY_HSCH4_V 0x1FFFFFF +#define LEDC_DUTY_HSCH4_S 0 + +#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) +/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH4 (BIT(31)) +#define LEDC_DUTY_START_HSCH4_M (BIT(31)) +#define LEDC_DUTY_START_HSCH4_V 0x1 +#define LEDC_DUTY_START_HSCH4_S 31 +/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel4.*/ +#define LEDC_DUTY_INC_HSCH4 (BIT(30)) +#define LEDC_DUTY_INC_HSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH4_V 0x1 +#define LEDC_DUTY_INC_HSCH4_S 30 +/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel1.*/ +#define LEDC_DUTY_NUM_HSCH4 0x000003FF +#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S)) +#define LEDC_DUTY_NUM_HSCH4_V 0x3FF +#define LEDC_DUTY_NUM_HSCH4_S 20 +/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch4 cycles for high speed channel4.*/ +#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S)) +#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH4_S 10 +/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel4.*/ +#define LEDC_DUTY_SCALE_HSCH4 0x000003FF +#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S)) +#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH4_S 0 + +#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) +/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel4.*/ +#define LEDC_DUTY_HSCH4 0x01FFFFFF +#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) +#define LEDC_DUTY_HSCH4_V 0x1FFFFFF +#define LEDC_DUTY_HSCH4_S 0 + +#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) +/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel5 is off.*/ +#define LEDC_IDLE_LV_HSCH5 (BIT(3)) +#define LEDC_IDLE_LV_HSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH5_V 0x1 +#define LEDC_IDLE_LV_HSCH5_S 3 +/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel5.*/ +#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH5_S 2 +/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH5 0x00000003 +#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S)) +#define LEDC_TIMER_SEL_HSCH5_V 0x3 +#define LEDC_TIMER_SEL_HSCH5_S 0 + +#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) +/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/ +#define LEDC_HPOINT_HSCH5 0x000FFFFF +#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S)) +#define LEDC_HPOINT_HSCH5_V 0xFFFFF +#define LEDC_HPOINT_HSCH5_S 0 + +#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) +/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH5 0x01FFFFFF +#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) +#define LEDC_DUTY_HSCH5_V 0x1FFFFFF +#define LEDC_DUTY_HSCH5_S 0 + +#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) +/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5 + has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH5 (BIT(31)) +#define LEDC_DUTY_START_HSCH5_M (BIT(31)) +#define LEDC_DUTY_START_HSCH5_V 0x1 +#define LEDC_DUTY_START_HSCH5_S 31 +/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel5.*/ +#define LEDC_DUTY_INC_HSCH5 (BIT(30)) +#define LEDC_DUTY_INC_HSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH5_V 0x1 +#define LEDC_DUTY_INC_HSCH5_S 30 +/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel5.*/ +#define LEDC_DUTY_NUM_HSCH5 0x000003FF +#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S)) +#define LEDC_DUTY_NUM_HSCH5_V 0x3FF +#define LEDC_DUTY_NUM_HSCH5_S 20 +/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch5 cycles for high speed channel5.*/ +#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S)) +#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH5_S 10 +/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel5.*/ +#define LEDC_DUTY_SCALE_HSCH5 0x000003FF +#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S)) +#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH5_S 0 + +#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) +/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel5.*/ +#define LEDC_DUTY_HSCH5 0x01FFFFFF +#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) +#define LEDC_DUTY_HSCH5_V 0x1FFFFFF +#define LEDC_DUTY_HSCH5_S 0 + +#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) +/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel6 is off.*/ +#define LEDC_IDLE_LV_HSCH6 (BIT(3)) +#define LEDC_IDLE_LV_HSCH6_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH6_V 0x1 +#define LEDC_IDLE_LV_HSCH6_S 3 +/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel6*/ +#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH6_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH6_S 2 +/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH6 0x00000003 +#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S)) +#define LEDC_TIMER_SEL_HSCH6_V 0x3 +#define LEDC_TIMER_SEL_HSCH6_S 0 + +#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) +/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/ +#define LEDC_HPOINT_HSCH6 0x000FFFFF +#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S)) +#define LEDC_HPOINT_HSCH6_V 0xFFFFF +#define LEDC_HPOINT_HSCH6_S 0 + +#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) +/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH6 0x01FFFFFF +#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) +#define LEDC_DUTY_HSCH6_V 0x1FFFFFF +#define LEDC_DUTY_HSCH6_S 0 + +#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) +/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH6 (BIT(31)) +#define LEDC_DUTY_START_HSCH6_M (BIT(31)) +#define LEDC_DUTY_START_HSCH6_V 0x1 +#define LEDC_DUTY_START_HSCH6_S 31 +/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel6.*/ +#define LEDC_DUTY_INC_HSCH6 (BIT(30)) +#define LEDC_DUTY_INC_HSCH6_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH6_V 0x1 +#define LEDC_DUTY_INC_HSCH6_S 30 +/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel6.*/ +#define LEDC_DUTY_NUM_HSCH6 0x000003FF +#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S)) +#define LEDC_DUTY_NUM_HSCH6_V 0x3FF +#define LEDC_DUTY_NUM_HSCH6_S 20 +/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch6 cycles for high speed channel6.*/ +#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S)) +#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH6_S 10 +/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel6.*/ +#define LEDC_DUTY_SCALE_HSCH6 0x000003FF +#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S)) +#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH6_S 0 + +#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) +/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel6.*/ +#define LEDC_DUTY_HSCH6 0x01FFFFFF +#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) +#define LEDC_DUTY_HSCH6_V 0x1FFFFFF +#define LEDC_DUTY_HSCH6_S 0 + +#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) +/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel7 is off.*/ +#define LEDC_IDLE_LV_HSCH7 (BIT(3)) +#define LEDC_IDLE_LV_HSCH7_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH7_V 0x1 +#define LEDC_IDLE_LV_HSCH7_S 3 +/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel7.*/ +#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH7_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH7_S 2 +/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH7 0x00000003 +#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S)) +#define LEDC_TIMER_SEL_HSCH7_V 0x3 +#define LEDC_TIMER_SEL_HSCH7_S 0 + +#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) +/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/ +#define LEDC_HPOINT_HSCH7 0x000FFFFF +#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S)) +#define LEDC_HPOINT_HSCH7_V 0xFFFFF +#define LEDC_HPOINT_HSCH7_S 0 + +#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) +/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH7 0x01FFFFFF +#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) +#define LEDC_DUTY_HSCH7_V 0x1FFFFFF +#define LEDC_DUTY_HSCH7_S 0 + +#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) +/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH7 (BIT(31)) +#define LEDC_DUTY_START_HSCH7_M (BIT(31)) +#define LEDC_DUTY_START_HSCH7_V 0x1 +#define LEDC_DUTY_START_HSCH7_S 31 +/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel6.*/ +#define LEDC_DUTY_INC_HSCH7 (BIT(30)) +#define LEDC_DUTY_INC_HSCH7_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH7_V 0x1 +#define LEDC_DUTY_INC_HSCH7_S 30 +/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel6.*/ +#define LEDC_DUTY_NUM_HSCH7 0x000003FF +#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S)) +#define LEDC_DUTY_NUM_HSCH7_V 0x3FF +#define LEDC_DUTY_NUM_HSCH7_S 20 +/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch7 cycles for high speed channel7.*/ +#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S)) +#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH7_S 10 +/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel7.*/ +#define LEDC_DUTY_SCALE_HSCH7 0x000003FF +#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S)) +#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH7_S 0 + +#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) +/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel7.*/ +#define LEDC_DUTY_HSCH7 0x01FFFFFF +#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) +#define LEDC_DUTY_HSCH7_V 0x1FFFFFF +#define LEDC_DUTY_HSCH7_S 0 + +#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0) +/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY + for low speed channel0.*/ +#define LEDC_PARA_UP_LSCH0 (BIT(4)) +#define LEDC_PARA_UP_LSCH0_M (BIT(4)) +#define LEDC_PARA_UP_LSCH0_V 0x1 +#define LEDC_PARA_UP_LSCH0_S 4 +/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel0 is off.*/ +#define LEDC_IDLE_LV_LSCH0 (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_V 0x1 +#define LEDC_IDLE_LV_LSCH0_S 3 +/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel0.*/ +#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH0_S 2 +/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH0 0x00000003 +#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) +#define LEDC_TIMER_SEL_LSCH0_V 0x3 +#define LEDC_TIMER_SEL_LSCH0_S 0 + +#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4) +/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/ +#define LEDC_HPOINT_LSCH0 0x000FFFFF +#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) +#define LEDC_HPOINT_LSCH0_V 0xFFFFF +#define LEDC_HPOINT_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8) +/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC) +/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH0 (BIT(31)) +#define LEDC_DUTY_START_LSCH0_M (BIT(31)) +#define LEDC_DUTY_START_LSCH0_V 0x1 +#define LEDC_DUTY_START_LSCH0_S 31 +/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel6.*/ +#define LEDC_DUTY_INC_LSCH0 (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_V 0x1 +#define LEDC_DUTY_INC_LSCH0_S 30 +/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel6.*/ +#define LEDC_DUTY_NUM_LSCH0 0x000003FF +#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) +#define LEDC_DUTY_NUM_LSCH0_V 0x3FF +#define LEDC_DUTY_NUM_LSCH0_S 20 +/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch0 cycles for low speed channel0.*/ +#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) +#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH0_S 10 +/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel0.*/ +#define LEDC_DUTY_SCALE_LSCH0 0x000003FF +#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) +#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0) +/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel0.*/ +#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4) +/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY + for low speed channel1.*/ +#define LEDC_PARA_UP_LSCH1 (BIT(4)) +#define LEDC_PARA_UP_LSCH1_M (BIT(4)) +#define LEDC_PARA_UP_LSCH1_V 0x1 +#define LEDC_PARA_UP_LSCH1_S 4 +/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel1 is off.*/ +#define LEDC_IDLE_LV_LSCH1 (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_V 0x1 +#define LEDC_IDLE_LV_LSCH1_S 3 +/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel1.*/ +#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH1_S 2 +/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH1 0x00000003 +#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) +#define LEDC_TIMER_SEL_LSCH1_V 0x3 +#define LEDC_TIMER_SEL_LSCH1_S 0 + +#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8) +/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/ +#define LEDC_HPOINT_LSCH1 0x000FFFFF +#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) +#define LEDC_HPOINT_LSCH1_V 0xFFFFF +#define LEDC_HPOINT_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC) +/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0) +/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH1 (BIT(31)) +#define LEDC_DUTY_START_LSCH1_M (BIT(31)) +#define LEDC_DUTY_START_LSCH1_V 0x1 +#define LEDC_DUTY_START_LSCH1_S 31 +/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel1.*/ +#define LEDC_DUTY_INC_LSCH1 (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_V 0x1 +#define LEDC_DUTY_INC_LSCH1_S 30 +/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel1.*/ +#define LEDC_DUTY_NUM_LSCH1 0x000003FF +#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) +#define LEDC_DUTY_NUM_LSCH1_V 0x3FF +#define LEDC_DUTY_NUM_LSCH1_S 20 +/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch1 cycles for low speed channel1.*/ +#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) +#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH1_S 10 +/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel1.*/ +#define LEDC_DUTY_SCALE_LSCH1 0x000003FF +#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) +#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4) +/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel1.*/ +#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8) +/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY + for low speed channel2.*/ +#define LEDC_PARA_UP_LSCH2 (BIT(4)) +#define LEDC_PARA_UP_LSCH2_M (BIT(4)) +#define LEDC_PARA_UP_LSCH2_V 0x1 +#define LEDC_PARA_UP_LSCH2_S 4 +/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel2 is off.*/ +#define LEDC_IDLE_LV_LSCH2 (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_V 0x1 +#define LEDC_IDLE_LV_LSCH2_S 3 +/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel2.*/ +#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH2_S 2 +/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH2 0x00000003 +#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) +#define LEDC_TIMER_SEL_LSCH2_V 0x3 +#define LEDC_TIMER_SEL_LSCH2_S 0 + +#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC) +/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/ +#define LEDC_HPOINT_LSCH2 0x000FFFFF +#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) +#define LEDC_HPOINT_LSCH2_V 0xFFFFF +#define LEDC_HPOINT_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0) +/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4) +/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 + has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH2 (BIT(31)) +#define LEDC_DUTY_START_LSCH2_M (BIT(31)) +#define LEDC_DUTY_START_LSCH2_V 0x1 +#define LEDC_DUTY_START_LSCH2_S 31 +/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel2.*/ +#define LEDC_DUTY_INC_LSCH2 (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_V 0x1 +#define LEDC_DUTY_INC_LSCH2_S 30 +/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel2.*/ +#define LEDC_DUTY_NUM_LSCH2 0x000003FF +#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) +#define LEDC_DUTY_NUM_LSCH2_V 0x3FF +#define LEDC_DUTY_NUM_LSCH2_S 20 +/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch2 cycles for low speed channel2.*/ +#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) +#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH2_S 10 +/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel2.*/ +#define LEDC_DUTY_SCALE_LSCH2 0x000003FF +#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) +#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8) +/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel2.*/ +#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC) +/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY + for low speed channel3.*/ +#define LEDC_PARA_UP_LSCH3 (BIT(4)) +#define LEDC_PARA_UP_LSCH3_M (BIT(4)) +#define LEDC_PARA_UP_LSCH3_V 0x1 +#define LEDC_PARA_UP_LSCH3_S 4 +/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel3 is off.*/ +#define LEDC_IDLE_LV_LSCH3 (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_V 0x1 +#define LEDC_IDLE_LV_LSCH3_S 3 +/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel3.*/ +#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH3_S 2 +/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH3 0x00000003 +#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) +#define LEDC_TIMER_SEL_LSCH3_V 0x3 +#define LEDC_TIMER_SEL_LSCH3_S 0 + +#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0) +/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/ +#define LEDC_HPOINT_LSCH3 0x000FFFFF +#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) +#define LEDC_HPOINT_LSCH3_V 0xFFFFF +#define LEDC_HPOINT_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4) +/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8) +/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 + has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH3 (BIT(31)) +#define LEDC_DUTY_START_LSCH3_M (BIT(31)) +#define LEDC_DUTY_START_LSCH3_V 0x1 +#define LEDC_DUTY_START_LSCH3_S 31 +/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel3.*/ +#define LEDC_DUTY_INC_LSCH3 (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_V 0x1 +#define LEDC_DUTY_INC_LSCH3_S 30 +/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel3.*/ +#define LEDC_DUTY_NUM_LSCH3 0x000003FF +#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) +#define LEDC_DUTY_NUM_LSCH3_V 0x3FF +#define LEDC_DUTY_NUM_LSCH3_S 20 +/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch3 cycles for low speed channel3.*/ +#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) +#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH3_S 10 +/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel3.*/ +#define LEDC_DUTY_SCALE_LSCH3 0x000003FF +#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) +#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC) +/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel3.*/ +#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0) +/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY + for low speed channel4.*/ +#define LEDC_PARA_UP_LSCH4 (BIT(4)) +#define LEDC_PARA_UP_LSCH4_M (BIT(4)) +#define LEDC_PARA_UP_LSCH4_V 0x1 +#define LEDC_PARA_UP_LSCH4_S 4 +/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel4 is off.*/ +#define LEDC_IDLE_LV_LSCH4 (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_V 0x1 +#define LEDC_IDLE_LV_LSCH4_S 3 +/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel4.*/ +#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH4_S 2 +/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH4 0x00000003 +#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) +#define LEDC_TIMER_SEL_LSCH4_V 0x3 +#define LEDC_TIMER_SEL_LSCH4_S 0 + +#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4) +/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/ +#define LEDC_HPOINT_LSCH4 0x000FFFFF +#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) +#define LEDC_HPOINT_LSCH4_V 0xFFFFF +#define LEDC_HPOINT_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8) +/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC) +/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH4 (BIT(31)) +#define LEDC_DUTY_START_LSCH4_M (BIT(31)) +#define LEDC_DUTY_START_LSCH4_V 0x1 +#define LEDC_DUTY_START_LSCH4_S 31 +/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel4.*/ +#define LEDC_DUTY_INC_LSCH4 (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_V 0x1 +#define LEDC_DUTY_INC_LSCH4_S 30 +/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel4.*/ +#define LEDC_DUTY_NUM_LSCH4 0x000003FF +#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) +#define LEDC_DUTY_NUM_LSCH4_V 0x3FF +#define LEDC_DUTY_NUM_LSCH4_S 20 +/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch4 cycles for low speed channel4.*/ +#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) +#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH4_S 10 +/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel4.*/ +#define LEDC_DUTY_SCALE_LSCH4 0x000003FF +#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) +#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100) +/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel4.*/ +#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104) +/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY + for low speed channel5.*/ +#define LEDC_PARA_UP_LSCH5 (BIT(4)) +#define LEDC_PARA_UP_LSCH5_M (BIT(4)) +#define LEDC_PARA_UP_LSCH5_V 0x1 +#define LEDC_PARA_UP_LSCH5_S 4 +/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel5 is off.*/ +#define LEDC_IDLE_LV_LSCH5 (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_V 0x1 +#define LEDC_IDLE_LV_LSCH5_S 3 +/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel5.*/ +#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH5_S 2 +/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH5 0x00000003 +#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) +#define LEDC_TIMER_SEL_LSCH5_V 0x3 +#define LEDC_TIMER_SEL_LSCH5_S 0 + +#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108) +/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/ +#define LEDC_HPOINT_LSCH5 0x000FFFFF +#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) +#define LEDC_HPOINT_LSCH5_V 0xFFFFF +#define LEDC_HPOINT_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C) +/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110) +/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH5 (BIT(31)) +#define LEDC_DUTY_START_LSCH5_M (BIT(31)) +#define LEDC_DUTY_START_LSCH5_V 0x1 +#define LEDC_DUTY_START_LSCH5_S 31 +/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel5.*/ +#define LEDC_DUTY_INC_LSCH5 (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_V 0x1 +#define LEDC_DUTY_INC_LSCH5_S 30 +/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel5.*/ +#define LEDC_DUTY_NUM_LSCH5 0x000003FF +#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) +#define LEDC_DUTY_NUM_LSCH5_V 0x3FF +#define LEDC_DUTY_NUM_LSCH5_S 20 +/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch5 cycles for low speed channel4.*/ +#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) +#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH5_S 10 +/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel5.*/ +#define LEDC_DUTY_SCALE_LSCH5 0x000003FF +#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) +#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114) +/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel5.*/ +#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118) +/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY + for low speed channel6.*/ +#define LEDC_PARA_UP_LSCH6 (BIT(4)) +#define LEDC_PARA_UP_LSCH6_M (BIT(4)) +#define LEDC_PARA_UP_LSCH6_V 0x1 +#define LEDC_PARA_UP_LSCH6_S 4 +/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel6 is off.*/ +#define LEDC_IDLE_LV_LSCH6 (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_V 0x1 +#define LEDC_IDLE_LV_LSCH6_S 3 +/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel6.*/ +#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH6_S 2 +/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH6 0x00000003 +#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S)) +#define LEDC_TIMER_SEL_LSCH6_V 0x3 +#define LEDC_TIMER_SEL_LSCH6_S 0 + +#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C) +/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/ +#define LEDC_HPOINT_LSCH6 0x000FFFFF +#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S)) +#define LEDC_HPOINT_LSCH6_V 0xFFFFF +#define LEDC_HPOINT_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120) +/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124) +/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6 + has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH6 (BIT(31)) +#define LEDC_DUTY_START_LSCH6_M (BIT(31)) +#define LEDC_DUTY_START_LSCH6_V 0x1 +#define LEDC_DUTY_START_LSCH6_S 31 +/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel6.*/ +#define LEDC_DUTY_INC_LSCH6 (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_V 0x1 +#define LEDC_DUTY_INC_LSCH6_S 30 +/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel6.*/ +#define LEDC_DUTY_NUM_LSCH6 0x000003FF +#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S)) +#define LEDC_DUTY_NUM_LSCH6_V 0x3FF +#define LEDC_DUTY_NUM_LSCH6_S 20 +/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch6 cycles for low speed channel6.*/ +#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S)) +#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH6_S 10 +/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel6.*/ +#define LEDC_DUTY_SCALE_LSCH6 0x000003FF +#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S)) +#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128) +/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel6.*/ +#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C) +/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY + for low speed channel7.*/ +#define LEDC_PARA_UP_LSCH7 (BIT(4)) +#define LEDC_PARA_UP_LSCH7_M (BIT(4)) +#define LEDC_PARA_UP_LSCH7_V 0x1 +#define LEDC_PARA_UP_LSCH7_S 4 +/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel7 is off.*/ +#define LEDC_IDLE_LV_LSCH7 (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_V 0x1 +#define LEDC_IDLE_LV_LSCH7_S 3 +/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel7.*/ +#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH7_S 2 +/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH7 0x00000003 +#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S)) +#define LEDC_TIMER_SEL_LSCH7_V 0x3 +#define LEDC_TIMER_SEL_LSCH7_S 0 + +#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130) +/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/ +#define LEDC_HPOINT_LSCH7 0x000FFFFF +#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S)) +#define LEDC_HPOINT_LSCH7_V 0xFFFFF +#define LEDC_HPOINT_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134) +/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138) +/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH7 (BIT(31)) +#define LEDC_DUTY_START_LSCH7_M (BIT(31)) +#define LEDC_DUTY_START_LSCH7_V 0x1 +#define LEDC_DUTY_START_LSCH7_S 31 +/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel4.*/ +#define LEDC_DUTY_INC_LSCH7 (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_V 0x1 +#define LEDC_DUTY_INC_LSCH7_S 30 +/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel4.*/ +#define LEDC_DUTY_NUM_LSCH7 0x000003FF +#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S)) +#define LEDC_DUTY_NUM_LSCH7_V 0x3FF +#define LEDC_DUTY_NUM_LSCH7_S 20 +/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch7 cycles for low speed channel7.*/ +#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S)) +#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH7_S 10 +/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel7.*/ +#define LEDC_DUTY_SCALE_LSCH7 0x000003FF +#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S)) +#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C) +/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel7.*/ +#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140) +/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer0. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER0 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER0_V 0x1 +#define LEDC_TICK_SEL_HSTIMER0_S 25 +/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER0_RST (BIT(24)) +#define LEDC_HSTIMER0_RST_M (BIT(24)) +#define LEDC_HSTIMER0_RST_V 0x1 +#define LEDC_HSTIMER0_RST_S 24 +/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer0*/ +#define LEDC_HSTIMER0_PAUSE (BIT(23)) +#define LEDC_HSTIMER0_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER0_PAUSE_V 0x1 +#define LEDC_HSTIMER0_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer0 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S)) +#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER0_S 5 +/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER0_DUTY_RES 0x0000001F +#define LEDC_HSTIMER0_DUTY_RES_M ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S)) +#define LEDC_HSTIMER0_DUTY_RES_V 0x1F +#define LEDC_HSTIMER0_DUTY_RES_S 0 +// Keep the definitions below to be compatible with previous version +#define LEDC_HSTIMER0_LIM LEDC_HSTIMER0_DUTY_RES +#define LEDC_HSTIMER0_LIM_M LEDC_HSTIMER0_DUTY_RES_M +#define LEDC_HSTIMER0_LIM_V LEDC_HSTIMER0_DUTY_RES_V +#define LEDC_HSTIMER0_LIM_S LEDC_HSTIMER0_DUTY_RES_S + +#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144) +/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer0*/ +#define LEDC_HSTIMER0_CNT 0x000FFFFF +#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S)) +#define LEDC_HSTIMER0_CNT_V 0xFFFFF +#define LEDC_HSTIMER0_CNT_S 0 + +#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148) +/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer1. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER1 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER1_V 0x1 +#define LEDC_TICK_SEL_HSTIMER1_S 25 +/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER1_RST (BIT(24)) +#define LEDC_HSTIMER1_RST_M (BIT(24)) +#define LEDC_HSTIMER1_RST_V 0x1 +#define LEDC_HSTIMER1_RST_S 24 +/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer1*/ +#define LEDC_HSTIMER1_PAUSE (BIT(23)) +#define LEDC_HSTIMER1_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER1_PAUSE_V 0x1 +#define LEDC_HSTIMER1_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer1 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S)) +#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER1_S 5 +/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER1_DUTY_RES 0x0000001F +#define LEDC_HSTIMER1_DUTY_RES_M ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S)) +#define LEDC_HSTIMER1_DUTY_RES_V 0x1F +#define LEDC_HSTIMER1_DUTY_RES_S 0 +// Keep the definitions below to be compatible with previous version +#define LEDC_HSTIMER1_LIM LEDC_HSTIMER1_DUTY_RES +#define LEDC_HSTIMER1_LIM_M LEDC_HSTIMER1_DUTY_RES_M +#define LEDC_HSTIMER1_LIM_V LEDC_HSTIMER1_DUTY_RES_V +#define LEDC_HSTIMER1_LIM_S LEDC_HSTIMER1_DUTY_RES_S + +#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C) +/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer1.*/ +#define LEDC_HSTIMER1_CNT 0x000FFFFF +#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S)) +#define LEDC_HSTIMER1_CNT_V 0xFFFFF +#define LEDC_HSTIMER1_CNT_S 0 + +#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150) +/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer2. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER2 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER2_V 0x1 +#define LEDC_TICK_SEL_HSTIMER2_S 25 +/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER2_RST (BIT(24)) +#define LEDC_HSTIMER2_RST_M (BIT(24)) +#define LEDC_HSTIMER2_RST_V 0x1 +#define LEDC_HSTIMER2_RST_S 24 +/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer2*/ +#define LEDC_HSTIMER2_PAUSE (BIT(23)) +#define LEDC_HSTIMER2_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER2_PAUSE_V 0x1 +#define LEDC_HSTIMER2_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer2 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S)) +#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER2_S 5 +/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER2_DUTY_RES 0x0000001F +#define LEDC_HSTIMER2_DUTY_RES_M ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S)) +#define LEDC_HSTIMER2_DUTY_RES_V 0x1F +#define LEDC_HSTIMER2_DUTY_RES_S 0 +// Keep the definitions below to be compatible with previous version +#define LEDC_HSTIMER2_LIM LEDC_HSTIMER2_DUTY_RES +#define LEDC_HSTIMER2_LIM_M LEDC_HSTIMER2_DUTY_RES_M +#define LEDC_HSTIMER2_LIM_V LEDC_HSTIMER2_DUTY_RES_V +#define LEDC_HSTIMER2_LIM_S LEDC_HSTIMER2_DUTY_RES_S + +#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154) +/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer2*/ +#define LEDC_HSTIMER2_CNT 0x000FFFFF +#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S)) +#define LEDC_HSTIMER2_CNT_V 0xFFFFF +#define LEDC_HSTIMER2_CNT_S 0 + +#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158) +/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer3. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER3 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER3_V 0x1 +#define LEDC_TICK_SEL_HSTIMER3_S 25 +/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER3_RST (BIT(24)) +#define LEDC_HSTIMER3_RST_M (BIT(24)) +#define LEDC_HSTIMER3_RST_V 0x1 +#define LEDC_HSTIMER3_RST_S 24 +/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer3*/ +#define LEDC_HSTIMER3_PAUSE (BIT(23)) +#define LEDC_HSTIMER3_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER3_PAUSE_V 0x1 +#define LEDC_HSTIMER3_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer3 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S)) +#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER3_S 5 +/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER3_DUTY_RES 0x0000001F +#define LEDC_HSTIMER3_DUTY_RES_M ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S)) +#define LEDC_HSTIMER3_DUTY_RES_V 0x1F +#define LEDC_HSTIMER3_DUTY_RES_S 0 +// Keep the definitions below to be compatible with previous version +#define LEDC_HSTIMER3_LIM LEDC_HSTIMER3_DUTY_RES +#define LEDC_HSTIMER3_LIM_M LEDC_HSTIMER3_DUTY_RES_M +#define LEDC_HSTIMER3_LIM_V LEDC_HSTIMER3_DUTY_RES_V +#define LEDC_HSTIMER3_LIM_S LEDC_HSTIMER3_DUTY_RES_S + +#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C) +/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer3*/ +#define LEDC_HSTIMER3_CNT 0x000FFFFF +#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S)) +#define LEDC_HSTIMER3_CNT_V 0xFFFFF +#define LEDC_HSTIMER3_CNT_S 0 + +#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160) +/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ +#define LEDC_LSTIMER0_PARA_UP (BIT(26)) +#define LEDC_LSTIMER0_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER0_PARA_UP_V 0x1 +#define LEDC_LSTIMER0_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer0. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER0 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER0_V 0x1 +#define LEDC_TICK_SEL_LSTIMER0_S 25 +/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER0_RST (BIT(24)) +#define LEDC_LSTIMER0_RST_M (BIT(24)) +#define LEDC_LSTIMER0_RST_V 0x1 +#define LEDC_LSTIMER0_RST_S 24 +/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer0.*/ +#define LEDC_LSTIMER0_PAUSE (BIT(23)) +#define LEDC_LSTIMER0_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER0_PAUSE_V 0x1 +#define LEDC_LSTIMER0_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer0 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S)) +#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER0_S 5 +/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER0_DUTY_RES 0x0000001F +#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S)) +#define LEDC_LSTIMER0_DUTY_RES_V 0x1F +#define LEDC_LSTIMER0_DUTY_RES_S 0 +// Keep the definitions below to be compatible with previous version +#define LEDC_LSTIMER0_LIM LEDC_LSTIMER0_DUTY_RES +#define LEDC_LSTIMER0_LIM_M LEDC_LSTIMER0_DUTY_RES_M +#define LEDC_LSTIMER0_LIM_V LEDC_LSTIMER0_DUTY_RES_V +#define LEDC_LSTIMER0_LIM_S LEDC_LSTIMER0_DUTY_RES_S + +#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164) +/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer0.*/ +#define LEDC_LSTIMER0_CNT 0x000FFFFF +#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) +#define LEDC_LSTIMER0_CNT_V 0xFFFFF +#define LEDC_LSTIMER0_CNT_S 0 + +#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168) +/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/ +#define LEDC_LSTIMER1_PARA_UP (BIT(26)) +#define LEDC_LSTIMER1_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER1_PARA_UP_V 0x1 +#define LEDC_LSTIMER1_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer1. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER1 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER1_V 0x1 +#define LEDC_TICK_SEL_LSTIMER1_S 25 +/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER1_RST (BIT(24)) +#define LEDC_LSTIMER1_RST_M (BIT(24)) +#define LEDC_LSTIMER1_RST_V 0x1 +#define LEDC_LSTIMER1_RST_S 24 +/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer1.*/ +#define LEDC_LSTIMER1_PAUSE (BIT(23)) +#define LEDC_LSTIMER1_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER1_PAUSE_V 0x1 +#define LEDC_LSTIMER1_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer1 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S)) +#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER1_S 5 +/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER1_DUTY_RES 0x0000001F +#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S)) +#define LEDC_LSTIMER1_DUTY_RES_V 0x1F +#define LEDC_LSTIMER1_DUTY_RES_S 0 +// Keep the definitions below to be compatible with previous version +#define LEDC_LSTIMER1_LIM LEDC_LSTIMER1_DUTY_RES +#define LEDC_LSTIMER1_LIM_M LEDC_LSTIMER1_DUTY_RES_M +#define LEDC_LSTIMER1_LIM_V LEDC_LSTIMER1_DUTY_RES_V +#define LEDC_LSTIMER1_LIM_S LEDC_LSTIMER1_DUTY_RES_S + +#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C) +/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer1.*/ +#define LEDC_LSTIMER1_CNT 0x000FFFFF +#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) +#define LEDC_LSTIMER1_CNT_V 0xFFFFF +#define LEDC_LSTIMER1_CNT_S 0 + +#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170) +/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/ +#define LEDC_LSTIMER2_PARA_UP (BIT(26)) +#define LEDC_LSTIMER2_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER2_PARA_UP_V 0x1 +#define LEDC_LSTIMER2_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer2. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER2 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER2_V 0x1 +#define LEDC_TICK_SEL_LSTIMER2_S 25 +/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER2_RST (BIT(24)) +#define LEDC_LSTIMER2_RST_M (BIT(24)) +#define LEDC_LSTIMER2_RST_V 0x1 +#define LEDC_LSTIMER2_RST_S 24 +/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer2.*/ +#define LEDC_LSTIMER2_PAUSE (BIT(23)) +#define LEDC_LSTIMER2_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER2_PAUSE_V 0x1 +#define LEDC_LSTIMER2_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer2 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S)) +#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER2_S 5 +/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER2_DUTY_RES 0x0000001F +#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S)) +#define LEDC_LSTIMER2_DUTY_RES_V 0x1F +#define LEDC_LSTIMER2_DUTY_RES_S 0 +// Keep the definitions below to be compatible with previous version +#define LEDC_LSTIMER2_LIM LEDC_LSTIMER2_DUTY_RES +#define LEDC_LSTIMER2_LIM_M LEDC_LSTIMER2_DUTY_RES_M +#define LEDC_LSTIMER2_LIM_V LEDC_LSTIMER2_DUTY_RES_V +#define LEDC_LSTIMER2_LIM_S LEDC_LSTIMER2_DUTY_RES_S + +#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174) +/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer2.*/ +#define LEDC_LSTIMER2_CNT 0x000FFFFF +#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) +#define LEDC_LSTIMER2_CNT_V 0xFFFFF +#define LEDC_LSTIMER2_CNT_S 0 + +#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178) +/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/ +#define LEDC_LSTIMER3_PARA_UP (BIT(26)) +#define LEDC_LSTIMER3_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER3_PARA_UP_V 0x1 +#define LEDC_LSTIMER3_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer3. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER3 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER3_V 0x1 +#define LEDC_TICK_SEL_LSTIMER3_S 25 +/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER3_RST (BIT(24)) +#define LEDC_LSTIMER3_RST_M (BIT(24)) +#define LEDC_LSTIMER3_RST_V 0x1 +#define LEDC_LSTIMER3_RST_S 24 +/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer3.*/ +#define LEDC_LSTIMER3_PAUSE (BIT(23)) +#define LEDC_LSTIMER3_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER3_PAUSE_V 0x1 +#define LEDC_LSTIMER3_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer3 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S)) +#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER3_S 5 +/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER3_DUTY_RES 0x0000001F +#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S)) +#define LEDC_LSTIMER3_DUTY_RES_V 0x1F +#define LEDC_LSTIMER3_DUTY_RES_S 0 +// Keep the definitions below to be compatible with previous version +#define LEDC_LSTIMER3_LIM LEDC_LSTIMER3_DUTY_RES +#define LEDC_LSTIMER3_LIM_M LEDC_LSTIMER3_DUTY_RES_M +#define LEDC_LSTIMER3_LIM_V LEDC_LSTIMER3_DUTY_RES_V +#define LEDC_LSTIMER3_LIM_S LEDC_LSTIMER3_DUTY_RES_S + +#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C) +/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer3.*/ +#define LEDC_LSTIMER3_CNT 0x000FFFFF +#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) +#define LEDC_LSTIMER3_CNT_V 0xFFFFF +#define LEDC_LSTIMER3_CNT_S 0 + +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 7 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 6 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 5 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 4 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 3 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 2 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 1 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 0 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 7 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 6 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 5 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 4 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 3 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 2 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 1 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 0 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8 +/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel3 counter overflow.*/ +#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_RAW_S 7 +/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel2 counter overflow.*/ +#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_RAW_S 6 +/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel1 counter overflow.*/ +#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_RAW_S 5 +/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel0 counter overflow.*/ +#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_RAW_S 4 +/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel3 counter overflow.*/ +#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_RAW_S 3 +/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel2 counter overflow.*/ +#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_RAW_S 2 +/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel1 counter overflow.*/ +#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_RAW_S 1 +/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel0 counter overflow.*/ +#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_RAW_S 0 + +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: The interrupt status bit for low speed channel 7 duty change done event*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 6 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 5 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 4 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 3 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 2 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 1 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 0 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 7 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 6 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 5 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 4 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 3 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 2 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 1 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 0 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8 +/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel3 counter overflow event.*/ +#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ST_S 7 +/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel2 counter overflow event.*/ +#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ST_S 6 +/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel1 counter overflow event.*/ +#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ST_S 5 +/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel0 counter overflow event.*/ +#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ST_S 4 +/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel3 counter overflow event.*/ +#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_ST_S 3 +/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel2 counter overflow event.*/ +#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_ST_S 2 +/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel1 counter overflow event.*/ +#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_ST_S 1 +/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel0 counter overflow event.*/ +#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_ST_S 0 + +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8 +/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ +#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ENA_S 7 +/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ +#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ENA_S 6 +/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ +#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ENA_S 5 +/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ +#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ENA_S 4 +/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ +#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_ENA_S 3 +/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ +#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_ENA_S 2 +/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ +#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_ENA_S 1 +/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ +#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_ENA_S 0 + +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8 +/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/ +#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_CLR_S 7 +/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/ +#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_CLR_S 6 +/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/ +#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_CLR_S 5 +/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/ +#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_CLR_S 4 +/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/ +#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_CLR_S 3 +/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/ +#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_CLR_S 2 +/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/ +#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_CLR_S 1 +/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/ +#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_CLR_S 0 + +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190) +/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ +#define LEDC_APB_CLK_SEL (BIT(0)) +#define LEDC_APB_CLK_SEL_M (BIT(0)) +#define LEDC_APB_CLK_SEL_V 0x1 +#define LEDC_APB_CLK_SEL_S 0 + +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC) +/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */ +/*description: This register represents the version .*/ +#define LEDC_DATE 0xFFFFFFFF +#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) +#define LEDC_DATE_V 0xFFFFFFFF +#define LEDC_DATE_S 0 + + + + +#endif /*_SOC_LEDC_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/ledc_struct.h b/tools/sdk/include/soc/include/soc/ledc_struct.h new file mode 100644 index 00000000000..d07e059f209 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/ledc_struct.h @@ -0,0 +1,263 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_STRUCT_H_ +#define _SOC_LEDC_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + struct { + struct { + union { + struct { + uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ + uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ + uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ + uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/ + uint32_t reserved4: 26; + uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } hpoint; + union { + struct { + uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } duty; + union { + struct { + uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ + uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ + uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ + uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ + uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } duty_rd; + } channel[8]; + } channel_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ + struct { + struct { + union { + struct { + uint32_t duty_resolution: 5; /*This register controls resolution of PWN duty by defining the bit width of timer's counter. The max bit width of the counter is 20.*/ + uint32_t clock_divider: 18; /*This register is used to configure the divider of clock at the entry of timer. The least significant eight bits represent the decimal part.*/ + uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/ + uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/ + uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/ + uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/ + uint32_t reserved26: 5; + }; + struct { + uint32_t bit_num: 5 __attribute__((deprecated)); /*Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1.*/ + uint32_t div_num: 18 __attribute__((deprecated)); /*Deprecated in ESP-IDF 3.0. This is an alias to 'clock_divider' for backward compatibility with ESP-IDF 2.1.*/ + uint32_t place_holder: 9 __attribute__((deprecated)); /*A place holder to accommodate deprecated members*/ + }; + uint32_t val; + } conf; + union { + struct { + uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } value; + } timer[4]; + } timer_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ + union { + struct { + uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ + uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ + uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ + uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ + uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ + uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ + uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ + uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ + uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ + uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ + uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ + uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ + uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ + uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ + uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ + uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ + uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ + uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ + uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ + uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ + uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ + uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ + uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ + uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ + uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ + uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ + uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ + uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ + uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ + uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done event.*/ + uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ + uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ + uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ + uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ + uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ + uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ + uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ + uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ + uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ + uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ + uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ + uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ + uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ + uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ + uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ + uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ + uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ + uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ + uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ + uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ + uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ + uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ + uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ + uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ + uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ + uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ + uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ + uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ + uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ + uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t apb_clk_sel: 1; /*This bit decides the slow clock for LEDC low speed channels, so we want to replace the field name with slow_clk_sel*/ + uint32_t reserved1: 31; + }; + struct { + uint32_t slow_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz, (only used by LEDC low speed channels/timers)*/ + uint32_t reserved: 31; + }; + uint32_t val; + } conf; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t date; /*This register represents the version .*/ +} ledc_dev_t; +extern ledc_dev_t LEDC; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_LEDC_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/mcpwm_reg.h b/tools/sdk/include/soc/include/soc/mcpwm_reg.h new file mode 100644 index 00000000000..1dce94d4694 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/mcpwm_reg.h @@ -0,0 +1,3028 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_MCPWM_REG_H_ +#define _SOC_MCPWM_REG_H_ +#include "soc.h" + +#define REG_MCPWM_BASE(i) (DR_REG_PWM_BASE + i * (0xE000)) +#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000) +/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ +#define MCPWM_CLK_PRESCALE 0x000000FF +#define MCPWM_CLK_PRESCALE_M ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S)) +#define MCPWM_CLK_PRESCALE_V 0xFF +#define MCPWM_CLK_PRESCALE_S 0 + +#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0004) +/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: Update method for active reg of PWM timer0 period 0: immediate + 1: TEZ 2: sync 3: TEZ or sync. TEZ here and below means timer equal zero event*/ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 +/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ +/*description: Period shadow reg of PWM timer0*/ +#define MCPWM_TIMER0_PERIOD 0x0000FFFF +#define MCPWM_TIMER0_PERIOD_M ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S)) +#define MCPWM_TIMER0_PERIOD_V 0xFFFF +#define MCPWM_TIMER0_PERIOD_S 8 +/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/ +#define MCPWM_TIMER0_PRESCALE 0x000000FF +#define MCPWM_TIMER0_PRESCALE_M ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S)) +#define MCPWM_TIMER0_PRESCALE_V 0xFF +#define MCPWM_TIMER0_PRESCALE_S 0 + +#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0008) +/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: PWM timer0 working mode 0: freeze 1: increase mod 2: decrease + mod 3: up-down mod*/ +#define MCPWM_TIMER0_MOD 0x00000003 +#define MCPWM_TIMER0_MOD_M ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S)) +#define MCPWM_TIMER0_MOD_V 0x3 +#define MCPWM_TIMER0_MOD_S 3 +/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP + 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/ +#define MCPWM_TIMER0_START 0x00000007 +#define MCPWM_TIMER0_START_M ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S)) +#define MCPWM_TIMER0_START_V 0x7 +#define MCPWM_TIMER0_START_S 0 + +#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x000c) +/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ +/*description: Phase for timer reload on sync event*/ +#define MCPWM_TIMER0_PHASE 0x0001FFFF +#define MCPWM_TIMER0_PHASE_M ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S)) +#define MCPWM_TIMER0_PHASE_V 0x1FFFF +#define MCPWM_TIMER0_PHASE_S 4 +/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER0_SYNCO_SEL_M ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S)) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Toggling this bit will trigger a software sync*/ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_V 0x1 +#define MCPWM_TIMER0_SYNC_SW_S 1 +/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When set timer reload with phase on sync input event is enabled*/ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_V 0x1 +#define MCPWM_TIMER0_SYNCI_EN_S 0 + +#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0010) +/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: Current PWM timer0 counter direction 0: increment 1: decrement*/ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_V 0x1 +#define MCPWM_TIMER0_DIRECTION_S 16 +/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Current PWM timer0 counter value*/ +#define MCPWM_TIMER0_VALUE 0x0000FFFF +#define MCPWM_TIMER0_VALUE_M ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S)) +#define MCPWM_TIMER0_VALUE_V 0xFFFF +#define MCPWM_TIMER0_VALUE_S 0 + +#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0014) +/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: Update method for active reg of PWM timer1 period 0: immediate + 1: TEZ 2: sync 3: TEZ or sync*/ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 +/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ +/*description: Period shadow reg of PWM timer1*/ +#define MCPWM_TIMER1_PERIOD 0x0000FFFF +#define MCPWM_TIMER1_PERIOD_M ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S)) +#define MCPWM_TIMER1_PERIOD_V 0xFFFF +#define MCPWM_TIMER1_PERIOD_S 8 +/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)*/ +#define MCPWM_TIMER1_PRESCALE 0x000000FF +#define MCPWM_TIMER1_PRESCALE_M ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S)) +#define MCPWM_TIMER1_PRESCALE_V 0xFF +#define MCPWM_TIMER1_PRESCALE_S 0 + +#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0018) +/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: PWM timer1 working mode 0: freeze 1: increase mod 2: decrease + mod 3: up-down mod*/ +#define MCPWM_TIMER1_MOD 0x00000003 +#define MCPWM_TIMER1_MOD_M ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S)) +#define MCPWM_TIMER1_MOD_V 0x3 +#define MCPWM_TIMER1_MOD_S 3 +/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: PWM timer1 start and stop control. 0: stop @ TEZ 1: stop @ TEP + 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP.*/ +#define MCPWM_TIMER1_START 0x00000007 +#define MCPWM_TIMER1_START_M ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S)) +#define MCPWM_TIMER1_START_V 0x7 +#define MCPWM_TIMER1_START_S 0 + +#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x001c) +/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ +/*description: Phase for timer reload on sync event*/ +#define MCPWM_TIMER1_PHASE 0x0001FFFF +#define MCPWM_TIMER1_PHASE_M ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S)) +#define MCPWM_TIMER1_PHASE_V 0x1FFFF +#define MCPWM_TIMER1_PHASE_S 4 +/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: PWM timer1 synco selection 0: synci 1: TEZ 2: TEP else 0*/ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER1_SYNCO_SEL_M ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S)) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Toggling this bit will trigger a software sync*/ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_V 0x1 +#define MCPWM_TIMER1_SYNC_SW_S 1 +/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When set timer reload with phase on sync input event is enabled*/ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_V 0x1 +#define MCPWM_TIMER1_SYNCI_EN_S 0 + +#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0020) +/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: Current PWM timer1 counter direction 0: increment 1: decrement*/ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_V 0x1 +#define MCPWM_TIMER1_DIRECTION_S 16 +/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Current PWM timer1 counter value*/ +#define MCPWM_TIMER1_VALUE 0x0000FFFF +#define MCPWM_TIMER1_VALUE_M ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S)) +#define MCPWM_TIMER1_VALUE_V 0xFFFF +#define MCPWM_TIMER1_VALUE_S 0 + +#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0024) +/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: Update method for active reg of PWM timer2 period 0: immediate + 1: TEZ 2: sync 3: TEZ or sync*/ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 +/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ +/*description: Period shadow reg of PWM timer2*/ +#define MCPWM_TIMER2_PERIOD 0x0000FFFF +#define MCPWM_TIMER2_PERIOD_M ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S)) +#define MCPWM_TIMER2_PERIOD_V 0xFFFF +#define MCPWM_TIMER2_PERIOD_S 8 +/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)*/ +#define MCPWM_TIMER2_PRESCALE 0x000000FF +#define MCPWM_TIMER2_PRESCALE_M ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S)) +#define MCPWM_TIMER2_PRESCALE_V 0xFF +#define MCPWM_TIMER2_PRESCALE_S 0 + +#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0028) +/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: PWM timer2 working mode 0: freeze 1: increase mod 2: decrease + mod 3: up-down mod*/ +#define MCPWM_TIMER2_MOD 0x00000003 +#define MCPWM_TIMER2_MOD_M ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S)) +#define MCPWM_TIMER2_MOD_V 0x3 +#define MCPWM_TIMER2_MOD_S 3 +/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: PWM timer2 start and stop control. 0: stop @ TEZ 1: stop @ TEP + 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP.*/ +#define MCPWM_TIMER2_START 0x00000007 +#define MCPWM_TIMER2_START_M ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S)) +#define MCPWM_TIMER2_START_V 0x7 +#define MCPWM_TIMER2_START_S 0 + +#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x002c) +/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ +/*description: Phase for timer reload on sync event*/ +#define MCPWM_TIMER2_PHASE 0x0001FFFF +#define MCPWM_TIMER2_PHASE_M ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S)) +#define MCPWM_TIMER2_PHASE_V 0x1FFFF +#define MCPWM_TIMER2_PHASE_S 4 +/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: PWM timer2 synco selection 0: synci 1: TEZ 2: TEP else 0*/ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER2_SYNCO_SEL_M ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S)) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Toggling this bit will trigger a software sync*/ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_V 0x1 +#define MCPWM_TIMER2_SYNC_SW_S 1 +/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When set timer reload with phase on sync input event is enabled*/ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_V 0x1 +#define MCPWM_TIMER2_SYNCI_EN_S 0 + +#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0030) +/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: Current PWM timer2 counter direction 0: increment 1: decrement*/ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_V 0x1 +#define MCPWM_TIMER2_DIRECTION_S 16 +/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Current PWM timer2 counter value*/ +#define MCPWM_TIMER2_VALUE 0x0000FFFF +#define MCPWM_TIMER2_VALUE_M ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S)) +#define MCPWM_TIMER2_VALUE_V 0xFFFF +#define MCPWM_TIMER2_VALUE_S 0 + +#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0034) +/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: Onvert SYNC2 from GPIO matrix*/ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 +/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Invert SYNC1 from GPIO matrix*/ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Invert SYNC0 from GPIO matrix*/ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */ +/*description: Select sync input for PWM timer2 1: PWM timer0 synco 2: PWM + timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ +#define MCPWM_TIMER2_SYNCISEL 0x00000007 +#define MCPWM_TIMER2_SYNCISEL_M ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S)) +#define MCPWM_TIMER2_SYNCISEL_V 0x7 +#define MCPWM_TIMER2_SYNCISEL_S 6 +/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */ +/*description: Select sync input for PWM timer1 1: PWM timer0 synco 2: PWM + timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ +#define MCPWM_TIMER1_SYNCISEL 0x00000007 +#define MCPWM_TIMER1_SYNCISEL_M ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S)) +#define MCPWM_TIMER1_SYNCISEL_V 0x7 +#define MCPWM_TIMER1_SYNCISEL_S 3 +/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: Select sync input for PWM timer0 1: PWM timer0 synco 2: PWM + timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ +#define MCPWM_TIMER0_SYNCISEL 0x00000007 +#define MCPWM_TIMER0_SYNCISEL_M ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S)) +#define MCPWM_TIMER0_SYNCISEL_V 0x7 +#define MCPWM_TIMER0_SYNCISEL_S 0 + +#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x0038) +/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Select which PWM timer's is the timing reference for PWM operator2 + 0: timer0 1: timer1 2: timer2*/ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR2_TIMERSEL_M ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S)) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR2_TIMERSEL_S 4 +/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Select which PWM timer's is the timing reference for PWM operator1 + 0: timer0 1: timer1 2: timer2*/ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR1_TIMERSEL_M ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S)) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Select which PWM timer's is the timing reference for PWM operator0 + 0: timer0 1: timer1 2: timer2*/ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR0_TIMERSEL_M ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S)) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR0_TIMERSEL_S 0 + +#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x003c) +/* MCPWM_GEN0_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 0 time stamp + B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN0_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN0_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_GEN0_B_SHDW_FULL_V 0x1 +#define MCPWM_GEN0_B_SHDW_FULL_S 9 +/* MCPWM_GEN0_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 0 time stamp + A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN0_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN0_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_GEN0_A_SHDW_FULL_V 0x1 +#define MCPWM_GEN0_A_SHDW_FULL_S 8 +/* MCPWM_GEN0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 0 time stamp B's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN0_B_UPMETHOD 0x0000000F +#define MCPWM_GEN0_B_UPMETHOD_M ((MCPWM_GEN0_B_UPMETHOD_V)<<(MCPWM_GEN0_B_UPMETHOD_S)) +#define MCPWM_GEN0_B_UPMETHOD_V 0xF +#define MCPWM_GEN0_B_UPMETHOD_S 4 +/* MCPWM_GEN0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 0 time stamp A's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN0_A_UPMETHOD 0x0000000F +#define MCPWM_GEN0_A_UPMETHOD_M ((MCPWM_GEN0_A_UPMETHOD_V)<<(MCPWM_GEN0_A_UPMETHOD_S)) +#define MCPWM_GEN0_A_UPMETHOD_V 0xF +#define MCPWM_GEN0_A_UPMETHOD_S 0 + +#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x0040) +/* MCPWM_GEN0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 0 time stamp A's shadow reg*/ +#define MCPWM_GEN0_A 0x0000FFFF +#define MCPWM_GEN0_A_M ((MCPWM_GEN0_A_V)<<(MCPWM_GEN0_A_S)) +#define MCPWM_GEN0_A_V 0xFFFF +#define MCPWM_GEN0_A_S 0 + +#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x0044) +/* MCPWM_GEN0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 0 time stamp B's shadow reg*/ +#define MCPWM_GEN0_B 0x0000FFFF +#define MCPWM_GEN0_B_M ((MCPWM_GEN0_B_V)<<(MCPWM_GEN0_B_S)) +#define MCPWM_GEN0_B_V 0xFFFF +#define MCPWM_GEN0_B_S 0 + +#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0048) +/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ +/*description: Source selection for PWM generator 0 event_t1 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN0_T1_SEL 0x00000007 +#define MCPWM_GEN0_T1_SEL_M ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S)) +#define MCPWM_GEN0_T1_SEL_V 0x7 +#define MCPWM_GEN0_T1_SEL_S 7 +/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ +/*description: Source selection for PWM generator 0 event_t0 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN0_T0_SEL 0x00000007 +#define MCPWM_GEN0_T0_SEL_M ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S)) +#define MCPWM_GEN0_T0_SEL_V 0x7 +#define MCPWM_GEN0_T0_SEL_S 4 +/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 0's active reg of configuration. + 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN0_CFG_UPMETHOD_M ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S)) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN0_CFG_UPMETHOD_S 0 + +#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x004c) +/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM0B 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN0_B_NCIFORCE_MODE_M ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 +/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM0B a + toggle will trigger a force event*/ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_V 0x1 +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM0A 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN0_A_NCIFORCE_MODE_M ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM0A a + toggle will trigger a force event*/ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_V 0x1 +#define MCPWM_GEN0_A_NCIFORCE_S 10 +/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM0B. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM0A. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: Update method for continuous software force of PWM generator0. + 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 + +#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x0050) +/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN0_A_DT1 0x00000003 +#define MCPWM_GEN0_A_DT1_M ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S)) +#define MCPWM_GEN0_A_DT1_V 0x3 +#define MCPWM_GEN0_A_DT1_S 22 +/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN0_A_DT0 0x00000003 +#define MCPWM_GEN0_A_DT0_M ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S)) +#define MCPWM_GEN0_A_DT0_V 0x3 +#define MCPWM_GEN0_A_DT0_S 20 +/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN0_A_DTEB 0x00000003 +#define MCPWM_GEN0_A_DTEB_M ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S)) +#define MCPWM_GEN0_A_DTEB_V 0x3 +#define MCPWM_GEN0_A_DTEB_S 18 +/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN0_A_DTEA 0x00000003 +#define MCPWM_GEN0_A_DTEA_M ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S)) +#define MCPWM_GEN0_A_DTEA_V 0x3 +#define MCPWM_GEN0_A_DTEA_S 16 +/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN0_A_DTEP 0x00000003 +#define MCPWM_GEN0_A_DTEP_M ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S)) +#define MCPWM_GEN0_A_DTEP_V 0x3 +#define MCPWM_GEN0_A_DTEP_S 14 +/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN0_A_DTEZ 0x00000003 +#define MCPWM_GEN0_A_DTEZ_M ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S)) +#define MCPWM_GEN0_A_DTEZ_V 0x3 +#define MCPWM_GEN0_A_DTEZ_S 12 +/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN0_A_UT1 0x00000003 +#define MCPWM_GEN0_A_UT1_M ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S)) +#define MCPWM_GEN0_A_UT1_V 0x3 +#define MCPWM_GEN0_A_UT1_S 10 +/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN0_A_UT0 0x00000003 +#define MCPWM_GEN0_A_UT0_M ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S)) +#define MCPWM_GEN0_A_UT0_V 0x3 +#define MCPWM_GEN0_A_UT0_S 8 +/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEB when timer increasing*/ +#define MCPWM_GEN0_A_UTEB 0x00000003 +#define MCPWM_GEN0_A_UTEB_M ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S)) +#define MCPWM_GEN0_A_UTEB_V 0x3 +#define MCPWM_GEN0_A_UTEB_S 6 +/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEA when timer increasing*/ +#define MCPWM_GEN0_A_UTEA 0x00000003 +#define MCPWM_GEN0_A_UTEA_M ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S)) +#define MCPWM_GEN0_A_UTEA_V 0x3 +#define MCPWM_GEN0_A_UTEA_S 4 +/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEP when timer increasing*/ +#define MCPWM_GEN0_A_UTEP 0x00000003 +#define MCPWM_GEN0_A_UTEP_M ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S)) +#define MCPWM_GEN0_A_UTEP_V 0x3 +#define MCPWM_GEN0_A_UTEP_S 2 +/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN0_A_UTEZ 0x00000003 +#define MCPWM_GEN0_A_UTEZ_M ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S)) +#define MCPWM_GEN0_A_UTEZ_V 0x3 +#define MCPWM_GEN0_A_UTEZ_S 0 + +#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x0054) +/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN0_B_DT1 0x00000003 +#define MCPWM_GEN0_B_DT1_M ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S)) +#define MCPWM_GEN0_B_DT1_V 0x3 +#define MCPWM_GEN0_B_DT1_S 22 +/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN0_B_DT0 0x00000003 +#define MCPWM_GEN0_B_DT0_M ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S)) +#define MCPWM_GEN0_B_DT0_V 0x3 +#define MCPWM_GEN0_B_DT0_S 20 +/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN0_B_DTEB 0x00000003 +#define MCPWM_GEN0_B_DTEB_M ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S)) +#define MCPWM_GEN0_B_DTEB_V 0x3 +#define MCPWM_GEN0_B_DTEB_S 18 +/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN0_B_DTEA 0x00000003 +#define MCPWM_GEN0_B_DTEA_M ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S)) +#define MCPWM_GEN0_B_DTEA_V 0x3 +#define MCPWM_GEN0_B_DTEA_S 16 +/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN0_B_DTEP 0x00000003 +#define MCPWM_GEN0_B_DTEP_M ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S)) +#define MCPWM_GEN0_B_DTEP_V 0x3 +#define MCPWM_GEN0_B_DTEP_S 14 +/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN0_B_DTEZ 0x00000003 +#define MCPWM_GEN0_B_DTEZ_M ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S)) +#define MCPWM_GEN0_B_DTEZ_V 0x3 +#define MCPWM_GEN0_B_DTEZ_S 12 +/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN0_B_UT1 0x00000003 +#define MCPWM_GEN0_B_UT1_M ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S)) +#define MCPWM_GEN0_B_UT1_V 0x3 +#define MCPWM_GEN0_B_UT1_S 10 +/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN0_B_UT0 0x00000003 +#define MCPWM_GEN0_B_UT0_M ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S)) +#define MCPWM_GEN0_B_UT0_V 0x3 +#define MCPWM_GEN0_B_UT0_S 8 +/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEB when timer increasing*/ +#define MCPWM_GEN0_B_UTEB 0x00000003 +#define MCPWM_GEN0_B_UTEB_M ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S)) +#define MCPWM_GEN0_B_UTEB_V 0x3 +#define MCPWM_GEN0_B_UTEB_S 6 +/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEA when timer increasing*/ +#define MCPWM_GEN0_B_UTEA 0x00000003 +#define MCPWM_GEN0_B_UTEA_M ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S)) +#define MCPWM_GEN0_B_UTEA_V 0x3 +#define MCPWM_GEN0_B_UTEA_S 4 +/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEP when timer increasing*/ +#define MCPWM_GEN0_B_UTEP 0x00000003 +#define MCPWM_GEN0_B_UTEP_M ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S)) +#define MCPWM_GEN0_B_UTEP_V 0x3 +#define MCPWM_GEN0_B_UTEP_S 2 +/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN0_B_UTEZ 0x00000003 +#define MCPWM_GEN0_B_UTEZ_M ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S)) +#define MCPWM_GEN0_B_UTEZ_V 0x3 +#define MCPWM_GEN0_B_UTEZ_S 0 + +#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0058) +/* MCPWM_DT0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Dead time generator 0 clock selection. 0: PWM_clk 1: PT_clk*/ +#define MCPWM_DT0_CLK_SEL (BIT(17)) +#define MCPWM_DT0_CLK_SEL_M (BIT(17)) +#define MCPWM_DT0_CLK_SEL_V 0x1 +#define MCPWM_DT0_CLK_SEL_S 17 +/* MCPWM_DT0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: S0 in documentation*/ +#define MCPWM_DT0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT0_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DT0_B_OUTBYPASS_V 0x1 +#define MCPWM_DT0_B_OUTBYPASS_S 16 +/* MCPWM_DT0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: S1 in documentation*/ +#define MCPWM_DT0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT0_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DT0_A_OUTBYPASS_V 0x1 +#define MCPWM_DT0_A_OUTBYPASS_S 15 +/* MCPWM_DT0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: S3 in documentation*/ +#define MCPWM_DT0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT0_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DT0_FED_OUTINVERT_V 0x1 +#define MCPWM_DT0_FED_OUTINVERT_S 14 +/* MCPWM_DT0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: S2 in documentation*/ +#define MCPWM_DT0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT0_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DT0_RED_OUTINVERT_V 0x1 +#define MCPWM_DT0_RED_OUTINVERT_S 13 +/* MCPWM_DT0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: S5 in documentation*/ +#define MCPWM_DT0_FED_INSEL (BIT(12)) +#define MCPWM_DT0_FED_INSEL_M (BIT(12)) +#define MCPWM_DT0_FED_INSEL_V 0x1 +#define MCPWM_DT0_FED_INSEL_S 12 +/* MCPWM_DT0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: S4 in documentation*/ +#define MCPWM_DT0_RED_INSEL (BIT(11)) +#define MCPWM_DT0_RED_INSEL_M (BIT(11)) +#define MCPWM_DT0_RED_INSEL_V 0x1 +#define MCPWM_DT0_RED_INSEL_S 11 +/* MCPWM_DT0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: S7 in documentation*/ +#define MCPWM_DT0_B_OUTSWAP (BIT(10)) +#define MCPWM_DT0_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DT0_B_OUTSWAP_V 0x1 +#define MCPWM_DT0_B_OUTSWAP_S 10 +/* MCPWM_DT0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: S6 in documentation*/ +#define MCPWM_DT0_A_OUTSWAP (BIT(9)) +#define MCPWM_DT0_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DT0_A_OUTSWAP_V 0x1 +#define MCPWM_DT0_A_OUTSWAP_S 9 +/* MCPWM_DT0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect + on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ +#define MCPWM_DT0_DEB_MODE (BIT(8)) +#define MCPWM_DT0_DEB_MODE_M (BIT(8)) +#define MCPWM_DT0_DEB_MODE_V 0x1 +#define MCPWM_DT0_DEB_MODE_S 8 +/* MCPWM_DT0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for RED (rising edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT0_RED_UPMETHOD 0x0000000F +#define MCPWM_DT0_RED_UPMETHOD_M ((MCPWM_DT0_RED_UPMETHOD_V)<<(MCPWM_DT0_RED_UPMETHOD_S)) +#define MCPWM_DT0_RED_UPMETHOD_V 0xF +#define MCPWM_DT0_RED_UPMETHOD_S 4 +/* MCPWM_DT0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for FED (falling edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT0_FED_UPMETHOD 0x0000000F +#define MCPWM_DT0_FED_UPMETHOD_M ((MCPWM_DT0_FED_UPMETHOD_V)<<(MCPWM_DT0_FED_UPMETHOD_S)) +#define MCPWM_DT0_FED_UPMETHOD_V 0xF +#define MCPWM_DT0_FED_UPMETHOD_S 0 + +#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x005c) +/* MCPWM_DT0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for FED*/ +#define MCPWM_DT0_FED 0x0000FFFF +#define MCPWM_DT0_FED_M ((MCPWM_DT0_FED_V)<<(MCPWM_DT0_FED_S)) +#define MCPWM_DT0_FED_V 0xFFFF +#define MCPWM_DT0_FED_S 0 + +#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0060) +/* MCPWM_DT0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for RED*/ +#define MCPWM_DT0_RED 0x0000FFFF +#define MCPWM_DT0_RED_M ((MCPWM_DT0_RED_V)<<(MCPWM_DT0_RED_S)) +#define MCPWM_DT0_RED_V 0xFFFF +#define MCPWM_DT0_RED_S 0 + +#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0064) +/* MCPWM_CARRIER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: When set invert the input of PWM0A and PWM0B for this submodule*/ +#define MCPWM_CARRIER0_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER0_IN_INVERT_M (BIT(13)) +#define MCPWM_CARRIER0_IN_INVERT_V 0x1 +#define MCPWM_CARRIER0_IN_INVERT_S 13 +/* MCPWM_CARRIER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: When set invert the output of PWM0A and PWM0B for this submodule*/ +#define MCPWM_CARRIER0_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER0_OUT_INVERT_M (BIT(12)) +#define MCPWM_CARRIER0_OUT_INVERT_V 0x1 +#define MCPWM_CARRIER0_OUT_INVERT_S 12 +/* MCPWM_CARRIER0_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: Width of the fist pulse in number of periods of the carrier*/ +#define MCPWM_CARRIER0_OSHWTH 0x0000000F +#define MCPWM_CARRIER0_OSHWTH_M ((MCPWM_CARRIER0_OSHWTH_V)<<(MCPWM_CARRIER0_OSHWTH_S)) +#define MCPWM_CARRIER0_OSHWTH_V 0xF +#define MCPWM_CARRIER0_OSHWTH_S 8 +/* MCPWM_CARRIER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: Carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/ +#define MCPWM_CARRIER0_DUTY 0x00000007 +#define MCPWM_CARRIER0_DUTY_M ((MCPWM_CARRIER0_DUTY_V)<<(MCPWM_CARRIER0_DUTY_S)) +#define MCPWM_CARRIER0_DUTY_V 0x7 +#define MCPWM_CARRIER0_DUTY_S 5 +/* MCPWM_CARRIER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk + = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/ +#define MCPWM_CARRIER0_PRESCALE 0x0000000F +#define MCPWM_CARRIER0_PRESCALE_M ((MCPWM_CARRIER0_PRESCALE_V)<<(MCPWM_CARRIER0_PRESCALE_S)) +#define MCPWM_CARRIER0_PRESCALE_V 0xF +#define MCPWM_CARRIER0_PRESCALE_S 1 +/* MCPWM_CARRIER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set carrier0 function is enabled. When cleared carrier0 is bypassed*/ +#define MCPWM_CARRIER0_EN (BIT(0)) +#define MCPWM_CARRIER0_EN_M (BIT(0)) +#define MCPWM_CARRIER0_EN_V 0x1 +#define MCPWM_CARRIER0_EN_S 0 + +#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0068) +/* MCPWM_FH0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM0B when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_B_OST_U 0x00000003 +#define MCPWM_FH0_B_OST_U_M ((MCPWM_FH0_B_OST_U_V)<<(MCPWM_FH0_B_OST_U_S)) +#define MCPWM_FH0_B_OST_U_V 0x3 +#define MCPWM_FH0_B_OST_U_S 22 +/* MCPWM_FH0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM0B when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_B_OST_D 0x00000003 +#define MCPWM_FH0_B_OST_D_M ((MCPWM_FH0_B_OST_D_V)<<(MCPWM_FH0_B_OST_D_S)) +#define MCPWM_FH0_B_OST_D_V 0x3 +#define MCPWM_FH0_B_OST_D_S 20 +/* MCPWM_FH0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_B_CBC_U 0x00000003 +#define MCPWM_FH0_B_CBC_U_M ((MCPWM_FH0_B_CBC_U_V)<<(MCPWM_FH0_B_CBC_U_S)) +#define MCPWM_FH0_B_CBC_U_V 0x3 +#define MCPWM_FH0_B_CBC_U_S 18 +/* MCPWM_FH0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_B_CBC_D 0x00000003 +#define MCPWM_FH0_B_CBC_D_M ((MCPWM_FH0_B_CBC_D_V)<<(MCPWM_FH0_B_CBC_D_S)) +#define MCPWM_FH0_B_CBC_D_V 0x3 +#define MCPWM_FH0_B_CBC_D_S 16 +/* MCPWM_FH0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM0A when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_A_OST_U 0x00000003 +#define MCPWM_FH0_A_OST_U_M ((MCPWM_FH0_A_OST_U_V)<<(MCPWM_FH0_A_OST_U_S)) +#define MCPWM_FH0_A_OST_U_V 0x3 +#define MCPWM_FH0_A_OST_U_S 14 +/* MCPWM_FH0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM0A when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_A_OST_D 0x00000003 +#define MCPWM_FH0_A_OST_D_M ((MCPWM_FH0_A_OST_D_V)<<(MCPWM_FH0_A_OST_D_S)) +#define MCPWM_FH0_A_OST_D_V 0x3 +#define MCPWM_FH0_A_OST_D_S 12 +/* MCPWM_FH0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_A_CBC_U 0x00000003 +#define MCPWM_FH0_A_CBC_U_M ((MCPWM_FH0_A_CBC_U_V)<<(MCPWM_FH0_A_CBC_U_S)) +#define MCPWM_FH0_A_CBC_U_V 0x3 +#define MCPWM_FH0_A_CBC_U_S 10 +/* MCPWM_FH0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_A_CBC_D 0x00000003 +#define MCPWM_FH0_A_CBC_D_M ((MCPWM_FH0_A_CBC_D_V)<<(MCPWM_FH0_A_CBC_D_S)) +#define MCPWM_FH0_A_CBC_D_V 0x3 +#define MCPWM_FH0_A_CBC_D_S 8 +/* MCPWM_FH0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F0_OST (BIT(7)) +#define MCPWM_FH0_F0_OST_M (BIT(7)) +#define MCPWM_FH0_F0_OST_V 0x1 +#define MCPWM_FH0_F0_OST_S 7 +/* MCPWM_FH0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F1_OST (BIT(6)) +#define MCPWM_FH0_F1_OST_M (BIT(6)) +#define MCPWM_FH0_F1_OST_V 0x1 +#define MCPWM_FH0_F1_OST_S 6 +/* MCPWM_FH0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F2_OST (BIT(5)) +#define MCPWM_FH0_F2_OST_M (BIT(5)) +#define MCPWM_FH0_F2_OST_V 0x1 +#define MCPWM_FH0_F2_OST_S 5 +/* MCPWM_FH0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_SW_OST (BIT(4)) +#define MCPWM_FH0_SW_OST_M (BIT(4)) +#define MCPWM_FH0_SW_OST_V 0x1 +#define MCPWM_FH0_SW_OST_S 4 +/* MCPWM_FH0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F0_CBC (BIT(3)) +#define MCPWM_FH0_F0_CBC_M (BIT(3)) +#define MCPWM_FH0_F0_CBC_V 0x1 +#define MCPWM_FH0_F0_CBC_S 3 +/* MCPWM_FH0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F1_CBC (BIT(2)) +#define MCPWM_FH0_F1_CBC_M (BIT(2)) +#define MCPWM_FH0_F1_CBC_V 0x1 +#define MCPWM_FH0_F1_CBC_S 2 +/* MCPWM_FH0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F2_CBC (BIT(1)) +#define MCPWM_FH0_F2_CBC_M (BIT(1)) +#define MCPWM_FH0_F2_CBC_V 0x1 +#define MCPWM_FH0_F2_CBC_S 1 +/* MCPWM_FH0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Enable register for software force cycle-by-cycle mode action. + 0: disable 1: enable*/ +#define MCPWM_FH0_SW_CBC (BIT(0)) +#define MCPWM_FH0_SW_CBC_M (BIT(0)) +#define MCPWM_FH0_SW_CBC_V 0x1 +#define MCPWM_FH0_SW_CBC_S 0 + +#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x006c) +/* MCPWM_FH0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) triggers a + one-shot mode action*/ +#define MCPWM_FH0_FORCE_OST (BIT(4)) +#define MCPWM_FH0_FORCE_OST_M (BIT(4)) +#define MCPWM_FH0_FORCE_OST_V 0x1 +#define MCPWM_FH0_FORCE_OST_S 4 +/* MCPWM_FH0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: A toggle triggers a cycle-by-cycle mode action*/ +#define MCPWM_FH0_FORCE_CBC (BIT(3)) +#define MCPWM_FH0_FORCE_CBC_M (BIT(3)) +#define MCPWM_FH0_FORCE_CBC_V 0x1 +#define MCPWM_FH0_FORCE_CBC_S 3 +/* MCPWM_FH0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ +#define MCPWM_FH0_CBCPULSE 0x00000003 +#define MCPWM_FH0_CBCPULSE_M ((MCPWM_FH0_CBCPULSE_V)<<(MCPWM_FH0_CBCPULSE_S)) +#define MCPWM_FH0_CBCPULSE_V 0x3 +#define MCPWM_FH0_CBCPULSE_S 1 +/* MCPWM_FH0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: A toggle will clear on going one-shot mode action*/ +#define MCPWM_FH0_CLR_OST (BIT(0)) +#define MCPWM_FH0_CLR_OST_M (BIT(0)) +#define MCPWM_FH0_CLR_OST_V 0x1 +#define MCPWM_FH0_CLR_OST_S 0 + +#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0070) +/* MCPWM_FH0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ +#define MCPWM_FH0_OST_ON (BIT(1)) +#define MCPWM_FH0_OST_ON_M (BIT(1)) +#define MCPWM_FH0_OST_ON_V 0x1 +#define MCPWM_FH0_OST_ON_S 1 +/* MCPWM_FH0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ +#define MCPWM_FH0_CBC_ON (BIT(0)) +#define MCPWM_FH0_CBC_ON_M (BIT(0)) +#define MCPWM_FH0_CBC_ON_V 0x1 +#define MCPWM_FH0_CBC_ON_S 0 + +#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0074) +/* MCPWM_GEN1_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 1 time stamp + B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN1_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN1_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_GEN1_B_SHDW_FULL_V 0x1 +#define MCPWM_GEN1_B_SHDW_FULL_S 9 +/* MCPWM_GEN1_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 1 time stamp + A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN1_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN1_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_GEN1_A_SHDW_FULL_V 0x1 +#define MCPWM_GEN1_A_SHDW_FULL_S 8 +/* MCPWM_GEN1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 1 time stamp B's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN1_B_UPMETHOD 0x0000000F +#define MCPWM_GEN1_B_UPMETHOD_M ((MCPWM_GEN1_B_UPMETHOD_V)<<(MCPWM_GEN1_B_UPMETHOD_S)) +#define MCPWM_GEN1_B_UPMETHOD_V 0xF +#define MCPWM_GEN1_B_UPMETHOD_S 4 +/* MCPWM_GEN1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 1 time stamp A's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN1_A_UPMETHOD 0x0000000F +#define MCPWM_GEN1_A_UPMETHOD_M ((MCPWM_GEN1_A_UPMETHOD_V)<<(MCPWM_GEN1_A_UPMETHOD_S)) +#define MCPWM_GEN1_A_UPMETHOD_V 0xF +#define MCPWM_GEN1_A_UPMETHOD_S 0 + +#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x0078) +/* MCPWM_GEN1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 1 time stamp A's shadow reg*/ +#define MCPWM_GEN1_A 0x0000FFFF +#define MCPWM_GEN1_A_M ((MCPWM_GEN1_A_V)<<(MCPWM_GEN1_A_S)) +#define MCPWM_GEN1_A_V 0xFFFF +#define MCPWM_GEN1_A_S 0 + +#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x007c) +/* MCPWM_GEN1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 1 time stamp B's shadow reg*/ +#define MCPWM_GEN1_B 0x0000FFFF +#define MCPWM_GEN1_B_M ((MCPWM_GEN1_B_V)<<(MCPWM_GEN1_B_S)) +#define MCPWM_GEN1_B_V 0xFFFF +#define MCPWM_GEN1_B_S 0 + +#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0080) +/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ +/*description: Source selection for PWM generate1 event_t1 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN1_T1_SEL 0x00000007 +#define MCPWM_GEN1_T1_SEL_M ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S)) +#define MCPWM_GEN1_T1_SEL_V 0x7 +#define MCPWM_GEN1_T1_SEL_S 7 +/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ +/*description: Source selection for PWM generate1 event_t0 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN1_T0_SEL 0x00000007 +#define MCPWM_GEN1_T0_SEL_M ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S)) +#define MCPWM_GEN1_T0_SEL_V 0x7 +#define MCPWM_GEN1_T0_SEL_S 4 +/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generate1's active reg of configuration. + 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN1_CFG_UPMETHOD_M ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S)) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN1_CFG_UPMETHOD_S 0 + +#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x0084) +/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM1B 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN1_B_NCIFORCE_MODE_M ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 +/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM1B a + toggle will trigger a force event*/ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_V 0x1 +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM1A 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN1_A_NCIFORCE_MODE_M ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM1A a + toggle will trigger a force event*/ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_V 0x1 +#define MCPWM_GEN1_A_NCIFORCE_S 10 +/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM1B. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM1A. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: Update method for continuous software force of PWM generator1. + 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 + +#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x0088) +/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN1_A_DT1 0x00000003 +#define MCPWM_GEN1_A_DT1_M ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S)) +#define MCPWM_GEN1_A_DT1_V 0x3 +#define MCPWM_GEN1_A_DT1_S 22 +/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN1_A_DT0 0x00000003 +#define MCPWM_GEN1_A_DT0_M ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S)) +#define MCPWM_GEN1_A_DT0_V 0x3 +#define MCPWM_GEN1_A_DT0_S 20 +/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN1_A_DTEB 0x00000003 +#define MCPWM_GEN1_A_DTEB_M ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S)) +#define MCPWM_GEN1_A_DTEB_V 0x3 +#define MCPWM_GEN1_A_DTEB_S 18 +/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN1_A_DTEA 0x00000003 +#define MCPWM_GEN1_A_DTEA_M ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S)) +#define MCPWM_GEN1_A_DTEA_V 0x3 +#define MCPWM_GEN1_A_DTEA_S 16 +/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN1_A_DTEP 0x00000003 +#define MCPWM_GEN1_A_DTEP_M ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S)) +#define MCPWM_GEN1_A_DTEP_V 0x3 +#define MCPWM_GEN1_A_DTEP_S 14 +/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN1_A_DTEZ 0x00000003 +#define MCPWM_GEN1_A_DTEZ_M ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S)) +#define MCPWM_GEN1_A_DTEZ_V 0x3 +#define MCPWM_GEN1_A_DTEZ_S 12 +/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN1_A_UT1 0x00000003 +#define MCPWM_GEN1_A_UT1_M ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S)) +#define MCPWM_GEN1_A_UT1_V 0x3 +#define MCPWM_GEN1_A_UT1_S 10 +/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN1_A_UT0 0x00000003 +#define MCPWM_GEN1_A_UT0_M ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S)) +#define MCPWM_GEN1_A_UT0_V 0x3 +#define MCPWM_GEN1_A_UT0_S 8 +/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEB when timer increasing*/ +#define MCPWM_GEN1_A_UTEB 0x00000003 +#define MCPWM_GEN1_A_UTEB_M ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S)) +#define MCPWM_GEN1_A_UTEB_V 0x3 +#define MCPWM_GEN1_A_UTEB_S 6 +/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEA when timer increasing*/ +#define MCPWM_GEN1_A_UTEA 0x00000003 +#define MCPWM_GEN1_A_UTEA_M ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S)) +#define MCPWM_GEN1_A_UTEA_V 0x3 +#define MCPWM_GEN1_A_UTEA_S 4 +/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEP when timer increasing*/ +#define MCPWM_GEN1_A_UTEP 0x00000003 +#define MCPWM_GEN1_A_UTEP_M ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S)) +#define MCPWM_GEN1_A_UTEP_V 0x3 +#define MCPWM_GEN1_A_UTEP_S 2 +/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN1_A_UTEZ 0x00000003 +#define MCPWM_GEN1_A_UTEZ_M ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S)) +#define MCPWM_GEN1_A_UTEZ_V 0x3 +#define MCPWM_GEN1_A_UTEZ_S 0 + +#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x008c) +/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN1_B_DT1 0x00000003 +#define MCPWM_GEN1_B_DT1_M ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S)) +#define MCPWM_GEN1_B_DT1_V 0x3 +#define MCPWM_GEN1_B_DT1_S 22 +/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN1_B_DT0 0x00000003 +#define MCPWM_GEN1_B_DT0_M ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S)) +#define MCPWM_GEN1_B_DT0_V 0x3 +#define MCPWM_GEN1_B_DT0_S 20 +/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN1_B_DTEB 0x00000003 +#define MCPWM_GEN1_B_DTEB_M ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S)) +#define MCPWM_GEN1_B_DTEB_V 0x3 +#define MCPWM_GEN1_B_DTEB_S 18 +/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN1_B_DTEA 0x00000003 +#define MCPWM_GEN1_B_DTEA_M ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S)) +#define MCPWM_GEN1_B_DTEA_V 0x3 +#define MCPWM_GEN1_B_DTEA_S 16 +/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN1_B_DTEP 0x00000003 +#define MCPWM_GEN1_B_DTEP_M ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S)) +#define MCPWM_GEN1_B_DTEP_V 0x3 +#define MCPWM_GEN1_B_DTEP_S 14 +/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN1_B_DTEZ 0x00000003 +#define MCPWM_GEN1_B_DTEZ_M ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S)) +#define MCPWM_GEN1_B_DTEZ_V 0x3 +#define MCPWM_GEN1_B_DTEZ_S 12 +/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN1_B_UT1 0x00000003 +#define MCPWM_GEN1_B_UT1_M ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S)) +#define MCPWM_GEN1_B_UT1_V 0x3 +#define MCPWM_GEN1_B_UT1_S 10 +/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN1_B_UT0 0x00000003 +#define MCPWM_GEN1_B_UT0_M ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S)) +#define MCPWM_GEN1_B_UT0_V 0x3 +#define MCPWM_GEN1_B_UT0_S 8 +/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEB when timer increasing*/ +#define MCPWM_GEN1_B_UTEB 0x00000003 +#define MCPWM_GEN1_B_UTEB_M ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S)) +#define MCPWM_GEN1_B_UTEB_V 0x3 +#define MCPWM_GEN1_B_UTEB_S 6 +/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEA when timer increasing*/ +#define MCPWM_GEN1_B_UTEA 0x00000003 +#define MCPWM_GEN1_B_UTEA_M ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S)) +#define MCPWM_GEN1_B_UTEA_V 0x3 +#define MCPWM_GEN1_B_UTEA_S 4 +/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEP when timer increasing*/ +#define MCPWM_GEN1_B_UTEP 0x00000003 +#define MCPWM_GEN1_B_UTEP_M ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S)) +#define MCPWM_GEN1_B_UTEP_V 0x3 +#define MCPWM_GEN1_B_UTEP_S 2 +/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN1_B_UTEZ 0x00000003 +#define MCPWM_GEN1_B_UTEZ_M ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S)) +#define MCPWM_GEN1_B_UTEZ_V 0x3 +#define MCPWM_GEN1_B_UTEZ_S 0 + +#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0090) +/* MCPWM_DT1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Dead time generator 1 clock selection. 0: PWM_clk 1: PT_clk*/ +#define MCPWM_DT1_CLK_SEL (BIT(17)) +#define MCPWM_DT1_CLK_SEL_M (BIT(17)) +#define MCPWM_DT1_CLK_SEL_V 0x1 +#define MCPWM_DT1_CLK_SEL_S 17 +/* MCPWM_DT1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: S0 in documentation*/ +#define MCPWM_DT1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT1_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DT1_B_OUTBYPASS_V 0x1 +#define MCPWM_DT1_B_OUTBYPASS_S 16 +/* MCPWM_DT1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: S1 in documentation*/ +#define MCPWM_DT1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT1_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DT1_A_OUTBYPASS_V 0x1 +#define MCPWM_DT1_A_OUTBYPASS_S 15 +/* MCPWM_DT1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: S3 in documentation*/ +#define MCPWM_DT1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT1_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DT1_FED_OUTINVERT_V 0x1 +#define MCPWM_DT1_FED_OUTINVERT_S 14 +/* MCPWM_DT1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: S2 in documentation*/ +#define MCPWM_DT1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT1_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DT1_RED_OUTINVERT_V 0x1 +#define MCPWM_DT1_RED_OUTINVERT_S 13 +/* MCPWM_DT1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: S5 in documentation*/ +#define MCPWM_DT1_FED_INSEL (BIT(12)) +#define MCPWM_DT1_FED_INSEL_M (BIT(12)) +#define MCPWM_DT1_FED_INSEL_V 0x1 +#define MCPWM_DT1_FED_INSEL_S 12 +/* MCPWM_DT1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: S4 in documentation*/ +#define MCPWM_DT1_RED_INSEL (BIT(11)) +#define MCPWM_DT1_RED_INSEL_M (BIT(11)) +#define MCPWM_DT1_RED_INSEL_V 0x1 +#define MCPWM_DT1_RED_INSEL_S 11 +/* MCPWM_DT1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: S7 in documentation*/ +#define MCPWM_DT1_B_OUTSWAP (BIT(10)) +#define MCPWM_DT1_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DT1_B_OUTSWAP_V 0x1 +#define MCPWM_DT1_B_OUTSWAP_S 10 +/* MCPWM_DT1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: S6 in documentation*/ +#define MCPWM_DT1_A_OUTSWAP (BIT(9)) +#define MCPWM_DT1_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DT1_A_OUTSWAP_V 0x1 +#define MCPWM_DT1_A_OUTSWAP_S 9 +/* MCPWM_DT1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect + on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ +#define MCPWM_DT1_DEB_MODE (BIT(8)) +#define MCPWM_DT1_DEB_MODE_M (BIT(8)) +#define MCPWM_DT1_DEB_MODE_V 0x1 +#define MCPWM_DT1_DEB_MODE_S 8 +/* MCPWM_DT1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for RED (rising edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT1_RED_UPMETHOD 0x0000000F +#define MCPWM_DT1_RED_UPMETHOD_M ((MCPWM_DT1_RED_UPMETHOD_V)<<(MCPWM_DT1_RED_UPMETHOD_S)) +#define MCPWM_DT1_RED_UPMETHOD_V 0xF +#define MCPWM_DT1_RED_UPMETHOD_S 4 +/* MCPWM_DT1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for FED (falling edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT1_FED_UPMETHOD 0x0000000F +#define MCPWM_DT1_FED_UPMETHOD_M ((MCPWM_DT1_FED_UPMETHOD_V)<<(MCPWM_DT1_FED_UPMETHOD_S)) +#define MCPWM_DT1_FED_UPMETHOD_V 0xF +#define MCPWM_DT1_FED_UPMETHOD_S 0 + +#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0094) +/* MCPWM_DT1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for FED*/ +#define MCPWM_DT1_FED 0x0000FFFF +#define MCPWM_DT1_FED_M ((MCPWM_DT1_FED_V)<<(MCPWM_DT1_FED_S)) +#define MCPWM_DT1_FED_V 0xFFFF +#define MCPWM_DT1_FED_S 0 + +#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0098) +/* MCPWM_DT1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for RED*/ +#define MCPWM_DT1_RED 0x0000FFFF +#define MCPWM_DT1_RED_M ((MCPWM_DT1_RED_V)<<(MCPWM_DT1_RED_S)) +#define MCPWM_DT1_RED_V 0xFFFF +#define MCPWM_DT1_RED_S 0 + +#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x009c) +/* MCPWM_CARRIER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: When set invert the input of PWM1A and PWM1B for this submodule*/ +#define MCPWM_CARRIER1_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER1_IN_INVERT_M (BIT(13)) +#define MCPWM_CARRIER1_IN_INVERT_V 0x1 +#define MCPWM_CARRIER1_IN_INVERT_S 13 +/* MCPWM_CARRIER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: When set invert the output of PWM1A and PWM1B for this submodule*/ +#define MCPWM_CARRIER1_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER1_OUT_INVERT_M (BIT(12)) +#define MCPWM_CARRIER1_OUT_INVERT_V 0x1 +#define MCPWM_CARRIER1_OUT_INVERT_S 12 +/* MCPWM_CARRIER1_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: Width of the fist pulse in number of periods of the carrier*/ +#define MCPWM_CARRIER1_OSHWTH 0x0000000F +#define MCPWM_CARRIER1_OSHWTH_M ((MCPWM_CARRIER1_OSHWTH_V)<<(MCPWM_CARRIER1_OSHWTH_S)) +#define MCPWM_CARRIER1_OSHWTH_V 0xF +#define MCPWM_CARRIER1_OSHWTH_S 8 +/* MCPWM_CARRIER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: Carrier duty selection. Duty = PWM_CARRIER1_DUTY / 8*/ +#define MCPWM_CARRIER1_DUTY 0x00000007 +#define MCPWM_CARRIER1_DUTY_M ((MCPWM_CARRIER1_DUTY_V)<<(MCPWM_CARRIER1_DUTY_S)) +#define MCPWM_CARRIER1_DUTY_V 0x7 +#define MCPWM_CARRIER1_DUTY_S 5 +/* MCPWM_CARRIER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk + = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)*/ +#define MCPWM_CARRIER1_PRESCALE 0x0000000F +#define MCPWM_CARRIER1_PRESCALE_M ((MCPWM_CARRIER1_PRESCALE_V)<<(MCPWM_CARRIER1_PRESCALE_S)) +#define MCPWM_CARRIER1_PRESCALE_V 0xF +#define MCPWM_CARRIER1_PRESCALE_S 1 +/* MCPWM_CARRIER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set carrier1 function is enabled. When cleared carrier1 is bypassed*/ +#define MCPWM_CARRIER1_EN (BIT(0)) +#define MCPWM_CARRIER1_EN_M (BIT(0)) +#define MCPWM_CARRIER1_EN_V 0x1 +#define MCPWM_CARRIER1_EN_S 0 + +#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00a0) +/* MCPWM_FH1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM1B when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_B_OST_U 0x00000003 +#define MCPWM_FH1_B_OST_U_M ((MCPWM_FH1_B_OST_U_V)<<(MCPWM_FH1_B_OST_U_S)) +#define MCPWM_FH1_B_OST_U_V 0x3 +#define MCPWM_FH1_B_OST_U_S 22 +/* MCPWM_FH1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM1B when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_B_OST_D 0x00000003 +#define MCPWM_FH1_B_OST_D_M ((MCPWM_FH1_B_OST_D_V)<<(MCPWM_FH1_B_OST_D_S)) +#define MCPWM_FH1_B_OST_D_V 0x3 +#define MCPWM_FH1_B_OST_D_S 20 +/* MCPWM_FH1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_B_CBC_U 0x00000003 +#define MCPWM_FH1_B_CBC_U_M ((MCPWM_FH1_B_CBC_U_V)<<(MCPWM_FH1_B_CBC_U_S)) +#define MCPWM_FH1_B_CBC_U_V 0x3 +#define MCPWM_FH1_B_CBC_U_S 18 +/* MCPWM_FH1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_B_CBC_D 0x00000003 +#define MCPWM_FH1_B_CBC_D_M ((MCPWM_FH1_B_CBC_D_V)<<(MCPWM_FH1_B_CBC_D_S)) +#define MCPWM_FH1_B_CBC_D_V 0x3 +#define MCPWM_FH1_B_CBC_D_S 16 +/* MCPWM_FH1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM1A when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_A_OST_U 0x00000003 +#define MCPWM_FH1_A_OST_U_M ((MCPWM_FH1_A_OST_U_V)<<(MCPWM_FH1_A_OST_U_S)) +#define MCPWM_FH1_A_OST_U_V 0x3 +#define MCPWM_FH1_A_OST_U_S 14 +/* MCPWM_FH1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM1A when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_A_OST_D 0x00000003 +#define MCPWM_FH1_A_OST_D_M ((MCPWM_FH1_A_OST_D_V)<<(MCPWM_FH1_A_OST_D_S)) +#define MCPWM_FH1_A_OST_D_V 0x3 +#define MCPWM_FH1_A_OST_D_S 12 +/* MCPWM_FH1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_A_CBC_U 0x00000003 +#define MCPWM_FH1_A_CBC_U_M ((MCPWM_FH1_A_CBC_U_V)<<(MCPWM_FH1_A_CBC_U_S)) +#define MCPWM_FH1_A_CBC_U_V 0x3 +#define MCPWM_FH1_A_CBC_U_S 10 +/* MCPWM_FH1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_A_CBC_D 0x00000003 +#define MCPWM_FH1_A_CBC_D_M ((MCPWM_FH1_A_CBC_D_V)<<(MCPWM_FH1_A_CBC_D_S)) +#define MCPWM_FH1_A_CBC_D_V 0x3 +#define MCPWM_FH1_A_CBC_D_S 8 +/* MCPWM_FH1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F0_OST (BIT(7)) +#define MCPWM_FH1_F0_OST_M (BIT(7)) +#define MCPWM_FH1_F0_OST_V 0x1 +#define MCPWM_FH1_F0_OST_S 7 +/* MCPWM_FH1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F1_OST (BIT(6)) +#define MCPWM_FH1_F1_OST_M (BIT(6)) +#define MCPWM_FH1_F1_OST_V 0x1 +#define MCPWM_FH1_F1_OST_S 6 +/* MCPWM_FH1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F2_OST (BIT(5)) +#define MCPWM_FH1_F2_OST_M (BIT(5)) +#define MCPWM_FH1_F2_OST_V 0x1 +#define MCPWM_FH1_F2_OST_S 5 +/* MCPWM_FH1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_SW_OST (BIT(4)) +#define MCPWM_FH1_SW_OST_M (BIT(4)) +#define MCPWM_FH1_SW_OST_V 0x1 +#define MCPWM_FH1_SW_OST_S 4 +/* MCPWM_FH1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F0_CBC (BIT(3)) +#define MCPWM_FH1_F0_CBC_M (BIT(3)) +#define MCPWM_FH1_F0_CBC_V 0x1 +#define MCPWM_FH1_F0_CBC_S 3 +/* MCPWM_FH1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F1_CBC (BIT(2)) +#define MCPWM_FH1_F1_CBC_M (BIT(2)) +#define MCPWM_FH1_F1_CBC_V 0x1 +#define MCPWM_FH1_F1_CBC_S 2 +/* MCPWM_FH1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F2_CBC (BIT(1)) +#define MCPWM_FH1_F2_CBC_M (BIT(1)) +#define MCPWM_FH1_F2_CBC_V 0x1 +#define MCPWM_FH1_F2_CBC_S 1 +/* MCPWM_FH1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Enable register for software force cycle-by-cycle mode action. + 0: disable 1: enable*/ +#define MCPWM_FH1_SW_CBC (BIT(0)) +#define MCPWM_FH1_SW_CBC_M (BIT(0)) +#define MCPWM_FH1_SW_CBC_V 0x1 +#define MCPWM_FH1_SW_CBC_S 0 + +#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00a4) +/* MCPWM_FH1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) triggers a + one-shot mode action*/ +#define MCPWM_FH1_FORCE_OST (BIT(4)) +#define MCPWM_FH1_FORCE_OST_M (BIT(4)) +#define MCPWM_FH1_FORCE_OST_V 0x1 +#define MCPWM_FH1_FORCE_OST_S 4 +/* MCPWM_FH1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: A toggle triggers a cycle-by-cycle mode action*/ +#define MCPWM_FH1_FORCE_CBC (BIT(3)) +#define MCPWM_FH1_FORCE_CBC_M (BIT(3)) +#define MCPWM_FH1_FORCE_CBC_V 0x1 +#define MCPWM_FH1_FORCE_CBC_S 3 +/* MCPWM_FH1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ +#define MCPWM_FH1_CBCPULSE 0x00000003 +#define MCPWM_FH1_CBCPULSE_M ((MCPWM_FH1_CBCPULSE_V)<<(MCPWM_FH1_CBCPULSE_S)) +#define MCPWM_FH1_CBCPULSE_V 0x3 +#define MCPWM_FH1_CBCPULSE_S 1 +/* MCPWM_FH1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: A toggle will clear on going one-shot mode action*/ +#define MCPWM_FH1_CLR_OST (BIT(0)) +#define MCPWM_FH1_CLR_OST_M (BIT(0)) +#define MCPWM_FH1_CLR_OST_V 0x1 +#define MCPWM_FH1_CLR_OST_S 0 + +#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00a8) +/* MCPWM_FH1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ +#define MCPWM_FH1_OST_ON (BIT(1)) +#define MCPWM_FH1_OST_ON_M (BIT(1)) +#define MCPWM_FH1_OST_ON_V 0x1 +#define MCPWM_FH1_OST_ON_S 1 +/* MCPWM_FH1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ +#define MCPWM_FH1_CBC_ON (BIT(0)) +#define MCPWM_FH1_CBC_ON_M (BIT(0)) +#define MCPWM_FH1_CBC_ON_V 0x1 +#define MCPWM_FH1_CBC_ON_S 0 + +#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00ac) +/* MCPWM_GEN2_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 2 time stamp + B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN2_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN2_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_GEN2_B_SHDW_FULL_V 0x1 +#define MCPWM_GEN2_B_SHDW_FULL_S 9 +/* MCPWM_GEN2_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 2 time stamp + A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN2_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN2_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_GEN2_A_SHDW_FULL_V 0x1 +#define MCPWM_GEN2_A_SHDW_FULL_S 8 +/* MCPWM_GEN2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 2 time stamp B's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN2_B_UPMETHOD 0x0000000F +#define MCPWM_GEN2_B_UPMETHOD_M ((MCPWM_GEN2_B_UPMETHOD_V)<<(MCPWM_GEN2_B_UPMETHOD_S)) +#define MCPWM_GEN2_B_UPMETHOD_V 0xF +#define MCPWM_GEN2_B_UPMETHOD_S 4 +/* MCPWM_GEN2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 2 time stamp A's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN2_A_UPMETHOD 0x0000000F +#define MCPWM_GEN2_A_UPMETHOD_M ((MCPWM_GEN2_A_UPMETHOD_V)<<(MCPWM_GEN2_A_UPMETHOD_S)) +#define MCPWM_GEN2_A_UPMETHOD_V 0xF +#define MCPWM_GEN2_A_UPMETHOD_S 0 + +#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x00b0) +/* MCPWM_GEN2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 2 time stamp A's shadow reg*/ +#define MCPWM_GEN2_A 0x0000FFFF +#define MCPWM_GEN2_A_M ((MCPWM_GEN2_A_V)<<(MCPWM_GEN2_A_S)) +#define MCPWM_GEN2_A_V 0xFFFF +#define MCPWM_GEN2_A_S 0 + +#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x00b4) +/* MCPWM_GEN2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 2 time stamp B's shadow reg*/ +#define MCPWM_GEN2_B 0x0000FFFF +#define MCPWM_GEN2_B_M ((MCPWM_GEN2_B_V)<<(MCPWM_GEN2_B_S)) +#define MCPWM_GEN2_B_V 0xFFFF +#define MCPWM_GEN2_B_S 0 + +#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00b8) +/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ +/*description: Source selection for PWM generate2 event_t1 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN2_T1_SEL 0x00000007 +#define MCPWM_GEN2_T1_SEL_M ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S)) +#define MCPWM_GEN2_T1_SEL_V 0x7 +#define MCPWM_GEN2_T1_SEL_S 7 +/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ +/*description: Source selection for PWM generate2 event_t0 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN2_T0_SEL 0x00000007 +#define MCPWM_GEN2_T0_SEL_M ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S)) +#define MCPWM_GEN2_T0_SEL_V 0x7 +#define MCPWM_GEN2_T0_SEL_S 4 +/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generate2's active reg of configuration. + 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN2_CFG_UPMETHOD_M ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S)) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN2_CFG_UPMETHOD_S 0 + +#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x00bc) +/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM2B 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN2_B_NCIFORCE_MODE_M ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 +/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM2B a + toggle will trigger a force event*/ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_V 0x1 +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM2A 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN2_A_NCIFORCE_MODE_M ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM2A a + toggle will trigger a force event*/ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_V 0x1 +#define MCPWM_GEN2_A_NCIFORCE_S 10 +/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM2B. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM2A. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: Update method for continuous software force of PWM generator2. + 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 + +#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0x00c0) +/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN2_A_DT1 0x00000003 +#define MCPWM_GEN2_A_DT1_M ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S)) +#define MCPWM_GEN2_A_DT1_V 0x3 +#define MCPWM_GEN2_A_DT1_S 22 +/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN2_A_DT0 0x00000003 +#define MCPWM_GEN2_A_DT0_M ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S)) +#define MCPWM_GEN2_A_DT0_V 0x3 +#define MCPWM_GEN2_A_DT0_S 20 +/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN2_A_DTEB 0x00000003 +#define MCPWM_GEN2_A_DTEB_M ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S)) +#define MCPWM_GEN2_A_DTEB_V 0x3 +#define MCPWM_GEN2_A_DTEB_S 18 +/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN2_A_DTEA 0x00000003 +#define MCPWM_GEN2_A_DTEA_M ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S)) +#define MCPWM_GEN2_A_DTEA_V 0x3 +#define MCPWM_GEN2_A_DTEA_S 16 +/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN2_A_DTEP 0x00000003 +#define MCPWM_GEN2_A_DTEP_M ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S)) +#define MCPWM_GEN2_A_DTEP_V 0x3 +#define MCPWM_GEN2_A_DTEP_S 14 +/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN2_A_DTEZ 0x00000003 +#define MCPWM_GEN2_A_DTEZ_M ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S)) +#define MCPWM_GEN2_A_DTEZ_V 0x3 +#define MCPWM_GEN2_A_DTEZ_S 12 +/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN2_A_UT1 0x00000003 +#define MCPWM_GEN2_A_UT1_M ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S)) +#define MCPWM_GEN2_A_UT1_V 0x3 +#define MCPWM_GEN2_A_UT1_S 10 +/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN2_A_UT0 0x00000003 +#define MCPWM_GEN2_A_UT0_M ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S)) +#define MCPWM_GEN2_A_UT0_V 0x3 +#define MCPWM_GEN2_A_UT0_S 8 +/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEB when timer increasing*/ +#define MCPWM_GEN2_A_UTEB 0x00000003 +#define MCPWM_GEN2_A_UTEB_M ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S)) +#define MCPWM_GEN2_A_UTEB_V 0x3 +#define MCPWM_GEN2_A_UTEB_S 6 +/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEA when timer increasing*/ +#define MCPWM_GEN2_A_UTEA 0x00000003 +#define MCPWM_GEN2_A_UTEA_M ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S)) +#define MCPWM_GEN2_A_UTEA_V 0x3 +#define MCPWM_GEN2_A_UTEA_S 4 +/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEP when timer increasing*/ +#define MCPWM_GEN2_A_UTEP 0x00000003 +#define MCPWM_GEN2_A_UTEP_M ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S)) +#define MCPWM_GEN2_A_UTEP_V 0x3 +#define MCPWM_GEN2_A_UTEP_S 2 +/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN2_A_UTEZ 0x00000003 +#define MCPWM_GEN2_A_UTEZ_M ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S)) +#define MCPWM_GEN2_A_UTEZ_V 0x3 +#define MCPWM_GEN2_A_UTEZ_S 0 + +#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0x00c4) +/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN2_B_DT1 0x00000003 +#define MCPWM_GEN2_B_DT1_M ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S)) +#define MCPWM_GEN2_B_DT1_V 0x3 +#define MCPWM_GEN2_B_DT1_S 22 +/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN2_B_DT0 0x00000003 +#define MCPWM_GEN2_B_DT0_M ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S)) +#define MCPWM_GEN2_B_DT0_V 0x3 +#define MCPWM_GEN2_B_DT0_S 20 +/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN2_B_DTEB 0x00000003 +#define MCPWM_GEN2_B_DTEB_M ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S)) +#define MCPWM_GEN2_B_DTEB_V 0x3 +#define MCPWM_GEN2_B_DTEB_S 18 +/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN2_B_DTEA 0x00000003 +#define MCPWM_GEN2_B_DTEA_M ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S)) +#define MCPWM_GEN2_B_DTEA_V 0x3 +#define MCPWM_GEN2_B_DTEA_S 16 +/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN2_B_DTEP 0x00000003 +#define MCPWM_GEN2_B_DTEP_M ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S)) +#define MCPWM_GEN2_B_DTEP_V 0x3 +#define MCPWM_GEN2_B_DTEP_S 14 +/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN2_B_DTEZ 0x00000003 +#define MCPWM_GEN2_B_DTEZ_M ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S)) +#define MCPWM_GEN2_B_DTEZ_V 0x3 +#define MCPWM_GEN2_B_DTEZ_S 12 +/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN2_B_UT1 0x00000003 +#define MCPWM_GEN2_B_UT1_M ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S)) +#define MCPWM_GEN2_B_UT1_V 0x3 +#define MCPWM_GEN2_B_UT1_S 10 +/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN2_B_UT0 0x00000003 +#define MCPWM_GEN2_B_UT0_M ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S)) +#define MCPWM_GEN2_B_UT0_V 0x3 +#define MCPWM_GEN2_B_UT0_S 8 +/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEB when timer increasing*/ +#define MCPWM_GEN2_B_UTEB 0x00000003 +#define MCPWM_GEN2_B_UTEB_M ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S)) +#define MCPWM_GEN2_B_UTEB_V 0x3 +#define MCPWM_GEN2_B_UTEB_S 6 +/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEA when timer increasing*/ +#define MCPWM_GEN2_B_UTEA 0x00000003 +#define MCPWM_GEN2_B_UTEA_M ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S)) +#define MCPWM_GEN2_B_UTEA_V 0x3 +#define MCPWM_GEN2_B_UTEA_S 4 +/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEP when timer increasing*/ +#define MCPWM_GEN2_B_UTEP 0x00000003 +#define MCPWM_GEN2_B_UTEP_M ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S)) +#define MCPWM_GEN2_B_UTEP_V 0x3 +#define MCPWM_GEN2_B_UTEP_S 2 +/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN2_B_UTEZ 0x00000003 +#define MCPWM_GEN2_B_UTEZ_M ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S)) +#define MCPWM_GEN2_B_UTEZ_V 0x3 +#define MCPWM_GEN2_B_UTEZ_S 0 + +#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00c8) +/* MCPWM_DT2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Dead time generator 1 clock selection. 0: PWM_clk 1: PT_clk*/ +#define MCPWM_DT2_CLK_SEL (BIT(17)) +#define MCPWM_DT2_CLK_SEL_M (BIT(17)) +#define MCPWM_DT2_CLK_SEL_V 0x1 +#define MCPWM_DT2_CLK_SEL_S 17 +/* MCPWM_DT2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: S0 in documentation*/ +#define MCPWM_DT2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT2_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DT2_B_OUTBYPASS_V 0x1 +#define MCPWM_DT2_B_OUTBYPASS_S 16 +/* MCPWM_DT2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: S1 in documentation*/ +#define MCPWM_DT2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT2_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DT2_A_OUTBYPASS_V 0x1 +#define MCPWM_DT2_A_OUTBYPASS_S 15 +/* MCPWM_DT2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: S3 in documentation*/ +#define MCPWM_DT2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT2_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DT2_FED_OUTINVERT_V 0x1 +#define MCPWM_DT2_FED_OUTINVERT_S 14 +/* MCPWM_DT2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: S2 in documentation*/ +#define MCPWM_DT2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT2_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DT2_RED_OUTINVERT_V 0x1 +#define MCPWM_DT2_RED_OUTINVERT_S 13 +/* MCPWM_DT2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: S5 in documentation*/ +#define MCPWM_DT2_FED_INSEL (BIT(12)) +#define MCPWM_DT2_FED_INSEL_M (BIT(12)) +#define MCPWM_DT2_FED_INSEL_V 0x1 +#define MCPWM_DT2_FED_INSEL_S 12 +/* MCPWM_DT2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: S4 in documentation*/ +#define MCPWM_DT2_RED_INSEL (BIT(11)) +#define MCPWM_DT2_RED_INSEL_M (BIT(11)) +#define MCPWM_DT2_RED_INSEL_V 0x1 +#define MCPWM_DT2_RED_INSEL_S 11 +/* MCPWM_DT2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: S7 in documentation*/ +#define MCPWM_DT2_B_OUTSWAP (BIT(10)) +#define MCPWM_DT2_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DT2_B_OUTSWAP_V 0x1 +#define MCPWM_DT2_B_OUTSWAP_S 10 +/* MCPWM_DT2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: S6 in documentation*/ +#define MCPWM_DT2_A_OUTSWAP (BIT(9)) +#define MCPWM_DT2_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DT2_A_OUTSWAP_V 0x1 +#define MCPWM_DT2_A_OUTSWAP_S 9 +/* MCPWM_DT2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect + on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ +#define MCPWM_DT2_DEB_MODE (BIT(8)) +#define MCPWM_DT2_DEB_MODE_M (BIT(8)) +#define MCPWM_DT2_DEB_MODE_V 0x1 +#define MCPWM_DT2_DEB_MODE_S 8 +/* MCPWM_DT2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for RED (rising edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT2_RED_UPMETHOD 0x0000000F +#define MCPWM_DT2_RED_UPMETHOD_M ((MCPWM_DT2_RED_UPMETHOD_V)<<(MCPWM_DT2_RED_UPMETHOD_S)) +#define MCPWM_DT2_RED_UPMETHOD_V 0xF +#define MCPWM_DT2_RED_UPMETHOD_S 4 +/* MCPWM_DT2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for FED (falling edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT2_FED_UPMETHOD 0x0000000F +#define MCPWM_DT2_FED_UPMETHOD_M ((MCPWM_DT2_FED_UPMETHOD_V)<<(MCPWM_DT2_FED_UPMETHOD_S)) +#define MCPWM_DT2_FED_UPMETHOD_V 0xF +#define MCPWM_DT2_FED_UPMETHOD_S 0 + +#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00cc) +/* MCPWM_DT2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for FED*/ +#define MCPWM_DT2_FED 0x0000FFFF +#define MCPWM_DT2_FED_M ((MCPWM_DT2_FED_V)<<(MCPWM_DT2_FED_S)) +#define MCPWM_DT2_FED_V 0xFFFF +#define MCPWM_DT2_FED_S 0 + +#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d0) +/* MCPWM_DT2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for RED*/ +#define MCPWM_DT2_RED 0x0000FFFF +#define MCPWM_DT2_RED_M ((MCPWM_DT2_RED_V)<<(MCPWM_DT2_RED_S)) +#define MCPWM_DT2_RED_V 0xFFFF +#define MCPWM_DT2_RED_S 0 + +#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d4) +/* MCPWM_CARRIER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: When set invert the input of PWM2A and PWM2B for this submodule*/ +#define MCPWM_CARRIER2_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER2_IN_INVERT_M (BIT(13)) +#define MCPWM_CARRIER2_IN_INVERT_V 0x1 +#define MCPWM_CARRIER2_IN_INVERT_S 13 +/* MCPWM_CARRIER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: When set invert the output of PWM2A and PWM2B for this submodule*/ +#define MCPWM_CARRIER2_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER2_OUT_INVERT_M (BIT(12)) +#define MCPWM_CARRIER2_OUT_INVERT_V 0x1 +#define MCPWM_CARRIER2_OUT_INVERT_S 12 +/* MCPWM_CARRIER2_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: Width of the fist pulse in number of periods of the carrier*/ +#define MCPWM_CARRIER2_OSHWTH 0x0000000F +#define MCPWM_CARRIER2_OSHWTH_M ((MCPWM_CARRIER2_OSHWTH_V)<<(MCPWM_CARRIER2_OSHWTH_S)) +#define MCPWM_CARRIER2_OSHWTH_V 0xF +#define MCPWM_CARRIER2_OSHWTH_S 8 +/* MCPWM_CARRIER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: Carrier duty selection. Duty = PWM_CARRIER2_DUTY / 8*/ +#define MCPWM_CARRIER2_DUTY 0x00000007 +#define MCPWM_CARRIER2_DUTY_M ((MCPWM_CARRIER2_DUTY_V)<<(MCPWM_CARRIER2_DUTY_S)) +#define MCPWM_CARRIER2_DUTY_V 0x7 +#define MCPWM_CARRIER2_DUTY_S 5 +/* MCPWM_CARRIER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk + = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)*/ +#define MCPWM_CARRIER2_PRESCALE 0x0000000F +#define MCPWM_CARRIER2_PRESCALE_M ((MCPWM_CARRIER2_PRESCALE_V)<<(MCPWM_CARRIER2_PRESCALE_S)) +#define MCPWM_CARRIER2_PRESCALE_V 0xF +#define MCPWM_CARRIER2_PRESCALE_S 1 +/* MCPWM_CARRIER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set carrier2 function is enabled. When cleared carrier2 is bypassed*/ +#define MCPWM_CARRIER2_EN (BIT(0)) +#define MCPWM_CARRIER2_EN_M (BIT(0)) +#define MCPWM_CARRIER2_EN_V 0x1 +#define MCPWM_CARRIER2_EN_S 0 + +#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00d8) +/* MCPWM_FH2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM2B when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_B_OST_U 0x00000003 +#define MCPWM_FH2_B_OST_U_M ((MCPWM_FH2_B_OST_U_V)<<(MCPWM_FH2_B_OST_U_S)) +#define MCPWM_FH2_B_OST_U_V 0x3 +#define MCPWM_FH2_B_OST_U_S 22 +/* MCPWM_FH2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM2B when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_B_OST_D 0x00000003 +#define MCPWM_FH2_B_OST_D_M ((MCPWM_FH2_B_OST_D_V)<<(MCPWM_FH2_B_OST_D_S)) +#define MCPWM_FH2_B_OST_D_V 0x3 +#define MCPWM_FH2_B_OST_D_S 20 +/* MCPWM_FH2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_B_CBC_U 0x00000003 +#define MCPWM_FH2_B_CBC_U_M ((MCPWM_FH2_B_CBC_U_V)<<(MCPWM_FH2_B_CBC_U_S)) +#define MCPWM_FH2_B_CBC_U_V 0x3 +#define MCPWM_FH2_B_CBC_U_S 18 +/* MCPWM_FH2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_B_CBC_D 0x00000003 +#define MCPWM_FH2_B_CBC_D_M ((MCPWM_FH2_B_CBC_D_V)<<(MCPWM_FH2_B_CBC_D_S)) +#define MCPWM_FH2_B_CBC_D_V 0x3 +#define MCPWM_FH2_B_CBC_D_S 16 +/* MCPWM_FH2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM2A when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_A_OST_U 0x00000003 +#define MCPWM_FH2_A_OST_U_M ((MCPWM_FH2_A_OST_U_V)<<(MCPWM_FH2_A_OST_U_S)) +#define MCPWM_FH2_A_OST_U_V 0x3 +#define MCPWM_FH2_A_OST_U_S 14 +/* MCPWM_FH2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM2A when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_A_OST_D 0x00000003 +#define MCPWM_FH2_A_OST_D_M ((MCPWM_FH2_A_OST_D_V)<<(MCPWM_FH2_A_OST_D_S)) +#define MCPWM_FH2_A_OST_D_V 0x3 +#define MCPWM_FH2_A_OST_D_S 12 +/* MCPWM_FH2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_A_CBC_U 0x00000003 +#define MCPWM_FH2_A_CBC_U_M ((MCPWM_FH2_A_CBC_U_V)<<(MCPWM_FH2_A_CBC_U_S)) +#define MCPWM_FH2_A_CBC_U_V 0x3 +#define MCPWM_FH2_A_CBC_U_S 10 +/* MCPWM_FH2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_A_CBC_D 0x00000003 +#define MCPWM_FH2_A_CBC_D_M ((MCPWM_FH2_A_CBC_D_V)<<(MCPWM_FH2_A_CBC_D_S)) +#define MCPWM_FH2_A_CBC_D_V 0x3 +#define MCPWM_FH2_A_CBC_D_S 8 +/* MCPWM_FH2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F0_OST (BIT(7)) +#define MCPWM_FH2_F0_OST_M (BIT(7)) +#define MCPWM_FH2_F0_OST_V 0x1 +#define MCPWM_FH2_F0_OST_S 7 +/* MCPWM_FH2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F1_OST (BIT(6)) +#define MCPWM_FH2_F1_OST_M (BIT(6)) +#define MCPWM_FH2_F1_OST_V 0x1 +#define MCPWM_FH2_F1_OST_S 6 +/* MCPWM_FH2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F2_OST (BIT(5)) +#define MCPWM_FH2_F2_OST_M (BIT(5)) +#define MCPWM_FH2_F2_OST_V 0x1 +#define MCPWM_FH2_F2_OST_S 5 +/* MCPWM_FH2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_SW_OST (BIT(4)) +#define MCPWM_FH2_SW_OST_M (BIT(4)) +#define MCPWM_FH2_SW_OST_V 0x1 +#define MCPWM_FH2_SW_OST_S 4 +/* MCPWM_FH2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F0_CBC (BIT(3)) +#define MCPWM_FH2_F0_CBC_M (BIT(3)) +#define MCPWM_FH2_F0_CBC_V 0x1 +#define MCPWM_FH2_F0_CBC_S 3 +/* MCPWM_FH2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F1_CBC (BIT(2)) +#define MCPWM_FH2_F1_CBC_M (BIT(2)) +#define MCPWM_FH2_F1_CBC_V 0x1 +#define MCPWM_FH2_F1_CBC_S 2 +/* MCPWM_FH2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F2_CBC (BIT(1)) +#define MCPWM_FH2_F2_CBC_M (BIT(1)) +#define MCPWM_FH2_F2_CBC_V 0x1 +#define MCPWM_FH2_F2_CBC_S 1 +/* MCPWM_FH2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Enable register for software force cycle-by-cycle mode action. + 0: disable 1: enable*/ +#define MCPWM_FH2_SW_CBC (BIT(0)) +#define MCPWM_FH2_SW_CBC_M (BIT(0)) +#define MCPWM_FH2_SW_CBC_V 0x1 +#define MCPWM_FH2_SW_CBC_S 0 + +#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00dc) +/* MCPWM_FH2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) triggers a + one-shot mode action*/ +#define MCPWM_FH2_FORCE_OST (BIT(4)) +#define MCPWM_FH2_FORCE_OST_M (BIT(4)) +#define MCPWM_FH2_FORCE_OST_V 0x1 +#define MCPWM_FH2_FORCE_OST_S 4 +/* MCPWM_FH2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: A toggle triggers a cycle-by-cycle mode action*/ +#define MCPWM_FH2_FORCE_CBC (BIT(3)) +#define MCPWM_FH2_FORCE_CBC_M (BIT(3)) +#define MCPWM_FH2_FORCE_CBC_V 0x1 +#define MCPWM_FH2_FORCE_CBC_S 3 +/* MCPWM_FH2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ +#define MCPWM_FH2_CBCPULSE 0x00000003 +#define MCPWM_FH2_CBCPULSE_M ((MCPWM_FH2_CBCPULSE_V)<<(MCPWM_FH2_CBCPULSE_S)) +#define MCPWM_FH2_CBCPULSE_V 0x3 +#define MCPWM_FH2_CBCPULSE_S 1 +/* MCPWM_FH2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: A toggle will clear on going one-shot mode action*/ +#define MCPWM_FH2_CLR_OST (BIT(0)) +#define MCPWM_FH2_CLR_OST_M (BIT(0)) +#define MCPWM_FH2_CLR_OST_V 0x1 +#define MCPWM_FH2_CLR_OST_S 0 + +#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00e0) +/* MCPWM_FH2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ +#define MCPWM_FH2_OST_ON (BIT(1)) +#define MCPWM_FH2_OST_ON_M (BIT(1)) +#define MCPWM_FH2_OST_ON_V 0x1 +#define MCPWM_FH2_OST_ON_S 1 +/* MCPWM_FH2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ +#define MCPWM_FH2_CBC_ON (BIT(0)) +#define MCPWM_FH2_CBC_ON_M (BIT(0)) +#define MCPWM_FH2_CBC_ON_V 0x1 +#define MCPWM_FH2_CBC_ON_S 0 + +#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0x00e4) +/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set event_f2 is on going*/ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (BIT(8)) +#define MCPWM_EVENT_F2_V 0x1 +#define MCPWM_EVENT_F2_S 8 +/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set event_f1 is on going*/ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (BIT(7)) +#define MCPWM_EVENT_F1_V 0x1 +#define MCPWM_EVENT_F1_S 7 +/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set event_f0 is on going*/ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (BIT(6)) +#define MCPWM_EVENT_F0_V 0x1 +#define MCPWM_EVENT_F0_S 6 +/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. + 0: level low 1: level high*/ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (BIT(5)) +#define MCPWM_F2_POLE_V 0x1 +#define MCPWM_F2_POLE_S 5 +/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. + 0: level low 1: level high*/ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (BIT(4)) +#define MCPWM_F1_POLE_V 0x1 +#define MCPWM_F1_POLE_S 4 +/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. + 0: level low 1: level high*/ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (BIT(3)) +#define MCPWM_F0_POLE_V 0x1 +#define MCPWM_F0_POLE_S 3 +/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: Set to enable generation of event_f2*/ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (BIT(2)) +#define MCPWM_F2_EN_V 0x1 +#define MCPWM_F2_EN_S 2 +/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Set to enable generation of event_f1*/ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (BIT(1)) +#define MCPWM_F1_EN_V 0x1 +#define MCPWM_F1_EN_S 1 +/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Set to enable generation of event_f0*/ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (BIT(0)) +#define MCPWM_F0_EN_V 0x1 +#define MCPWM_F0_EN_S 0 + +#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00e8) +/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */ +/*description: Set this bit to force a capture timer sync capture timer is + loaded with value in phase register.*/ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (BIT(5)) +#define MCPWM_CAP_SYNC_SW_V 0x1 +#define MCPWM_CAP_SYNC_SW_S 5 +/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: Capture module sync input selection. 0: none 1: timer0 synco + 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/ +#define MCPWM_CAP_SYNCI_SEL 0x00000007 +#define MCPWM_CAP_SYNCI_SEL_M ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S)) +#define MCPWM_CAP_SYNCI_SEL_V 0x7 +#define MCPWM_CAP_SYNCI_SEL_S 2 +/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: When set capture timer sync is enabled.*/ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_V 0x1 +#define MCPWM_CAP_SYNCI_EN_S 1 +/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set capture timer incrementing under APB_clk is enabled.*/ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (BIT(0)) +#define MCPWM_CAP_TIMER_EN_V 0x1 +#define MCPWM_CAP_TIMER_EN_S 0 + +#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0x00ec) +/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: Phase value for capture timer sync operation.*/ +#define MCPWM_CAP_PHASE 0xFFFFFFFF +#define MCPWM_CAP_PHASE_M ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S)) +#define MCPWM_CAP_PHASE_V 0xFFFFFFFF +#define MCPWM_CAP_PHASE_S 0 + +#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f0) +/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Write 1 will trigger a software forced capture on channel 0*/ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (BIT(12)) +#define MCPWM_CAP0_SW_V 0x1 +#define MCPWM_CAP0_SW_S 12 +/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: When set CAP0 form GPIO matrix is inverted before prescale*/ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_V 0x1 +#define MCPWM_CAP0_IN_INVERT_S 11 +/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: Value of prescale on possitive edge of CAP0. Prescale value = + PWM_CAP0_PRESCALE + 1*/ +#define MCPWM_CAP0_PRESCALE 0x000000FF +#define MCPWM_CAP0_PRESCALE_M ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S)) +#define MCPWM_CAP0_PRESCALE_V 0xFF +#define MCPWM_CAP0_PRESCALE_S 3 +/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: Edge of capture on channel 0 after prescale. bit0: negedge cap + en bit1: posedge cap en*/ +#define MCPWM_CAP0_MODE 0x00000003 +#define MCPWM_CAP0_MODE_M ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S)) +#define MCPWM_CAP0_MODE_V 0x3 +#define MCPWM_CAP0_MODE_S 1 +/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set capture on channel 0 is enabled*/ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (BIT(0)) +#define MCPWM_CAP0_EN_V 0x1 +#define MCPWM_CAP0_EN_S 0 + +#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f4) +/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Write 1 will trigger a software forced capture on channel 1*/ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (BIT(12)) +#define MCPWM_CAP1_SW_V 0x1 +#define MCPWM_CAP1_SW_S 12 +/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: When set CAP1 form GPIO matrix is inverted before prescale*/ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_V 0x1 +#define MCPWM_CAP1_IN_INVERT_S 11 +/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: Value of prescale on possitive edge of CAP1. Prescale value = + PWM_CAP1_PRESCALE + 1*/ +#define MCPWM_CAP1_PRESCALE 0x000000FF +#define MCPWM_CAP1_PRESCALE_M ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S)) +#define MCPWM_CAP1_PRESCALE_V 0xFF +#define MCPWM_CAP1_PRESCALE_S 3 +/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: Edge of capture on channel 1 after prescale. bit0: negedge cap + en bit1: posedge cap en*/ +#define MCPWM_CAP1_MODE 0x00000003 +#define MCPWM_CAP1_MODE_M ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S)) +#define MCPWM_CAP1_MODE_V 0x3 +#define MCPWM_CAP1_MODE_S 1 +/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set capture on channel 1 is enabled*/ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (BIT(0)) +#define MCPWM_CAP1_EN_V 0x1 +#define MCPWM_CAP1_EN_S 0 + +#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f8) +/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Write 1 will trigger a software forced capture on channel 2*/ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (BIT(12)) +#define MCPWM_CAP2_SW_V 0x1 +#define MCPWM_CAP2_SW_S 12 +/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: When set CAP2 form GPIO matrix is inverted before prescale*/ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_V 0x1 +#define MCPWM_CAP2_IN_INVERT_S 11 +/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: Value of prescale on possitive edge of CAP2. Prescale value = + PWM_CAP2_PRESCALE + 1*/ +#define MCPWM_CAP2_PRESCALE 0x000000FF +#define MCPWM_CAP2_PRESCALE_M ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S)) +#define MCPWM_CAP2_PRESCALE_V 0xFF +#define MCPWM_CAP2_PRESCALE_S 3 +/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: Edge of capture on channel 2 after prescale. bit0: negedge cap + en bit1: posedge cap en*/ +#define MCPWM_CAP2_MODE 0x00000003 +#define MCPWM_CAP2_MODE_M ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S)) +#define MCPWM_CAP2_MODE_V 0x3 +#define MCPWM_CAP2_MODE_S 1 +/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set capture on channel 2 is enabled*/ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (BIT(0)) +#define MCPWM_CAP2_EN_V 0x1 +#define MCPWM_CAP2_EN_S 0 + +#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0x00fc) +/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: Value of last capture on channel 0*/ +#define MCPWM_CAP0_VALUE 0xFFFFFFFF +#define MCPWM_CAP0_VALUE_M ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S)) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP0_VALUE_S 0 + +#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x0100) +/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: Value of last capture on channel 1*/ +#define MCPWM_CAP1_VALUE 0xFFFFFFFF +#define MCPWM_CAP1_VALUE_M ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S)) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP1_VALUE_S 0 + +#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x0104) +/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: Value of last capture on channel 2*/ +#define MCPWM_CAP2_VALUE 0xFFFFFFFF +#define MCPWM_CAP2_VALUE_M ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S)) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP2_VALUE_S 0 + +#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0108) +/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */ +/*description: Edge of last capture trigger on channel 2 0: posedge 1: negedge*/ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (BIT(2)) +#define MCPWM_CAP2_EDGE_V 0x1 +#define MCPWM_CAP2_EDGE_S 2 +/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Edge of last capture trigger on channel 1 0: posedge 1: negedge*/ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (BIT(1)) +#define MCPWM_CAP1_EDGE_V 0x1 +#define MCPWM_CAP1_EDGE_S 1 +/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Edge of last capture trigger on channel 0 0: posedge 1: negedge*/ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (BIT(0)) +#define MCPWM_CAP0_EDGE_V 0x1 +#define MCPWM_CAP0_EDGE_S 0 + +#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x010c) +/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) will trigger + a forced update of active registers in PWM operator 2*/ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (BIT(7)) +#define MCPWM_OP2_FORCE_UP_V 0x1 +#define MCPWM_OP2_FORCE_UP_S 7 +/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers + in PWM operator 2 are enabled*/ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (BIT(6)) +#define MCPWM_OP2_UP_EN_V 0x1 +#define MCPWM_OP2_UP_EN_S 6 +/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) will trigger + a forced update of active registers in PWM operator 1*/ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (BIT(5)) +#define MCPWM_OP1_FORCE_UP_V 0x1 +#define MCPWM_OP1_FORCE_UP_S 5 +/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */ +/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers + in PWM operator 1 are enabled*/ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (BIT(4)) +#define MCPWM_OP1_UP_EN_V 0x1 +#define MCPWM_OP1_UP_EN_S 4 +/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) will trigger + a forced update of active registers in PWM operator 0*/ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (BIT(3)) +#define MCPWM_OP0_FORCE_UP_V 0x1 +#define MCPWM_OP0_FORCE_UP_S 3 +/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */ +/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers + in PWM operator 0 are enabled*/ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (BIT(2)) +#define MCPWM_OP0_UP_EN_V 0x1 +#define MCPWM_OP0_UP_EN_S 2 +/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) will trigger + a forced update of all active registers in MCPWM module*/ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_V 0x1 +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: The global enable of update of all active registers in MCPWM module*/ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_V 0x1 +#define MCPWM_GLOBAL_UP_EN_S 0 + +#define MCMCPWM_INT_ENA_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0110) +/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by captureon channel 2*/ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (BIT(29)) +#define MCPWM_CAP2_INT_ENA_V 0x1 +#define MCPWM_CAP2_INT_ENA_S 29 +/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by captureon channel 1*/ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (BIT(28)) +#define MCPWM_CAP1_INT_ENA_V 0x1 +#define MCPWM_CAP1_INT_ENA_S 28 +/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by captureon channel 0*/ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (BIT(27)) +#define MCPWM_CAP0_INT_ENA_V 0x1 +#define MCPWM_CAP0_INT_ENA_S 27 +/* MCPWM_FH2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM2*/ +#define MCPWM_FH2_OST_INT_ENA (BIT(26)) +#define MCPWM_FH2_OST_INT_ENA_M (BIT(26)) +#define MCPWM_FH2_OST_INT_ENA_V 0x1 +#define MCPWM_FH2_OST_INT_ENA_S 26 +/* MCPWM_FH1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH1_OST_INT_ENA (BIT(25)) +#define MCPWM_FH1_OST_INT_ENA_M (BIT(25)) +#define MCPWM_FH1_OST_INT_ENA_V 0x1 +#define MCPWM_FH1_OST_INT_ENA_S 25 +/* MCPWM_FH0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH0_OST_INT_ENA (BIT(24)) +#define MCPWM_FH0_OST_INT_ENA_M (BIT(24)) +#define MCPWM_FH0_OST_INT_ENA_V 0x1 +#define MCPWM_FH0_OST_INT_ENA_S 24 +/* MCPWM_FH2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM2*/ +#define MCPWM_FH2_CBC_INT_ENA (BIT(23)) +#define MCPWM_FH2_CBC_INT_ENA_M (BIT(23)) +#define MCPWM_FH2_CBC_INT_ENA_V 0x1 +#define MCPWM_FH2_CBC_INT_ENA_S 23 +/* MCPWM_FH1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM1*/ +#define MCPWM_FH1_CBC_INT_ENA (BIT(22)) +#define MCPWM_FH1_CBC_INT_ENA_M (BIT(22)) +#define MCPWM_FH1_CBC_INT_ENA_V 0x1 +#define MCPWM_FH1_CBC_INT_ENA_S 22 +/* MCPWM_FH0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM0*/ +#define MCPWM_FH0_CBC_INT_ENA (BIT(21)) +#define MCPWM_FH0_CBC_INT_ENA_M (BIT(21)) +#define MCPWM_FH0_CBC_INT_ENA_V 0x1 +#define MCPWM_FH0_CBC_INT_ENA_S 21 +/* MCPWM_OP2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 2 TEB event*/ +#define MCPWM_OP2_TEB_INT_ENA (BIT(20)) +#define MCPWM_OP2_TEB_INT_ENA_M (BIT(20)) +#define MCPWM_OP2_TEB_INT_ENA_V 0x1 +#define MCPWM_OP2_TEB_INT_ENA_S 20 +/* MCPWM_OP1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 1 TEB event*/ +#define MCPWM_OP1_TEB_INT_ENA (BIT(19)) +#define MCPWM_OP1_TEB_INT_ENA_M (BIT(19)) +#define MCPWM_OP1_TEB_INT_ENA_V 0x1 +#define MCPWM_OP1_TEB_INT_ENA_S 19 +/* MCPWM_OP0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 0 TEB event*/ +#define MCPWM_OP0_TEB_INT_ENA (BIT(18)) +#define MCPWM_OP0_TEB_INT_ENA_M (BIT(18)) +#define MCPWM_OP0_TEB_INT_ENA_V 0x1 +#define MCPWM_OP0_TEB_INT_ENA_S 18 +/* MCPWM_OP2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 2 TEA event*/ +#define MCPWM_OP2_TEA_INT_ENA (BIT(17)) +#define MCPWM_OP2_TEA_INT_ENA_M (BIT(17)) +#define MCPWM_OP2_TEA_INT_ENA_V 0x1 +#define MCPWM_OP2_TEA_INT_ENA_S 17 +/* MCPWM_OP1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 1 TEA event*/ +#define MCPWM_OP1_TEA_INT_ENA (BIT(16)) +#define MCPWM_OP1_TEA_INT_ENA_M (BIT(16)) +#define MCPWM_OP1_TEA_INT_ENA_V 0x1 +#define MCPWM_OP1_TEA_INT_ENA_S 16 +/* MCPWM_OP0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 0 TEA event*/ +#define MCPWM_OP0_TEA_INT_ENA (BIT(15)) +#define MCPWM_OP0_TEA_INT_ENA_M (BIT(15)) +#define MCPWM_OP0_TEA_INT_ENA_V 0x1 +#define MCPWM_OP0_TEA_INT_ENA_S 15 +/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f2 ends*/ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f1 ends*/ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f0 ends*/ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f2 starts*/ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_V 0x1 +#define MCPWM_FAULT2_INT_ENA_S 11 +/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f1 starts*/ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_V 0x1 +#define MCPWM_FAULT1_INT_ENA_S 10 +/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f0 starts*/ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_V 0x1 +#define MCPWM_FAULT0_INT_ENA_S 9 +/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 2 TEP event*/ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 1 TEP event*/ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 0 TEP event*/ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 2 TEZ event*/ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 1 TEZ event*/ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 0 TEZ event*/ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered when timer 2 stops*/ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered when timer 1 stops*/ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered when timer 0 stops*/ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ENA_S 0 + +#define MCMCPWM_INT_RAW_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0114) +/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by captureon channel 2*/ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (BIT(29)) +#define MCPWM_CAP2_INT_RAW_V 0x1 +#define MCPWM_CAP2_INT_RAW_S 29 +/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by captureon channel 1*/ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (BIT(28)) +#define MCPWM_CAP1_INT_RAW_V 0x1 +#define MCPWM_CAP1_INT_RAW_S 28 +/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by captureon channel 0*/ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (BIT(27)) +#define MCPWM_CAP0_INT_RAW_V 0x1 +#define MCPWM_CAP0_INT_RAW_S 27 +/* MCPWM_FH2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM2*/ +#define MCPWM_FH2_OST_INT_RAW (BIT(26)) +#define MCPWM_FH2_OST_INT_RAW_M (BIT(26)) +#define MCPWM_FH2_OST_INT_RAW_V 0x1 +#define MCPWM_FH2_OST_INT_RAW_S 26 +/* MCPWM_FH1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH1_OST_INT_RAW (BIT(25)) +#define MCPWM_FH1_OST_INT_RAW_M (BIT(25)) +#define MCPWM_FH1_OST_INT_RAW_V 0x1 +#define MCPWM_FH1_OST_INT_RAW_S 25 +/* MCPWM_FH0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH0_OST_INT_RAW (BIT(24)) +#define MCPWM_FH0_OST_INT_RAW_M (BIT(24)) +#define MCPWM_FH0_OST_INT_RAW_V 0x1 +#define MCPWM_FH0_OST_INT_RAW_S 24 +/* MCPWM_FH2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM2*/ +#define MCPWM_FH2_CBC_INT_RAW (BIT(23)) +#define MCPWM_FH2_CBC_INT_RAW_M (BIT(23)) +#define MCPWM_FH2_CBC_INT_RAW_V 0x1 +#define MCPWM_FH2_CBC_INT_RAW_S 23 +/* MCPWM_FH1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM1*/ +#define MCPWM_FH1_CBC_INT_RAW (BIT(22)) +#define MCPWM_FH1_CBC_INT_RAW_M (BIT(22)) +#define MCPWM_FH1_CBC_INT_RAW_V 0x1 +#define MCPWM_FH1_CBC_INT_RAW_S 22 +/* MCPWM_FH0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM0*/ +#define MCPWM_FH0_CBC_INT_RAW (BIT(21)) +#define MCPWM_FH0_CBC_INT_RAW_M (BIT(21)) +#define MCPWM_FH0_CBC_INT_RAW_V 0x1 +#define MCPWM_FH0_CBC_INT_RAW_S 21 +/* MCPWM_OP2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEB event*/ +#define MCPWM_OP2_TEB_INT_RAW (BIT(20)) +#define MCPWM_OP2_TEB_INT_RAW_M (BIT(20)) +#define MCPWM_OP2_TEB_INT_RAW_V 0x1 +#define MCPWM_OP2_TEB_INT_RAW_S 20 +/* MCPWM_OP1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEB event*/ +#define MCPWM_OP1_TEB_INT_RAW (BIT(19)) +#define MCPWM_OP1_TEB_INT_RAW_M (BIT(19)) +#define MCPWM_OP1_TEB_INT_RAW_V 0x1 +#define MCPWM_OP1_TEB_INT_RAW_S 19 +/* MCPWM_OP0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEB event*/ +#define MCPWM_OP0_TEB_INT_RAW (BIT(18)) +#define MCPWM_OP0_TEB_INT_RAW_M (BIT(18)) +#define MCPWM_OP0_TEB_INT_RAW_V 0x1 +#define MCPWM_OP0_TEB_INT_RAW_S 18 +/* MCPWM_OP2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEA event*/ +#define MCPWM_OP2_TEA_INT_RAW (BIT(17)) +#define MCPWM_OP2_TEA_INT_RAW_M (BIT(17)) +#define MCPWM_OP2_TEA_INT_RAW_V 0x1 +#define MCPWM_OP2_TEA_INT_RAW_S 17 +/* MCPWM_OP1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEA event*/ +#define MCPWM_OP1_TEA_INT_RAW (BIT(16)) +#define MCPWM_OP1_TEA_INT_RAW_M (BIT(16)) +#define MCPWM_OP1_TEA_INT_RAW_V 0x1 +#define MCPWM_OP1_TEA_INT_RAW_S 16 +/* MCPWM_OP0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEA event*/ +#define MCPWM_OP0_TEA_INT_RAW (BIT(15)) +#define MCPWM_OP0_TEA_INT_RAW_M (BIT(15)) +#define MCPWM_OP0_TEA_INT_RAW_V 0x1 +#define MCPWM_OP0_TEA_INT_RAW_S 15 +/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f2 ends*/ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f1 ends*/ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f0 ends*/ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f2 starts*/ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_V 0x1 +#define MCPWM_FAULT2_INT_RAW_S 11 +/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f1 starts*/ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_V 0x1 +#define MCPWM_FAULT1_INT_RAW_S 10 +/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f0 starts*/ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_V 0x1 +#define MCPWM_FAULT0_INT_RAW_S 9 +/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEP event*/ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEP event*/ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEP event*/ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEZ event*/ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEZ event*/ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEZ event*/ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered when timer 2 stops*/ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered when timer 1 stops*/ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered when timer 0 stops*/ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER0_STOP_INT_RAW_S 0 + +#define MCMCPWM_INT_ST_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0118) +/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by captureon channel 2*/ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (BIT(29)) +#define MCPWM_CAP2_INT_ST_V 0x1 +#define MCPWM_CAP2_INT_ST_S 29 +/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by captureon channel 1*/ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (BIT(28)) +#define MCPWM_CAP1_INT_ST_V 0x1 +#define MCPWM_CAP1_INT_ST_S 28 +/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by captureon channel 0*/ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (BIT(27)) +#define MCPWM_CAP0_INT_ST_V 0x1 +#define MCPWM_CAP0_INT_ST_S 27 +/* MCPWM_FH2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM2*/ +#define MCPWM_FH2_OST_INT_ST (BIT(26)) +#define MCPWM_FH2_OST_INT_ST_M (BIT(26)) +#define MCPWM_FH2_OST_INT_ST_V 0x1 +#define MCPWM_FH2_OST_INT_ST_S 26 +/* MCPWM_FH1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH1_OST_INT_ST (BIT(25)) +#define MCPWM_FH1_OST_INT_ST_M (BIT(25)) +#define MCPWM_FH1_OST_INT_ST_V 0x1 +#define MCPWM_FH1_OST_INT_ST_S 25 +/* MCPWM_FH0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH0_OST_INT_ST (BIT(24)) +#define MCPWM_FH0_OST_INT_ST_M (BIT(24)) +#define MCPWM_FH0_OST_INT_ST_V 0x1 +#define MCPWM_FH0_OST_INT_ST_S 24 +/* MCPWM_FH2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM2*/ +#define MCPWM_FH2_CBC_INT_ST (BIT(23)) +#define MCPWM_FH2_CBC_INT_ST_M (BIT(23)) +#define MCPWM_FH2_CBC_INT_ST_V 0x1 +#define MCPWM_FH2_CBC_INT_ST_S 23 +/* MCPWM_FH1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM1*/ +#define MCPWM_FH1_CBC_INT_ST (BIT(22)) +#define MCPWM_FH1_CBC_INT_ST_M (BIT(22)) +#define MCPWM_FH1_CBC_INT_ST_V 0x1 +#define MCPWM_FH1_CBC_INT_ST_S 22 +/* MCPWM_FH0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM0*/ +#define MCPWM_FH0_CBC_INT_ST (BIT(21)) +#define MCPWM_FH0_CBC_INT_ST_M (BIT(21)) +#define MCPWM_FH0_CBC_INT_ST_V 0x1 +#define MCPWM_FH0_CBC_INT_ST_S 21 +/* MCPWM_OP2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEB event*/ +#define MCPWM_OP2_TEB_INT_ST (BIT(20)) +#define MCPWM_OP2_TEB_INT_ST_M (BIT(20)) +#define MCPWM_OP2_TEB_INT_ST_V 0x1 +#define MCPWM_OP2_TEB_INT_ST_S 20 +/* MCPWM_OP1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEB event*/ +#define MCPWM_OP1_TEB_INT_ST (BIT(19)) +#define MCPWM_OP1_TEB_INT_ST_M (BIT(19)) +#define MCPWM_OP1_TEB_INT_ST_V 0x1 +#define MCPWM_OP1_TEB_INT_ST_S 19 +/* MCPWM_OP0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEB event*/ +#define MCPWM_OP0_TEB_INT_ST (BIT(18)) +#define MCPWM_OP0_TEB_INT_ST_M (BIT(18)) +#define MCPWM_OP0_TEB_INT_ST_V 0x1 +#define MCPWM_OP0_TEB_INT_ST_S 18 +/* MCPWM_OP2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEA event*/ +#define MCPWM_OP2_TEA_INT_ST (BIT(17)) +#define MCPWM_OP2_TEA_INT_ST_M (BIT(17)) +#define MCPWM_OP2_TEA_INT_ST_V 0x1 +#define MCPWM_OP2_TEA_INT_ST_S 17 +/* MCPWM_OP1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEA event*/ +#define MCPWM_OP1_TEA_INT_ST (BIT(16)) +#define MCPWM_OP1_TEA_INT_ST_M (BIT(16)) +#define MCPWM_OP1_TEA_INT_ST_V 0x1 +#define MCPWM_OP1_TEA_INT_ST_S 16 +/* MCPWM_OP0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEA event*/ +#define MCPWM_OP0_TEA_INT_ST (BIT(15)) +#define MCPWM_OP0_TEA_INT_ST_M (BIT(15)) +#define MCPWM_OP0_TEA_INT_ST_V 0x1 +#define MCPWM_OP0_TEA_INT_ST_S 15 +/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f2 ends*/ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f1 ends*/ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f0 ends*/ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f2 starts*/ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (BIT(11)) +#define MCPWM_FAULT2_INT_ST_V 0x1 +#define MCPWM_FAULT2_INT_ST_S 11 +/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f1 starts*/ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (BIT(10)) +#define MCPWM_FAULT1_INT_ST_V 0x1 +#define MCPWM_FAULT1_INT_ST_S 10 +/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f0 starts*/ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (BIT(9)) +#define MCPWM_FAULT0_INT_ST_V 0x1 +#define MCPWM_FAULT0_INT_ST_S 9 +/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEP event*/ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEP event*/ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEP event*/ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEZ event*/ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEZ event*/ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEZ event*/ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered when timer 2 stops*/ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered when timer 1 stops*/ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered when timer 0 stops*/ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ST_S 0 + +#define MCMCPWM_INT_CLR_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x011c) +/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by captureon channel 2*/ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (BIT(29)) +#define MCPWM_CAP2_INT_CLR_V 0x1 +#define MCPWM_CAP2_INT_CLR_S 29 +/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by captureon channel 1*/ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (BIT(28)) +#define MCPWM_CAP1_INT_CLR_V 0x1 +#define MCPWM_CAP1_INT_CLR_S 28 +/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by captureon channel 0*/ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (BIT(27)) +#define MCPWM_CAP0_INT_CLR_V 0x1 +#define MCPWM_CAP0_INT_CLR_S 27 +/* MCPWM_FH2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM2*/ +#define MCPWM_FH2_OST_INT_CLR (BIT(26)) +#define MCPWM_FH2_OST_INT_CLR_M (BIT(26)) +#define MCPWM_FH2_OST_INT_CLR_V 0x1 +#define MCPWM_FH2_OST_INT_CLR_S 26 +/* MCPWM_FH1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH1_OST_INT_CLR (BIT(25)) +#define MCPWM_FH1_OST_INT_CLR_M (BIT(25)) +#define MCPWM_FH1_OST_INT_CLR_V 0x1 +#define MCPWM_FH1_OST_INT_CLR_S 25 +/* MCPWM_FH0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH0_OST_INT_CLR (BIT(24)) +#define MCPWM_FH0_OST_INT_CLR_M (BIT(24)) +#define MCPWM_FH0_OST_INT_CLR_V 0x1 +#define MCPWM_FH0_OST_INT_CLR_S 24 +/* MCPWM_FH2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle + mode action on PWM2*/ +#define MCPWM_FH2_CBC_INT_CLR (BIT(23)) +#define MCPWM_FH2_CBC_INT_CLR_M (BIT(23)) +#define MCPWM_FH2_CBC_INT_CLR_V 0x1 +#define MCPWM_FH2_CBC_INT_CLR_S 23 +/* MCPWM_FH1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle + mode action on PWM1*/ +#define MCPWM_FH1_CBC_INT_CLR (BIT(22)) +#define MCPWM_FH1_CBC_INT_CLR_M (BIT(22)) +#define MCPWM_FH1_CBC_INT_CLR_V 0x1 +#define MCPWM_FH1_CBC_INT_CLR_S 22 +/* MCPWM_FH0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle + mode action on PWM0*/ +#define MCPWM_FH0_CBC_INT_CLR (BIT(21)) +#define MCPWM_FH0_CBC_INT_CLR_M (BIT(21)) +#define MCPWM_FH0_CBC_INT_CLR_V 0x1 +#define MCPWM_FH0_CBC_INT_CLR_S 21 +/* MCPWM_OP2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEB event*/ +#define MCPWM_OP2_TEB_INT_CLR (BIT(20)) +#define MCPWM_OP2_TEB_INT_CLR_M (BIT(20)) +#define MCPWM_OP2_TEB_INT_CLR_V 0x1 +#define MCPWM_OP2_TEB_INT_CLR_S 20 +/* MCPWM_OP1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEB event*/ +#define MCPWM_OP1_TEB_INT_CLR (BIT(19)) +#define MCPWM_OP1_TEB_INT_CLR_M (BIT(19)) +#define MCPWM_OP1_TEB_INT_CLR_V 0x1 +#define MCPWM_OP1_TEB_INT_CLR_S 19 +/* MCPWM_OP0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEB event*/ +#define MCPWM_OP0_TEB_INT_CLR (BIT(18)) +#define MCPWM_OP0_TEB_INT_CLR_M (BIT(18)) +#define MCPWM_OP0_TEB_INT_CLR_V 0x1 +#define MCPWM_OP0_TEB_INT_CLR_S 18 +/* MCPWM_OP2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEA event*/ +#define MCPWM_OP2_TEA_INT_CLR (BIT(17)) +#define MCPWM_OP2_TEA_INT_CLR_M (BIT(17)) +#define MCPWM_OP2_TEA_INT_CLR_V 0x1 +#define MCPWM_OP2_TEA_INT_CLR_S 17 +/* MCPWM_OP1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEA event*/ +#define MCPWM_OP1_TEA_INT_CLR (BIT(16)) +#define MCPWM_OP1_TEA_INT_CLR_M (BIT(16)) +#define MCPWM_OP1_TEA_INT_CLR_V 0x1 +#define MCPWM_OP1_TEA_INT_CLR_S 16 +/* MCPWM_OP0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEA event*/ +#define MCPWM_OP0_TEA_INT_CLR (BIT(15)) +#define MCPWM_OP0_TEA_INT_CLR_M (BIT(15)) +#define MCPWM_OP0_TEA_INT_CLR_V 0x1 +#define MCPWM_OP0_TEA_INT_CLR_S 15 +/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f2 ends*/ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f1 ends*/ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f0 ends*/ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f2 starts*/ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_V 0x1 +#define MCPWM_FAULT2_INT_CLR_S 11 +/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f1 starts*/ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_V 0x1 +#define MCPWM_FAULT1_INT_CLR_S 10 +/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f0 starts*/ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_V 0x1 +#define MCPWM_FAULT0_INT_CLR_S 9 +/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEP event*/ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEP event*/ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEP event*/ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event*/ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event*/ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event*/ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered when timer 2 stops*/ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered when timer 1 stops*/ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered when timer 0 stops*/ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER0_STOP_INT_CLR_S 0 + +#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x0120) +/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Force clock on for this reg file*/ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (BIT(0)) +#define MCPWM_CLK_EN_V 0x1 +#define MCPWM_CLK_EN_S 0 + +#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x0124) +/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */ +/*description: Version of this reg file*/ +#define MCPWM_DATE 0x0FFFFFFF +#define MCPWM_DATE_M ((MCPWM_DATE_V)<<(MCPWM_DATE_S)) +#define MCPWM_DATE_V 0xFFFFFFF +#define MCPWM_DATE_S 0 + + + + +#endif /*_SOC_MCPWM_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/mcpwm_struct.h b/tools/sdk/include/soc/include/soc/mcpwm_struct.h new file mode 100644 index 00000000000..1d5110bf8c9 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/mcpwm_struct.h @@ -0,0 +1,464 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_MCPWM_STRUCT_H__ +#define _SOC_MCPWM_STRUCT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ + uint32_t reserved8: 24; + }; + uint32_t val; + }clk_cfg; + struct { + union { + struct { + uint32_t prescale: 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/ + uint32_t period: 16; /*period shadow reg of PWM timer0*/ + uint32_t upmethod: 2; /*Update method for active reg of PWM timer0 period 0: immediate 1: TEZ 2: sync 3: TEZ | sync. TEZ here and below means timer equal zero event*/ + uint32_t reserved26: 6; + }; + uint32_t val; + }period; + union { + struct { + uint32_t start: 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/ + uint32_t mode: 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: decrease mod 3: up-down mod*/ + uint32_t reserved5: 27; + }; + uint32_t val; + }mode; + union { + struct { + uint32_t in_en: 1; /*when set timer reload with phase on sync input event is enabled*/ + uint32_t sync_sw: 1; /*write the negate value will trigger a software sync*/ + uint32_t out_sel: 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ + uint32_t timer_phase: 17; /*phase for timer reload on sync event*/ + uint32_t reserved21: 11; + }; + uint32_t val; + }sync; + union { + struct { + uint32_t value: 16; /*current PWM timer0 counter value*/ + uint32_t direction: 1; /*current PWM timer0 counter direction 0: increment 1: decrement*/ + uint32_t reserved17: 15; + }; + uint32_t val; + }status; + }timer[3]; + + + union { + struct { + uint32_t t0_in_sel: 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ + uint32_t t1_in_sel: 3; /*select sync input for PWM timer1 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ + uint32_t t2_in_sel: 3; /*select sync input for PWM timer2 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ + uint32_t ext_in0_inv: 1; /*invert SYNC0 from GPIO matrix*/ + uint32_t ext_in1_inv: 1; /*invert SYNC1 from GPIO matrix*/ + uint32_t ext_in2_inv: 1; /*invert SYNC2 from GPIO matrix*/ + uint32_t reserved12: 20; + }; + uint32_t val; + }timer_synci_cfg; + union { + struct { + uint32_t operator0_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator0 0: timer0 1: timer1 2: timer2*/ + uint32_t operator1_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator1 0: timer0 1: timer1 2: timer2*/ + uint32_t operator2_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator2 0: timer0 1: timer1 2: timer2*/ + uint32_t reserved6: 26; + }; + uint32_t val; + }timer_sel; + + + struct { + union { + struct { + uint32_t a_upmethod: 4; /*Update method for PWM compare0 A's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ + uint32_t b_upmethod: 4; /*Update method for PWM compare0 B's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ + uint32_t a_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ + uint32_t b_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ + uint32_t reserved10: 22; + }; + uint32_t val; + }cmpr_cfg; + union { + struct { + uint32_t cmpr_val: 16; /*PWM compare0 A's shadow reg*/ + uint32_t reserved16:16; + }; + uint32_t val; + }cmpr_value[2]; + union { + struct { + uint32_t upmethod: 4; /*Update method for PWM generate0's active reg of configuration. 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: freeze*/ + uint32_t t0_sel: 3; /*Source selection for PWM generate0 event_t0 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ + uint32_t t1_sel: 3; /*Source selection for PWM generate0 event_t1 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ + uint32_t reserved10: 22; + }; + uint32_t val; + }gen_cfg0; + union { + struct { + uint32_t cntu_force_upmethod: 6; /*Update method for continuous software force of PWM generate0. 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: freeze. (TEA/B here and below means timer equals A/B event)*/ + uint32_t a_cntuforce_mode: 2; /*Continuous software force mode for PWM0A. 0: disabled 1: low 2: high 3: disabled*/ + uint32_t b_cntuforce_mode: 2; /*Continuous software force mode for PWM0B. 0: disabled 1: low 2: high 3: disabled*/ + uint32_t a_nciforce: 1; /*non-continuous immediate software force trigger for PWM0A a toggle will trigger a force event*/ + uint32_t a_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0A 0: disabled 1: low 2: high 3: disabled*/ + uint32_t b_nciforce: 1; /*non-continuous immediate software force trigger for PWM0B a toggle will trigger a force event*/ + uint32_t b_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0B 0: disabled 1: low 2: high 3: disabled*/ + uint32_t reserved16: 16; + }; + uint32_t val; + }gen_force; + union { + struct { + uint32_t utez: 2; /*Action on PWM0A triggered by event TEZ when timer increasing*/ + uint32_t utep: 2; /*Action on PWM0A triggered by event TEP when timer increasing*/ + uint32_t utea: 2; /*Action on PWM0A triggered by event TEA when timer increasing*/ + uint32_t uteb: 2; /*Action on PWM0A triggered by event TEB when timer increasing*/ + uint32_t ut0: 2; /*Action on PWM0A triggered by event_t0 when timer increasing*/ + uint32_t ut1: 2; /*Action on PWM0A triggered by event_t1 when timer increasing*/ + uint32_t dtez: 2; /*Action on PWM0A triggered by event TEZ when timer decreasing*/ + uint32_t dtep: 2; /*Action on PWM0A triggered by event TEP when timer decreasing*/ + uint32_t dtea: 2; /*Action on PWM0A triggered by event TEA when timer decreasing*/ + uint32_t dteb: 2; /*Action on PWM0A triggered by event TEB when timer decreasing*/ + uint32_t dt0: 2; /*Action on PWM0A triggered by event_t0 when timer decreasing*/ + uint32_t dt1: 2; /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change 1: low 2: high 3: toggle*/ + uint32_t reserved24: 8; + }; + uint32_t val; + }generator[2]; + union { + struct { + uint32_t fed_upmethod: 4; /*Update method for FED (falling edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ + uint32_t red_upmethod: 4; /*Update method for RED (rising edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ + uint32_t deb_mode: 1; /*S8 in documentation dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/ + uint32_t a_outswap: 1; /*S6 in documentation*/ + uint32_t b_outswap: 1; /*S7 in documentation*/ + uint32_t red_insel: 1; /*S4 in documentation*/ + uint32_t fed_insel: 1; /*S5 in documentation*/ + uint32_t red_outinvert: 1; /*S2 in documentation*/ + uint32_t fed_outinvert: 1; /*S3 in documentation*/ + uint32_t a_outbypass: 1; /*S1 in documentation*/ + uint32_t b_outbypass: 1; /*S0 in documentation*/ + uint32_t clk_sel: 1; /*Dead band0 clock selection. 0: PWM_clk 1: PT_clk*/ + uint32_t reserved18: 14; + }; + uint32_t val; + }db_cfg; + union { + struct { + uint32_t fed: 16; /*Shadow reg for FED*/ + uint32_t reserved16:16; + }; + uint32_t val; + }db_fed_cfg; + union { + struct { + uint32_t red: 16; /*Shadow reg for RED*/ + uint32_t reserved16:16; + }; + uint32_t val; + }db_red_cfg; + union { + struct { + uint32_t en: 1; /*When set carrier0 function is enabled. When reset carrier0 is bypassed*/ + uint32_t prescale: 4; /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/ + uint32_t duty: 3; /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/ + uint32_t oshtwth: 4; /*width of the fist pulse in number of periods of the carrier*/ + uint32_t out_invert: 1; /*when set invert the output of PWM0A and PWM0B for this submodule*/ + uint32_t in_invert: 1; /*when set invert the input of PWM0A and PWM0B for this submodule*/ + uint32_t reserved14: 18; + }; + uint32_t val; + }carrier_cfg; + union { + struct { + uint32_t sw_cbc: 1; /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ + uint32_t f2_cbc: 1; /*event_f2 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ + uint32_t f1_cbc: 1; /*event_f1 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ + uint32_t f0_cbc: 1; /*event_f0 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ + uint32_t sw_ost: 1; /*one-shot tripping software force event will trigger one-shot trip event. 0: disable 1: enable*/ + uint32_t f2_ost: 1; /*event_f2 will trigger one-shot trip event. 0: disable 1: enable*/ + uint32_t f1_ost: 1; /*event_f1 will trigger one-shot trip event. 0: disable 1: enable*/ + uint32_t f0_ost: 1; /*event_f0 will trigger one-shot trip event. 0: disable 1: enable*/ + uint32_t a_cbc_d: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t a_cbc_u: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t a_ost_d: 2; /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t a_ost_u: 2; /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_cbc_d: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_cbc_u: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_ost_d: 2; /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_ost_u: 2; /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t reserved24: 8; + }; + uint32_t val; + }tz_cfg0; + union { + struct { + uint32_t clr_ost: 1; /*a toggle will clear on going one-shot tripping*/ + uint32_t cbcpulse: 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/ + uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/ + uint32_t force_ost: 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/ + uint32_t reserved5: 27; + }; + uint32_t val; + }tz_cfg1; + union { + struct { + uint32_t cbc_on: 1; /*Set and reset by hardware. If set an cycle-by-cycle trip event is on going*/ + uint32_t ost_on: 1; /*Set and reset by hardware. If set an one-shot trip event is on going*/ + uint32_t reserved2: 30; + }; + uint32_t val; + }tz_status; + }channel[3]; + + union { + struct { + uint32_t f0_en: 1; /*When set event_f0 generation is enabled*/ + uint32_t f1_en: 1; /*When set event_f1 generation is enabled*/ + uint32_t f2_en: 1; /*When set event_f2 generation is enabled*/ + uint32_t f0_pole: 1; /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ + uint32_t f1_pole: 1; /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ + uint32_t f2_pole: 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ + uint32_t event_f0: 1; /*Set and reset by hardware. If set event_f0 is on going*/ + uint32_t event_f1: 1; /*Set and reset by hardware. If set event_f1 is on going*/ + uint32_t event_f2: 1; /*Set and reset by hardware. If set event_f2 is on going*/ + uint32_t reserved9: 23; + }; + uint32_t val; + }fault_detect; + union { + struct { + uint32_t timer_en: 1; /*When set capture timer incrementing under APB_clk is enabled.*/ + uint32_t synci_en: 1; /*When set capture timer sync is enabled.*/ + uint32_t synci_sel: 3; /*capture module sync input selection. 0: none 1: timer0 synco 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/ + uint32_t sync_sw: 1; /*Write 1 will force a capture timer sync capture timer is loaded with value in phase register.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + }cap_timer_cfg; + uint32_t cap_timer_phase; /*Phase value for capture timer sync operation.*/ + union { + struct { + uint32_t en: 1; /*When set capture on channel 0 is enabled*/ + uint32_t mode: 2; /*Edge of capture on channel 0 after prescale. bit0: negedge cap en bit1: posedge cap en*/ + uint32_t prescale: 8; /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/ + uint32_t in_invert: 1; /*when set CAP0 form GPIO matrix is inverted before prescale*/ + uint32_t sw: 1; /*Write 1 will trigger a software forced capture on channel 0*/ + uint32_t reserved13: 19; + }; + uint32_t val; + }cap_cfg_ch[3]; + uint32_t cap_val_ch[3]; /*Value of last capture on channel 0*/ + union { + struct { + uint32_t cap0_edge: 1; /*Edge of last capture trigger on channel 0 0: posedge 1: negedge*/ + uint32_t cap1_edge: 1; /*Edge of last capture trigger on channel 1 0: posedge 1: negedge*/ + uint32_t cap2_edge: 1; /*Edge of last capture trigger on channel 2 0: posedge 1: negedge*/ + uint32_t reserved3: 29; + }; + uint32_t val; + }cap_status; + union { + struct { + uint32_t global_up_en: 1; /*The global enable of update of all active registers in MCPWM module*/ + uint32_t global_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/ + uint32_t op0_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 0 are enabled*/ + uint32_t op0_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/ + uint32_t op1_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 1 are enabled*/ + uint32_t op1_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/ + uint32_t op2_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 2 are enabled*/ + uint32_t op2_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/ + uint32_t reserved8: 24; + }; + uint32_t val; + }update_cfg; + union { + struct { + uint32_t timer0_stop_int_ena: 1; /*Interrupt when timer 0 stops*/ + uint32_t timer1_stop_int_ena: 1; /*Interrupt when timer 1 stops*/ + uint32_t timer2_stop_int_ena: 1; /*Interrupt when timer 2 stops*/ + uint32_t timer0_tez_int_ena: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ + uint32_t timer1_tez_int_ena: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ + uint32_t timer2_tez_int_ena: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ + uint32_t timer0_tep_int_ena: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ + uint32_t timer1_tep_int_ena: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ + uint32_t timer2_tep_int_ena: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ + uint32_t fault0_int_ena: 1; /*Interrupt when event_f0 starts*/ + uint32_t fault1_int_ena: 1; /*Interrupt when event_f1 starts*/ + uint32_t fault2_int_ena: 1; /*Interrupt when event_f2 starts*/ + uint32_t fault0_clr_int_ena: 1; /*Interrupt when event_f0 ends*/ + uint32_t fault1_clr_int_ena: 1; /*Interrupt when event_f1 ends*/ + uint32_t fault2_clr_int_ena: 1; /*Interrupt when event_f2 ends*/ + uint32_t cmpr0_tea_int_ena: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ + uint32_t cmpr1_tea_int_ena: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ + uint32_t cmpr2_tea_int_ena: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ + uint32_t cmpr0_teb_int_ena: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ + uint32_t cmpr1_teb_int_ena: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ + uint32_t cmpr2_teb_int_ena: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ + uint32_t tz0_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ + uint32_t tz0_ost_int_ena: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_ost_int_ena: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_ost_int_ena: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ + uint32_t cap0_int_ena: 1; /*A capture on channel 0 will trigger this interrupt*/ + uint32_t cap1_int_ena: 1; /*A capture on channel 1 will trigger this interrupt*/ + uint32_t cap2_int_ena: 1; /*A capture on channel 2 will trigger this interrupt*/ + uint32_t reserved30: 2; + }; + uint32_t val; + }int_ena; + union { + struct { + uint32_t timer0_stop_int_raw: 1; /*Interrupt when timer 0 stops*/ + uint32_t timer1_stop_int_raw: 1; /*Interrupt when timer 1 stops*/ + uint32_t timer2_stop_int_raw: 1; /*Interrupt when timer 2 stops*/ + uint32_t timer0_tez_int_raw: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ + uint32_t timer1_tez_int_raw: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ + uint32_t timer2_tez_int_raw: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ + uint32_t timer0_tep_int_raw: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ + uint32_t timer1_tep_int_raw: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ + uint32_t timer2_tep_int_raw: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ + uint32_t fault0_int_raw: 1; /*Interrupt when event_f0 starts*/ + uint32_t fault1_int_raw: 1; /*Interrupt when event_f1 starts*/ + uint32_t fault2_int_raw: 1; /*Interrupt when event_f2 starts*/ + uint32_t fault0_clr_int_raw: 1; /*Interrupt when event_f0 ends*/ + uint32_t fault1_clr_int_raw: 1; /*Interrupt when event_f1 ends*/ + uint32_t fault2_clr_int_raw: 1; /*Interrupt when event_f2 ends*/ + uint32_t cmpr0_tea_int_raw: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ + uint32_t cmpr1_tea_int_raw: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ + uint32_t cmpr2_tea_int_raw: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ + uint32_t cmpr0_teb_int_raw: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ + uint32_t cmpr1_teb_int_raw: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ + uint32_t cmpr2_teb_int_raw: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ + uint32_t tz0_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ + uint32_t tz0_ost_int_raw: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_ost_int_raw: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_ost_int_raw: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ + uint32_t cap0_int_raw: 1; /*A capture on channel 0 will trigger this interrupt*/ + uint32_t cap1_int_raw: 1; /*A capture on channel 1 will trigger this interrupt*/ + uint32_t cap2_int_raw: 1; /*A capture on channel 2 will trigger this interrupt*/ + uint32_t reserved30: 2; + }; + uint32_t val; + }int_raw; + union { + struct { + uint32_t timer0_stop_int_st: 1; /*Interrupt when timer 0 stops*/ + uint32_t timer1_stop_int_st: 1; /*Interrupt when timer 1 stops*/ + uint32_t timer2_stop_int_st: 1; /*Interrupt when timer 2 stops*/ + uint32_t timer0_tez_int_st: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ + uint32_t timer1_tez_int_st: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ + uint32_t timer2_tez_int_st: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ + uint32_t timer0_tep_int_st: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ + uint32_t timer1_tep_int_st: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ + uint32_t timer2_tep_int_st: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ + uint32_t fault0_int_st: 1; /*Interrupt when event_f0 starts*/ + uint32_t fault1_int_st: 1; /*Interrupt when event_f1 starts*/ + uint32_t fault2_int_st: 1; /*Interrupt when event_f2 starts*/ + uint32_t fault0_clr_int_st: 1; /*Interrupt when event_f0 ends*/ + uint32_t fault1_clr_int_st: 1; /*Interrupt when event_f1 ends*/ + uint32_t fault2_clr_int_st: 1; /*Interrupt when event_f2 ends*/ + uint32_t cmpr0_tea_int_st: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ + uint32_t cmpr1_tea_int_st: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ + uint32_t cmpr2_tea_int_st: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ + uint32_t cmpr0_teb_int_st: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ + uint32_t cmpr1_teb_int_st: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ + uint32_t cmpr2_teb_int_st: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ + uint32_t tz0_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ + uint32_t tz0_ost_int_st: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_ost_int_st: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_ost_int_st: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ + uint32_t cap0_int_st: 1; /*A capture on channel 0 will trigger this interrupt*/ + uint32_t cap1_int_st: 1; /*A capture on channel 1 will trigger this interrupt*/ + uint32_t cap2_int_st: 1; /*A capture on channel 2 will trigger this interrupt*/ + uint32_t reserved30: 2; + }; + uint32_t val; + }int_st; + union { + struct { + uint32_t timer0_stop_int_clr: 1; /*Interrupt when timer 0 stops*/ + uint32_t timer1_stop_int_clr: 1; /*Interrupt when timer 1 stops*/ + uint32_t timer2_stop_int_clr: 1; /*Interrupt when timer 2 stops*/ + uint32_t timer0_tez_int_clr: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ + uint32_t timer1_tez_int_clr: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ + uint32_t timer2_tez_int_clr: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ + uint32_t timer0_tep_int_clr: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ + uint32_t timer1_tep_int_clr: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ + uint32_t timer2_tep_int_clr: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ + uint32_t fault0_int_clr: 1; /*Interrupt when event_f0 starts*/ + uint32_t fault1_int_clr: 1; /*Interrupt when event_f1 starts*/ + uint32_t fault2_int_clr: 1; /*Interrupt when event_f2 starts*/ + uint32_t fault0_clr_int_clr: 1; /*Interrupt when event_f0 ends*/ + uint32_t fault1_clr_int_clr: 1; /*Interrupt when event_f1 ends*/ + uint32_t fault2_clr_int_clr: 1; /*Interrupt when event_f2 ends*/ + uint32_t cmpr0_tea_int_clr: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ + uint32_t cmpr1_tea_int_clr: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ + uint32_t cmpr2_tea_int_clr: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ + uint32_t cmpr0_teb_int_clr: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ + uint32_t cmpr1_teb_int_clr: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ + uint32_t cmpr2_teb_int_clr: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ + uint32_t tz0_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ + uint32_t tz0_ost_int_clr: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_ost_int_clr: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_ost_int_clr: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ + uint32_t cap0_int_clr: 1; /*A capture on channel 0 will trigger this interrupt*/ + uint32_t cap1_int_clr: 1; /*A capture on channel 1 will trigger this interrupt*/ + uint32_t cap2_int_clr: 1; /*A capture on channel 2 will trigger this interrupt*/ + uint32_t reserved30: 2; + }; + uint32_t val; + }int_clr; + union { + struct { + uint32_t clk_en: 1; /*Force clock on for this reg file*/ + uint32_t reserved1: 31; + }; + uint32_t val; + }reg_clk; + union { + struct { + uint32_t date: 28; /*Version of this reg file*/ + uint32_t reserved28: 4; + }; + uint32_t val; + }version; +} mcpwm_dev_t; +extern mcpwm_dev_t MCPWM0; +extern mcpwm_dev_t MCPWM1; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_MCPWM_STRUCT_H__ */ diff --git a/tools/sdk/include/soc/include/soc/nrx_reg.h b/tools/sdk/include/soc/include/soc/nrx_reg.h new file mode 100644 index 00000000000..ca338b89ab3 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/nrx_reg.h @@ -0,0 +1,55 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the WiFi RX control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4) +#define NRX_CHAN_EST_FORCE_PU (BIT(7)) +#define NRX_CHAN_EST_FORCE_PU_M (BIT(7)) +#define NRX_CHAN_EST_FORCE_PU_V 1 +#define NRX_CHAN_EST_FORCE_PU_S 7 +#define NRX_CHAN_EST_FORCE_PD (BIT(6)) +#define NRX_CHAN_EST_FORCE_PD_M (BIT(6)) +#define NRX_CHAN_EST_FORCE_PD_V 1 +#define NRX_CHAN_EST_FORCE_PD_S 6 +#define NRX_RX_ROT_FORCE_PU (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_M (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_V 1 +#define NRX_RX_ROT_FORCE_PU_S 5 +#define NRX_RX_ROT_FORCE_PD (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_M (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_V 1 +#define NRX_RX_ROT_FORCE_PD_S 4 +#define NRX_VIT_FORCE_PU (BIT(3)) +#define NRX_VIT_FORCE_PU_M (BIT(3)) +#define NRX_VIT_FORCE_PU_V 1 +#define NRX_VIT_FORCE_PU_S 3 +#define NRX_VIT_FORCE_PD (BIT(2)) +#define NRX_VIT_FORCE_PD_M (BIT(2)) +#define NRX_VIT_FORCE_PD_V 1 +#define NRX_VIT_FORCE_PD_S 2 +#define NRX_DEMAP_FORCE_PU (BIT(1)) +#define NRX_DEMAP_FORCE_PU_M (BIT(1)) +#define NRX_DEMAP_FORCE_PU_V 1 +#define NRX_DEMAP_FORCE_PU_S 1 +#define NRX_DEMAP_FORCE_PD (BIT(0)) +#define NRX_DEMAP_FORCE_PD_M (BIT(0)) +#define NRX_DEMAP_FORCE_PD_V 1 +#define NRX_DEMAP_FORCE_PD_S 0 diff --git a/tools/sdk/include/soc/include/soc/pcnt_reg.h b/tools/sdk/include/soc/include/soc/pcnt_reg.h new file mode 100644 index 00000000000..fa7dedc2528 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/pcnt_reg.h @@ -0,0 +1,1526 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PCNT_REG_H_ +#define _SOC_PCNT_REG_H_ + + +#include "soc.h" +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000) +/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S)) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U0_S 30 +/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S)) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U0 0x00000003 +#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S)) +#define PCNT_CH1_POS_MODE_U0_V 0x3 +#define PCNT_CH1_POS_MODE_U0_S 26 +/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U0 0x00000003 +#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S)) +#define PCNT_CH1_NEG_MODE_U0_V 0x3 +#define PCNT_CH1_NEG_MODE_U0_S 24 +/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S)) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S)) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U0 0x00000003 +#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S)) +#define PCNT_CH0_POS_MODE_U0_V 0x3 +#define PCNT_CH0_POS_MODE_U0_S 18 +/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U0 0x00000003 +#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S)) +#define PCNT_CH0_NEG_MODE_U0_V 0x3 +#define PCNT_CH0_NEG_MODE_U0_S 16 +/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit0's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_V 0x1 +#define PCNT_THR_THRES1_EN_U0_S 15 +/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit0's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_V 0x1 +#define PCNT_THR_THRES0_EN_U0_S 14 +/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_V 0x1 +#define PCNT_THR_L_LIM_EN_U0_S 13 +/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_V 0x1 +#define PCNT_THR_H_LIM_EN_U0_S 12 +/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_V 0x1 +#define PCNT_THR_ZERO_EN_U0_S 11 +/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit0.*/ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (BIT(10)) +#define PCNT_FILTER_EN_U0_V 0x1 +#define PCNT_FILTER_EN_U0_S 10 +/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit0.*/ +#define PCNT_FILTER_THRES_U0 0x000003FF +#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S)) +#define PCNT_FILTER_THRES_U0_V 0x3FF +#define PCNT_FILTER_THRES_U0_S 0 + +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004) +/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit0.*/ +#define PCNT_CNT_THRES1_U0 0x0000FFFF +#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S)) +#define PCNT_CNT_THRES1_U0_V 0xFFFF +#define PCNT_CNT_THRES1_U0_S 16 +/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit0.*/ +#define PCNT_CNT_THRES0_U0 0x0000FFFF +#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S)) +#define PCNT_CNT_THRES0_U0_V 0xFFFF +#define PCNT_CNT_THRES0_U0_S 0 + +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008) +/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit0.*/ +#define PCNT_CNT_L_LIM_U0 0x0000FFFF +#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S)) +#define PCNT_CNT_L_LIM_U0_V 0xFFFF +#define PCNT_CNT_L_LIM_U0_S 16 +/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit0.*/ +#define PCNT_CNT_H_LIM_U0 0x0000FFFF +#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S)) +#define PCNT_CNT_H_LIM_U0_V 0xFFFF +#define PCNT_CNT_H_LIM_U0_S 0 + +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c) +/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S)) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U1_S 30 +/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S)) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U1 0x00000003 +#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S)) +#define PCNT_CH1_POS_MODE_U1_V 0x3 +#define PCNT_CH1_POS_MODE_U1_S 26 +/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U1 0x00000003 +#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S)) +#define PCNT_CH1_NEG_MODE_U1_V 0x3 +#define PCNT_CH1_NEG_MODE_U1_S 24 +/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S)) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S)) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U1 0x00000003 +#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S)) +#define PCNT_CH0_POS_MODE_U1_V 0x3 +#define PCNT_CH0_POS_MODE_U1_S 18 +/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U1 0x00000003 +#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S)) +#define PCNT_CH0_NEG_MODE_U1_V 0x3 +#define PCNT_CH0_NEG_MODE_U1_S 16 +/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit1's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_V 0x1 +#define PCNT_THR_THRES1_EN_U1_S 15 +/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit1's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_V 0x1 +#define PCNT_THR_THRES0_EN_U1_S 14 +/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_V 0x1 +#define PCNT_THR_L_LIM_EN_U1_S 13 +/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_V 0x1 +#define PCNT_THR_H_LIM_EN_U1_S 12 +/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_V 0x1 +#define PCNT_THR_ZERO_EN_U1_S 11 +/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit1.*/ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (BIT(10)) +#define PCNT_FILTER_EN_U1_V 0x1 +#define PCNT_FILTER_EN_U1_S 10 +/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit1.*/ +#define PCNT_FILTER_THRES_U1 0x000003FF +#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S)) +#define PCNT_FILTER_THRES_U1_V 0x3FF +#define PCNT_FILTER_THRES_U1_S 0 + +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010) +/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit1.*/ +#define PCNT_CNT_THRES1_U1 0x0000FFFF +#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S)) +#define PCNT_CNT_THRES1_U1_V 0xFFFF +#define PCNT_CNT_THRES1_U1_S 16 +/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit1.*/ +#define PCNT_CNT_THRES0_U1 0x0000FFFF +#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S)) +#define PCNT_CNT_THRES0_U1_V 0xFFFF +#define PCNT_CNT_THRES0_U1_S 0 + +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014) +/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit1.*/ +#define PCNT_CNT_L_LIM_U1 0x0000FFFF +#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S)) +#define PCNT_CNT_L_LIM_U1_V 0xFFFF +#define PCNT_CNT_L_LIM_U1_S 16 +/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit1.*/ +#define PCNT_CNT_H_LIM_U1 0x0000FFFF +#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S)) +#define PCNT_CNT_H_LIM_U1_V 0xFFFF +#define PCNT_CNT_H_LIM_U1_S 0 + +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018) +/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S)) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U2_S 30 +/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S)) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U2 0x00000003 +#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S)) +#define PCNT_CH1_POS_MODE_U2_V 0x3 +#define PCNT_CH1_POS_MODE_U2_S 26 +/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U2 0x00000003 +#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S)) +#define PCNT_CH1_NEG_MODE_U2_V 0x3 +#define PCNT_CH1_NEG_MODE_U2_S 24 +/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S)) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S)) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U2 0x00000003 +#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S)) +#define PCNT_CH0_POS_MODE_U2_V 0x3 +#define PCNT_CH0_POS_MODE_U2_S 18 +/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U2 0x00000003 +#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S)) +#define PCNT_CH0_NEG_MODE_U2_V 0x3 +#define PCNT_CH0_NEG_MODE_U2_S 16 +/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit2's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_V 0x1 +#define PCNT_THR_THRES1_EN_U2_S 15 +/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit2's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_V 0x1 +#define PCNT_THR_THRES0_EN_U2_S 14 +/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_V 0x1 +#define PCNT_THR_L_LIM_EN_U2_S 13 +/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_V 0x1 +#define PCNT_THR_H_LIM_EN_U2_S 12 +/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_V 0x1 +#define PCNT_THR_ZERO_EN_U2_S 11 +/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit2.*/ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (BIT(10)) +#define PCNT_FILTER_EN_U2_V 0x1 +#define PCNT_FILTER_EN_U2_S 10 +/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit2.*/ +#define PCNT_FILTER_THRES_U2 0x000003FF +#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S)) +#define PCNT_FILTER_THRES_U2_V 0x3FF +#define PCNT_FILTER_THRES_U2_S 0 + +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c) +/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit2.*/ +#define PCNT_CNT_THRES1_U2 0x0000FFFF +#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S)) +#define PCNT_CNT_THRES1_U2_V 0xFFFF +#define PCNT_CNT_THRES1_U2_S 16 +/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit2.*/ +#define PCNT_CNT_THRES0_U2 0x0000FFFF +#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S)) +#define PCNT_CNT_THRES0_U2_V 0xFFFF +#define PCNT_CNT_THRES0_U2_S 0 + +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020) +/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit2.*/ +#define PCNT_CNT_L_LIM_U2 0x0000FFFF +#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S)) +#define PCNT_CNT_L_LIM_U2_V 0xFFFF +#define PCNT_CNT_L_LIM_U2_S 16 +/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit2.*/ +#define PCNT_CNT_H_LIM_U2 0x0000FFFF +#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S)) +#define PCNT_CNT_H_LIM_U2_V 0xFFFF +#define PCNT_CNT_H_LIM_U2_S 0 + +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024) +/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S)) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U3_S 30 +/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S)) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U3 0x00000003 +#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S)) +#define PCNT_CH1_POS_MODE_U3_V 0x3 +#define PCNT_CH1_POS_MODE_U3_S 26 +/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U3 0x00000003 +#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S)) +#define PCNT_CH1_NEG_MODE_U3_V 0x3 +#define PCNT_CH1_NEG_MODE_U3_S 24 +/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S)) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S)) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U3 0x00000003 +#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S)) +#define PCNT_CH0_POS_MODE_U3_V 0x3 +#define PCNT_CH0_POS_MODE_U3_S 18 +/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U3 0x00000003 +#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S)) +#define PCNT_CH0_NEG_MODE_U3_V 0x3 +#define PCNT_CH0_NEG_MODE_U3_S 16 +/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit3's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_V 0x1 +#define PCNT_THR_THRES1_EN_U3_S 15 +/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit3's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_V 0x1 +#define PCNT_THR_THRES0_EN_U3_S 14 +/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_V 0x1 +#define PCNT_THR_L_LIM_EN_U3_S 13 +/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_V 0x1 +#define PCNT_THR_H_LIM_EN_U3_S 12 +/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_V 0x1 +#define PCNT_THR_ZERO_EN_U3_S 11 +/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit3.*/ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (BIT(10)) +#define PCNT_FILTER_EN_U3_V 0x1 +#define PCNT_FILTER_EN_U3_S 10 +/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit3.*/ +#define PCNT_FILTER_THRES_U3 0x000003FF +#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S)) +#define PCNT_FILTER_THRES_U3_V 0x3FF +#define PCNT_FILTER_THRES_U3_S 0 + +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028) +/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit3.*/ +#define PCNT_CNT_THRES1_U3 0x0000FFFF +#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S)) +#define PCNT_CNT_THRES1_U3_V 0xFFFF +#define PCNT_CNT_THRES1_U3_S 16 +/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit3.*/ +#define PCNT_CNT_THRES0_U3 0x0000FFFF +#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S)) +#define PCNT_CNT_THRES0_U3_V 0xFFFF +#define PCNT_CNT_THRES0_U3_S 0 + +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c) +/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit3.*/ +#define PCNT_CNT_L_LIM_U3 0x0000FFFF +#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S)) +#define PCNT_CNT_L_LIM_U3_V 0xFFFF +#define PCNT_CNT_L_LIM_U3_S 16 +/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit3.*/ +#define PCNT_CNT_H_LIM_U3 0x0000FFFF +#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S)) +#define PCNT_CNT_H_LIM_U3_V 0xFFFF +#define PCNT_CNT_H_LIM_U3_S 0 + +#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030) +/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U4 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S)) +#define PCNT_CH1_LCTRL_MODE_U4_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U4_S 30 +/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U4 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S)) +#define PCNT_CH1_HCTRL_MODE_U4_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U4_S 28 +/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U4 0x00000003 +#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S)) +#define PCNT_CH1_POS_MODE_U4_V 0x3 +#define PCNT_CH1_POS_MODE_U4_S 26 +/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U4 0x00000003 +#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S)) +#define PCNT_CH1_NEG_MODE_U4_V 0x3 +#define PCNT_CH1_NEG_MODE_U4_S 24 +/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U4 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S)) +#define PCNT_CH0_LCTRL_MODE_U4_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U4_S 22 +/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U4 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S)) +#define PCNT_CH0_HCTRL_MODE_U4_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U4_S 20 +/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U4 0x00000003 +#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S)) +#define PCNT_CH0_POS_MODE_U4_V 0x3 +#define PCNT_CH0_POS_MODE_U4_S 18 +/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U4 0x00000003 +#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S)) +#define PCNT_CH0_NEG_MODE_U4_V 0x3 +#define PCNT_CH0_NEG_MODE_U4_S 16 +/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit4's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U4 (BIT(15)) +#define PCNT_THR_THRES1_EN_U4_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U4_V 0x1 +#define PCNT_THR_THRES1_EN_U4_S 15 +/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit4's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U4 (BIT(14)) +#define PCNT_THR_THRES0_EN_U4_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U4_V 0x1 +#define PCNT_THR_THRES0_EN_U4_S 14 +/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U4 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U4_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U4_V 0x1 +#define PCNT_THR_L_LIM_EN_U4_S 13 +/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U4 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U4_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U4_V 0x1 +#define PCNT_THR_H_LIM_EN_U4_S 12 +/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U4 (BIT(11)) +#define PCNT_THR_ZERO_EN_U4_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U4_V 0x1 +#define PCNT_THR_ZERO_EN_U4_S 11 +/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit4.*/ +#define PCNT_FILTER_EN_U4 (BIT(10)) +#define PCNT_FILTER_EN_U4_M (BIT(10)) +#define PCNT_FILTER_EN_U4_V 0x1 +#define PCNT_FILTER_EN_U4_S 10 +/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit4.*/ +#define PCNT_FILTER_THRES_U4 0x000003FF +#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S)) +#define PCNT_FILTER_THRES_U4_V 0x3FF +#define PCNT_FILTER_THRES_U4_S 0 + +#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034) +/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit4.*/ +#define PCNT_CNT_THRES1_U4 0x0000FFFF +#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S)) +#define PCNT_CNT_THRES1_U4_V 0xFFFF +#define PCNT_CNT_THRES1_U4_S 16 +/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit4.*/ +#define PCNT_CNT_THRES0_U4 0x0000FFFF +#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S)) +#define PCNT_CNT_THRES0_U4_V 0xFFFF +#define PCNT_CNT_THRES0_U4_S 0 + +#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038) +/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit4.*/ +#define PCNT_CNT_L_LIM_U4 0x0000FFFF +#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S)) +#define PCNT_CNT_L_LIM_U4_V 0xFFFF +#define PCNT_CNT_L_LIM_U4_S 16 +/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit4.*/ +#define PCNT_CNT_H_LIM_U4 0x0000FFFF +#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S)) +#define PCNT_CNT_H_LIM_U4_V 0xFFFF +#define PCNT_CNT_H_LIM_U4_S 0 + +#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c) +/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U5 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S)) +#define PCNT_CH1_LCTRL_MODE_U5_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U5_S 30 +/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U5 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S)) +#define PCNT_CH1_HCTRL_MODE_U5_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U5_S 28 +/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U5 0x00000003 +#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S)) +#define PCNT_CH1_POS_MODE_U5_V 0x3 +#define PCNT_CH1_POS_MODE_U5_S 26 +/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U5 0x00000003 +#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S)) +#define PCNT_CH1_NEG_MODE_U5_V 0x3 +#define PCNT_CH1_NEG_MODE_U5_S 24 +/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U5 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S)) +#define PCNT_CH0_LCTRL_MODE_U5_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U5_S 22 +/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U5 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S)) +#define PCNT_CH0_HCTRL_MODE_U5_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U5_S 20 +/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U5 0x00000003 +#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S)) +#define PCNT_CH0_POS_MODE_U5_V 0x3 +#define PCNT_CH0_POS_MODE_U5_S 18 +/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U5 0x00000003 +#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S)) +#define PCNT_CH0_NEG_MODE_U5_V 0x3 +#define PCNT_CH0_NEG_MODE_U5_S 16 +/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit5's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U5 (BIT(15)) +#define PCNT_THR_THRES1_EN_U5_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U5_V 0x1 +#define PCNT_THR_THRES1_EN_U5_S 15 +/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit5's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U5 (BIT(14)) +#define PCNT_THR_THRES0_EN_U5_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U5_V 0x1 +#define PCNT_THR_THRES0_EN_U5_S 14 +/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U5 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U5_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U5_V 0x1 +#define PCNT_THR_L_LIM_EN_U5_S 13 +/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U5 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U5_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U5_V 0x1 +#define PCNT_THR_H_LIM_EN_U5_S 12 +/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U5 (BIT(11)) +#define PCNT_THR_ZERO_EN_U5_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U5_V 0x1 +#define PCNT_THR_ZERO_EN_U5_S 11 +/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit5.*/ +#define PCNT_FILTER_EN_U5 (BIT(10)) +#define PCNT_FILTER_EN_U5_M (BIT(10)) +#define PCNT_FILTER_EN_U5_V 0x1 +#define PCNT_FILTER_EN_U5_S 10 +/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit5.*/ +#define PCNT_FILTER_THRES_U5 0x000003FF +#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S)) +#define PCNT_FILTER_THRES_U5_V 0x3FF +#define PCNT_FILTER_THRES_U5_S 0 + +#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040) +/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit5.*/ +#define PCNT_CNT_THRES1_U5 0x0000FFFF +#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S)) +#define PCNT_CNT_THRES1_U5_V 0xFFFF +#define PCNT_CNT_THRES1_U5_S 16 +/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit5.*/ +#define PCNT_CNT_THRES0_U5 0x0000FFFF +#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S)) +#define PCNT_CNT_THRES0_U5_V 0xFFFF +#define PCNT_CNT_THRES0_U5_S 0 + +#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044) +/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit5.*/ +#define PCNT_CNT_L_LIM_U5 0x0000FFFF +#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S)) +#define PCNT_CNT_L_LIM_U5_V 0xFFFF +#define PCNT_CNT_L_LIM_U5_S 16 +/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit5.*/ +#define PCNT_CNT_H_LIM_U5 0x0000FFFF +#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S)) +#define PCNT_CNT_H_LIM_U5_V 0xFFFF +#define PCNT_CNT_H_LIM_U5_S 0 + +#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048) +/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U6 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S)) +#define PCNT_CH1_LCTRL_MODE_U6_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U6_S 30 +/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U6 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S)) +#define PCNT_CH1_HCTRL_MODE_U6_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U6_S 28 +/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U6 0x00000003 +#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S)) +#define PCNT_CH1_POS_MODE_U6_V 0x3 +#define PCNT_CH1_POS_MODE_U6_S 26 +/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U6 0x00000003 +#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S)) +#define PCNT_CH1_NEG_MODE_U6_V 0x3 +#define PCNT_CH1_NEG_MODE_U6_S 24 +/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U6 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S)) +#define PCNT_CH0_LCTRL_MODE_U6_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U6_S 22 +/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U6 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S)) +#define PCNT_CH0_HCTRL_MODE_U6_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U6_S 20 +/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U6 0x00000003 +#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S)) +#define PCNT_CH0_POS_MODE_U6_V 0x3 +#define PCNT_CH0_POS_MODE_U6_S 18 +/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U6 0x00000003 +#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S)) +#define PCNT_CH0_NEG_MODE_U6_V 0x3 +#define PCNT_CH0_NEG_MODE_U6_S 16 +/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit6's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U6 (BIT(15)) +#define PCNT_THR_THRES1_EN_U6_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U6_V 0x1 +#define PCNT_THR_THRES1_EN_U6_S 15 +/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit6's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U6 (BIT(14)) +#define PCNT_THR_THRES0_EN_U6_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U6_V 0x1 +#define PCNT_THR_THRES0_EN_U6_S 14 +/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U6 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U6_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U6_V 0x1 +#define PCNT_THR_L_LIM_EN_U6_S 13 +/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U6 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U6_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U6_V 0x1 +#define PCNT_THR_H_LIM_EN_U6_S 12 +/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U6 (BIT(11)) +#define PCNT_THR_ZERO_EN_U6_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U6_V 0x1 +#define PCNT_THR_ZERO_EN_U6_S 11 +/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit6.*/ +#define PCNT_FILTER_EN_U6 (BIT(10)) +#define PCNT_FILTER_EN_U6_M (BIT(10)) +#define PCNT_FILTER_EN_U6_V 0x1 +#define PCNT_FILTER_EN_U6_S 10 +/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit6.*/ +#define PCNT_FILTER_THRES_U6 0x000003FF +#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S)) +#define PCNT_FILTER_THRES_U6_V 0x3FF +#define PCNT_FILTER_THRES_U6_S 0 + +#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c) +/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit6.*/ +#define PCNT_CNT_THRES1_U6 0x0000FFFF +#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S)) +#define PCNT_CNT_THRES1_U6_V 0xFFFF +#define PCNT_CNT_THRES1_U6_S 16 +/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit6.*/ +#define PCNT_CNT_THRES0_U6 0x0000FFFF +#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S)) +#define PCNT_CNT_THRES0_U6_V 0xFFFF +#define PCNT_CNT_THRES0_U6_S 0 + +#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050) +/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit6.*/ +#define PCNT_CNT_L_LIM_U6 0x0000FFFF +#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S)) +#define PCNT_CNT_L_LIM_U6_V 0xFFFF +#define PCNT_CNT_L_LIM_U6_S 16 +/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit6.*/ +#define PCNT_CNT_H_LIM_U6 0x0000FFFF +#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S)) +#define PCNT_CNT_H_LIM_U6_V 0xFFFF +#define PCNT_CNT_H_LIM_U6_S 0 + +#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054) +/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U7 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S)) +#define PCNT_CH1_LCTRL_MODE_U7_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U7_S 30 +/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U7 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S)) +#define PCNT_CH1_HCTRL_MODE_U7_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U7_S 28 +/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U7 0x00000003 +#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S)) +#define PCNT_CH1_POS_MODE_U7_V 0x3 +#define PCNT_CH1_POS_MODE_U7_S 26 +/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U7 0x00000003 +#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S)) +#define PCNT_CH1_NEG_MODE_U7_V 0x3 +#define PCNT_CH1_NEG_MODE_U7_S 24 +/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U7 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S)) +#define PCNT_CH0_LCTRL_MODE_U7_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U7_S 22 +/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U7 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S)) +#define PCNT_CH0_HCTRL_MODE_U7_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U7_S 20 +/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U7 0x00000003 +#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S)) +#define PCNT_CH0_POS_MODE_U7_V 0x3 +#define PCNT_CH0_POS_MODE_U7_S 18 +/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U7 0x00000003 +#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S)) +#define PCNT_CH0_NEG_MODE_U7_V 0x3 +#define PCNT_CH0_NEG_MODE_U7_S 16 +/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit7's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U7 (BIT(15)) +#define PCNT_THR_THRES1_EN_U7_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U7_V 0x1 +#define PCNT_THR_THRES1_EN_U7_S 15 +/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit7's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U7 (BIT(14)) +#define PCNT_THR_THRES0_EN_U7_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U7_V 0x1 +#define PCNT_THR_THRES0_EN_U7_S 14 +/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U7 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U7_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U7_V 0x1 +#define PCNT_THR_L_LIM_EN_U7_S 13 +/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U7 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U7_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U7_V 0x1 +#define PCNT_THR_H_LIM_EN_U7_S 12 +/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U7 (BIT(11)) +#define PCNT_THR_ZERO_EN_U7_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U7_V 0x1 +#define PCNT_THR_ZERO_EN_U7_S 11 +/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit7.*/ +#define PCNT_FILTER_EN_U7 (BIT(10)) +#define PCNT_FILTER_EN_U7_M (BIT(10)) +#define PCNT_FILTER_EN_U7_V 0x1 +#define PCNT_FILTER_EN_U7_S 10 +/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit7.*/ +#define PCNT_FILTER_THRES_U7 0x000003FF +#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S)) +#define PCNT_FILTER_THRES_U7_V 0x3FF +#define PCNT_FILTER_THRES_U7_S 0 + +#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058) +/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit7.*/ +#define PCNT_CNT_THRES1_U7 0x0000FFFF +#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S)) +#define PCNT_CNT_THRES1_U7_V 0xFFFF +#define PCNT_CNT_THRES1_U7_S 16 +/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit7.*/ +#define PCNT_CNT_THRES0_U7 0x0000FFFF +#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S)) +#define PCNT_CNT_THRES0_U7_V 0xFFFF +#define PCNT_CNT_THRES0_U7_S 0 + +#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c) +/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit7.*/ +#define PCNT_CNT_L_LIM_U7 0x0000FFFF +#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S)) +#define PCNT_CNT_L_LIM_U7_V 0xFFFF +#define PCNT_CNT_L_LIM_U7_S 16 +/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit7.*/ +#define PCNT_CNT_H_LIM_U7 0x0000FFFF +#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S)) +#define PCNT_CNT_H_LIM_U7_V 0xFFFF +#define PCNT_CNT_H_LIM_U7_S 0 + +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060) +/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit0.*/ +#define PCNT_PLUS_CNT_U0 0x0000FFFF +#define PCNT_PLUS_CNT_U0_M ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S)) +#define PCNT_PLUS_CNT_U0_V 0xFFFF +#define PCNT_PLUS_CNT_U0_S 0 + +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064) +/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit1.*/ +#define PCNT_PLUS_CNT_U1 0x0000FFFF +#define PCNT_PLUS_CNT_U1_M ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S)) +#define PCNT_PLUS_CNT_U1_V 0xFFFF +#define PCNT_PLUS_CNT_U1_S 0 + +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068) +/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit2.*/ +#define PCNT_PLUS_CNT_U2 0x0000FFFF +#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S)) +#define PCNT_PLUS_CNT_U2_V 0xFFFF +#define PCNT_PLUS_CNT_U2_S 0 + +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c) +/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit3.*/ +#define PCNT_PLUS_CNT_U3 0x0000FFFF +#define PCNT_PLUS_CNT_U3_M ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S)) +#define PCNT_PLUS_CNT_U3_V 0xFFFF +#define PCNT_PLUS_CNT_U3_S 0 + +#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070) +/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit4.*/ +#define PCNT_PLUS_CNT_U4 0x0000FFFF +#define PCNT_PLUS_CNT_U4_M ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S)) +#define PCNT_PLUS_CNT_U4_V 0xFFFF +#define PCNT_PLUS_CNT_U4_S 0 + +#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074) +/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit5.*/ +#define PCNT_PLUS_CNT_U5 0x0000FFFF +#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S)) +#define PCNT_PLUS_CNT_U5_V 0xFFFF +#define PCNT_PLUS_CNT_U5_S 0 + +#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078) +/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit6.*/ +#define PCNT_PLUS_CNT_U6 0x0000FFFF +#define PCNT_PLUS_CNT_U6_M ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S)) +#define PCNT_PLUS_CNT_U6_V 0xFFFF +#define PCNT_PLUS_CNT_U6_S 0 + +#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c) +/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit7.*/ +#define PCNT_PLUS_CNT_U7 0x0000FFFF +#define PCNT_PLUS_CNT_U7_M ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S)) +#define PCNT_PLUS_CNT_U7_V 0xFFFF +#define PCNT_PLUS_CNT_U7_S 0 + +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080) +/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 + +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084) +/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 + +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088) +/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 + +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c) +/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel7 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel6 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel5 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel4 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel3 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel2 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel1 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel0 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 + +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090) +/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U0 0xFFFFFFFF +#define PCNT_CORE_STATUS_U0_M ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S)) +#define PCNT_CORE_STATUS_U0_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U0_S 0 +/*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/ +#define PCNT_STATUS_CNT_MODE 0x3 +#define PCNT_STATUS_CNT_MODE_M ((PCNT_STATUS_CNT_MODE_V)<<(PCNT_STATUS_CNT_MODE_S)) +#define PCNT_STATUS_CNT_MODE_V 0x3 +#define PCNT_STATUS_CNT_MODE_S 0 +/* counter value equals to thresh1*/ +#define PCNT_STATUS_THRES1 BIT(2) +#define PCNT_STATUS_THRES1_M BIT(2) +#define PCNT_STATUS_THRES1_V 0x1 +#define PCNT_STATUS_THRES1_S 2 +/* counter value equals to thresh0*/ +#define PCNT_STATUS_THRES0 BIT(3) +#define PCNT_STATUS_THRES0_M BIT(3) +#define PCNT_STATUS_THRES0_V 0x1 +#define PCNT_STATUS_THRES0_S 3 +/* counter value reaches h_lim*/ +#define PCNT_STATUS_L_LIM BIT(4) +#define PCNT_STATUS_L_LIM_M BIT(4) +#define PCNT_STATUS_L_LIM_V 0x1 +#define PCNT_STATUS_L_LIM_S 4 +/* counter value reaches l_lim*/ +#define PCNT_STATUS_H_LIM BIT(5) +#define PCNT_STATUS_H_LIM_M BIT(5) +#define PCNT_STATUS_H_LIM_V 0x1 +#define PCNT_STATUS_H_LIM_S 5 +/* counter value equals to zero*/ +#define PCNT_STATUS_ZERO BIT(6) +#define PCNT_STATUS_ZERO_M BIT(6) +#define PCNT_STATUS_ZERO_V 0x1 +#define PCNT_STATUS_ZERO_S 6 + +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094) +/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U1 0xFFFFFFFF +#define PCNT_CORE_STATUS_U1_M ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S)) +#define PCNT_CORE_STATUS_U1_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U1_S 0 + +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098) +/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U2 0xFFFFFFFF +#define PCNT_CORE_STATUS_U2_M ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S)) +#define PCNT_CORE_STATUS_U2_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U2_S 0 + +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c) +/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U3 0xFFFFFFFF +#define PCNT_CORE_STATUS_U3_M ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S)) +#define PCNT_CORE_STATUS_U3_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U3_S 0 + +#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0) +/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U4 0xFFFFFFFF +#define PCNT_CORE_STATUS_U4_M ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S)) +#define PCNT_CORE_STATUS_U4_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U4_S 0 + +#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4) +/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U5 0xFFFFFFFF +#define PCNT_CORE_STATUS_U5_M ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S)) +#define PCNT_CORE_STATUS_U5_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U5_S 0 + +#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8) +/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U6 0xFFFFFFFF +#define PCNT_CORE_STATUS_U6_M ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S)) +#define PCNT_CORE_STATUS_U6_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U6_S 0 + +#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac) +/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U7 0xFFFFFFFF +#define PCNT_CORE_STATUS_U7_M ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S)) +#define PCNT_CORE_STATUS_U7_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U7_S 0 + +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0) +/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (BIT(16)) +#define PCNT_CLK_EN_V 0x1 +#define PCNT_CLK_EN_S 16 +/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit7's counter.*/ +#define PCNT_CNT_PAUSE_U7 (BIT(15)) +#define PCNT_CNT_PAUSE_U7_M (BIT(15)) +#define PCNT_CNT_PAUSE_U7_V 0x1 +#define PCNT_CNT_PAUSE_U7_S 15 +/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit7's counter.*/ +#define PCNT_PLUS_CNT_RST_U7 (BIT(14)) +#define PCNT_PLUS_CNT_RST_U7_M (BIT(14)) +#define PCNT_PLUS_CNT_RST_U7_V 0x1 +#define PCNT_PLUS_CNT_RST_U7_S 14 +/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit6's counter.*/ +#define PCNT_CNT_PAUSE_U6 (BIT(13)) +#define PCNT_CNT_PAUSE_U6_M (BIT(13)) +#define PCNT_CNT_PAUSE_U6_V 0x1 +#define PCNT_CNT_PAUSE_U6_S 13 +/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit6's counter.*/ +#define PCNT_PLUS_CNT_RST_U6 (BIT(12)) +#define PCNT_PLUS_CNT_RST_U6_M (BIT(12)) +#define PCNT_PLUS_CNT_RST_U6_V 0x1 +#define PCNT_PLUS_CNT_RST_U6_S 12 +/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit5's counter.*/ +#define PCNT_CNT_PAUSE_U5 (BIT(11)) +#define PCNT_CNT_PAUSE_U5_M (BIT(11)) +#define PCNT_CNT_PAUSE_U5_V 0x1 +#define PCNT_CNT_PAUSE_U5_S 11 +/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit5's counter.*/ +#define PCNT_PLUS_CNT_RST_U5 (BIT(10)) +#define PCNT_PLUS_CNT_RST_U5_M (BIT(10)) +#define PCNT_PLUS_CNT_RST_U5_V 0x1 +#define PCNT_PLUS_CNT_RST_U5_S 10 +/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit4's counter.*/ +#define PCNT_CNT_PAUSE_U4 (BIT(9)) +#define PCNT_CNT_PAUSE_U4_M (BIT(9)) +#define PCNT_CNT_PAUSE_U4_V 0x1 +#define PCNT_CNT_PAUSE_U4_S 9 +/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit4's counter.*/ +#define PCNT_PLUS_CNT_RST_U4 (BIT(8)) +#define PCNT_PLUS_CNT_RST_U4_M (BIT(8)) +#define PCNT_PLUS_CNT_RST_U4_V 0x1 +#define PCNT_PLUS_CNT_RST_U4_S 8 +/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit3's counter.*/ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (BIT(7)) +#define PCNT_CNT_PAUSE_U3_V 0x1 +#define PCNT_CNT_PAUSE_U3_S 7 +/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit3's counter.*/ +#define PCNT_PLUS_CNT_RST_U3 (BIT(6)) +#define PCNT_PLUS_CNT_RST_U3_M (BIT(6)) +#define PCNT_PLUS_CNT_RST_U3_V 0x1 +#define PCNT_PLUS_CNT_RST_U3_S 6 +/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit2's counter.*/ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (BIT(5)) +#define PCNT_CNT_PAUSE_U2_V 0x1 +#define PCNT_CNT_PAUSE_U2_S 5 +/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit2's counter.*/ +#define PCNT_PLUS_CNT_RST_U2 (BIT(4)) +#define PCNT_PLUS_CNT_RST_U2_M (BIT(4)) +#define PCNT_PLUS_CNT_RST_U2_V 0x1 +#define PCNT_PLUS_CNT_RST_U2_S 4 +/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit1's counter.*/ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (BIT(3)) +#define PCNT_CNT_PAUSE_U1_V 0x1 +#define PCNT_CNT_PAUSE_U1_S 3 +/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit1's counter.*/ +#define PCNT_PLUS_CNT_RST_U1 (BIT(2)) +#define PCNT_PLUS_CNT_RST_U1_M (BIT(2)) +#define PCNT_PLUS_CNT_RST_U1_V 0x1 +#define PCNT_PLUS_CNT_RST_U1_S 2 +/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit0's counter.*/ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (BIT(1)) +#define PCNT_CNT_PAUSE_U0_V 0x1 +#define PCNT_CNT_PAUSE_U0_S 1 +/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit0's counter.*/ +#define PCNT_PLUS_CNT_RST_U0 (BIT(0)) +#define PCNT_PLUS_CNT_RST_U0_M (BIT(0)) +#define PCNT_PLUS_CNT_RST_U0_V 0x1 +#define PCNT_PLUS_CNT_RST_U0_S 0 + +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc) +/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */ +/*description: */ +#define PCNT_DATE 0xFFFFFFFF +#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S)) +#define PCNT_DATE_V 0xFFFFFFFF +#define PCNT_DATE_S 0 + + + + +#endif /*_SOC_PCNT_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/pcnt_struct.h b/tools/sdk/include/soc/include/soc/pcnt_struct.h new file mode 100644 index 00000000000..a551835bb8f --- /dev/null +++ b/tools/sdk/include/soc/include/soc/pcnt_struct.h @@ -0,0 +1,184 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PCNT_STRUCT_H_ +#define _SOC_PCNT_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + struct{ + union { + struct { + uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/ + uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/ + uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/ + uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/ + uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/ + uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/ + uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/ + uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/ + uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/ + uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/ + }; + uint32_t val; + } conf2; + } conf_unit[8]; + union { + struct { + uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } cnt_unit[8]; + union { + struct { + uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/ + uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/ + uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/ + uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/ + uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/ + uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/ + uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/ + uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/ + uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/ + uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/ + uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/ + uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/ + uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/ + uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/ + uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/ + uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/ + uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/ + uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/ + uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/ + uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/ + uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/ + uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/ + uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/ + uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/ + uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/ + uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/ + uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/ + uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/ + uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t cnt_mode:2; /*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/ + uint32_t thres1_lat:1; /* counter value equals to thresh1*/ + uint32_t thres0_lat:1; /* counter value equals to thresh0*/ + uint32_t l_lim_lat:1; /* counter value reaches h_lim*/ + uint32_t h_lim_lat:1; /* counter value reaches l_lim*/ + uint32_t zero_lat:1; /* counter value equals zero*/ + uint32_t reserved7:25; + }; + uint32_t val; + } status_unit[8]; + union { + struct { + uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ + uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/ + uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/ + uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/ + uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/ + uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ + uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ + uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ + uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/ + uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/ + uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/ + uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/ + uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/ + uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/ + uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/ + uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/ + uint32_t clk_en: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } ctrl; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ +} pcnt_dev_t; +extern pcnt_dev_t PCNT; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_PCNT_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/periph_defs.h b/tools/sdk/include/soc/include/soc/periph_defs.h new file mode 100644 index 00000000000..c4ad589c9dd --- /dev/null +++ b/tools/sdk/include/soc/include/soc/periph_defs.h @@ -0,0 +1,64 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_PERIPH_DEFS_H_ +#define _SOC_PERIPH_DEFS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_UART2_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S0_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_PWM0_MODULE, + PERIPH_PWM1_MODULE, + PERIPH_PWM2_MODULE, + PERIPH_PWM3_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_UHCI1_MODULE, + PERIPH_RMT_MODULE, + PERIPH_PCNT_MODULE, + PERIPH_SPI_MODULE, + PERIPH_HSPI_MODULE, + PERIPH_VSPI_MODULE, + PERIPH_SPI_DMA_MODULE, + PERIPH_SDMMC_MODULE, + PERIPH_SDIO_SLAVE_MODULE, + PERIPH_CAN_MODULE, + PERIPH_EMAC_MODULE, + PERIPH_RNG_MODULE, + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_WIFI_BT_COMMON_MODULE, + PERIPH_BT_BASEBAND_MODULE, + PERIPH_BT_LC_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_RSA_MODULE, +} periph_module_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_PERIPH_DEFS_H_ */ diff --git a/tools/sdk/include/soc/include/soc/pid.h b/tools/sdk/include/soc/include/soc/pid.h new file mode 100644 index 00000000000..bd4e9f26d24 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/pid.h @@ -0,0 +1,65 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PID_H_ +#define _SOC_PID_H_ + +#define PROPID_GEN_BASE 0x3FF1F000 +//Bits 1..7: 1 if interrupt will be triggering PID change +#define PROPID_CONFIG_INTERRUPT_ENABLE ((PROPID_GEN_BASE)+0x000) +//Vectors for the various interrupt handlers +#define PROPID_CONFIG_INTERRUPT_ADDR_1 ((PROPID_GEN_BASE)+0x004) +#define PROPID_CONFIG_INTERRUPT_ADDR_2 ((PROPID_GEN_BASE)+0x008) +#define PROPID_CONFIG_INTERRUPT_ADDR_3 ((PROPID_GEN_BASE)+0x00C) +#define PROPID_CONFIG_INTERRUPT_ADDR_4 ((PROPID_GEN_BASE)+0x010) +#define PROPID_CONFIG_INTERRUPT_ADDR_5 ((PROPID_GEN_BASE)+0x014) +#define PROPID_CONFIG_INTERRUPT_ADDR_6 ((PROPID_GEN_BASE)+0x018) +#define PROPID_CONFIG_INTERRUPT_ADDR_7 ((PROPID_GEN_BASE)+0x01C) + +//Delay, in CPU cycles, before switching to new PID +#define PROPID_CONFIG_PID_DELAY ((PROPID_GEN_BASE)+0x020) +#define PROPID_CONFIG_NMI_DELAY ((PROPID_GEN_BASE)+0x024) + +//Last detected interrupt. Set by hw on int. +#define PROPID_TABLE_LEVEL ((PROPID_GEN_BASE)+0x028) +//PID/prev int data for each int +#define PROPID_FROM_1 ((PROPID_GEN_BASE)+0x02C) +#define PROPID_FROM_2 ((PROPID_GEN_BASE)+0x030) +#define PROPID_FROM_3 ((PROPID_GEN_BASE)+0x034) +#define PROPID_FROM_4 ((PROPID_GEN_BASE)+0x038) +#define PROPID_FROM_5 ((PROPID_GEN_BASE)+0x03C) +#define PROPID_FROM_6 ((PROPID_GEN_BASE)+0x040) +#define PROPID_FROM_7 ((PROPID_GEN_BASE)+0x044) +#define PROPID_FROM_PID_MASK 0x7 +#define PROPID_FROM_PID_S 0 +#define PROPID_FROM_INT_MASK 0xF +#define PROPID_FROM_INT_S 3 + +//PID to be set after confirm routine +#define PROPID_PID_NEW ((PROPID_GEN_BASE)+0x048) +//Write to kick off PID change +#define PROPID_PID_CONFIRM ((PROPID_GEN_BASE)+0x04c) +//current PID? +#define PROPID_PID_REG ((PROPID_GEN_BASE)+0x050) + +//Write to mask NMI +#define PROPID_PID_NMI_MASK_HW_ENABLE ((PROPID_GEN_BASE)+0x054) +//Write to unmask NMI +#define PROPID_PID_NMI_MASK_HW_DISABLE ((PROPID_GEN_BASE)+0x058) +#define PROPID_PID_NMI_MASK_HW_REG ((PROPID_GEN_BASE)+0x05c) + +//Debug regs +#define PROPID_PID ((PROPID_GEN_BASE)+0x060) +#define PROPID_NMI_MASK_HW ((PROPID_GEN_BASE)+0x064) + +#endif /* _SOC_PID_H_ */ diff --git a/tools/sdk/include/soc/include/soc/rmt_reg.h b/tools/sdk/include/soc/include/soc/rmt_reg.h new file mode 100644 index 00000000000..15c2f9a2dc6 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/rmt_reg.h @@ -0,0 +1,2604 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_REG_H_ +#define _SOC_RMT_REG_H_ + +#include "soc.h" +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) + +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) + +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) + +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) + +#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) + +#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) + +#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) + +#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) + +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) +/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: This bit is used to control clock.when software config RMT + internal registers it controls the register clock.*/ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (BIT(31)) +#define RMT_CLK_EN_V 0x1 +#define RMT_CLK_EN_S 31 +/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/ +#define RMT_MEM_PD (BIT(30)) +#define RMT_MEM_PD_M (BIT(30)) +#define RMT_MEM_PD_V 0x1 +#define RMT_MEM_PD_S 30 +/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure the way carrier wave is modulated + for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH0_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH0_V 0x1 +#define RMT_CARRIER_OUT_LV_CH0_S 29 +/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel0.*/ +#define RMT_CARRIER_EN_CH0 (BIT(28)) +#define RMT_CARRIER_EN_CH0_M (BIT(28)) +#define RMT_CARRIER_EN_CH0_V 0x1 +#define RMT_CARRIER_EN_CH0_S 28 +/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel0.*/ +#define RMT_MEM_SIZE_CH0 0x0000000F +#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) +#define RMT_MEM_SIZE_CH0_V 0xF +#define RMT_MEM_SIZE_CH0_S 24 +/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when no edge is detected on the input signal + for longer than reg_idle_thres_ch0 then the receive process is done.*/ +#define RMT_IDLE_THRES_CH0 0x0000FFFF +#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S)) +#define RMT_IDLE_THRES_CH0_V 0xFFFF +#define RMT_IDLE_THRES_CH0_S 8 +/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel0.*/ +#define RMT_DIV_CNT_CH0 0x000000FF +#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) +#define RMT_DIV_CNT_CH0_V 0xFF +#define RMT_DIV_CNT_CH0_S 0 + +#define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024) +/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel0 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH0 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH0_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH0_V 0x1 +#define RMT_IDLE_OUT_EN_CH0_S 19 +/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel0 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH0 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH0_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH0_V 0x1 +#define RMT_IDLE_OUT_LV_CH0_S 18 +/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH0_V 0x1 +#define RMT_REF_ALWAYS_ON_CH0_S 17 +/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel0.*/ +#define RMT_REF_CNT_RST_CH0 (BIT(16)) +#define RMT_REF_CNT_RST_CH0_M (BIT(16)) +#define RMT_REF_CNT_RST_CH0_V 0x1 +#define RMT_REF_CNT_RST_CH0_S 16 +/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel0 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH0 0x000000FF +#define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S)) +#define RMT_RX_FILTER_THRES_CH0_V 0xFF +#define RMT_RX_FILTER_THRES_CH0_S 8 +/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel0.*/ +#define RMT_RX_FILTER_EN_CH0 (BIT(7)) +#define RMT_RX_FILTER_EN_CH0_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH0_V 0x1 +#define RMT_RX_FILTER_EN_CH0_S 7 +/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel0 again and again.*/ +#define RMT_TX_CONTI_MODE_CH0 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH0_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH0_V 0x1 +#define RMT_TX_CONTI_MODE_CH0_S 6 +/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel0's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH0 (BIT(5)) +#define RMT_MEM_OWNER_CH0_M (BIT(5)) +#define RMT_MEM_OWNER_CH0_V 0x1 +#define RMT_MEM_OWNER_CH0_S 5 +/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH0 (BIT(4)) +#define RMT_APB_MEM_RST_CH0_M (BIT(4)) +#define RMT_APB_MEM_RST_CH0_V 0x1 +#define RMT_APB_MEM_RST_CH0_S 4 +/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH0 (BIT(3)) +#define RMT_MEM_RD_RST_CH0_M (BIT(3)) +#define RMT_MEM_RD_RST_CH0_V 0x1 +#define RMT_MEM_RD_RST_CH0_S 3 +/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel0 by receiver access.*/ +#define RMT_MEM_WR_RST_CH0 (BIT(2)) +#define RMT_MEM_WR_RST_CH0_M (BIT(2)) +#define RMT_MEM_WR_RST_CH0_V 0x1 +#define RMT_MEM_WR_RST_CH0_S 2 +/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel0.*/ +#define RMT_RX_EN_CH0 (BIT(1)) +#define RMT_RX_EN_CH0_M (BIT(1)) +#define RMT_RX_EN_CH0_V 0x1 +#define RMT_RX_EN_CH0_S 1 +/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel0.*/ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (BIT(0)) +#define RMT_TX_START_CH0_V 0x1 +#define RMT_TX_START_CH0_S 0 + +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028) +/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure the way carrier wave is modulated + for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH1_V 0x1 +#define RMT_CARRIER_OUT_LV_CH1_S 29 +/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel1.*/ +#define RMT_CARRIER_EN_CH1 (BIT(28)) +#define RMT_CARRIER_EN_CH1_M (BIT(28)) +#define RMT_CARRIER_EN_CH1_V 0x1 +#define RMT_CARRIER_EN_CH1_S 28 +/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel1.*/ +#define RMT_MEM_SIZE_CH1 0x0000000F +#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) +#define RMT_MEM_SIZE_CH1_V 0xF +#define RMT_MEM_SIZE_CH1_S 24 +/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel1.*/ +#define RMT_IDLE_THRES_CH1 0x0000FFFF +#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S)) +#define RMT_IDLE_THRES_CH1_V 0xFFFF +#define RMT_IDLE_THRES_CH1_S 8 +/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel1.*/ +#define RMT_DIV_CNT_CH1 0x000000FF +#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) +#define RMT_DIV_CNT_CH1_V 0xFF +#define RMT_DIV_CNT_CH1_S 0 + +#define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c) +/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel1 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH1 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH1_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH1_V 0x1 +#define RMT_IDLE_OUT_EN_CH1_S 19 +/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel1 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH1 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH1_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH1_V 0x1 +#define RMT_IDLE_OUT_LV_CH1_S 18 +/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH1 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH1_V 0x1 +#define RMT_REF_ALWAYS_ON_CH1_S 17 +/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel1.*/ +#define RMT_REF_CNT_RST_CH1 (BIT(16)) +#define RMT_REF_CNT_RST_CH1_M (BIT(16)) +#define RMT_REF_CNT_RST_CH1_V 0x1 +#define RMT_REF_CNT_RST_CH1_S 16 +/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel1 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH1 0x000000FF +#define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S)) +#define RMT_RX_FILTER_THRES_CH1_V 0xFF +#define RMT_RX_FILTER_THRES_CH1_S 8 +/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel1.*/ +#define RMT_RX_FILTER_EN_CH1 (BIT(7)) +#define RMT_RX_FILTER_EN_CH1_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH1_V 0x1 +#define RMT_RX_FILTER_EN_CH1_S 7 +/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel1 again and again.*/ +#define RMT_TX_CONTI_MODE_CH1 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH1_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH1_V 0x1 +#define RMT_TX_CONTI_MODE_CH1_S 6 +/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel1's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH1 (BIT(5)) +#define RMT_MEM_OWNER_CH1_M (BIT(5)) +#define RMT_MEM_OWNER_CH1_V 0x1 +#define RMT_MEM_OWNER_CH1_S 5 +/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH1 (BIT(4)) +#define RMT_APB_MEM_RST_CH1_M (BIT(4)) +#define RMT_APB_MEM_RST_CH1_V 0x1 +#define RMT_APB_MEM_RST_CH1_S 4 +/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH1 (BIT(3)) +#define RMT_MEM_RD_RST_CH1_M (BIT(3)) +#define RMT_MEM_RD_RST_CH1_V 0x1 +#define RMT_MEM_RD_RST_CH1_S 3 +/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel1 by receiver access.*/ +#define RMT_MEM_WR_RST_CH1 (BIT(2)) +#define RMT_MEM_WR_RST_CH1_M (BIT(2)) +#define RMT_MEM_WR_RST_CH1_V 0x1 +#define RMT_MEM_WR_RST_CH1_S 2 +/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel1.*/ +#define RMT_RX_EN_CH1 (BIT(1)) +#define RMT_RX_EN_CH1_M (BIT(1)) +#define RMT_RX_EN_CH1_V 0x1 +#define RMT_RX_EN_CH1_S 1 +/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel1.*/ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (BIT(0)) +#define RMT_TX_START_CH1_V 0x1 +#define RMT_TX_START_CH1_S 0 + +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030) +/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_V 0x1 +#define RMT_CARRIER_OUT_LV_CH2_S 29 +/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel2.*/ +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (BIT(28)) +#define RMT_CARRIER_EN_CH2_V 0x1 +#define RMT_CARRIER_EN_CH2_S 28 +/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel2.*/ +#define RMT_MEM_SIZE_CH2 0x0000000F +#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) +#define RMT_MEM_SIZE_CH2_V 0xF +#define RMT_MEM_SIZE_CH2_S 24 +/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH2 0x0000FFFF +#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S)) +#define RMT_IDLE_THRES_CH2_V 0xFFFF +#define RMT_IDLE_THRES_CH2_S 8 +/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel2.*/ +#define RMT_DIV_CNT_CH2 0x000000FF +#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) +#define RMT_DIV_CNT_CH2_V 0xFF +#define RMT_DIV_CNT_CH2_S 0 + +#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034) +/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel2 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH2 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH2_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH2_V 0x1 +#define RMT_IDLE_OUT_EN_CH2_S 19 +/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel2 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH2 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH2_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH2_V 0x1 +#define RMT_IDLE_OUT_LV_CH2_S 18 +/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH2 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH2_V 0x1 +#define RMT_REF_ALWAYS_ON_CH2_S 17 +/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel2.*/ +#define RMT_REF_CNT_RST_CH2 (BIT(16)) +#define RMT_REF_CNT_RST_CH2_M (BIT(16)) +#define RMT_REF_CNT_RST_CH2_V 0x1 +#define RMT_REF_CNT_RST_CH2_S 16 +/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel2 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH2 0x000000FF +#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S)) +#define RMT_RX_FILTER_THRES_CH2_V 0xFF +#define RMT_RX_FILTER_THRES_CH2_S 8 +/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel2.*/ +#define RMT_RX_FILTER_EN_CH2 (BIT(7)) +#define RMT_RX_FILTER_EN_CH2_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH2_V 0x1 +#define RMT_RX_FILTER_EN_CH2_S 7 +/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel2.*/ +#define RMT_TX_CONTI_MODE_CH2 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH2_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH2_V 0x1 +#define RMT_TX_CONTI_MODE_CH2_S 6 +/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel2's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH2 (BIT(5)) +#define RMT_MEM_OWNER_CH2_M (BIT(5)) +#define RMT_MEM_OWNER_CH2_V 0x1 +#define RMT_MEM_OWNER_CH2_S 5 +/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH2 (BIT(4)) +#define RMT_APB_MEM_RST_CH2_M (BIT(4)) +#define RMT_APB_MEM_RST_CH2_V 0x1 +#define RMT_APB_MEM_RST_CH2_S 4 +/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH2 (BIT(3)) +#define RMT_MEM_RD_RST_CH2_M (BIT(3)) +#define RMT_MEM_RD_RST_CH2_V 0x1 +#define RMT_MEM_RD_RST_CH2_S 3 +/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel2 by receiver access.*/ +#define RMT_MEM_WR_RST_CH2 (BIT(2)) +#define RMT_MEM_WR_RST_CH2_M (BIT(2)) +#define RMT_MEM_WR_RST_CH2_V 0x1 +#define RMT_MEM_WR_RST_CH2_S 2 +/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel2.*/ +#define RMT_RX_EN_CH2 (BIT(1)) +#define RMT_RX_EN_CH2_M (BIT(1)) +#define RMT_RX_EN_CH2_V 0x1 +#define RMT_RX_EN_CH2_S 1 +/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel2.*/ +#define RMT_TX_START_CH2 (BIT(0)) +#define RMT_TX_START_CH2_M (BIT(0)) +#define RMT_TX_START_CH2_V 0x1 +#define RMT_TX_START_CH2_S 0 + +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038) +/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_V 0x1 +#define RMT_CARRIER_OUT_LV_CH3_S 29 +/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel3.*/ +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (BIT(28)) +#define RMT_CARRIER_EN_CH3_V 0x1 +#define RMT_CARRIER_EN_CH3_S 28 +/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel3.*/ +#define RMT_MEM_SIZE_CH3 0x0000000F +#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) +#define RMT_MEM_SIZE_CH3_V 0xF +#define RMT_MEM_SIZE_CH3_S 24 +/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH3 0x0000FFFF +#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S)) +#define RMT_IDLE_THRES_CH3_V 0xFFFF +#define RMT_IDLE_THRES_CH3_S 8 +/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel3.*/ +#define RMT_DIV_CNT_CH3 0x000000FF +#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) +#define RMT_DIV_CNT_CH3_V 0xFF +#define RMT_DIV_CNT_CH3_S 0 + +#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c) +/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel3 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH3 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH3_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH3_V 0x1 +#define RMT_IDLE_OUT_EN_CH3_S 19 +/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel3 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH3 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH3_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH3_V 0x1 +#define RMT_IDLE_OUT_LV_CH3_S 18 +/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH3 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH3_V 0x1 +#define RMT_REF_ALWAYS_ON_CH3_S 17 +/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel3.*/ +#define RMT_REF_CNT_RST_CH3 (BIT(16)) +#define RMT_REF_CNT_RST_CH3_M (BIT(16)) +#define RMT_REF_CNT_RST_CH3_V 0x1 +#define RMT_REF_CNT_RST_CH3_S 16 +/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel3 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH3 0x000000FF +#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S)) +#define RMT_RX_FILTER_THRES_CH3_V 0xFF +#define RMT_RX_FILTER_THRES_CH3_S 8 +/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel3.*/ +#define RMT_RX_FILTER_EN_CH3 (BIT(7)) +#define RMT_RX_FILTER_EN_CH3_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH3_V 0x1 +#define RMT_RX_FILTER_EN_CH3_S 7 +/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel3.*/ +#define RMT_TX_CONTI_MODE_CH3 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH3_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH3_V 0x1 +#define RMT_TX_CONTI_MODE_CH3_S 6 +/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel3's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH3 (BIT(5)) +#define RMT_MEM_OWNER_CH3_M (BIT(5)) +#define RMT_MEM_OWNER_CH3_V 0x1 +#define RMT_MEM_OWNER_CH3_S 5 +/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH3 (BIT(4)) +#define RMT_APB_MEM_RST_CH3_M (BIT(4)) +#define RMT_APB_MEM_RST_CH3_V 0x1 +#define RMT_APB_MEM_RST_CH3_S 4 +/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH3 (BIT(3)) +#define RMT_MEM_RD_RST_CH3_M (BIT(3)) +#define RMT_MEM_RD_RST_CH3_V 0x1 +#define RMT_MEM_RD_RST_CH3_S 3 +/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel3 by receiver access.*/ +#define RMT_MEM_WR_RST_CH3 (BIT(2)) +#define RMT_MEM_WR_RST_CH3_M (BIT(2)) +#define RMT_MEM_WR_RST_CH3_V 0x1 +#define RMT_MEM_WR_RST_CH3_S 2 +/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel3.*/ +#define RMT_RX_EN_CH3 (BIT(1)) +#define RMT_RX_EN_CH3_M (BIT(1)) +#define RMT_RX_EN_CH3_V 0x1 +#define RMT_RX_EN_CH3_S 1 +/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel3.*/ +#define RMT_TX_START_CH3 (BIT(0)) +#define RMT_TX_START_CH3_M (BIT(0)) +#define RMT_TX_START_CH3_V 0x1 +#define RMT_TX_START_CH3_S 0 + +#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040) +/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_V 0x1 +#define RMT_CARRIER_OUT_LV_CH4_S 29 +/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel4.*/ +#define RMT_CARRIER_EN_CH4 (BIT(28)) +#define RMT_CARRIER_EN_CH4_M (BIT(28)) +#define RMT_CARRIER_EN_CH4_V 0x1 +#define RMT_CARRIER_EN_CH4_S 28 +/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel4.*/ +#define RMT_MEM_SIZE_CH4 0x0000000F +#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S)) +#define RMT_MEM_SIZE_CH4_V 0xF +#define RMT_MEM_SIZE_CH4_S 24 +/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH4 0x0000FFFF +#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S)) +#define RMT_IDLE_THRES_CH4_V 0xFFFF +#define RMT_IDLE_THRES_CH4_S 8 +/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel4.*/ +#define RMT_DIV_CNT_CH4 0x000000FF +#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S)) +#define RMT_DIV_CNT_CH4_V 0xFF +#define RMT_DIV_CNT_CH4_S 0 + +#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044) +/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel4 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH4 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH4_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH4_V 0x1 +#define RMT_IDLE_OUT_EN_CH4_S 19 +/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel4 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH4 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH4_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH4_V 0x1 +#define RMT_IDLE_OUT_LV_CH4_S 18 +/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH4 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH4_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH4_V 0x1 +#define RMT_REF_ALWAYS_ON_CH4_S 17 +/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel4.*/ +#define RMT_REF_CNT_RST_CH4 (BIT(16)) +#define RMT_REF_CNT_RST_CH4_M (BIT(16)) +#define RMT_REF_CNT_RST_CH4_V 0x1 +#define RMT_REF_CNT_RST_CH4_S 16 +/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel4 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH4 0x000000FF +#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S)) +#define RMT_RX_FILTER_THRES_CH4_V 0xFF +#define RMT_RX_FILTER_THRES_CH4_S 8 +/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel4.*/ +#define RMT_RX_FILTER_EN_CH4 (BIT(7)) +#define RMT_RX_FILTER_EN_CH4_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH4_V 0x1 +#define RMT_RX_FILTER_EN_CH4_S 7 +/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel4.*/ +#define RMT_TX_CONTI_MODE_CH4 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH4_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH4_V 0x1 +#define RMT_TX_CONTI_MODE_CH4_S 6 +/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel4's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH4 (BIT(5)) +#define RMT_MEM_OWNER_CH4_M (BIT(5)) +#define RMT_MEM_OWNER_CH4_V 0x1 +#define RMT_MEM_OWNER_CH4_S 5 +/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH4 (BIT(4)) +#define RMT_APB_MEM_RST_CH4_M (BIT(4)) +#define RMT_APB_MEM_RST_CH4_V 0x1 +#define RMT_APB_MEM_RST_CH4_S 4 +/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH4 (BIT(3)) +#define RMT_MEM_RD_RST_CH4_M (BIT(3)) +#define RMT_MEM_RD_RST_CH4_V 0x1 +#define RMT_MEM_RD_RST_CH4_S 3 +/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel4 by receiver access.*/ +#define RMT_MEM_WR_RST_CH4 (BIT(2)) +#define RMT_MEM_WR_RST_CH4_M (BIT(2)) +#define RMT_MEM_WR_RST_CH4_V 0x1 +#define RMT_MEM_WR_RST_CH4_S 2 +/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel4.*/ +#define RMT_RX_EN_CH4 (BIT(1)) +#define RMT_RX_EN_CH4_M (BIT(1)) +#define RMT_RX_EN_CH4_V 0x1 +#define RMT_RX_EN_CH4_S 1 +/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel4.*/ +#define RMT_TX_START_CH4 (BIT(0)) +#define RMT_TX_START_CH4_M (BIT(0)) +#define RMT_TX_START_CH4_V 0x1 +#define RMT_TX_START_CH4_S 0 + +#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048) +/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_V 0x1 +#define RMT_CARRIER_OUT_LV_CH5_S 29 +/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel5.*/ +#define RMT_CARRIER_EN_CH5 (BIT(28)) +#define RMT_CARRIER_EN_CH5_M (BIT(28)) +#define RMT_CARRIER_EN_CH5_V 0x1 +#define RMT_CARRIER_EN_CH5_S 28 +/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel5.*/ +#define RMT_MEM_SIZE_CH5 0x0000000F +#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S)) +#define RMT_MEM_SIZE_CH5_V 0xF +#define RMT_MEM_SIZE_CH5_S 24 +/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH5 0x0000FFFF +#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S)) +#define RMT_IDLE_THRES_CH5_V 0xFFFF +#define RMT_IDLE_THRES_CH5_S 8 +/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel5.*/ +#define RMT_DIV_CNT_CH5 0x000000FF +#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S)) +#define RMT_DIV_CNT_CH5_V 0xFF +#define RMT_DIV_CNT_CH5_S 0 + +#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c) +/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel5 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH5 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH5_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH5_V 0x1 +#define RMT_IDLE_OUT_EN_CH5_S 19 +/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel5 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH5 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH5_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH5_V 0x1 +#define RMT_IDLE_OUT_LV_CH5_S 18 +/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH5 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH5_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH5_V 0x1 +#define RMT_REF_ALWAYS_ON_CH5_S 17 +/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel5.*/ +#define RMT_REF_CNT_RST_CH5 (BIT(16)) +#define RMT_REF_CNT_RST_CH5_M (BIT(16)) +#define RMT_REF_CNT_RST_CH5_V 0x1 +#define RMT_REF_CNT_RST_CH5_S 16 +/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel5 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH5 0x000000FF +#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S)) +#define RMT_RX_FILTER_THRES_CH5_V 0xFF +#define RMT_RX_FILTER_THRES_CH5_S 8 +/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel5.*/ +#define RMT_RX_FILTER_EN_CH5 (BIT(7)) +#define RMT_RX_FILTER_EN_CH5_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH5_V 0x1 +#define RMT_RX_FILTER_EN_CH5_S 7 +/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel5.*/ +#define RMT_TX_CONTI_MODE_CH5 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH5_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH5_V 0x1 +#define RMT_TX_CONTI_MODE_CH5_S 6 +/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel5's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH5 (BIT(5)) +#define RMT_MEM_OWNER_CH5_M (BIT(5)) +#define RMT_MEM_OWNER_CH5_V 0x1 +#define RMT_MEM_OWNER_CH5_S 5 +/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH5 (BIT(4)) +#define RMT_APB_MEM_RST_CH5_M (BIT(4)) +#define RMT_APB_MEM_RST_CH5_V 0x1 +#define RMT_APB_MEM_RST_CH5_S 4 +/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH5 (BIT(3)) +#define RMT_MEM_RD_RST_CH5_M (BIT(3)) +#define RMT_MEM_RD_RST_CH5_V 0x1 +#define RMT_MEM_RD_RST_CH5_S 3 +/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel5 by receiver access.*/ +#define RMT_MEM_WR_RST_CH5 (BIT(2)) +#define RMT_MEM_WR_RST_CH5_M (BIT(2)) +#define RMT_MEM_WR_RST_CH5_V 0x1 +#define RMT_MEM_WR_RST_CH5_S 2 +/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel5.*/ +#define RMT_RX_EN_CH5 (BIT(1)) +#define RMT_RX_EN_CH5_M (BIT(1)) +#define RMT_RX_EN_CH5_V 0x1 +#define RMT_RX_EN_CH5_S 1 +/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel5.*/ +#define RMT_TX_START_CH5 (BIT(0)) +#define RMT_TX_START_CH5_M (BIT(0)) +#define RMT_TX_START_CH5_V 0x1 +#define RMT_TX_START_CH5_S 0 + +#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050) +/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_V 0x1 +#define RMT_CARRIER_OUT_LV_CH6_S 29 +/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel6.*/ +#define RMT_CARRIER_EN_CH6 (BIT(28)) +#define RMT_CARRIER_EN_CH6_M (BIT(28)) +#define RMT_CARRIER_EN_CH6_V 0x1 +#define RMT_CARRIER_EN_CH6_S 28 +/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel6.*/ +#define RMT_MEM_SIZE_CH6 0x0000000F +#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S)) +#define RMT_MEM_SIZE_CH6_V 0xF +#define RMT_MEM_SIZE_CH6_S 24 +/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH6 0x0000FFFF +#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S)) +#define RMT_IDLE_THRES_CH6_V 0xFFFF +#define RMT_IDLE_THRES_CH6_S 8 +/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel6.*/ +#define RMT_DIV_CNT_CH6 0x000000FF +#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S)) +#define RMT_DIV_CNT_CH6_V 0xFF +#define RMT_DIV_CNT_CH6_S 0 + +#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054) +/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH6 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH6_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH6_V 0x1 +#define RMT_IDLE_OUT_EN_CH6_S 19 +/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH6 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH6_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH6_V 0x1 +#define RMT_IDLE_OUT_LV_CH6_S 18 +/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH6 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH6_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH6_V 0x1 +#define RMT_REF_ALWAYS_ON_CH6_S 17 +/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel6.*/ +#define RMT_REF_CNT_RST_CH6 (BIT(16)) +#define RMT_REF_CNT_RST_CH6_M (BIT(16)) +#define RMT_REF_CNT_RST_CH6_V 0x1 +#define RMT_REF_CNT_RST_CH6_S 16 +/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel6 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH6 0x000000FF +#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S)) +#define RMT_RX_FILTER_THRES_CH6_V 0xFF +#define RMT_RX_FILTER_THRES_CH6_S 8 +/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel6.*/ +#define RMT_RX_FILTER_EN_CH6 (BIT(7)) +#define RMT_RX_FILTER_EN_CH6_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH6_V 0x1 +#define RMT_RX_FILTER_EN_CH6_S 7 +/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel6.*/ +#define RMT_TX_CONTI_MODE_CH6 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH6_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH6_V 0x1 +#define RMT_TX_CONTI_MODE_CH6_S 6 +/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel6's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH6 (BIT(5)) +#define RMT_MEM_OWNER_CH6_M (BIT(5)) +#define RMT_MEM_OWNER_CH6_V 0x1 +#define RMT_MEM_OWNER_CH6_S 5 +/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH6 (BIT(4)) +#define RMT_APB_MEM_RST_CH6_M (BIT(4)) +#define RMT_APB_MEM_RST_CH6_V 0x1 +#define RMT_APB_MEM_RST_CH6_S 4 +/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH6 (BIT(3)) +#define RMT_MEM_RD_RST_CH6_M (BIT(3)) +#define RMT_MEM_RD_RST_CH6_V 0x1 +#define RMT_MEM_RD_RST_CH6_S 3 +/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel6 by receiver access.*/ +#define RMT_MEM_WR_RST_CH6 (BIT(2)) +#define RMT_MEM_WR_RST_CH6_M (BIT(2)) +#define RMT_MEM_WR_RST_CH6_V 0x1 +#define RMT_MEM_WR_RST_CH6_S 2 +/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel6.*/ +#define RMT_RX_EN_CH6 (BIT(1)) +#define RMT_RX_EN_CH6_M (BIT(1)) +#define RMT_RX_EN_CH6_V 0x1 +#define RMT_RX_EN_CH6_S 1 +/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel6.*/ +#define RMT_TX_START_CH6 (BIT(0)) +#define RMT_TX_START_CH6_M (BIT(0)) +#define RMT_TX_START_CH6_V 0x1 +#define RMT_TX_START_CH6_S 0 + +#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058) +/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_V 0x1 +#define RMT_CARRIER_OUT_LV_CH7_S 29 +/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel7.*/ +#define RMT_CARRIER_EN_CH7 (BIT(28)) +#define RMT_CARRIER_EN_CH7_M (BIT(28)) +#define RMT_CARRIER_EN_CH7_V 0x1 +#define RMT_CARRIER_EN_CH7_S 28 +/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel7.*/ +#define RMT_MEM_SIZE_CH7 0x0000000F +#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S)) +#define RMT_MEM_SIZE_CH7_V 0xF +#define RMT_MEM_SIZE_CH7_S 24 +/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH7 0x0000FFFF +#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S)) +#define RMT_IDLE_THRES_CH7_V 0xFFFF +#define RMT_IDLE_THRES_CH7_S 8 +/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel7.*/ +#define RMT_DIV_CNT_CH7 0x000000FF +#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S)) +#define RMT_DIV_CNT_CH7_V 0xFF +#define RMT_DIV_CNT_CH7_S 0 + +#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c) +/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH7 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH7_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH7_V 0x1 +#define RMT_IDLE_OUT_EN_CH7_S 19 +/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel7 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH7 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH7_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH7_V 0x1 +#define RMT_IDLE_OUT_LV_CH7_S 18 +/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH7 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH7_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH7_V 0x1 +#define RMT_REF_ALWAYS_ON_CH7_S 17 +/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel7.*/ +#define RMT_REF_CNT_RST_CH7 (BIT(16)) +#define RMT_REF_CNT_RST_CH7_M (BIT(16)) +#define RMT_REF_CNT_RST_CH7_V 0x1 +#define RMT_REF_CNT_RST_CH7_S 16 +/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel7 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH7 0x000000FF +#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S)) +#define RMT_RX_FILTER_THRES_CH7_V 0xFF +#define RMT_RX_FILTER_THRES_CH7_S 8 +/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel7.*/ +#define RMT_RX_FILTER_EN_CH7 (BIT(7)) +#define RMT_RX_FILTER_EN_CH7_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH7_V 0x1 +#define RMT_RX_FILTER_EN_CH7_S 7 +/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel7.*/ +#define RMT_TX_CONTI_MODE_CH7 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH7_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH7_V 0x1 +#define RMT_TX_CONTI_MODE_CH7_S 6 +/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel7's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH7 (BIT(5)) +#define RMT_MEM_OWNER_CH7_M (BIT(5)) +#define RMT_MEM_OWNER_CH7_V 0x1 +#define RMT_MEM_OWNER_CH7_S 5 +/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH7 (BIT(4)) +#define RMT_APB_MEM_RST_CH7_M (BIT(4)) +#define RMT_APB_MEM_RST_CH7_V 0x1 +#define RMT_APB_MEM_RST_CH7_S 4 +/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH7 (BIT(3)) +#define RMT_MEM_RD_RST_CH7_M (BIT(3)) +#define RMT_MEM_RD_RST_CH7_V 0x1 +#define RMT_MEM_RD_RST_CH7_S 3 +/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel7 by receiver access.*/ +#define RMT_MEM_WR_RST_CH7 (BIT(2)) +#define RMT_MEM_WR_RST_CH7_M (BIT(2)) +#define RMT_MEM_WR_RST_CH7_V 0x1 +#define RMT_MEM_WR_RST_CH7_S 2 +/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel7.*/ +#define RMT_RX_EN_CH7 (BIT(1)) +#define RMT_RX_EN_CH7_M (BIT(1)) +#define RMT_RX_EN_CH7_V 0x1 +#define RMT_RX_EN_CH7_S 1 +/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel7.*/ +#define RMT_TX_START_CH7 (BIT(0)) +#define RMT_TX_START_CH7_M (BIT(0)) +#define RMT_TX_START_CH7_V 0x1 +#define RMT_TX_START_CH7_S 0 + +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060) +/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel0*/ +#define RMT_STATUS_CH0 0xFFFFFFFF +#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S)) +#define RMT_STATUS_CH0_V 0xFFFFFFFF +#define RMT_STATUS_CH0_S 0 +/* RMT_APB_MEM_RD_ERR_CH0 : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The apb read memory status bit for channel0 turns to + high level when the apb read address exceeds the configuration range.*/ +#define RMT_APB_MEM_RD_ERR_CH0 (BIT(31)) +#define RMT_APB_MEM_RD_ERR_CH0_M ((RMT_APB_MEM_RD_ERR_CH0_V)<<(RMT_APB_MEM_RD_ERR_CH0_S)) +#define RMT_APB_MEM_RD_ERR_CH0_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH0_S 31 +/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The apb write memory status bit for channel0 turns to + high level when the apb write address exceeds the configuration range.*/ +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(30)) +#define RMT_APB_MEM_WR_ERR_CH0_M ((RMT_APB_MEM_WR_ERR_CH0_V)<<(RMT_APB_MEM_WR_ERR_CH0_S)) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH0_S 30 +/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The memory empty status bit for channel0. in acyclic mode, + this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ +#define RMT_MEM_EMPTY_CH0 (BIT(29)) +#define RMT_MEM_EMPTY_CH0_M ((RMT_MEM_EMPTY_CH0_V)<<(RMT_MEM_EMPTY_CH0_S)) +#define RMT_MEM_EMPTY_CH0_V 0x1 +#define RMT_MEM_EMPTY_CH0_S 29 +/* RMT_MEM_FULL_CH0 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The memory full status bit for channel0 turns to high level + when mem_waddr_ex is greater than or equal to the configuration range.*/ +#define RMT_MEM_FULL_CH0 (BIT(28)) +#define RMT_MEM_FULL_CH0_M ((RMT_MEM_FULL_CH0_V)<<(RMT_MEM_FULL_CH0_S)) +#define RMT_MEM_FULL_CH0_V 0x1 +#define RMT_MEM_FULL_CH0_S 28 +/* RMT_MEM_OWNER_ERR_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: When channel0 is configured for receive mode, this bit will turn to high level + if rmt_mem_owner register is not set to 1.*/ +#define RMT_MEM_OWNER_ERR_CH0 (BIT(27)) +#define RMT_MEM_OWNER_ERR_CH0_M ((RMT_MEM_OWNER_ERR_CH0_V)<<(RMT_MEM_OWNER_ERR_CH0_S)) +#define RMT_MEM_OWNER_ERR_CH0_V 0x1 +#define RMT_MEM_OWNER_ERR_CH0_S 27 +/* RMT_STATE_CH0 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The channel0 state machine status register. +3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ +#define RMT_STATE_CH0 0x07000000 +#define RMT_STATE_CH0_M ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S)) +#define RMT_STATE_CH0_V 0x7 +#define RMT_STATE_CH0_S 24 +/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ +/*description: The current memory write address of channel0.*/ +#define RMT_MEM_RADDR_EX_CH0 0x003ff000 +#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S)) +#define RMT_MEM_RADDR_EX_CH0_V 0x3ff +#define RMT_MEM_RADDR_EX_CH0_S 12 +/* RMT_MEM_WADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The current memory read address of channel0.*/ +#define RMT_MEM_WADDR_EX_CH0 0x000003ff +#define RMT_MEM_WADDR_EX_CH0_M ((RMT_MEM_WADDR_EX_CH0_V)<<(RMT_MEM_WADDR_EX_CH0_S)) +#define RMT_MEM_WADDR_EX_CH0_V 0x3ff +#define RMT_MEM_WADDR_EX_CH0_S 0 + +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064) +/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel1*/ +#define RMT_STATUS_CH1 0xFFFFFFFF +#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S)) +#define RMT_STATUS_CH1_V 0xFFFFFFFF +#define RMT_STATUS_CH1_S 0 +/* RMT_APB_MEM_RD_ERR_CH1 : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The apb read memory status bit for channel1 turns to + high level when the apb read address exceeds the configuration range.*/ +#define RMT_APB_MEM_RD_ERR_CH1 (BIT(31)) +#define RMT_APB_MEM_RD_ERR_CH1_M ((RMT_APB_MEM_RD_ERR_CH1_V)<<(RMT_APB_MEM_RD_ERR_CH1_S)) +#define RMT_APB_MEM_RD_ERR_CH1_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH1_S 31 +/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The apb write memory status bit for channel1 turns to + high level when the apb write address exceeds the configuration range.*/ +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(30)) +#define RMT_APB_MEM_WR_ERR_CH1_M ((RMT_APB_MEM_WR_ERR_CH1_V)<<(RMT_APB_MEM_WR_ERR_CH1_S)) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH1_S 30 +/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The memory empty status bit for channel1. in acyclic mode, + this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ +#define RMT_MEM_EMPTY_CH1 (BIT(29)) +#define RMT_MEM_EMPTY_CH1_M ((RMT_MEM_EMPTY_CH1_V)<<(RMT_MEM_EMPTY_CH1_S)) +#define RMT_MEM_EMPTY_CH1_V 0x1 +#define RMT_MEM_EMPTY_CH1_S 29 +/* RMT_MEM_FULL_CH1 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The memory full status bit for channel1 turns to high level + when mem_waddr_ex is greater than or equal to the configuration range.*/ +#define RMT_MEM_FULL_CH1 (BIT(28)) +#define RMT_MEM_FULL_CH1_M ((RMT_MEM_FULL_CH1_V)<<(RMT_MEM_FULL_CH1_S)) +#define RMT_MEM_FULL_CH1_V 0x1 +#define RMT_MEM_FULL_CH1_S 28 +/* RMT_MEM_OWNER_ERR_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: When channel1 is configured for receive mode, this bit will turn to high level + if rmt_mem_owner register is not set to 1.*/ +#define RMT_MEM_OWNER_ERR_CH1 (BIT(27)) +#define RMT_MEM_OWNER_ERR_CH1_M ((RMT_MEM_OWNER_ERR_CH1_V)<<(RMT_MEM_OWNER_ERR_CH1_S)) +#define RMT_MEM_OWNER_ERR_CH1_V 0x1 +#define RMT_MEM_OWNER_ERR_CH1_S 27 +/* RMT_STATE_CH1 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The channel1 state machine status register. +3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ +#define RMT_STATE_CH1 0x07000000 +#define RMT_STATE_CH1_M ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S)) +#define RMT_STATE_CH1_V 0x7 +#define RMT_STATE_CH1_S 24 +/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ +/*description: The current memory write address of channel1.*/ +#define RMT_MEM_RADDR_EX_CH1 0x003ff000 +#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S)) +#define RMT_MEM_RADDR_EX_CH1_V 0x3ff +#define RMT_MEM_RADDR_EX_CH1_S 12 +/* RMT_MEM_WADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The current memory read address of channel1.*/ +#define RMT_MEM_WADDR_EX_CH1 0x000003ff +#define RMT_MEM_WADDR_EX_CH1_M ((RMT_MEM_WADDR_EX_CH1_V)<<(RMT_MEM_WADDR_EX_CH1_S)) +#define RMT_MEM_WADDR_EX_CH1_V 0x3ff +#define RMT_MEM_WADDR_EX_CH1_S 0 + +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068) +/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel2*/ +#define RMT_STATUS_CH2 0xFFFFFFFF +#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S)) +#define RMT_STATUS_CH2_V 0xFFFFFFFF +#define RMT_STATUS_CH2_S 0 +/* RMT_APB_MEM_RD_ERR_CH2 : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The apb read memory status bit for channel2 turns to + high level when the apb read address exceeds the configuration range.*/ +#define RMT_APB_MEM_RD_ERR_CH2 (BIT(31)) +#define RMT_APB_MEM_RD_ERR_CH2_M ((RMT_APB_MEM_RD_ERR_CH2_V)<<(RMT_APB_MEM_RD_ERR_CH2_S)) +#define RMT_APB_MEM_RD_ERR_CH2_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH2_S 31 +/* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The apb write memory status bit for channel2 turns to + high level when the apb write address exceeds the configuration range.*/ +#define RMT_APB_MEM_WR_ERR_CH2 (BIT(30)) +#define RMT_APB_MEM_WR_ERR_CH2_M ((RMT_APB_MEM_WR_ERR_CH2_V)<<(RMT_APB_MEM_WR_ERR_CH2_S)) +#define RMT_APB_MEM_WR_ERR_CH2_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH2_S 30 +/* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The memory empty status bit for channel2. in acyclic mode, + this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ +#define RMT_MEM_EMPTY_CH2 (BIT(29)) +#define RMT_MEM_EMPTY_CH2_M ((RMT_MEM_EMPTY_CH2_V)<<(RMT_MEM_EMPTY_CH2_S)) +#define RMT_MEM_EMPTY_CH2_V 0x1 +#define RMT_MEM_EMPTY_CH2_S 29 +/* RMT_MEM_FULL_CH2 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The memory full status bit for channel2 turns to high level + when mem_waddr_ex is greater than or equal to the configuration range.*/ +#define RMT_MEM_FULL_CH2 (BIT(28)) +#define RMT_MEM_FULL_CH2_M ((RMT_MEM_FULL_CH2_V)<<(RMT_MEM_FULL_CH2_S)) +#define RMT_MEM_FULL_CH2_V 0x1 +#define RMT_MEM_FULL_CH2_S 28 +/* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: When channel2 is configured for receive mode, this bit will turn to high level + if rmt_mem_owner register is not set to 1.*/ +#define RMT_MEM_OWNER_ERR_CH2 (BIT(27)) +#define RMT_MEM_OWNER_ERR_CH2_M ((RMT_MEM_OWNER_ERR_CH2_V)<<(RMT_MEM_OWNER_ERR_CH2_S)) +#define RMT_MEM_OWNER_ERR_CH2_V 0x1 +#define RMT_MEM_OWNER_ERR_CH2_S 27 +/* RMT_STATE_CH2 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The channel2 state machine status register. +3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ +#define RMT_STATE_CH2 0x07000000 +#define RMT_STATE_CH2_M ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S)) +#define RMT_STATE_CH2_V 0x7 +#define RMT_STATE_CH2_S 24 +/* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ +/*description: The current memory write address of channel2.*/ +#define RMT_MEM_RADDR_EX_CH2 0x003ff000 +#define RMT_MEM_RADDR_EX_CH2_M ((RMT_MEM_RADDR_EX_CH2_V)<<(RMT_MEM_RADDR_EX_CH2_S)) +#define RMT_MEM_RADDR_EX_CH2_V 0x3ff +#define RMT_MEM_RADDR_EX_CH2_S 12 +/* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The current memory read address of channel2.*/ +#define RMT_MEM_WADDR_EX_CH2 0x000003ff +#define RMT_MEM_WADDR_EX_CH2_M ((RMT_MEM_WADDR_EX_CH2_V)<<(RMT_MEM_WADDR_EX_CH2_S)) +#define RMT_MEM_WADDR_EX_CH2_V 0x3ff +#define RMT_MEM_WADDR_EX_CH2_S 0 + +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c) +/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel3*/ +#define RMT_STATUS_CH3 0xFFFFFFFF +#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S)) +#define RMT_STATUS_CH3_V 0xFFFFFFFF +#define RMT_STATUS_CH3_S 0 +/* RMT_APB_MEM_RD_ERR_CH3 : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The apb read memory status bit for channel3 turns to + high level when the apb read address exceeds the configuration range.*/ +#define RMT_APB_MEM_RD_ERR_CH3 (BIT(31)) +#define RMT_APB_MEM_RD_ERR_CH3_M ((RMT_APB_MEM_RD_ERR_CH3_V)<<(RMT_APB_MEM_RD_ERR_CH3_S)) +#define RMT_APB_MEM_RD_ERR_CH3_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH3_S 31 +/* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The apb write memory status bit for channel3 turns to + high level when the apb write address exceeds the configuration range.*/ +#define RMT_APB_MEM_WR_ERR_CH3 (BIT(30)) +#define RMT_APB_MEM_WR_ERR_CH3_M ((RMT_APB_MEM_WR_ERR_CH3_V)<<(RMT_APB_MEM_WR_ERR_CH3_S)) +#define RMT_APB_MEM_WR_ERR_CH3_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH3_S 30 +/* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The memory empty status bit for channel3. in acyclic mode, + this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ +#define RMT_MEM_EMPTY_CH3 (BIT(29)) +#define RMT_MEM_EMPTY_CH3_M ((RMT_MEM_EMPTY_CH3_V)<<(RMT_MEM_EMPTY_CH3_S)) +#define RMT_MEM_EMPTY_CH3_V 0x1 +#define RMT_MEM_EMPTY_CH3_S 29 +/* RMT_MEM_FULL_CH3 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The memory full status bit for channel3 turns to high level + when mem_waddr_ex is greater than or equal to the configuration range.*/ +#define RMT_MEM_FULL_CH3 (BIT(28)) +#define RMT_MEM_FULL_CH3_M ((RMT_MEM_FULL_CH3_V)<<(RMT_MEM_FULL_CH3_S)) +#define RMT_MEM_FULL_CH3_V 0x1 +#define RMT_MEM_FULL_CH3_S 28 +/* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: When channel3 is configured for receive mode, this bit will turn to high level + if rmt_mem_owner register is not set to 1.*/ +#define RMT_MEM_OWNER_ERR_CH3 (BIT(27)) +#define RMT_MEM_OWNER_ERR_CH3_M ((RMT_MEM_OWNER_ERR_CH3_V)<<(RMT_MEM_OWNER_ERR_CH3_S)) +#define RMT_MEM_OWNER_ERR_CH3_V 0x1 +#define RMT_MEM_OWNER_ERR_CH3_S 27 +/* RMT_STATE_CH3 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The channel3 state machine status register. +3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ +#define RMT_STATE_CH3 0x07000000 +#define RMT_STATE_CH3_M ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S)) +#define RMT_STATE_CH3_V 0x7 +#define RMT_STATE_CH3_S 24 +/* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ +/*description: The current memory write address of channel3.*/ +#define RMT_MEM_RADDR_EX_CH3 0x003ff000 +#define RMT_MEM_RADDR_EX_CH3_M ((RMT_MEM_RADDR_EX_CH3_V)<<(RMT_MEM_RADDR_EX_CH3_S)) +#define RMT_MEM_RADDR_EX_CH3_V 0x3ff +#define RMT_MEM_RADDR_EX_CH3_S 12 +/* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The current memory read address of channel3.*/ +#define RMT_MEM_WADDR_EX_CH3 0x000003ff +#define RMT_MEM_WADDR_EX_CH3_M ((RMT_MEM_WADDR_EX_CH3_V)<<(RMT_MEM_WADDR_EX_CH3_S)) +#define RMT_MEM_WADDR_EX_CH3_V 0x3ff +#define RMT_MEM_WADDR_EX_CH3_S 0 + +#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070) +/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel4*/ +#define RMT_STATUS_CH4 0xFFFFFFFF +#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S)) +#define RMT_STATUS_CH4_V 0xFFFFFFFF +#define RMT_STATUS_CH4_S 0 +/* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The apb read memory status bit for channel4 turns to + high level when the apb read address exceeds the configuration range.*/ +#define RMT_APB_MEM_RD_ERR_CH4 (BIT(31)) +#define RMT_APB_MEM_RD_ERR_CH4_M ((RMT_APB_MEM_RD_ERR_CH4_V)<<(RMT_APB_MEM_RD_ERR_CH4_S)) +#define RMT_APB_MEM_RD_ERR_CH4_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH4_S 31 +/* RMT_APB_MEM_WR_ERR_CH4 : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The apb write memory status bit for channel4 turns to + high level when the apb write address exceeds the configuration range.*/ +#define RMT_APB_MEM_WR_ERR_CH4 (BIT(30)) +#define RMT_APB_MEM_WR_ERR_CH4_M ((RMT_APB_MEM_WR_ERR_CH4_V)<<(RMT_APB_MEM_WR_ERR_CH4_S)) +#define RMT_APB_MEM_WR_ERR_CH4_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH4_S 30 +/* RMT_MEM_EMPTY_CH4 : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The memory empty status bit for channel4. in acyclic mode, + this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ +#define RMT_MEM_EMPTY_CH4 (BIT(29)) +#define RMT_MEM_EMPTY_CH4_M ((RMT_MEM_EMPTY_CH4_V)<<(RMT_MEM_EMPTY_CH4_S)) +#define RMT_MEM_EMPTY_CH4_V 0x1 +#define RMT_MEM_EMPTY_CH4_S 29 +/* RMT_MEM_FULL_CH4 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The memory full status bit for channel4 turns to high level + when mem_waddr_ex is greater than or equal to the configuration range.*/ +#define RMT_MEM_FULL_CH4 (BIT(28)) +#define RMT_MEM_FULL_CH4_M ((RMT_MEM_FULL_CH4_V)<<(RMT_MEM_FULL_CH4_S)) +#define RMT_MEM_FULL_CH4_V 0x1 +#define RMT_MEM_FULL_CH4_S 28 +/* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: When channel4 is configured for receive mode, this bit will turn to high level + if rmt_mem_owner register is not set to 1.*/ +#define RMT_MEM_OWNER_ERR_CH4 (BIT(27)) +#define RMT_MEM_OWNER_ERR_CH4_M ((RMT_MEM_OWNER_ERR_CH4_V)<<(RMT_MEM_OWNER_ERR_CH4_S)) +#define RMT_MEM_OWNER_ERR_CH4_V 0x1 +#define RMT_MEM_OWNER_ERR_CH4_S 27 +/* RMT_STATE_CH4 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The channel4 state machine status register. +3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ +#define RMT_STATE_CH4 0x07000000 +#define RMT_STATE_CH4_M ((RMT_STATE_CH4_V)<<(RMT_STATE_CH4_S)) +#define RMT_STATE_CH4_V 0x7 +#define RMT_STATE_CH4_S 24 +/* RMT_MEM_RADDR_EX_CH4 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ +/*description: The current memory write address of channel4.*/ +#define RMT_MEM_RADDR_EX_CH4 0x003ff000 +#define RMT_MEM_RADDR_EX_CH4_M ((RMT_MEM_RADDR_EX_CH4_V)<<(RMT_MEM_RADDR_EX_CH4_S)) +#define RMT_MEM_RADDR_EX_CH4_V 0x3ff +#define RMT_MEM_RADDR_EX_CH4_S 12 +/* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The current memory read address of channel4.*/ +#define RMT_MEM_WADDR_EX_CH4 0x000003ff +#define RMT_MEM_WADDR_EX_CH4_M ((RMT_MEM_WADDR_EX_CH4_V)<<(RMT_MEM_WADDR_EX_CH4_S)) +#define RMT_MEM_WADDR_EX_CH4_V 0x3ff +#define RMT_MEM_WADDR_EX_CH4_S 0 + +#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074) +/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel5*/ +#define RMT_STATUS_CH5 0xFFFFFFFF +#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S)) +#define RMT_STATUS_CH5_V 0xFFFFFFFF +#define RMT_STATUS_CH5_S 0 +/* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The apb read memory status bit for channel5 turns to + high level when the apb read address exceeds the configuration range.*/ +#define RMT_APB_MEM_RD_ERR_CH5 (BIT(31)) +#define RMT_APB_MEM_RD_ERR_CH5_M ((RMT_APB_MEM_RD_ERR_CH5_V)<<(RMT_APB_MEM_RD_ERR_CH5_S)) +#define RMT_APB_MEM_RD_ERR_CH5_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH5_S 31 +/* RMT_APB_MEM_WR_ERR_CH5 : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The apb write memory status bit for channel5 turns to + high level when the apb write address exceeds the configuration range.*/ +#define RMT_APB_MEM_WR_ERR_CH5 (BIT(30)) +#define RMT_APB_MEM_WR_ERR_CH5_M ((RMT_APB_MEM_WR_ERR_CH5_V)<<(RMT_APB_MEM_WR_ERR_CH5_S)) +#define RMT_APB_MEM_WR_ERR_CH5_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH5_S 30 +/* RMT_MEM_EMPTY_CH5 : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The memory empty status bit for channel5. in acyclic mode, + this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ +#define RMT_MEM_EMPTY_CH5 (BIT(29)) +#define RMT_MEM_EMPTY_CH5_M ((RMT_MEM_EMPTY_CH5_V)<<(RMT_MEM_EMPTY_CH5_S)) +#define RMT_MEM_EMPTY_CH5_V 0x1 +#define RMT_MEM_EMPTY_CH5_S 29 +/* RMT_MEM_FULL_CH5 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The memory full status bit for channel5 turns to high level + when mem_waddr_ex is greater than or equal to the configuration range.*/ +#define RMT_MEM_FULL_CH5 (BIT(28)) +#define RMT_MEM_FULL_CH5_M ((RMT_MEM_FULL_CH5_V)<<(RMT_MEM_FULL_CH5_S)) +#define RMT_MEM_FULL_CH5_V 0x1 +#define RMT_MEM_FULL_CH5_S 28 +/* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: When channel5 is configured for receive mode, this bit will turn to high level + if rmt_mem_owner register is not set to 1.*/ +#define RMT_MEM_OWNER_ERR_CH5 (BIT(27)) +#define RMT_MEM_OWNER_ERR_CH5_M ((RMT_MEM_OWNER_ERR_CH5_V)<<(RMT_MEM_OWNER_ERR_CH5_S)) +#define RMT_MEM_OWNER_ERR_CH5_V 0x1 +#define RMT_MEM_OWNER_ERR_CH5_S 27 +/* RMT_STATE_CH5 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The channel5 state machine status register. +3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ +#define RMT_STATE_CH5 0x07000000 +#define RMT_STATE_CH5_M ((RMT_STATE_CH5_V)<<(RMT_STATE_CH5_S)) +#define RMT_STATE_CH5_V 0x7 +#define RMT_STATE_CH5_S 24 +/* RMT_MEM_RADDR_EX_CH5 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ +/*description: The current memory write address of channel5.*/ +#define RMT_MEM_RADDR_EX_CH5 0x003ff000 +#define RMT_MEM_RADDR_EX_CH5_M ((RMT_MEM_RADDR_EX_CH5_V)<<(RMT_MEM_RADDR_EX_CH5_S)) +#define RMT_MEM_RADDR_EX_CH5_V 0x3ff +#define RMT_MEM_RADDR_EX_CH5_S 12 +/* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The current memory read address of channel5.*/ +#define RMT_MEM_WADDR_EX_CH5 0x000003ff +#define RMT_MEM_WADDR_EX_CH5_M ((RMT_MEM_WADDR_EX_CH5_V)<<(RMT_MEM_WADDR_EX_CH5_S)) +#define RMT_MEM_WADDR_EX_CH5_V 0x3ff +#define RMT_MEM_WADDR_EX_CH5_S 0 + +#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078) +/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel6*/ +#define RMT_STATUS_CH6 0xFFFFFFFF +#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S)) +#define RMT_STATUS_CH6_V 0xFFFFFFFF +#define RMT_STATUS_CH6_S 0 +/* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The apb read memory status bit for channel6 turns to + high level when the apb read address exceeds the configuration range.*/ +#define RMT_APB_MEM_RD_ERR_CH6 (BIT(31)) +#define RMT_APB_MEM_RD_ERR_CH6_M ((RMT_APB_MEM_RD_ERR_CH6_V)<<(RMT_APB_MEM_RD_ERR_CH6_S)) +#define RMT_APB_MEM_RD_ERR_CH6_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH6_S 31 +/* RMT_APB_MEM_WR_ERR_CH6 : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The apb write memory status bit for channel6 turns to + high level when the apb write address exceeds the configuration range.*/ +#define RMT_APB_MEM_WR_ERR_CH6 (BIT(30)) +#define RMT_APB_MEM_WR_ERR_CH6_M ((RMT_APB_MEM_WR_ERR_CH6_V)<<(RMT_APB_MEM_WR_ERR_CH6_S)) +#define RMT_APB_MEM_WR_ERR_CH6_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH6_S 30 +/* RMT_MEM_EMPTY_CH6 : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The memory empty status bit for channel6. in acyclic mode, + this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ +#define RMT_MEM_EMPTY_CH6 (BIT(29)) +#define RMT_MEM_EMPTY_CH6_M ((RMT_MEM_EMPTY_CH6_V)<<(RMT_MEM_EMPTY_CH6_S)) +#define RMT_MEM_EMPTY_CH6_V 0x1 +#define RMT_MEM_EMPTY_CH6_S 29 +/* RMT_MEM_FULL_CH6 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The memory full status bit for channel6 turns to high level + when mem_waddr_ex is greater than or equal to the configuration range.*/ +#define RMT_MEM_FULL_CH6 (BIT(28)) +#define RMT_MEM_FULL_CH6_M ((RMT_MEM_FULL_CH6_V)<<(RMT_MEM_FULL_CH6_S)) +#define RMT_MEM_FULL_CH6_V 0x1 +#define RMT_MEM_FULL_CH6_S 28 +/* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: When channel6 is configured for receive mode, this bit will turn to high level + if rmt_mem_owner register is not set to 1.*/ +#define RMT_MEM_OWNER_ERR_CH6 (BIT(27)) +#define RMT_MEM_OWNER_ERR_CH6_M ((RMT_MEM_OWNER_ERR_CH6_V)<<(RMT_MEM_OWNER_ERR_CH6_S)) +#define RMT_MEM_OWNER_ERR_CH6_V 0x1 +#define RMT_MEM_OWNER_ERR_CH6_S 27 +/* RMT_STATE_CH6 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The channel6 state machine status register. +3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ +#define RMT_STATE_CH6 0x07000000 +#define RMT_STATE_CH6_M ((RMT_STATE_CH6_V)<<(RMT_STATE_CH6_S)) +#define RMT_STATE_CH6_V 0x7 +#define RMT_STATE_CH6_S 24 +/* RMT_MEM_RADDR_EX_CH6 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ +/*description: The current memory write address of channel6.*/ +#define RMT_MEM_RADDR_EX_CH6 0x003ff000 +#define RMT_MEM_RADDR_EX_CH6_M ((RMT_MEM_RADDR_EX_CH6_V)<<(RMT_MEM_RADDR_EX_CH6_S)) +#define RMT_MEM_RADDR_EX_CH6_V 0x3ff +#define RMT_MEM_RADDR_EX_CH6_S 12 +/* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The current memory read address of channel6.*/ +#define RMT_MEM_WADDR_EX_CH6 0x000003ff +#define RMT_MEM_WADDR_EX_CH6_M ((RMT_MEM_WADDR_EX_CH6_V)<<(RMT_MEM_WADDR_EX_CH6_S)) +#define RMT_MEM_WADDR_EX_CH6_V 0x3ff +#define RMT_MEM_WADDR_EX_CH6_S 0 + +#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c) +/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel7*/ +#define RMT_STATUS_CH7 0xFFFFFFFF +#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S)) +#define RMT_STATUS_CH7_V 0xFFFFFFFF +#define RMT_STATUS_CH7_S 0 +/* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The apb read memory status bit for channel7 turns to + high level when the apb read address exceeds the configuration range.*/ +#define RMT_APB_MEM_RD_ERR_CH7 (BIT(31)) +#define RMT_APB_MEM_RD_ERR_CH7_M ((RMT_APB_MEM_RD_ERR_CH7_V)<<(RMT_APB_MEM_RD_ERR_CH7_S)) +#define RMT_APB_MEM_RD_ERR_CH7_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH7_S 31 +/* RMT_APB_MEM_WR_ERR_CH7 : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The apb write memory status bit for channel7 turns to + high level when the apb write address exceeds the configuration range.*/ +#define RMT_APB_MEM_WR_ERR_CH7 (BIT(30)) +#define RMT_APB_MEM_WR_ERR_CH7_M ((RMT_APB_MEM_WR_ERR_CH7_V)<<(RMT_APB_MEM_WR_ERR_CH7_S)) +#define RMT_APB_MEM_WR_ERR_CH7_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH7_S 30 +/* RMT_MEM_EMPTY_CH7 : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The memory empty status bit for channel7. in acyclic mode, + this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ +#define RMT_MEM_EMPTY_CH7 (BIT(29)) +#define RMT_MEM_EMPTY_CH7_M ((RMT_MEM_EMPTY_CH7_V)<<(RMT_MEM_EMPTY_CH7_S)) +#define RMT_MEM_EMPTY_CH7_V 0x1 +#define RMT_MEM_EMPTY_CH7_S 29 +/* RMT_MEM_FULL_CH7 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The memory full status bit for channel7 turns to high level + when mem_waddr_ex is greater than or equal to the configuration range.*/ +#define RMT_MEM_FULL_CH7 (BIT(28)) +#define RMT_MEM_FULL_CH7_M ((RMT_MEM_FULL_CH7_V)<<(RMT_MEM_FULL_CH7_S)) +#define RMT_MEM_FULL_CH7_V 0x1 +#define RMT_MEM_FULL_CH7_S 28 +/* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: When channel7 is configured for receive mode, this bit will turn to high level + if rmt_mem_owner register is not set to 1.*/ +#define RMT_MEM_OWNER_ERR_CH7 (BIT(27)) +#define RMT_MEM_OWNER_ERR_CH7_M ((RMT_MEM_OWNER_ERR_CH7_V)<<(RMT_MEM_OWNER_ERR_CH7_S)) +#define RMT_MEM_OWNER_ERR_CH7_V 0x1 +#define RMT_MEM_OWNER_ERR_CH7_S 27 +/* RMT_STATE_CH7 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The channel7 state machine status register. +3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ +#define RMT_STATE_CH7 0x07000000 +#define RMT_STATE_CH7_M ((RMT_STATE_CH7_V)<<(RMT_STATE_CH7_S)) +#define RMT_STATE_CH7_V 0x7 +#define RMT_STATE_CH7_S 24 +/* RMT_MEM_RADDR_EX_CH7 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ +/*description: The current memory write address of channel7.*/ +#define RMT_MEM_RADDR_EX_CH7 0x003ff000 +#define RMT_MEM_RADDR_EX_CH7_M ((RMT_MEM_RADDR_EX_CH7_V)<<(RMT_MEM_RADDR_EX_CH7_S)) +#define RMT_MEM_RADDR_EX_CH7_V 0x3ff +#define RMT_MEM_RADDR_EX_CH7_S 12 +/* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The current memory read address of channel7.*/ +#define RMT_MEM_WADDR_EX_CH7 0x000003ff +#define RMT_MEM_WADDR_EX_CH7_M ((RMT_MEM_WADDR_EX_CH7_V)<<(RMT_MEM_WADDR_EX_CH7_S)) +#define RMT_MEM_WADDR_EX_CH7_V 0x3ff +#define RMT_MEM_WADDR_EX_CH7_S 0 + +#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080) +/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel0 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S)) +#define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH0_S 0 + +#define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084) +/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel1 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S)) +#define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH1_S 0 + +#define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088) +/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel2 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S)) +#define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH2_S 0 + +#define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c) +/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel3 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S)) +#define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH3_S 0 + +#define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090) +/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel4 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S)) +#define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH4_S 0 + +#define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094) +/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel5 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S)) +#define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH5_S 0 + +#define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098) +/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel6 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S)) +#define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH6_S 0 + +#define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c) +/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel7 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S)) +#define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH7_S 0 + +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0) +/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel7 turns to high level when + transmitter in channle 7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24 +/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + channle 7 detects some errors.*/ +#define RMT_CH7_ERR_INT_RAW (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_V 0x1 +#define RMT_CH7_ERR_INT_RAW_S 23 +/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + the receive process is done.*/ +#define RMT_CH7_RX_END_INT_RAW (BIT(22)) +#define RMT_CH7_RX_END_INT_RAW_M (BIT(22)) +#define RMT_CH7_RX_END_INT_RAW_V 0x1 +#define RMT_CH7_RX_END_INT_RAW_S 22 +/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + the transmit process is done.*/ +#define RMT_CH7_TX_END_INT_RAW (BIT(21)) +#define RMT_CH7_TX_END_INT_RAW_M (BIT(21)) +#define RMT_CH7_TX_END_INT_RAW_V 0x1 +#define RMT_CH7_TX_END_INT_RAW_S 21 +/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + channle 6 detects some errors.*/ +#define RMT_CH6_ERR_INT_RAW (BIT(20)) +#define RMT_CH6_ERR_INT_RAW_M (BIT(20)) +#define RMT_CH6_ERR_INT_RAW_V 0x1 +#define RMT_CH6_ERR_INT_RAW_S 20 +/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + the receive process is done.*/ +#define RMT_CH6_RX_END_INT_RAW (BIT(19)) +#define RMT_CH6_RX_END_INT_RAW_M (BIT(19)) +#define RMT_CH6_RX_END_INT_RAW_V 0x1 +#define RMT_CH6_RX_END_INT_RAW_S 19 +/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + the transmit process is done.*/ +#define RMT_CH6_TX_END_INT_RAW (BIT(18)) +#define RMT_CH6_TX_END_INT_RAW_M (BIT(18)) +#define RMT_CH6_TX_END_INT_RAW_V 0x1 +#define RMT_CH6_TX_END_INT_RAW_S 18 +/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + channle 5 detects some errors.*/ +#define RMT_CH5_ERR_INT_RAW (BIT(17)) +#define RMT_CH5_ERR_INT_RAW_M (BIT(17)) +#define RMT_CH5_ERR_INT_RAW_V 0x1 +#define RMT_CH5_ERR_INT_RAW_S 17 +/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + the receive process is done.*/ +#define RMT_CH5_RX_END_INT_RAW (BIT(16)) +#define RMT_CH5_RX_END_INT_RAW_M (BIT(16)) +#define RMT_CH5_RX_END_INT_RAW_V 0x1 +#define RMT_CH5_RX_END_INT_RAW_S 16 +/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + the transmit process is done.*/ +#define RMT_CH5_TX_END_INT_RAW (BIT(15)) +#define RMT_CH5_TX_END_INT_RAW_M (BIT(15)) +#define RMT_CH5_TX_END_INT_RAW_V 0x1 +#define RMT_CH5_TX_END_INT_RAW_S 15 +/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + channle 4 detects some errors.*/ +#define RMT_CH4_ERR_INT_RAW (BIT(14)) +#define RMT_CH4_ERR_INT_RAW_M (BIT(14)) +#define RMT_CH4_ERR_INT_RAW_V 0x1 +#define RMT_CH4_ERR_INT_RAW_S 14 +/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + the receive process is done.*/ +#define RMT_CH4_RX_END_INT_RAW (BIT(13)) +#define RMT_CH4_RX_END_INT_RAW_M (BIT(13)) +#define RMT_CH4_RX_END_INT_RAW_V 0x1 +#define RMT_CH4_RX_END_INT_RAW_S 13 +/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + the transmit process is done.*/ +#define RMT_CH4_TX_END_INT_RAW (BIT(12)) +#define RMT_CH4_TX_END_INT_RAW_M (BIT(12)) +#define RMT_CH4_TX_END_INT_RAW_V 0x1 +#define RMT_CH4_TX_END_INT_RAW_S 12 +/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + channle 3 detects some errors.*/ +#define RMT_CH3_ERR_INT_RAW (BIT(11)) +#define RMT_CH3_ERR_INT_RAW_M (BIT(11)) +#define RMT_CH3_ERR_INT_RAW_V 0x1 +#define RMT_CH3_ERR_INT_RAW_S 11 +/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + the receive process is done.*/ +#define RMT_CH3_RX_END_INT_RAW (BIT(10)) +#define RMT_CH3_RX_END_INT_RAW_M (BIT(10)) +#define RMT_CH3_RX_END_INT_RAW_V 0x1 +#define RMT_CH3_RX_END_INT_RAW_S 10 +/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + the transmit process is done.*/ +#define RMT_CH3_TX_END_INT_RAW (BIT(9)) +#define RMT_CH3_TX_END_INT_RAW_M (BIT(9)) +#define RMT_CH3_TX_END_INT_RAW_V 0x1 +#define RMT_CH3_TX_END_INT_RAW_S 9 +/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + channle 2 detects some errors.*/ +#define RMT_CH2_ERR_INT_RAW (BIT(8)) +#define RMT_CH2_ERR_INT_RAW_M (BIT(8)) +#define RMT_CH2_ERR_INT_RAW_V 0x1 +#define RMT_CH2_ERR_INT_RAW_S 8 +/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + the receive process is done.*/ +#define RMT_CH2_RX_END_INT_RAW (BIT(7)) +#define RMT_CH2_RX_END_INT_RAW_M (BIT(7)) +#define RMT_CH2_RX_END_INT_RAW_V 0x1 +#define RMT_CH2_RX_END_INT_RAW_S 7 +/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + the transmit process is done.*/ +#define RMT_CH2_TX_END_INT_RAW (BIT(6)) +#define RMT_CH2_TX_END_INT_RAW_M (BIT(6)) +#define RMT_CH2_TX_END_INT_RAW_V 0x1 +#define RMT_CH2_TX_END_INT_RAW_S 6 +/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + channle 1 detects some errors.*/ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_V 0x1 +#define RMT_CH1_ERR_INT_RAW_S 5 +/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + the receive process is done.*/ +#define RMT_CH1_RX_END_INT_RAW (BIT(4)) +#define RMT_CH1_RX_END_INT_RAW_M (BIT(4)) +#define RMT_CH1_RX_END_INT_RAW_V 0x1 +#define RMT_CH1_RX_END_INT_RAW_S 4 +/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + the transmit process is done.*/ +#define RMT_CH1_TX_END_INT_RAW (BIT(3)) +#define RMT_CH1_TX_END_INT_RAW_M (BIT(3)) +#define RMT_CH1_TX_END_INT_RAW_V 0x1 +#define RMT_CH1_TX_END_INT_RAW_S 3 +/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + channle 0 detects some errors.*/ +#define RMT_CH0_ERR_INT_RAW (BIT(2)) +#define RMT_CH0_ERR_INT_RAW_M (BIT(2)) +#define RMT_CH0_ERR_INT_RAW_V 0x1 +#define RMT_CH0_ERR_INT_RAW_S 2 +/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + the receive process is done.*/ +#define RMT_CH0_RX_END_INT_RAW (BIT(1)) +#define RMT_CH0_RX_END_INT_RAW_M (BIT(1)) +#define RMT_CH0_RX_END_INT_RAW_V 0x1 +#define RMT_CH0_RX_END_INT_RAW_S 1 +/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + the transmit process is done.*/ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_V 0x1 +#define RMT_CH0_TX_END_INT_RAW_S 0 + +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4) +/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw + when mt_ch7_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_ST_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw + when mt_ch6_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_ST_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw + when mt_ch5_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_ST_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw + when mt_ch4_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_ST_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw + when mt_ch3_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ST_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw + when mt_ch2_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ST_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw + when mt_ch1_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw + when mt_ch0_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 24 +/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw + when rmt_ch7_err_int_ena is set to 1.*/ +#define RMT_CH7_ERR_INT_ST (BIT(23)) +#define RMT_CH7_ERR_INT_ST_M (BIT(23)) +#define RMT_CH7_ERR_INT_ST_V 0x1 +#define RMT_CH7_ERR_INT_ST_S 23 +/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw + when rmt_ch7_rx_end_int_ena is set to 1.*/ +#define RMT_CH7_RX_END_INT_ST (BIT(22)) +#define RMT_CH7_RX_END_INT_ST_M (BIT(22)) +#define RMT_CH7_RX_END_INT_ST_V 0x1 +#define RMT_CH7_RX_END_INT_ST_S 22 +/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw + when mt_ch7_tx_end_int_ena is set to 1.*/ +#define RMT_CH7_TX_END_INT_ST (BIT(21)) +#define RMT_CH7_TX_END_INT_ST_M (BIT(21)) +#define RMT_CH7_TX_END_INT_ST_V 0x1 +#define RMT_CH7_TX_END_INT_ST_S 21 +/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw + when rmt_ch6_err_int_ena is set to 1.*/ +#define RMT_CH6_ERR_INT_ST (BIT(20)) +#define RMT_CH6_ERR_INT_ST_M (BIT(20)) +#define RMT_CH6_ERR_INT_ST_V 0x1 +#define RMT_CH6_ERR_INT_ST_S 20 +/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw + when rmt_ch6_rx_end_int_ena is set to 1.*/ +#define RMT_CH6_RX_END_INT_ST (BIT(19)) +#define RMT_CH6_RX_END_INT_ST_M (BIT(19)) +#define RMT_CH6_RX_END_INT_ST_V 0x1 +#define RMT_CH6_RX_END_INT_ST_S 19 +/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw + when mt_ch6_tx_end_int_ena is set to 1.*/ +#define RMT_CH6_TX_END_INT_ST (BIT(18)) +#define RMT_CH6_TX_END_INT_ST_M (BIT(18)) +#define RMT_CH6_TX_END_INT_ST_V 0x1 +#define RMT_CH6_TX_END_INT_ST_S 18 +/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw + when rmt_ch5_err_int_ena is set to 1.*/ +#define RMT_CH5_ERR_INT_ST (BIT(17)) +#define RMT_CH5_ERR_INT_ST_M (BIT(17)) +#define RMT_CH5_ERR_INT_ST_V 0x1 +#define RMT_CH5_ERR_INT_ST_S 17 +/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw + when rmt_ch5_rx_end_int_ena is set to 1.*/ +#define RMT_CH5_RX_END_INT_ST (BIT(16)) +#define RMT_CH5_RX_END_INT_ST_M (BIT(16)) +#define RMT_CH5_RX_END_INT_ST_V 0x1 +#define RMT_CH5_RX_END_INT_ST_S 16 +/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw + when mt_ch5_tx_end_int_ena is set to 1.*/ +#define RMT_CH5_TX_END_INT_ST (BIT(15)) +#define RMT_CH5_TX_END_INT_ST_M (BIT(15)) +#define RMT_CH5_TX_END_INT_ST_V 0x1 +#define RMT_CH5_TX_END_INT_ST_S 15 +/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw + when rmt_ch4_err_int_ena is set to 1.*/ +#define RMT_CH4_ERR_INT_ST (BIT(14)) +#define RMT_CH4_ERR_INT_ST_M (BIT(14)) +#define RMT_CH4_ERR_INT_ST_V 0x1 +#define RMT_CH4_ERR_INT_ST_S 14 +/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw + when rmt_ch4_rx_end_int_ena is set to 1.*/ +#define RMT_CH4_RX_END_INT_ST (BIT(13)) +#define RMT_CH4_RX_END_INT_ST_M (BIT(13)) +#define RMT_CH4_RX_END_INT_ST_V 0x1 +#define RMT_CH4_RX_END_INT_ST_S 13 +/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw + when mt_ch4_tx_end_int_ena is set to 1.*/ +#define RMT_CH4_TX_END_INT_ST (BIT(12)) +#define RMT_CH4_TX_END_INT_ST_M (BIT(12)) +#define RMT_CH4_TX_END_INT_ST_V 0x1 +#define RMT_CH4_TX_END_INT_ST_S 12 +/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw + when rmt_ch3_err_int_ena is set to 1.*/ +#define RMT_CH3_ERR_INT_ST (BIT(11)) +#define RMT_CH3_ERR_INT_ST_M (BIT(11)) +#define RMT_CH3_ERR_INT_ST_V 0x1 +#define RMT_CH3_ERR_INT_ST_S 11 +/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw + when rmt_ch3_rx_end_int_ena is set to 1.*/ +#define RMT_CH3_RX_END_INT_ST (BIT(10)) +#define RMT_CH3_RX_END_INT_ST_M (BIT(10)) +#define RMT_CH3_RX_END_INT_ST_V 0x1 +#define RMT_CH3_RX_END_INT_ST_S 10 +/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw + when mt_ch3_tx_end_int_ena is set to 1.*/ +#define RMT_CH3_TX_END_INT_ST (BIT(9)) +#define RMT_CH3_TX_END_INT_ST_M (BIT(9)) +#define RMT_CH3_TX_END_INT_ST_V 0x1 +#define RMT_CH3_TX_END_INT_ST_S 9 +/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw + when rmt_ch2_err_int_ena is set to 1.*/ +#define RMT_CH2_ERR_INT_ST (BIT(8)) +#define RMT_CH2_ERR_INT_ST_M (BIT(8)) +#define RMT_CH2_ERR_INT_ST_V 0x1 +#define RMT_CH2_ERR_INT_ST_S 8 +/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw + when rmt_ch2_rx_end_int_ena is set to 1.*/ +#define RMT_CH2_RX_END_INT_ST (BIT(7)) +#define RMT_CH2_RX_END_INT_ST_M (BIT(7)) +#define RMT_CH2_RX_END_INT_ST_V 0x1 +#define RMT_CH2_RX_END_INT_ST_S 7 +/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw + when mt_ch2_tx_end_int_ena is set to 1.*/ +#define RMT_CH2_TX_END_INT_ST (BIT(6)) +#define RMT_CH2_TX_END_INT_ST_M (BIT(6)) +#define RMT_CH2_TX_END_INT_ST_V 0x1 +#define RMT_CH2_TX_END_INT_ST_S 6 +/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw + when rmt_ch1_err_int_ena is set to 1.*/ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (BIT(5)) +#define RMT_CH1_ERR_INT_ST_V 0x1 +#define RMT_CH1_ERR_INT_ST_S 5 +/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw + when rmt_ch1_rx_end_int_ena is set to 1.*/ +#define RMT_CH1_RX_END_INT_ST (BIT(4)) +#define RMT_CH1_RX_END_INT_ST_M (BIT(4)) +#define RMT_CH1_RX_END_INT_ST_V 0x1 +#define RMT_CH1_RX_END_INT_ST_S 4 +/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw + when mt_ch1_tx_end_int_ena is set to 1.*/ +#define RMT_CH1_TX_END_INT_ST (BIT(3)) +#define RMT_CH1_TX_END_INT_ST_M (BIT(3)) +#define RMT_CH1_TX_END_INT_ST_V 0x1 +#define RMT_CH1_TX_END_INT_ST_S 3 +/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw + when rmt_ch0_err_int_ena is set to 0.*/ +#define RMT_CH0_ERR_INT_ST (BIT(2)) +#define RMT_CH0_ERR_INT_ST_M (BIT(2)) +#define RMT_CH0_ERR_INT_ST_V 0x1 +#define RMT_CH0_ERR_INT_ST_S 2 +/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw + when rmt_ch0_rx_end_int_ena is set to 0.*/ +#define RMT_CH0_RX_END_INT_ST (BIT(1)) +#define RMT_CH0_RX_END_INT_ST_M (BIT(1)) +#define RMT_CH0_RX_END_INT_ST_V 0x1 +#define RMT_CH0_RX_END_INT_ST_S 1 +/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw + when mt_ch0_tx_end_int_ena is set to 0.*/ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_V 0x1 +#define RMT_CH0_TX_END_INT_ST_S 0 + +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8) +/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ +#define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ +#define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ +#define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ +#define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ +#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ +#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24 +/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_err_int_st.*/ +#define RMT_CH7_ERR_INT_ENA (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_V 0x1 +#define RMT_CH7_ERR_INT_ENA_S 23 +/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/ +#define RMT_CH7_RX_END_INT_ENA (BIT(22)) +#define RMT_CH7_RX_END_INT_ENA_M (BIT(22)) +#define RMT_CH7_RX_END_INT_ENA_V 0x1 +#define RMT_CH7_RX_END_INT_ENA_S 22 +/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/ +#define RMT_CH7_TX_END_INT_ENA (BIT(21)) +#define RMT_CH7_TX_END_INT_ENA_M (BIT(21)) +#define RMT_CH7_TX_END_INT_ENA_V 0x1 +#define RMT_CH7_TX_END_INT_ENA_S 21 +/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_err_int_st.*/ +#define RMT_CH6_ERR_INT_ENA (BIT(20)) +#define RMT_CH6_ERR_INT_ENA_M (BIT(20)) +#define RMT_CH6_ERR_INT_ENA_V 0x1 +#define RMT_CH6_ERR_INT_ENA_S 20 +/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/ +#define RMT_CH6_RX_END_INT_ENA (BIT(19)) +#define RMT_CH6_RX_END_INT_ENA_M (BIT(19)) +#define RMT_CH6_RX_END_INT_ENA_V 0x1 +#define RMT_CH6_RX_END_INT_ENA_S 19 +/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/ +#define RMT_CH6_TX_END_INT_ENA (BIT(18)) +#define RMT_CH6_TX_END_INT_ENA_M (BIT(18)) +#define RMT_CH6_TX_END_INT_ENA_V 0x1 +#define RMT_CH6_TX_END_INT_ENA_S 18 +/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_err_int_st.*/ +#define RMT_CH5_ERR_INT_ENA (BIT(17)) +#define RMT_CH5_ERR_INT_ENA_M (BIT(17)) +#define RMT_CH5_ERR_INT_ENA_V 0x1 +#define RMT_CH5_ERR_INT_ENA_S 17 +/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/ +#define RMT_CH5_RX_END_INT_ENA (BIT(16)) +#define RMT_CH5_RX_END_INT_ENA_M (BIT(16)) +#define RMT_CH5_RX_END_INT_ENA_V 0x1 +#define RMT_CH5_RX_END_INT_ENA_S 16 +/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/ +#define RMT_CH5_TX_END_INT_ENA (BIT(15)) +#define RMT_CH5_TX_END_INT_ENA_M (BIT(15)) +#define RMT_CH5_TX_END_INT_ENA_V 0x1 +#define RMT_CH5_TX_END_INT_ENA_S 15 +/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_err_int_st.*/ +#define RMT_CH4_ERR_INT_ENA (BIT(14)) +#define RMT_CH4_ERR_INT_ENA_M (BIT(14)) +#define RMT_CH4_ERR_INT_ENA_V 0x1 +#define RMT_CH4_ERR_INT_ENA_S 14 +/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/ +#define RMT_CH4_RX_END_INT_ENA (BIT(13)) +#define RMT_CH4_RX_END_INT_ENA_M (BIT(13)) +#define RMT_CH4_RX_END_INT_ENA_V 0x1 +#define RMT_CH4_RX_END_INT_ENA_S 13 +/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/ +#define RMT_CH4_TX_END_INT_ENA (BIT(12)) +#define RMT_CH4_TX_END_INT_ENA_M (BIT(12)) +#define RMT_CH4_TX_END_INT_ENA_V 0x1 +#define RMT_CH4_TX_END_INT_ENA_S 12 +/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_err_int_st.*/ +#define RMT_CH3_ERR_INT_ENA (BIT(11)) +#define RMT_CH3_ERR_INT_ENA_M (BIT(11)) +#define RMT_CH3_ERR_INT_ENA_V 0x1 +#define RMT_CH3_ERR_INT_ENA_S 11 +/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/ +#define RMT_CH3_RX_END_INT_ENA (BIT(10)) +#define RMT_CH3_RX_END_INT_ENA_M (BIT(10)) +#define RMT_CH3_RX_END_INT_ENA_V 0x1 +#define RMT_CH3_RX_END_INT_ENA_S 10 +/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/ +#define RMT_CH3_TX_END_INT_ENA (BIT(9)) +#define RMT_CH3_TX_END_INT_ENA_M (BIT(9)) +#define RMT_CH3_TX_END_INT_ENA_V 0x1 +#define RMT_CH3_TX_END_INT_ENA_S 9 +/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_err_int_st.*/ +#define RMT_CH2_ERR_INT_ENA (BIT(8)) +#define RMT_CH2_ERR_INT_ENA_M (BIT(8)) +#define RMT_CH2_ERR_INT_ENA_V 0x1 +#define RMT_CH2_ERR_INT_ENA_S 8 +/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/ +#define RMT_CH2_RX_END_INT_ENA (BIT(7)) +#define RMT_CH2_RX_END_INT_ENA_M (BIT(7)) +#define RMT_CH2_RX_END_INT_ENA_V 0x1 +#define RMT_CH2_RX_END_INT_ENA_S 7 +/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/ +#define RMT_CH2_TX_END_INT_ENA (BIT(6)) +#define RMT_CH2_TX_END_INT_ENA_M (BIT(6)) +#define RMT_CH2_TX_END_INT_ENA_V 0x1 +#define RMT_CH2_TX_END_INT_ENA_S 6 +/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_err_int_st.*/ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_V 0x1 +#define RMT_CH1_ERR_INT_ENA_S 5 +/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/ +#define RMT_CH1_RX_END_INT_ENA (BIT(4)) +#define RMT_CH1_RX_END_INT_ENA_M (BIT(4)) +#define RMT_CH1_RX_END_INT_ENA_V 0x1 +#define RMT_CH1_RX_END_INT_ENA_S 4 +/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/ +#define RMT_CH1_TX_END_INT_ENA (BIT(3)) +#define RMT_CH1_TX_END_INT_ENA_M (BIT(3)) +#define RMT_CH1_TX_END_INT_ENA_V 0x1 +#define RMT_CH1_TX_END_INT_ENA_S 3 +/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_err_int_st.*/ +#define RMT_CH0_ERR_INT_ENA (BIT(2)) +#define RMT_CH0_ERR_INT_ENA_M (BIT(2)) +#define RMT_CH0_ERR_INT_ENA_V 0x1 +#define RMT_CH0_ERR_INT_ENA_S 2 +/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/ +#define RMT_CH0_RX_END_INT_ENA (BIT(1)) +#define RMT_CH0_RX_END_INT_ENA_M (BIT(1)) +#define RMT_CH0_RX_END_INT_ENA_V 0x1 +#define RMT_CH0_RX_END_INT_ENA_S 1 +/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_V 0x1 +#define RMT_CH0_TX_END_INT_ENA_S 0 + +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac) +/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24 +/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_err_int_raw.*/ +#define RMT_CH7_ERR_INT_CLR (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_V 0x1 +#define RMT_CH7_ERR_INT_CLR_S 23 +/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ +#define RMT_CH7_RX_END_INT_CLR (BIT(22)) +#define RMT_CH7_RX_END_INT_CLR_M (BIT(22)) +#define RMT_CH7_RX_END_INT_CLR_V 0x1 +#define RMT_CH7_RX_END_INT_CLR_S 22 +/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ +#define RMT_CH7_TX_END_INT_CLR (BIT(21)) +#define RMT_CH7_TX_END_INT_CLR_M (BIT(21)) +#define RMT_CH7_TX_END_INT_CLR_V 0x1 +#define RMT_CH7_TX_END_INT_CLR_S 21 +/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_err_int_raw.*/ +#define RMT_CH6_ERR_INT_CLR (BIT(20)) +#define RMT_CH6_ERR_INT_CLR_M (BIT(20)) +#define RMT_CH6_ERR_INT_CLR_V 0x1 +#define RMT_CH6_ERR_INT_CLR_S 20 +/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ +#define RMT_CH6_RX_END_INT_CLR (BIT(19)) +#define RMT_CH6_RX_END_INT_CLR_M (BIT(19)) +#define RMT_CH6_RX_END_INT_CLR_V 0x1 +#define RMT_CH6_RX_END_INT_CLR_S 19 +/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ +#define RMT_CH6_TX_END_INT_CLR (BIT(18)) +#define RMT_CH6_TX_END_INT_CLR_M (BIT(18)) +#define RMT_CH6_TX_END_INT_CLR_V 0x1 +#define RMT_CH6_TX_END_INT_CLR_S 18 +/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_err_int_raw.*/ +#define RMT_CH5_ERR_INT_CLR (BIT(17)) +#define RMT_CH5_ERR_INT_CLR_M (BIT(17)) +#define RMT_CH5_ERR_INT_CLR_V 0x1 +#define RMT_CH5_ERR_INT_CLR_S 17 +/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ +#define RMT_CH5_RX_END_INT_CLR (BIT(16)) +#define RMT_CH5_RX_END_INT_CLR_M (BIT(16)) +#define RMT_CH5_RX_END_INT_CLR_V 0x1 +#define RMT_CH5_RX_END_INT_CLR_S 16 +/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ +#define RMT_CH5_TX_END_INT_CLR (BIT(15)) +#define RMT_CH5_TX_END_INT_CLR_M (BIT(15)) +#define RMT_CH5_TX_END_INT_CLR_V 0x1 +#define RMT_CH5_TX_END_INT_CLR_S 15 +/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_err_int_raw.*/ +#define RMT_CH4_ERR_INT_CLR (BIT(14)) +#define RMT_CH4_ERR_INT_CLR_M (BIT(14)) +#define RMT_CH4_ERR_INT_CLR_V 0x1 +#define RMT_CH4_ERR_INT_CLR_S 14 +/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ +#define RMT_CH4_RX_END_INT_CLR (BIT(13)) +#define RMT_CH4_RX_END_INT_CLR_M (BIT(13)) +#define RMT_CH4_RX_END_INT_CLR_V 0x1 +#define RMT_CH4_RX_END_INT_CLR_S 13 +/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ +#define RMT_CH4_TX_END_INT_CLR (BIT(12)) +#define RMT_CH4_TX_END_INT_CLR_M (BIT(12)) +#define RMT_CH4_TX_END_INT_CLR_V 0x1 +#define RMT_CH4_TX_END_INT_CLR_S 12 +/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_err_int_raw.*/ +#define RMT_CH3_ERR_INT_CLR (BIT(11)) +#define RMT_CH3_ERR_INT_CLR_M (BIT(11)) +#define RMT_CH3_ERR_INT_CLR_V 0x1 +#define RMT_CH3_ERR_INT_CLR_S 11 +/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ +#define RMT_CH3_RX_END_INT_CLR (BIT(10)) +#define RMT_CH3_RX_END_INT_CLR_M (BIT(10)) +#define RMT_CH3_RX_END_INT_CLR_V 0x1 +#define RMT_CH3_RX_END_INT_CLR_S 10 +/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ +#define RMT_CH3_TX_END_INT_CLR (BIT(9)) +#define RMT_CH3_TX_END_INT_CLR_M (BIT(9)) +#define RMT_CH3_TX_END_INT_CLR_V 0x1 +#define RMT_CH3_TX_END_INT_CLR_S 9 +/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_err_int_raw.*/ +#define RMT_CH2_ERR_INT_CLR (BIT(8)) +#define RMT_CH2_ERR_INT_CLR_M (BIT(8)) +#define RMT_CH2_ERR_INT_CLR_V 0x1 +#define RMT_CH2_ERR_INT_CLR_S 8 +/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ +#define RMT_CH2_RX_END_INT_CLR (BIT(7)) +#define RMT_CH2_RX_END_INT_CLR_M (BIT(7)) +#define RMT_CH2_RX_END_INT_CLR_V 0x1 +#define RMT_CH2_RX_END_INT_CLR_S 7 +/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ +#define RMT_CH2_TX_END_INT_CLR (BIT(6)) +#define RMT_CH2_TX_END_INT_CLR_M (BIT(6)) +#define RMT_CH2_TX_END_INT_CLR_V 0x1 +#define RMT_CH2_TX_END_INT_CLR_S 6 +/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_err_int_raw.*/ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_V 0x1 +#define RMT_CH1_ERR_INT_CLR_S 5 +/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ +#define RMT_CH1_RX_END_INT_CLR (BIT(4)) +#define RMT_CH1_RX_END_INT_CLR_M (BIT(4)) +#define RMT_CH1_RX_END_INT_CLR_V 0x1 +#define RMT_CH1_RX_END_INT_CLR_S 4 +/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ +#define RMT_CH1_TX_END_INT_CLR (BIT(3)) +#define RMT_CH1_TX_END_INT_CLR_M (BIT(3)) +#define RMT_CH1_TX_END_INT_CLR_V 0x1 +#define RMT_CH1_TX_END_INT_CLR_S 3 +/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_err_int_raw.*/ +#define RMT_CH0_ERR_INT_CLR (BIT(2)) +#define RMT_CH0_ERR_INT_CLR_M (BIT(2)) +#define RMT_CH0_ERR_INT_CLR_V 0x1 +#define RMT_CH0_ERR_INT_CLR_S 2 +/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ +#define RMT_CH0_RX_END_INT_CLR (BIT(1)) +#define RMT_CH0_RX_END_INT_CLR_M (BIT(1)) +#define RMT_CH0_RX_END_INT_CLR_V 0x1 +#define RMT_CH0_RX_END_INT_CLR_S 1 +/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_V 0x1 +#define RMT_CH0_TX_END_INT_CLR_S 0 + +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0) +/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel0.*/ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFF +#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) +#define RMT_CARRIER_HIGH_CH0_V 0xFFFF +#define RMT_CARRIER_HIGH_CH0_S 16 +/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel0.*/ +#define RMT_CARRIER_LOW_CH0 0x0000FFFF +#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) +#define RMT_CARRIER_LOW_CH0_V 0xFFFF +#define RMT_CARRIER_LOW_CH0_S 0 + +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4) +/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel1.*/ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFF +#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) +#define RMT_CARRIER_HIGH_CH1_V 0xFFFF +#define RMT_CARRIER_HIGH_CH1_S 16 +/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel1.*/ +#define RMT_CARRIER_LOW_CH1 0x0000FFFF +#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) +#define RMT_CARRIER_LOW_CH1_V 0xFFFF +#define RMT_CARRIER_LOW_CH1_S 0 + +#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8) +/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel2.*/ +#define RMT_CARRIER_HIGH_CH2 0x0000FFFF +#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S)) +#define RMT_CARRIER_HIGH_CH2_V 0xFFFF +#define RMT_CARRIER_HIGH_CH2_S 16 +/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel2.*/ +#define RMT_CARRIER_LOW_CH2 0x0000FFFF +#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S)) +#define RMT_CARRIER_LOW_CH2_V 0xFFFF +#define RMT_CARRIER_LOW_CH2_S 0 + +#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc) +/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel3.*/ +#define RMT_CARRIER_HIGH_CH3 0x0000FFFF +#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S)) +#define RMT_CARRIER_HIGH_CH3_V 0xFFFF +#define RMT_CARRIER_HIGH_CH3_S 16 +/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel3.*/ +#define RMT_CARRIER_LOW_CH3 0x0000FFFF +#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S)) +#define RMT_CARRIER_LOW_CH3_V 0xFFFF +#define RMT_CARRIER_LOW_CH3_S 0 + +#define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0) +/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel4.*/ +#define RMT_CARRIER_HIGH_CH4 0x0000FFFF +#define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S)) +#define RMT_CARRIER_HIGH_CH4_V 0xFFFF +#define RMT_CARRIER_HIGH_CH4_S 16 +/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel4.*/ +#define RMT_CARRIER_LOW_CH4 0x0000FFFF +#define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S)) +#define RMT_CARRIER_LOW_CH4_V 0xFFFF +#define RMT_CARRIER_LOW_CH4_S 0 + +#define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4) +/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel5.*/ +#define RMT_CARRIER_HIGH_CH5 0x0000FFFF +#define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S)) +#define RMT_CARRIER_HIGH_CH5_V 0xFFFF +#define RMT_CARRIER_HIGH_CH5_S 16 +/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel5.*/ +#define RMT_CARRIER_LOW_CH5 0x0000FFFF +#define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S)) +#define RMT_CARRIER_LOW_CH5_V 0xFFFF +#define RMT_CARRIER_LOW_CH5_S 0 + +#define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8) +/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel6.*/ +#define RMT_CARRIER_HIGH_CH6 0x0000FFFF +#define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S)) +#define RMT_CARRIER_HIGH_CH6_V 0xFFFF +#define RMT_CARRIER_HIGH_CH6_S 16 +/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel6.*/ +#define RMT_CARRIER_LOW_CH6 0x0000FFFF +#define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S)) +#define RMT_CARRIER_LOW_CH6_V 0xFFFF +#define RMT_CARRIER_LOW_CH6_S 0 + +#define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc) +/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel7.*/ +#define RMT_CARRIER_HIGH_CH7 0x0000FFFF +#define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S)) +#define RMT_CARRIER_HIGH_CH7_V 0xFFFF +#define RMT_CARRIER_HIGH_CH7_S 16 +/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel7.*/ +#define RMT_CARRIER_LOW_CH7 0x0000FFFF +#define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S)) +#define RMT_CARRIER_LOW_CH7_V 0xFFFF +#define RMT_CARRIER_LOW_CH7_S 0 + +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0) +/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH0 0x000001FF +#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) +#define RMT_TX_LIM_CH0_V 0x1FF +#define RMT_TX_LIM_CH0_S 0 + +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4) +/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH1 0x000001FF +#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) +#define RMT_TX_LIM_CH1_V 0x1FF +#define RMT_TX_LIM_CH1_S 0 + +#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8) +/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH2 0x000001FF +#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S)) +#define RMT_TX_LIM_CH2_V 0x1FF +#define RMT_TX_LIM_CH2_S 0 + +#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc) +/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH3 0x000001FF +#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S)) +#define RMT_TX_LIM_CH3_V 0x1FF +#define RMT_TX_LIM_CH3_S 0 + +#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0) +/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH4 0x000001FF +#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S)) +#define RMT_TX_LIM_CH4_V 0x1FF +#define RMT_TX_LIM_CH4_S 0 + +#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4) +/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH5 0x000001FF +#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S)) +#define RMT_TX_LIM_CH5_V 0x1FF +#define RMT_TX_LIM_CH5_S 0 + +#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8) +/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH6 0x000001FF +#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S)) +#define RMT_TX_LIM_CH6_V 0x1FF +#define RMT_TX_LIM_CH6_S 0 + +#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec) +/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH7 0x000001FF +#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S)) +#define RMT_TX_LIM_CH7_V 0x1FF +#define RMT_TX_LIM_CH7_S 0 + +#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0) +/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when datas need to be send is more than channel's mem can store + then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/ +#define RMT_MEM_TX_WRAP_EN (BIT(1)) +#define RMT_MEM_TX_WRAP_EN_M (BIT(1)) +#define RMT_MEM_TX_WRAP_EN_V 0x1 +#define RMT_MEM_TX_WRAP_EN_S 1 +/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to disable apb fifo access*/ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (BIT(0)) +#define RMT_APB_FIFO_MASK_V 0x1 +#define RMT_APB_FIFO_MASK_S 0 + +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc) +/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */ +/*description: This is the version register.*/ +#define RMT_DATE 0xFFFFFFFF +#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) +#define RMT_DATE_V 0xFFFFFFFF +#define RMT_DATE_S 0 + +/* RMT memory block address */ +#define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i)) + + +#endif /*_SOC_RMT_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/rmt_struct.h b/tools/sdk/include/soc/include/soc/rmt_struct.h new file mode 100644 index 00000000000..bc4cd7a2ec5 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/rmt_struct.h @@ -0,0 +1,264 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_STRUCT_H_ +#define _SOC_RMT_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access. + Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue + and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/ + struct{ + union { + struct { + uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/ + uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/ + uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/ + uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/ + uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ + uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/ + uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/ + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/ + uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/ + uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/ + uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/ + uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/ + uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/ + uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/ + uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/ + uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/ + uint32_t ref_cnt_rst: 1; /*This bit is used to reset divider in channel0-7.*/ + uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ + uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/ + uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } conf1; + } conf_ch[8]; + uint32_t status_ch[8]; /*The status for channel0-7*/ + uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/ + union { + struct { + uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/ + uint32_t ch0_rx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/ + uint32_t ch0_err: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/ + uint32_t ch1_tx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/ + uint32_t ch1_rx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/ + uint32_t ch1_err: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/ + uint32_t ch2_tx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/ + uint32_t ch2_rx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/ + uint32_t ch2_err: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/ + uint32_t ch3_tx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/ + uint32_t ch3_rx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/ + uint32_t ch3_err: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/ + uint32_t ch4_tx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/ + uint32_t ch4_rx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/ + uint32_t ch4_err: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/ + uint32_t ch5_tx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/ + uint32_t ch5_rx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/ + uint32_t ch5_err: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/ + uint32_t ch6_tx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/ + uint32_t ch6_rx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/ + uint32_t ch6_err: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/ + uint32_t ch7_tx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/ + uint32_t ch7_rx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/ + uint32_t ch7_err: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/ + uint32_t ch0_tx_thr_event: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch1_tx_thr_event: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch2_tx_thr_event: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch3_tx_thr_event: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch4_tx_thr_event: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch5_tx_thr_event: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch6_tx_thr_event: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch7_tx_thr_event: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/ + uint32_t ch0_rx_end: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/ + uint32_t ch0_err: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/ + uint32_t ch1_tx_end: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/ + uint32_t ch1_rx_end: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/ + uint32_t ch1_err: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/ + uint32_t ch2_tx_end: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/ + uint32_t ch2_rx_end: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/ + uint32_t ch2_err: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/ + uint32_t ch3_tx_end: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/ + uint32_t ch3_rx_end: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/ + uint32_t ch3_err: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/ + uint32_t ch4_tx_end: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/ + uint32_t ch4_rx_end: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/ + uint32_t ch4_err: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/ + uint32_t ch5_tx_end: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/ + uint32_t ch5_rx_end: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/ + uint32_t ch5_err: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/ + uint32_t ch6_tx_end: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/ + uint32_t ch6_rx_end: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/ + uint32_t ch6_err: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/ + uint32_t ch7_tx_end: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/ + uint32_t ch7_rx_end: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/ + uint32_t ch7_err: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/ + uint32_t ch0_tx_thr_event: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch1_tx_thr_event: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch2_tx_thr_event: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch3_tx_thr_event: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch4_tx_thr_event: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch5_tx_thr_event: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch6_tx_thr_event: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch7_tx_thr_event: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/ + uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/ + uint32_t ch0_err: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/ + uint32_t ch1_tx_end: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/ + uint32_t ch1_rx_end: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/ + uint32_t ch1_err: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/ + uint32_t ch2_tx_end: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/ + uint32_t ch2_rx_end: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/ + uint32_t ch2_err: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/ + uint32_t ch3_tx_end: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/ + uint32_t ch3_rx_end: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/ + uint32_t ch3_err: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/ + uint32_t ch4_tx_end: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/ + uint32_t ch4_rx_end: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/ + uint32_t ch4_err: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/ + uint32_t ch5_tx_end: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/ + uint32_t ch5_rx_end: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/ + uint32_t ch5_err: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/ + uint32_t ch6_tx_end: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/ + uint32_t ch6_rx_end: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/ + uint32_t ch6_err: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/ + uint32_t ch7_tx_end: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/ + uint32_t ch7_rx_end: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/ + uint32_t ch7_err: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/ + uint32_t ch0_tx_thr_event: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ + uint32_t ch1_tx_thr_event: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ + uint32_t ch2_tx_thr_event: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ + uint32_t ch3_tx_thr_event: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ + uint32_t ch4_tx_thr_event: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ + uint32_t ch5_tx_thr_event: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ + uint32_t ch6_tx_thr_event: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ + uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ + uint32_t ch0_rx_end: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ + uint32_t ch0_err: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/ + uint32_t ch1_tx_end: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ + uint32_t ch1_rx_end: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ + uint32_t ch1_err: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/ + uint32_t ch2_tx_end: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ + uint32_t ch2_rx_end: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ + uint32_t ch2_err: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/ + uint32_t ch3_tx_end: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ + uint32_t ch3_rx_end: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ + uint32_t ch3_err: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/ + uint32_t ch4_tx_end: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ + uint32_t ch4_rx_end: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ + uint32_t ch4_err: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/ + uint32_t ch5_tx_end: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ + uint32_t ch5_rx_end: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ + uint32_t ch5_err: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/ + uint32_t ch6_tx_end: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ + uint32_t ch6_rx_end: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ + uint32_t ch6_err: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/ + uint32_t ch7_tx_end: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ + uint32_t ch7_rx_end: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ + uint32_t ch7_err: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/ + uint32_t ch0_tx_thr_event: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ + uint32_t ch1_tx_thr_event: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ + uint32_t ch2_tx_thr_event: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ + uint32_t ch3_tx_thr_event: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ + uint32_t ch4_tx_thr_event: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ + uint32_t ch5_tx_thr_event: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ + uint32_t ch6_tx_thr_event: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ + uint32_t ch7_tx_thr_event: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/ + uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ + }; + uint32_t val; + } carrier_duty_ch[8]; + union { + struct { + uint32_t limit: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } tx_lim_ch[8]; + union { + struct { + uint32_t fifo_mask: 1; /*Set this bit to enable RMTMEM and disable apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/ + uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } apb_conf; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /*This is the version register.*/ +} rmt_dev_t; +extern rmt_dev_t RMT; + +typedef struct { + union { + struct { + uint32_t duration0 :15; + uint32_t level0 :1; + uint32_t duration1 :15; + uint32_t level1 :1; + }; + uint32_t val; + }; +} rmt_item32_t; + +//Allow access to RMT memory using RMTMEM.chan[0].data32[8] +typedef volatile struct { + struct { + union { + rmt_item32_t data32[64]; + }; + } chan[8]; +} rmt_mem_t; +extern rmt_mem_t RMTMEM; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/rtc.h b/tools/sdk/include/soc/include/soc/rtc.h new file mode 100644 index 00000000000..a528bdd15de --- /dev/null +++ b/tools/sdk/include/soc/include/soc/rtc.h @@ -0,0 +1,726 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file rtc.h + * @brief Low-level RTC power, clock, and sleep functions. + * + * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + * - rtc_sleep: entry into sleep modes + * - rtc_init: initialization + */ + + +/** + * @brief Possible main XTAL frequency values. + * + * Enum values should be equal to frequency in MHz. + */ +typedef enum { + RTC_XTAL_FREQ_AUTO = 0, //!< Automatic XTAL frequency detection + RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL + RTC_XTAL_FREQ_26M = 26, //!< 26 MHz XTAL + RTC_XTAL_FREQ_24M = 24, //!< 24 MHz XTAL +} rtc_xtal_freq_t; + +/** + * @brief CPU frequency values + */ +typedef enum { + RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency + RTC_CPU_FREQ_80M = 1, //!< 80 MHz + RTC_CPU_FREQ_160M = 2, //!< 160 MHz + RTC_CPU_FREQ_240M = 3, //!< 240 MHz + RTC_CPU_FREQ_2M = 4, //!< 2 MHz +} rtc_cpu_freq_t; + +/** + * @brief CPU clock source + */ +typedef enum { + RTC_CPU_FREQ_SRC_XTAL, //!< XTAL + RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M) + RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator + RTC_CPU_FREQ_SRC_APLL //!< APLL +} rtc_cpu_freq_src_t; + +/** + * @brief CPU clock configuration structure + */ +typedef struct { + rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived + uint32_t source_freq_mhz; //!< Source clock frequency + uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div + uint32_t freq_mhz; //!< CPU clock frequency +} rtc_cpu_freq_config_t; + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef enum { + RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator + RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL + RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 +} rtc_slow_freq_t; + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef enum { + RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 + RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator +} rtc_fast_freq_t; + +/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ +#define RTC_FAST_CLK_FREQ_APPROX 8500000 + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + */ +typedef enum { + RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK + RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256 + RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + rtc_cpu_freq_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set + rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = RTC_XTAL_FREQ_AUTO, \ + .cpu_freq_mhz = 80, \ + .fast_freq = RTC_FAST_FREQ_8M, \ + .slow_freq = RTC_SLOW_FREQ_RTC, \ + .clk_8m_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ +} + +/** + * Initialize clocks and set CPU frequency + * + * If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt + * to auto detect XTAL frequency. Auto detection is performed by comparing + * XTAL frequency with the frequency of internal 8MHz oscillator. Note that at + * high temperatures the frequency of the internal 8MHz oscillator may drift + * enough for auto detection to be unreliable. + * Auto detection code will attempt to distinguish between 26MHz and 40MHz + * crystals. 24 MHz crystals are not supported by auto detection code. + * If XTAL frequency can not be auto detected, this 26MHz frequency will be used. + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to + * rtc_clk_init function, or if the value was RTC_XTAL_FREQ_AUTO, the detected + * XTAL frequency. + * + * @return XTAL frequency, one of rtc_xtal_freq_t + */ +rtc_xtal_freq_t rtc_clk_xtal_freq_get(); + +/** + * @brief Update XTAL frequency + * + * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored + * after startup. + * + * @param xtal_freq New frequency value + */ +void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Configure 32 kHz XTAL oscillator to accept external clock signal + */ +void rtc_clk_32k_enable_external(); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(); + +/** + * @brief Enable 32k oscillator, configuring it for fast startup time. + * Note: to achieve higher frequency stability, rtc_clk_32k_enable function + * must be called one the 32k XTAL oscillator has started up. This function + * will initially disable the 32k XTAL oscillator, so it should not be called + * when the system is using 32k XTAL as RTC_SLOW_CLK. + * + * @param cycle Number of 32kHz cycles to bootstrap external crystal. + * If 0, no square wave will be used to bootstrap crystal oscillation. + */ +void rtc_clk_32k_bootstrap(uint32_t cycle); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * Output from 8 MHz internal oscillator is passed into a configurable + * divider, which by default divides the input clock frequency by 256. + * Output of the divider may be used as RTC_SLOW_CLK source. + * Output of the divider is referred to in register descriptions and code as + * 8md256 or simply d256. Divider values other than 256 may be configured, but + * this facility is not currently needed, so is not exposed in the code. + * + * When 8MHz/256 divided output is not needed, the divider should be disabled + * to reduce power consumption. + * + * @param clk_8m_en true to enable 8MHz generator + * @param d256_en true to enable /256 divider + */ +void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(); + +/** + * @brief Get the state of /256 divider which is applied to 8MHz clock + * @return true if the divided output is enabled + */ +bool rtc_clk_8md256_enabled(); + +/** + * @brief Enable or disable APLL + * + * Output frequency is given by the formula: + * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) + * + * The dividend in this expression should be in the range of 240 - 600 MHz. + * + * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0. + * + * @param enable true to enable, false to disable + * @param sdm0 frequency adjustment parameter, 0..255 + * @param sdm1 frequency adjustment parameter, 0..255 + * @param sdm2 frequency adjustment parameter, 0..63 + * @param o_div frequency divider, 0..31 + */ +void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, + uint32_t sdm2, uint32_t o_div); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param slow_freq clock source (one of rtc_slow_freq_t values) + */ +void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of rtc_slow_freq_t values) + */ +rtc_slow_freq_t rtc_clk_slow_freq_get(); + +/** + * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 + * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 + * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 + * + * rtc_clk_cal function can be used to get more precise value by comparing + * RTC_SLOW_CLK frequency to the frequency of main XTAL. + * + * @return RTC_SLOW_CLK frequency, in Hz + */ +uint32_t rtc_clk_slow_freq_get_hz(); + +/** + * @brief Select source for RTC_FAST_CLK + * @param fast_freq clock source (one of rtc_fast_freq_t values) + */ +void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of rtc_fast_freq_t values) + */ +rtc_fast_freq_t rtc_clk_fast_freq_get(); + +/** + * @brief Switch CPU frequency + * + * @note This function is deprecated and will be removed. + * See rtc_clk_cpu_freq_config_set instead. + * + * If a PLL-derived frequency is requested (80, 160, 240 MHz), this function + * will enable the PLL. Otherwise, PLL will be disabled. + * Note: this function is not optimized for switching speed. It may take several + * hundred microseconds to perform frequency switch. + * + * @param cpu_freq new CPU frequency + */ +void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated)); + +/** + * @brief Switch CPU frequency + * + * @note This function is deprecated and will be removed. + * See rtc_clk_cpu_freq_set_config_fast instead. + * + * This is a faster version of rtc_clk_cpu_freq_set, which can handle some of + * the frequency switch paths (XTAL -> PLL, PLL -> XTAL). + * When switching from PLL to XTAL, PLL is not disabled (unlike rtc_clk_cpu_freq_set). + * When switching back from XTAL to PLL, only the same PLL can be used. + * Therefore it is not possible to switch 240 -> XTAL -> (80 or 160) using this + * function. + * + * For unsupported cases, this function falls back to rtc_clk_cpu_freq_set. + * + * Unlike rtc_clk_cpu_freq_set, this function relies on static data, so it is + * less safe to use it e.g. from a panic handler (when memory might be corrupted). + * + * @param cpu_freq new CPU frequency + */ +void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated)); + +/** + * @brief Get the currently selected CPU frequency + * + * @note This function is deprecated and will be removed. + * See rtc_clk_cpu_freq_get_config instead. + * + * Although CPU can be clocked by APLL and RTC 8M sources, such support is not + * exposed through this library. As such, this function will not return + * meaningful values when these clock sources are configured (e.g. using direct + * access to clock selection registers). In debug builds, it will assert; in + * release builds, it will return RTC_CPU_FREQ_XTAL. + * + * @return CPU frequency (one of rtc_cpu_freq_t values) + */ +rtc_cpu_freq_t rtc_clk_cpu_freq_get() __attribute__((deprecated)); + +/** + * @brief Get corresponding frequency value for rtc_cpu_freq_t enum value + * + * @note This function is deprecated and will be removed. + * See rtc_clk_cpu_freq_get/set_config instead. + * + * @param cpu_freq CPU frequency, on of rtc_cpu_freq_t values + * @return CPU frequency, in HZ + */ +uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated)); + +/** + * @brief Get rtc_cpu_freq_t enum value for given CPU frequency + * + * @note This function is deprecated and will be removed. + * See rtc_clk_cpu_freq_mhz_to_config instead. + * + * @param cpu_freq_mhz CPU frequency, one of 80, 160, 240, 2, and XTAL frequency + * @param[out] out_val output, rtc_cpu_freq_t value corresponding to the frequency + * @return true if the given frequency value matches one of enum values + */ + bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t* out_val) __attribute__((deprecated)); + +/** + * @brief Get CPU frequency config corresponding to a rtc_cpu_freq_t value + * @param cpu_freq CPU frequency enumeration value + * @param[out] out_config Output, CPU frequency configuration structure + */ + void rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq, rtc_cpu_freq_config_t* out_config); + + /** + * @brief Get CPU frequency config for a given frequency + * @param freq_mhz Frequency in MHz + * @param[out] out_config Output, CPU frequency configuration structure + * @return true if frequency can be obtained, false otherwise + */ + bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config); + + /** + * @brief Switch CPU frequency + * + * This function sets CPU frequency according to the given configuration + * structure. It enables PLLs, if necessary. + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ + void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config); + + /** + * @brief Switch CPU frequency (optimized for speed) + * + * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. + * It works faster because it does not disable PLLs when switching from PLL to + * XTAL and does not enabled them when switching back. If PLL is not already + * enabled when this function is called to switch from XTAL to PLL frequency, + * or the PLL which is enabled is the wrong one, this function will fall back + * to calling rtc_clk_cpu_freq_set_config. + * + * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, + * so it is less safe to use it e.g. from a panic handler (when memory might + * be corrupted). + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ + void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config); + + /** + * @brief Get the currently used CPU frequency configuration + * @param[out] out_config Output, CPU frequency configuration structure + */ + void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config); + + /** + * @brief Switch CPU clock source to XTAL + * + * Short form for filling in rtc_cpu_freq_config_t structure and calling + * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. + * Assumes that XTAL frequency has been determined — don't call in startup code. + */ + void rtc_clk_cpu_freq_set_xtal(); + + +/** + * @brief Store new APB frequency value into RTC_APB_FREQ_REG + * + * This function doesn't change any hardware clocks. + * + * Functions which perform frequency switching and change APB frequency call + * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG + * (one of RTC general purpose retention registers). This should not normally + * be called from application code. + * + * @param apb_freq new APB frequency, in Hz + */ +void rtc_clk_apb_freq_update(uint32_t apb_freq); + +/** + * @brief Get the current stored APB frequency. + * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. + */ +uint32_t rtc_clk_apb_freq_get(); + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Measure ratio between XTAL frequency and RTC slow clock frequency + * @param cal_clk slow clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average ratio between XTAL frequency and slow clock frequency, + * Q13.19 fixed point format, or 0 if calibration has timed out. + */ +uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(); + +/** + * @brief Busy loop until next RTC_SLOW_CLK cycle + * + * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. + * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return + * one RTC_SLOW_CLK cycle later. + */ +void rtc_clk_wait_for_slow_cycle(); + +/** + * @brief sleep configuration for rtc_sleep_init function + */ +typedef struct { + uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) + uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory) + uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) + uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory + uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory + uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals + uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t rom_mem_pd_en : 1; //!< power down main RAM and ROM + uint32_t deep_slp : 1; //!< power down digital domain + uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode + uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode + uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode + uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode + uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode + uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags + uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator + uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep +} rtc_sleep_config_t; + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ + .lslp_mem_inf_fpu = 0, \ + .rtc_mem_inf_fpu = 0, \ + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ + .wifi_pd_en = 0, \ + .rom_mem_pd_en = 0, \ + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ + .wdt_flashboot_mod_en = 0, \ + .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .lslp_meminf_pd = 1, \ + .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \ +}; + +#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) +#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals +#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory +#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory +#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU +#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator +#define RTC_SLEEP_PD_XTAL BIT(6) //!< Power down main XTAL + +/** + * @brief Prepare the chip to enter sleep mode + * + * This function configures various power control state machines to handle + * entry into light sleep or deep sleep mode, switches APB and CPU clock source + * (usually to XTAL), and sets bias voltages for digital and RTC power domains. + * + * This function does not actually enter sleep mode; this is done using + * rtc_sleep_start function. Software may do some other actions between + * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure + * wakeup sources. + * @param cfg sleep mode configuration + */ +void rtc_sleep_init(rtc_sleep_config_t cfg); + + +/** + * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source + * @param t value of RTC counter at which wakeup from sleep will happen; + * only the lower 48 bits are used + */ +void rtc_sleep_set_wakeup_time(uint64_t t); + + +#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup +#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup +#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only) +#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup +#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only) +#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only) +#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) +#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) +#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup +#define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup +#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) + +/** + * @brief Enter deep or light sleep mode + * + * This function enters the sleep mode previously configured using rtc_sleep_init + * function. Before entering sleep, software should configure wake up sources + * appropriately (set up GPIO wakeup registers, timer wakeup registers, + * and so on). + * + * If deep sleep mode was configured using rtc_sleep_init, and sleep is not + * rejected by hardware (based on reject_opt flags), this function never returns. + * When the chip wakes up from deep sleep, CPU is reset and execution starts + * from ROM bootloader. + * + * If light sleep mode was configured using rtc_sleep_init, this function + * returns on wakeup, or if sleep is rejected by hardware. + * + * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags + * combined with OR) + * @param reject_opt bit mask of sleep reject reasons: + * - RTC_CNTL_GPIO_REJECT_EN + * - RTC_CNTL_SDIO_REJECT_EN + * These flags are used to prevent entering sleep when e.g. + * an external host is communicating via SDIO slave + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); + +/** + * RTC power and clock control initialization settings + */ +typedef struct { + uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready + uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready + uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready + uint32_t clkctl_init : 1; //!< Perform clock control related initialization + uint32_t pwrctl_init : 1; //!< Perform power control related initialization + uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST +} rtc_config_t; + +/** + * Default initializer of rtc_config_t. + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use). + */ +#define RTC_CONFIG_DEFAULT() {\ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ + .clkctl_init = 1, \ + .pwrctl_init = 1, \ + .rtc_dboost_fpd = 1 \ +} + +/** + * Initialize RTC clock and power control related functions + * @param cfg configuration options as rtc_config_t + */ +void rtc_init(rtc_config_t cfg); + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + +/** + * Structure describing vddsdio configuration + */ +typedef struct { + uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. + uint32_t enable : 1; //!< Enable VDDSDIO regulator + uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V + uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator +} rtc_vddsdio_config_t; + +/** + * Get current VDDSDIO configuration + * If VDDSDIO configuration is overridden by RTC, get values from RTC + * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE + * Otherwise, use default values and the level of MTDI bootstrapping pin. + * @return currently used VDDSDIO configuration + */ +rtc_vddsdio_config_t rtc_vddsdio_get_config(); + +/** + * Set new VDDSDIO configuration using RTC registers. + * If config.force == 1, this overrides configuration done using bootstrapping + * pins and EFUSE. + * + * @param config new VDDSDIO configuration + */ +void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); + +#ifdef __cplusplus +} +#endif + diff --git a/tools/sdk/include/soc/include/soc/rtc_cntl_reg.h b/tools/sdk/include/soc/include/soc/rtc_cntl_reg.h new file mode 100644 index 00000000000..090b3f7072c --- /dev/null +++ b/tools/sdk/include/soc/include/soc/rtc_cntl_reg.h @@ -0,0 +1,2072 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_CNTL_REG_H_ +#define _SOC_RTC_CNTL_REG_H_ + +/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ +#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 + + +#include "soc.h" +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ +/*description: BIAS_CORE force power up*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22 +/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: BIAS_CORE force power down*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21 +/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: BIAS_CORE follow CK8M*/ +#define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_CORE_FOLW_8M_S 20 +/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: BIAS_I2C force power up*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19 +/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: BIAS_I2C force power down*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18 +/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: BIAS_I2C follow CK8M*/ +#define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_I2C_FOLW_8M_S 17 +/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: BIAS_SLEEP force no sleep*/ +#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16 +/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP force sleep*/ +#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15 +/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP follow CK8M*/ +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC sleep timer low 32 bits*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: To indicate the register is updated*/ +#define RTC_CNTL_TIME_VALID (BIT(30)) +#define RTC_CNTL_TIME_VALID_M (BIT(30)) +#define RTC_CNTL_TIME_VALID_V 0x1 +#define RTC_CNTL_TIME_VALID_S 30 + +#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) +/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIME_LO 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_M ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S)) +#define RTC_CNTL_TIME_LO_V 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_S 0 + +#define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) +/* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIME_HI 0x0000FFFF +#define RTC_CNTL_TIME_HI_M ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S)) +#define RTC_CNTL_TIME_HI_V 0xFFFF +#define RTC_CNTL_TIME_HI_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: sleep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: sleep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: ULP-coprocessor timer enable bit*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 24 +/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: touch timer enable bit*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge 0: APB to RTC using sync*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: ULP-coprocessor force wake up*/ +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S 21 +/* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: touch controller force wake up*/ +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + start to work*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) +/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 +/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) +#define RTC_CNTL_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_POWERUP_TIMER_S 9 +/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) +#define RTC_CNTL_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) +/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 +/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) +#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +#define RTC_CNTL_MIN_SLP_VAL_MIN 2 +/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S)) +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V 0xFF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S 0 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: 1: PLL_I2C power up otherwise power down*/ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up otherwise power down*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up otherwise power down*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up otherwise power down*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up otherwise power down*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */ +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x000007FF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x7FF +#define RTC_CNTL_WAKEUP_ENA_S 11 +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 7 +/* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch interrupt*/ +#define RTC_CNTL_TOUCH_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_INT_ENA_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 +/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable RTC time valid interrupt*/ +#define RTC_CNTL_TIME_VALID_INT_ENA (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ENA_S 4 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 8 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 7 +/* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt raw*/ +#define RTC_CNTL_TOUCH_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_INT_RAW_S 6 +/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt raw*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 +/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt raw*/ +#define RTC_CNTL_TIME_VALID_INT_RAW (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_RAW_S 4 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt raw*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 7 +/* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_INT_ST_S 6 +/* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_ST (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_M (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_V 0x1 +#define RTC_CNTL_SAR_INT_ST_S 5 +/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_ST (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ST_S 4 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 8 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 7 +/* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Clear touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_INT_CLR_S 6 +/* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Clear ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_CLR (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_M (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_V 0x1 +#define RTC_CNTL_SAR_INT_CLR_S 5 +/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Clear RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_CLR_S 4 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Clear SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable control XTAL by external pads*/ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0000000F +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0xF +#define RTC_CNTL_REJECT_CAUSE_S 28 +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26 +/* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: enable SDIO reject*/ +#define RTC_CNTL_SDIO_REJECT_EN (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_M (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_V 0x1 +#define RTC_CNTL_SDIO_REJECT_EN_S 25 +/* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: enable GPIO reject*/ +#define RTC_CNTL_GPIO_REJECT_EN (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_M (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_V 0x1 +#define RTC_CNTL_GPIO_REJECT_EN_S 24 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: CPU period sel*/ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) +/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ +/*description: */ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ +#define RTC_CNTL_SOC_CLK_SEL 0x00000003 +#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) +#define RTC_CNTL_SOC_CLK_SEL_V 0x3 +#define RTC_CNTL_SOC_CLK_SEL_S 27 +#define RTC_CNTL_SOC_CLK_SEL_XTL 0 +#define RTC_CNTL_SOC_CLK_SEL_PLL 1 +#define RTC_CNTL_SOC_CLK_SEL_8M 2 +#define RTC_CNTL_SOC_CLK_SEL_APLL 3 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1 +#define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG 0: use state machine*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) +/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: RST_BIAS_I2C*/ +#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_V 0x1 +#define RTC_CNTL_RST_BIAS_I2C_S 31 +/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_WIDTH*/ +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 +/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 +/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 +/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_REFRESH*/ +#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 +/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: ENB_SCK_XTAL*/ +#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_V 0x1 +#define RTC_CNTL_ENB_SCK_XTAL_S 26 +/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */ +/*description: DBG_ATTEN*/ +#define RTC_CNTL_DBG_ATTEN 0x00000003 +#define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S)) +#define RTC_CNTL_DBG_ATTEN_V 0x3 +#define RTC_CNTL_DBG_ATTEN_S 24 +#define RTC_CNTL_DBG_ATTEN_DEFAULT 3 +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: RTC_REG force power up*/ +#define RTC_CNTL_FORCE_PU (BIT(31)) +#define RTC_CNTL_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 31 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_FORCE_PD (BIT(30)) +#define RTC_CNTL_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during wakeup*/ +#define RTC_CNTL_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) +#define RTC_CNTL_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DBIAS_WAK_S 25 +/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during sleep*/ +#define RTC_CNTL_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) +#define RTC_CNTL_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DBIAS_SLP_S 22 +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 +/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during wakeup*/ +#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S)) +#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DIG_DBIAS_WAK_S 11 +/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during sleep*/ +#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DIG_DBIAS_SLP_S 8 +/* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: N/A*/ +#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_M (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_V 0x1 +#define RTC_CNTL_SCK_DCAP_FORCE_S 7 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DBIAS_0V90 0 +#define RTC_CNTL_DBIAS_0V95 1 +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V05 3 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V15 5 +#define RTC_CNTL_DBIAS_1V20 6 +#define RTC_CNTL_DBIAS_1V25 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) +/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: enable power down rtc_peri in sleep*/ +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (BIT(20)) +#define RTC_CNTL_PD_EN_V 0x1 +#define RTC_CNTL_PD_EN_S 20 +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: rtc_peri force power up*/ +#define RTC_CNTL_PWC_FORCE_PU (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_V 0x1 +#define RTC_CNTL_PWC_FORCE_PU_S 19 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc_peri force power down*/ +#define RTC_CNTL_PWC_FORCE_PD (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_V 0x1 +#define RTC_CNTL_PWC_FORCE_PD_S 18 +/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable power down RTC memory in sleep*/ +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 +/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: RTC memory force power up*/ +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 +/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: RTC memory force power down*/ +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 +/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable power down fast RTC memory in sleep*/ +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 +/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: Fast RTC memory force power up*/ +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 +/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Fast RTC memory force power down*/ +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: RTC memory force no PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC memory force PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Fast RTC memory force PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following + RTC state machine*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 +/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: rtc_peri force no ISO*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FORCE_NOISO_S 5 +/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: rtc_peri force ISO*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (BIT(4)) +#define RTC_CNTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_FORCE_ISO_S 4 +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC memory force ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: RTC memory force no ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Fast RTC memory force ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 + +/* Useful groups of RTC_CNTL_PWC_REG bits */ +#define RTC_CNTL_MEM_FORCE_ISO \ + (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO) +#define RTC_CNTL_MEM_FORCE_NOISO \ + (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) +#define RTC_CNTL_MEM_PD_EN \ + (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN) +#define RTC_CNTL_MEM_FORCE_PU \ + (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) +#define RTC_CNTL_MEM_FORCE_PD \ + (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD) +#define RTC_CNTL_MEM_FOLW_CPU \ + (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) +#define RTC_CNTL_MEM_FORCE_LPU \ + (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU) +#define RTC_CNTL_MEM_FORCE_LPD \ + (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ +/*description: enable power down digital core in sleep*/ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ +/*description: enable power down internal SRAM 4 in sleep*/ +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 +/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ +/*description: enable power down internal SRAM 3 in sleep*/ +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 +/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ +/*description: enable power down internal SRAM 2 in sleep*/ +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 +/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ +/*description: enable power down internal SRAM 1 in sleep*/ +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 +/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ +/*description: enable power down internal SRAM 0 in sleep*/ +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 +/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ +/*description: enable power down ROM in sleep*/ +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_V 0x1 +#define RTC_CNTL_ROM0_PD_EN_S 24 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force power up*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 +/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: internal SRAM 4 force power down*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 +/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force power up*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 +/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: internal SRAM 3 force power down*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 +/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force power up*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 +/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: internal SRAM 2 force power down*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 +/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force power up*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 +/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: internal SRAM 1 force power down*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 +/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force power up*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 +/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: internal SRAM 0 force power down*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 +/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: ROM force power up*/ +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 +/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ROM force power down*/ +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +/* Useful groups of RTC_CNTL_DIG_PWC_REG bits */ +#define RTC_CNTL_CPU_ROM_RAM_PD_EN \ + (RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\ + RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\ + RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \ + (RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\ + RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\ + RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \ + (RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\ + RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\ + RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: digital core force no ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force no ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 +/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: internal SRAM 4 force ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 +/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force no ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 +/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: internal SRAM 3 force ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 +/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force no ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 +/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: internal SRAM 2 force ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 +/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force no ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 +/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: internal SRAM 1 force ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 +/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force no ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 +/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: internal SRAM 0 force ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 +/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ +/*description: ROM force no ISO*/ +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 +/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: ROM force ISO*/ +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +/* Useful groups of RTC_CNTL_DIG_ISO_REG bits */ +#define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO \ + (RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\ + RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\ + RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \ + (RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\ + RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\ + RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO) + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: enable RTC WDT*/ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_M (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_V 0x1 +#define RTC_CNTL_WDT_EDGE_INT_EN_S 18 +/* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_M (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_V 0x1 +#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17 +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */ +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */ +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7 +/* RTC_CNTL_WDT_STGX : */ +/*description: stage action selection values */ +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) +/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: DTEST_RTC*/ +#define RTC_CNTL_DTEST_RTC 0x00000003 +#define RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S)) +#define RTC_CNTL_DTEST_RTC_V 0x3 +#define RTC_CNTL_DTEST_RTC_S 30 +/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ENT_RTC*/ +#define RTC_CNTL_ENT_RTC (BIT(29)) +#define RTC_CNTL_ENT_RTC_M (BIT(29)) +#define RTC_CNTL_ENT_RTC_V 0x1 +#define RTC_CNTL_ENT_RTC_S 29 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xc0) +/* RTC_CNTL_RDY_FOR_WAKEUP : R/0; bitpos:[19]; default: 0 */ +/*description: 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise */ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 + +/* Compatibility definition */ +#define RTC_CNTL_DIAG0_REG RTC_CNTL_LOW_POWER_ST_REG +/* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_M ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S)) +#define RTC_CNTL_LOW_POWER_DIAG0_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_S 0 + +#define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) +/* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32N_HOLD_FORCE_S 17 +/* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32P_HOLD_FORCE_S 16 +/* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15 +/* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14 +/* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13 +/* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12 +/* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11 +/* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10 +/* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9 +/* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8 +/* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7 +/* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6 +/* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5 +/* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4 +/* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3 +/* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2 +/* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC2_HOLD_FORCE_S 1 +/* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC1_HOLD_FORCE_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: clear ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: Bitmap to select RTC pads for ext wakeup1*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: brown out detect*/ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */ +/*description: brown out threshold*/ +#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007 +#define RTC_CNTL_DBROWN_OUT_THRES_M ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S)) +#define RTC_CNTL_DBROWN_OUT_THRES_V 0x7 +#define RTC_CNTL_DBROWN_OUT_THRES_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 + +#define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) +#define RTC_MEM_CRC_FINISH (BIT(31)) +#define RTC_MEM_CRC_FINISH_M (BIT(31)) +#define RTC_MEM_CRC_FINISH_V 0x1 +#define RTC_MEM_CRC_FINISH_S (31) +#define RTC_MEM_CRC_LEN (0x7ff) +#define RTC_MEM_CRC_LEN_M ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S)) +#define RTC_MEM_CRC_LEN_V (0x7ff) +#define RTC_MEM_CRC_LEN_S (20) +#define RTC_MEM_CRC_ADDR (0x7ff) +#define RTC_MEM_CRC_ADDR_M ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S)) +#define RTC_MEM_CRC_ADDR_V (0x7ff) +#define RTC_MEM_CRC_ADDR_S (9) +#define RTC_MEM_CRC_START (BIT(8)) +#define RTC_MEM_CRC_START_M (BIT(8)) +#define RTC_MEM_CRC_START_V 0x1 +#define RTC_MEM_CRC_START_S (8) +#define RTC_MEM_PID_CONF (0xff) +#define RTC_MEM_PID_CONF_M (0xff) +#define RTC_MEM_PID_CONF_V (0xff) +#define RTC_MEM_PID_CONF_S (0) + +#define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 +#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280 + + + + +#endif /*_SOC_RTC_CNTL_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/rtc_cntl_struct.h b/tools/sdk/include/soc/include/soc/rtc_cntl_struct.h new file mode 100644 index 00000000000..17a2d180382 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/rtc_cntl_struct.h @@ -0,0 +1,566 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_CNTL_STRUCT_H_ +#define _SOC_RTC_CNTL_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd: 1; /*crystall force power down*/ + uint32_t xtl_force_pu: 1; /*crystall force power up*/ + uint32_t bias_sleep_folw_8m: 1; /*BIAS_SLEEP follow CK8M*/ + uint32_t bias_force_sleep: 1; /*BIAS_SLEEP force sleep*/ + uint32_t bias_force_nosleep: 1; /*BIAS_SLEEP force no sleep*/ + uint32_t bias_i2c_folw_8m: 1; /*BIAS_I2C follow CK8M*/ + uint32_t bias_i2c_force_pd: 1; /*BIAS_I2C force power down*/ + uint32_t bias_i2c_force_pu: 1; /*BIAS_I2C force power up*/ + uint32_t bias_core_folw_8m: 1; /*BIAS_CORE follow CK8M*/ + uint32_t bias_core_force_pd: 1; /*BIAS_CORE force power down*/ + uint32_t bias_core_force_pu: 1; /*BIAS_CORE force power up*/ + uint32_t xtl_force_iso: 1; + uint32_t pll_force_iso: 1; + uint32_t analog_force_iso: 1; + uint32_t xtl_force_noiso: 1; + uint32_t pll_force_noiso: 1; + uint32_t analog_force_noiso: 1; + uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst: 1; /*SW system reset*/ + }; + uint32_t val; + } options0; + uint32_t slp_timer0; /*RTC sleep timer low 32 bits*/ + union { + struct { + uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } slp_timer1; + union { + struct { + uint32_t reserved0: 30; + uint32_t valid: 1; /*To indicate the register is updated*/ + uint32_t update: 1; /*Set 1: to update register with RTC timer*/ + }; + uint32_t val; + } time_update; + uint32_t time0; /*RTC timer low 32 bits*/ + union { + struct { + uint32_t time_hi:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } time1; + union { + struct { + uint32_t reserved0: 20; + uint32_t touch_wakeup_force_en: 1; /*touch controller force wake up*/ + uint32_t ulp_cp_wakeup_force_en: 1; /*ULP-coprocessor force wake up*/ + uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/ + uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ + uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ + uint32_t reserved25: 3; + uint32_t sdio_active_ind: 1; /*SDIO active indication*/ + uint32_t slp_wakeup: 1; /*sleep wakeup bit*/ + uint32_t slp_reject: 1; /*sleep reject bit*/ + uint32_t sleep_en: 1; /*sleep enable bit*/ + }; + uint32_t val; + } state0; + union { + struct { + uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ + }; + uint32_t val; + } timer1; + union { + struct { + uint32_t reserved0: 15; + uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ + uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + }; + uint32_t val; + } timer2; + union { + struct { + uint32_t wifi_wait_timer: 9; + uint32_t wifi_powerup_timer: 7; + uint32_t rom_ram_wait_timer: 9; + uint32_t rom_ram_powerup_timer: 7; + }; + uint32_t val; + } timer3; + union { + struct { + uint32_t rtc_wait_timer: 9; + uint32_t rtc_powerup_timer: 7; + uint32_t dg_wrap_wait_timer: 9; + uint32_t dg_wrap_powerup_timer: 7; + }; + uint32_t val; + } timer4; + union { + struct { + uint32_t ulp_cp_subtimer_prediv: 8; + uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t rtcmem_wait_timer: 9; + uint32_t rtcmem_powerup_timer: 7; + }; + uint32_t val; + } timer5; + union { + struct { + uint32_t reserved0: 23; + uint32_t plla_force_pd: 1; /*PLLA force power down*/ + uint32_t plla_force_pu: 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu: 1; /*1: PVTMON power up otherwise power down*/ + uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up otherwise power down*/ + uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up otherwise power down*/ + uint32_t reserved29: 1; + uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up otherwise power down*/ + uint32_t pll_i2c_pu: 1; /*1: PLL_I2C power up otherwise power down*/ + }; + uint32_t val; + } ana_conf; + union { + struct { + uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ + uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/ + uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } reset_state; + union { + struct { + uint32_t wakeup_cause: 11; /*wakeup cause*/ + uint32_t rtc_wakeup_ena: 11; /*wakeup enable bitmap*/ + uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } wakeup_state; + union { + struct { + uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/ + uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch: 1; /*enable touch interrupt*/ + uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/ + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ + uint32_t rtc_touch: 1; /*touch interrupt raw*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/ + uint32_t rtc_sar: 1; /*ULP-coprocessor interrupt state*/ + uint32_t rtc_touch: 1; /*touch interrupt state*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/ + uint32_t rtc_sar: 1; /*Clear ULP-coprocessor interrupt state*/ + uint32_t rtc_touch: 1; /*Clear touch interrupt state*/ + uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_clr; + uint32_t rtc_store0; /*32-bit general purpose retention register*/ + uint32_t rtc_store1; /*32-bit general purpose retention register*/ + uint32_t rtc_store2; /*32-bit general purpose retention register*/ + uint32_t rtc_store3; /*32-bit general purpose retention register*/ + union { + struct { + uint32_t reserved0: 30; + uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/ + uint32_t ctr_en: 1; /*enable control XTAL by external pads*/ + }; + uint32_t val; + } ext_xtl_conf; + union { + struct { + uint32_t reserved0: 30; + uint32_t wakeup0_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ + uint32_t wakeup1_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ + }; + uint32_t val; + } ext_wakeup_conf; + union { + struct { + uint32_t reserved0: 24; + uint32_t gpio_reject_en: 1; /*enable GPIO reject*/ + uint32_t sdio_reject_en: 1; /*enable SDIO reject*/ + uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ + uint32_t reject_cause: 4; /*sleep reject cause*/ + }; + uint32_t val; + } slp_reject_conf; + union { + struct { + uint32_t reserved0: 29; + uint32_t cpusel_conf: 1; /*CPU sel option*/ + uint32_t cpuperiod_sel: 2; /*CPU period sel*/ + }; + uint32_t val; + } cpu_period_conf; + union { + struct { + uint32_t reserved0: 22; + uint32_t sdio_act_dnum:10; + }; + uint32_t val; + } sdio_act_conf; + union { + struct { + uint32_t reserved0: 4; + uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ + uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ + uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ + uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t ck8m_dfreq_force: 1; + uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ + uint32_t soc_clk_sel: 2; /*SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ + uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ + uint32_t ana_clk_rtc_sel: 2; /*slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t reserved0: 21; + uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/ + uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio: 1; /*SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ + }; + uint32_t val; + } sdio_conf; + union { + struct { + uint32_t reserved0: 24; + uint32_t dbg_atten: 2; /*DBG_ATTEN*/ + uint32_t enb_sck_xtal: 1; /*ENB_SCK_XTAL*/ + uint32_t inc_heartbeat_refresh: 1; /*INC_HEARTBEAT_REFRESH*/ + uint32_t dec_heartbeat_period: 1; /*DEC_HEARTBEAT_PERIOD*/ + uint32_t inc_heartbeat_period: 1; /*INC_HEARTBEAT_PERIOD*/ + uint32_t dec_heartbeat_width: 1; /*DEC_HEARTBEAT_WIDTH*/ + uint32_t rst_bias_i2c: 1; /*RST_BIAS_I2C*/ + }; + uint32_t val; + } bias_conf; + union { + struct { + uint32_t reserved0: 7; + uint32_t sck_dcap_force: 1; /*N/A*/ + uint32_t dig_dbias_slp: 3; /*DIG_REG_DBIAS during sleep*/ + uint32_t dig_dbias_wak: 3; /*DIG_REG_DBIAS during wakeup*/ + uint32_t sck_dcap: 8; /*SCK_DCAP*/ + uint32_t rtc_dbias_slp: 3; /*RTC_DBIAS during sleep*/ + uint32_t rtc_dbias_wak: 3; /*RTC_DBIAS during wakeup*/ + uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ + uint32_t rtc_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtc_force_pu: 1; /*RTC_REG force power up*/ + }; + uint32_t val; + } rtc; + union { + struct { + uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/ + uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/ + uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/ + uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/ + uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/ + uint32_t force_noiso: 1; /*rtc_peri force no ISO*/ + uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine*/ + uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/ + uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/ + uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ + uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/ + uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/ + uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/ + uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/ + uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/ + uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/ + uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/ + uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/ + uint32_t pwc_force_pd: 1; /*rtc_peri force power down*/ + uint32_t pwc_force_pu: 1; /*rtc_peri force power up*/ + uint32_t pd_en: 1; /*enable power down rtc_peri in sleep*/ + uint32_t reserved21: 11; + }; + uint32_t val; + } rtc_pwc; + union { + struct { + uint32_t reserved0: 3; + uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ + uint32_t rom0_force_pd: 1; /*ROM force power down*/ + uint32_t rom0_force_pu: 1; /*ROM force power up*/ + uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/ + uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/ + uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/ + uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/ + uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/ + uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/ + uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/ + uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/ + uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/ + uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/ + uint32_t wifi_force_pd: 1; /*wifi force power down*/ + uint32_t wifi_force_pu: 1; /*wifi force power up*/ + uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ + uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ + uint32_t reserved21: 3; + uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/ + uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/ + uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/ + uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/ + uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/ + uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/ + uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ + uint32_t dg_wrap_pd_en: 1; /*enable power down digital core in sleep*/ + }; + uint32_t val; + } dig_pwc; + union { + struct { + uint32_t reserved0: 7; + uint32_t dig_iso_force_off: 1; + uint32_t dig_iso_force_on: 1; + uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ + uint32_t rom0_force_iso: 1; /*ROM force ISO*/ + uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/ + uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/ + uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/ + uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/ + uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/ + uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/ + uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/ + uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/ + uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/ + uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/ + uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/ + uint32_t wifi_force_iso: 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ + uint32_t dg_wrap_force_noiso: 1; /*digital core force no ISO*/ + }; + uint32_t val; + } dig_iso; + union { + struct { + uint32_t reserved0: 7; + uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length: 3; /*system reset counter length*/ + uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ + uint32_t level_int_en: 1; /*N/A*/ + uint32_t edge_int_en: 1; /*N/A*/ + uint32_t stg3: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg2: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg1: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg0: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t en: 1; /*enable RTC WDT*/ + }; + uint32_t val; + } wdt_config0; + uint32_t wdt_config1; /**/ + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ + union { + struct { + uint32_t reserved0: 31; + uint32_t feed: 1; + }; + uint32_t val; + } wdt_feed; + uint32_t wdt_wprotect; /**/ + union { + struct { + uint32_t reserved0: 29; + uint32_t ent_rtc: 1; /*ENT_RTC*/ + uint32_t dtest_rtc: 2; /*DTEST_RTC*/ + }; + uint32_t val; + } test_mux; + union { + struct { + uint32_t reserved0: 20; + uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t procpu_c1: 6; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + }; + uint32_t val; + } sw_cpu_stall; + uint32_t store4; /*32-bit general purpose retention register*/ + uint32_t store5; /*32-bit general purpose retention register*/ + uint32_t store6; /*32-bit general purpose retention register*/ + uint32_t store7; /*32-bit general purpose retention register*/ + uint32_t diag0; /**/ + uint32_t diag1; /**/ + union { + struct { + uint32_t adc1_hold_force: 1; + uint32_t adc2_hold_force: 1; + uint32_t pdac1_hold_force: 1; + uint32_t pdac2_hold_force: 1; + uint32_t sense1_hold_force: 1; + uint32_t sense2_hold_force: 1; + uint32_t sense3_hold_force: 1; + uint32_t sense4_hold_force: 1; + uint32_t touch_pad0_hold_force: 1; + uint32_t touch_pad1_hold_force: 1; + uint32_t touch_pad2_hold_force: 1; + uint32_t touch_pad3_hold_force: 1; + uint32_t touch_pad4_hold_force: 1; + uint32_t touch_pad5_hold_force: 1; + uint32_t touch_pad6_hold_force: 1; + uint32_t touch_pad7_hold_force: 1; + uint32_t x32p_hold_force: 1; + uint32_t x32n_hold_force: 1; + uint32_t reserved18: 14; + }; + uint32_t val; + } hold_force; + union { + struct { + uint32_t ext_wakeup1_sel: 18; /*Bitmap to select RTC pads for ext wakeup1*/ + uint32_t ext_wakeup1_status_clr: 1; /*clear ext wakeup1 status*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } ext_wakeup1; + union { + struct { + uint32_t ext_wakeup1_status:18; /*ext wakeup1 status*/ + uint32_t reserved18: 14; + }; + uint32_t val; + } ext_wakeup1_status; + union { + struct { + uint32_t reserved0: 14; + uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait: 10; /*brown out reset wait cycles*/ + uint32_t rst_ena: 1; /*enable brown out reset*/ + uint32_t thres: 3; /*brown out threshold*/ + uint32_t ena: 1; /*enable brown out*/ + uint32_t det: 1; /*brown out detect*/ + }; + uint32_t val; + } brown_out; + uint32_t reserved_39; + uint32_t reserved_3d; + uint32_t reserved_41; + uint32_t reserved_45; + uint32_t reserved_49; + uint32_t reserved_4d; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_cntl_dev_t; +extern rtc_cntl_dev_t RTCCNTL; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_RTC_CNTL_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/rtc_gpio_channel.h b/tools/sdk/include/soc/include/soc/rtc_gpio_channel.h new file mode 100644 index 00000000000..c5107a0fb1d --- /dev/null +++ b/tools/sdk/include/soc/include/soc/rtc_gpio_channel.h @@ -0,0 +1,73 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_RTC_GPIO_CHANNEL_H +#define _SOC_RTC_GPIO_CHANNEL_H + +//RTC GPIO channels +#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0 +#define RTCIO_CHANNEL_0_GPIO_NUM 36 + +#define RTCIO_GPIO37_CHANNEL 1 //RTCIO_CHANNEL_1 +#define RTCIO_CHANNEL_1_GPIO_NUM 37 + +#define RTCIO_GPIO38_CHANNEL 2 //RTCIO_CHANNEL_2 +#define RTCIO_CHANNEL_2_GPIO_NUM 38 + +#define RTCIO_GPIO39_CHANNEL 3 //RTCIO_CHANNEL_3 +#define RTCIO_CHANNEL_3_GPIO_NUM 39 + +#define RTCIO_GPIO34_CHANNEL 4 //RTCIO_CHANNEL_4 +#define RTCIO_CHANNEL_4_GPIO_NUM 34 + +#define RTCIO_GPIO35_CHANNEL 5 //RTCIO_CHANNEL_5 +#define RTCIO_CHANNEL_5_GPIO_NUM 35 + +#define RTCIO_GPIO25_CHANNEL 6 //RTCIO_CHANNEL_6 +#define RTCIO_CHANNEL_6_GPIO_NUM 25 + +#define RTCIO_GPIO26_CHANNEL 7 //RTCIO_CHANNEL_7 +#define RTCIO_CHANNEL_7_GPIO_NUM 26 + +#define RTCIO_GPIO33_CHANNEL 8 //RTCIO_CHANNEL_8 +#define RTCIO_CHANNEL_8_GPIO_NUM 33 + +#define RTCIO_GPIO32_CHANNEL 9 //RTCIO_CHANNEL_9 +#define RTCIO_CHANNEL_9_GPIO_NUM 32 + +#define RTCIO_GPIO4_CHANNEL 10 //RTCIO_CHANNEL_10 +#define RTCIO_CHANNEL_10_GPIO_NUM 4 + +#define RTCIO_GPIO0_CHANNEL 11 //RTCIO_CHANNEL_11 +#define RTCIO_CHANNEL_11_GPIO_NUM 0 + +#define RTCIO_GPIO2_CHANNEL 12 //RTCIO_CHANNEL_12 +#define RTCIO_CHANNEL_12_GPIO_NUM 2 + +#define RTCIO_GPIO15_CHANNEL 13 //RTCIO_CHANNEL_13 +#define RTCIO_CHANNEL_13_GPIO_NUM 15 + +#define RTCIO_GPIO13_CHANNEL 14 //RTCIO_CHANNEL_14 +#define RTCIO_CHANNEL_14_GPIO_NUM 13 + +#define RTCIO_GPIO12_CHANNEL 15 //RTCIO_CHANNEL_15 +#define RTCIO_CHANNEL_15_GPIO_NUM 12 + +#define RTCIO_GPIO14_CHANNEL 16 //RTCIO_CHANNEL_16 +#define RTCIO_CHANNEL_16_GPIO_NUM 14 + +#define RTCIO_GPIO27_CHANNEL 17 //RTCIO_CHANNEL_17 +#define RTCIO_CHANNEL_17_GPIO_NUM 27 + +#endif diff --git a/tools/sdk/include/soc/include/soc/rtc_i2c_reg.h b/tools/sdk/include/soc/include/soc/rtc_i2c_reg.h new file mode 100644 index 00000000000..be7b64c6b1c --- /dev/null +++ b/tools/sdk/include/soc/include/soc/rtc_i2c_reg.h @@ -0,0 +1,288 @@ +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc.h" + +/** + * This file lists peripheral registers of an I2C controller which is part of the RTC. + * ULP coprocessor uses this controller to implement I2C_RD and I2C_WR instructions. + * + * Part of the functionality of this controller (such as slave mode, and multi-byte + * transfers) is not wired to the ULP, and is such, is not available to the + * ULP programs. + */ + +#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x000) +/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[18:0] ;default: 19'b0 ; */ +/*description: number of cycles that scl == 0 */ +#define RTC_I2C_SCL_LOW_PERIOD 0x1FFFFFF +#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S)) +#define RTC_I2C_SCL_LOW_PERIOD_V 0x1FFFFFF +#define RTC_I2C_SCL_LOW_PERIOD_S 0 + +#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x004) +/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Send LSB first */ +#define RTC_I2C_RX_LSB_FIRST BIT(7) +#define RTC_I2C_RX_LSB_FIRST_M BIT(7) +#define RTC_I2C_RX_LSB_FIRST_V (1) +#define RTC_I2C_RX_LSB_FIRST_S (7) +/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Receive LSB first */ +#define RTC_I2C_TX_LSB_FIRST BIT(6) +#define RTC_I2C_TX_LSB_FIRST_M BIT(6) +#define RTC_I2C_TX_LSB_FIRST_V (1) +#define RTC_I2C_TX_LSB_FIRST_S (6) +/* RTC_I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Force to generate start condition */ +#define RTC_I2C_TRANS_START BIT(5) +#define RTC_I2C_TRANS_START_M BIT(5) +#define RTC_I2C_TRANS_START_V (1) +#define RTC_I2C_TRANS_START_S (5) +/* RTC_I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Master (1) or slave (0) */ +#define RTC_I2C_MS_MODE BIT(4) +#define RTC_I2C_MS_MODE_M BIT(4) +#define RTC_I2C_MS_MODE_V (1) +#define RTC_I2C_MS_MODE_S (4) +/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: SCL is push-pull (1) or open-drain (0) */ +#define RTC_I2C_SCL_FORCE_OUT BIT(1) +#define RTC_I2C_SCL_FORCE_OUT_M BIT(1) +#define RTC_I2C_SCL_FORCE_OUT_V (1) +#define RTC_I2C_SCL_FORCE_OUT_S (1) +/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SDA is push-pull (1) or open-drain (0) */ +#define RTC_I2C_SDA_FORCE_OUT BIT(0) +#define RTC_I2C_SDA_FORCE_OUT_M BIT(0) +#define RTC_I2C_SDA_FORCE_OUT_V (1) +#define RTC_I2C_SDA_FORCE_OUT_S (0) + +#define RTC_I2C_DEBUG_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x008) +/* RTC_I2C_SCL_STATE : R/W ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: state of SCL state machine */ +#define RTC_I2C_SCL_STATE 0x7 +#define RTC_I2C_SCL_STATE_M ((RTC_I2C_SCL_STATE_V)<<(RTC_I2C_SCL_STATE_S)) +#define RTC_I2C_SCL_STATE_V 0x7 +#define RTC_I2C_SCL_STATE_S 28 +/* RTC_I2C_MAIN_STATE : R/W ;bitpos:[27:25] ;default: 3'b0 ; */ +/*description: state of the main state machine */ +#define RTC_I2C_MAIN_STATE 0x7 +#define RTC_I2C_MAIN_STATE_M ((RTC_I2C_MAIN_STATE_V)<<(RTC_I2C_MAIN_STATE_S)) +#define RTC_I2C_MAIN_STATE_V 0x7 +#define RTC_I2C_MAIN_STATE_S 25 +/* RTC_I2C_BYTE_TRANS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 8 bit transmit done */ +#define RTC_I2C_BYTE_TRANS BIT(6) +#define RTC_I2C_BYTE_TRANS_M BIT(6) +#define RTC_I2C_BYTE_TRANS_V (1) +#define RTC_I2C_BYTE_TRANS_S (6) +/* RTC_I2C_SLAVE_ADDR_MATCH : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: When working as a slave, whether address was matched */ +#define RTC_I2C_SLAVE_ADDR_MATCH BIT(5) +#define RTC_I2C_SLAVE_ADDR_MATCH_M BIT(5) +#define RTC_I2C_SLAVE_ADDR_MATCH_V (1) +#define RTC_I2C_SLAVE_ADDR_MATCH_S (5) +/* RTC_I2C_BUS_BUSY : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: operation is in progress */ +#define RTC_I2C_BUS_BUSY BIT(4) +#define RTC_I2C_BUS_BUSY_M BIT(4) +#define RTC_I2C_BUS_BUSY_V (1) +#define RTC_I2C_BUS_BUSY_S (4) +/* RTC_I2C_ARB_LOST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: When working as a master, lost control of I2C bus */ +#define RTC_I2C_ARB_LOST BIT(3) +#define RTC_I2C_ARB_LOST_M BIT(3) +#define RTC_I2C_ARB_LOST_V (1) +#define RTC_I2C_ARB_LOST_S (3) +/* RTC_I2C_TIMED_OUT : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Transfer has timed out */ +#define RTC_I2C_TIMED_OUT BIT(2) +#define RTC_I2C_TIMED_OUT_M BIT(2) +#define RTC_I2C_TIMED_OUT_V (1) +#define RTC_I2C_TIMED_OUT_S (2) +/* RTC_I2C_SLAVE_RW : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: When working as a slave, the value of R/W bit received */ +#define RTC_I2C_SLAVE_RW BIT(1) +#define RTC_I2C_SLAVE_RW_M BIT(1) +#define RTC_I2C_SLAVE_RW_V (1) +#define RTC_I2C_SLAVE_RW_S (1) +/* RTC_I2C_ACK_VAL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The value of an acknowledge signal on the bus */ +#define RTC_I2C_ACK_VAL BIT(0) +#define RTC_I2C_ACK_VAL_M BIT(0) +#define RTC_I2C_ACK_VAL_V (1) +#define RTC_I2C_ACK_VAL_S (0) + +#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x00c) +/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Maximum number of FAST_CLK cycles that the transmission can take */ +#define RTC_I2C_TIMEOUT 0xFFFFF +#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S)) +#define RTC_I2C_TIMEOUT_V 0xFFFFF +#define RTC_I2C_TIMEOUT_S 0 + +#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x010) +/* RTC_I2C_SLAVE_ADDR_10BIT : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set if local slave address is 10-bit */ +#define RTC_I2C_SLAVE_ADDR_10BIT BIT(31) +#define RTC_I2C_SLAVE_ADDR_10BIT_M BIT(31) +#define RTC_I2C_SLAVE_ADDR_10BIT_V (1) +#define RTC_I2C_SLAVE_ADDR_10BIT_S (31) +/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: local slave address */ +#define RTC_I2C_SLAVE_ADDR 0x7FFF +#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S)) +#define RTC_I2C_SLAVE_ADDR_V 0x7FFF +#define RTC_I2C_SLAVE_ADDR_S 0 + +/* Result of last read operation. Not used directly as the data will be + * returned to the ULP. Listed for debugging purposes. + */ +#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x01c) + +/* Interrupt registers; since the interrupt from RTC_I2C is not connected, + * these registers are only listed for debugging purposes. + */ + +/* Interrupt raw status register */ +#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x020) +/* RTC_I2C_TIME_OUT_INT_RAW : R/O ;bitpos:[7] ;default: 1'b0 ; */ +/*description: time out interrupt raw status */ +#define RTC_I2C_TIME_OUT_INT_RAW BIT(7) +#define RTC_I2C_TIME_OUT_INT_RAW_M BIT(7) +#define RTC_I2C_TIME_OUT_INT_RAW_V (1) +#define RTC_I2C_TIME_OUT_INT_RAW_S (7) +/* RTC_I2C_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Stop condition has been detected interrupt raw status */ +#define RTC_I2C_TRANS_COMPLETE_INT_RAW BIT(6) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M BIT(6) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V (1) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S (6) +/* RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW BIT(5) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_M BIT(5) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_V (1) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_S (5) +/* RTC_I2C_ARBITRATION_LOST_INT_RAW : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Master lost arbitration */ +#define RTC_I2C_ARBITRATION_LOST_INT_RAW BIT(4) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M BIT(4) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V (1) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S (4) +/* RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Slave accepted 1 byte and address matched */ +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW BIT(3) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_M BIT(3) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_V (1) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_S (3) + +/* Interrupt clear register */ +#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x024) +/* RTC_I2C_TIME_OUT_INT_CLR : W/O ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_TIME_OUT_INT_CLR BIT(8) +#define RTC_I2C_TIME_OUT_INT_CLR_M BIT(8) +#define RTC_I2C_TIME_OUT_INT_CLR_V (1) +#define RTC_I2C_TIME_OUT_INT_CLR_S (8) +/* RTC_I2C_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_TRANS_COMPLETE_INT_CLR BIT(7) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M BIT(7) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V (1) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S (7) +/* RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR BIT(6) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_M BIT(6) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_V (1) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_S (6) +/* RTC_I2C_ARBITRATION_LOST_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_ARBITRATION_LOST_INT_CLR BIT(5) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M BIT(5) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V (1) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S (5) +/* RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR BIT(4) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_M BIT(4) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_V (1) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_S (4) + +/* Interrupt enable register. + * Bit definitions are not given here, because interrupt functionality + * of RTC_I2C is not used. + */ +#define RTC_I2C_INT_EN_REG (DR_REG_RTC_I2C_BASE + 0x028) + +/* Masked interrupt status register. + * Bit definitions are not given here, because interrupt functionality + * of RTC_I2C is not used. + */ +#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x02c) + +#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x030) +/* RTC_I2C_SDA_DUTY : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Number of FAST_CLK cycles SDA will switch after falling edge of SCL */ +#define RTC_I2C_SDA_DUTY 0xFFFFF +#define RTC_I2C_SDA_DUTY_M ((RTC_I2C_SDA_DUTY_V)<<(RTC_I2C_SDA_DUTY_S)) +#define RTC_I2C_SDA_DUTY_V 0xFFFFF +#define RTC_I2C_SDA_DUTY_S 0 + +#define RTC_I2C_SCL_HIGH_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x038) +/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Number of FAST_CLK cycles for SCL to be high */ +#define RTC_I2C_SCL_HIGH_PERIOD 0xFFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S)) +#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_S 0 + +#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x040) +/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Number of FAST_CLK cycles to wait before generating start condition */ +#define RTC_I2C_SCL_START_PERIOD 0xFFFFF +#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S)) +#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_START_PERIOD_S 0 + +#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x044) +/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Number of FAST_CLK cycles to wait before generating stop condition */ +#define RTC_I2C_SCL_STOP_PERIOD 0xFFFFF +#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S)) +#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_STOP_PERIOD_S 0 + +/* A block of 16 RTC_I2C_CMD registers which describe I2C operation to be + * performed. Unused when ULP is controlling RTC_I2C. + */ +#define RTC_I2C_CMD_REG_COUNT 16 +#define RTC_I2C_CMD_REG(i) (DR_REG_RTC_I2C_BASE + 0x048 + (i) * 4) +/* RTC_I2C_CMD_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Bit is set by HW when command is done */ +#define RTC_I2C_CMD_DONE BIT(31) +#define RTC_I2C_CMD_DONE_M BIT(31) +#define RTC_I2C_CMD_DONE_V (1) +#define RTC_I2C_CMD_DONE_S (31) +/* RTC_I2C_VAL : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: Command content */ +#define RTC_I2C_VAL 0 +#define RTC_I2C_VAL_M ((RTC_I2C_VAL_V)<<(RTC_I2C_VAL_S)) +#define RTC_I2C_VAL_V 0x3FFF +#define RTC_I2C_VAL_S 0 + diff --git a/tools/sdk/include/soc/include/soc/rtc_io_reg.h b/tools/sdk/include/soc/include/soc/rtc_io_reg.h new file mode 100644 index 00000000000..5a3ce10d422 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/rtc_io_reg.h @@ -0,0 +1,1954 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_IO_REG_H_ +#define _SOC_RTC_IO_REG_H_ + + +#include "soc.h" +#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) +/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value*/ +#define RTC_GPIO_OUT_DATA 0x0003FFFF +#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S)) +#define RTC_GPIO_OUT_DATA_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_S 14 + +#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) +/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value write 1 to set*/ +#define RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF +#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S)) +#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_W1TS_S 14 + +#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) +/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value write 1 to clear*/ +#define RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF +#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S)) +#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_W1TC_S 14 + +#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) +/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable*/ +#define RTC_GPIO_ENABLE 0x0003FFFF +#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S)) +#define RTC_GPIO_ENABLE_V 0x3FFFF +#define RTC_GPIO_ENABLE_S 14 + +#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) +/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable write 1 to set*/ +#define RTC_GPIO_ENABLE_W1TS 0x0003FFFF +#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S)) +#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFF +#define RTC_GPIO_ENABLE_W1TS_S 14 + +#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) +/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable write 1 to clear*/ +#define RTC_GPIO_ENABLE_W1TC 0x0003FFFF +#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S)) +#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFF +#define RTC_GPIO_ENABLE_W1TC_S 14 + +#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) +/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status*/ +#define RTC_GPIO_STATUS_INT 0x0003FFFF +#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S)) +#define RTC_GPIO_STATUS_INT_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_S 14 + +#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) +/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status write 1 to set*/ +#define RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF +#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S)) +#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_W1TS_S 14 + +#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) +/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status write 1 to clear*/ +#define RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF +#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S)) +#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_W1TC_S 14 + +#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) +/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default: ; */ +/*description: GPIO0~17 input value*/ +#define RTC_GPIO_IN_NEXT 0x0003FFFF +#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S)) +#define RTC_GPIO_IN_NEXT_V 0x3FFFF +#define RTC_GPIO_IN_NEXT_S 14 + +#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) +/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S)) +#define RTC_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN0_INT_TYPE_S 7 +/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN0_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) +/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S)) +#define RTC_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN1_INT_TYPE_S 7 +/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN1_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) +/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S)) +#define RTC_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN2_INT_TYPE_S 7 +/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN2_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) +/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S)) +#define RTC_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN3_INT_TYPE_S 7 +/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN3_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) +/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S)) +#define RTC_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN4_INT_TYPE_S 7 +/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN4_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) +/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S)) +#define RTC_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN5_INT_TYPE_S 7 +/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN5_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) +/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN6_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S)) +#define RTC_GPIO_PIN6_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN6_INT_TYPE_S 7 +/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN6_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) +/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN7_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S)) +#define RTC_GPIO_PIN7_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN7_INT_TYPE_S 7 +/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN7_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) +/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN8_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S)) +#define RTC_GPIO_PIN8_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN8_INT_TYPE_S 7 +/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN8_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) +/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN9_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S)) +#define RTC_GPIO_PIN9_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN9_INT_TYPE_S 7 +/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN9_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) +/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN10_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S)) +#define RTC_GPIO_PIN10_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN10_INT_TYPE_S 7 +/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN10_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) +/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN11_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S)) +#define RTC_GPIO_PIN11_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN11_INT_TYPE_S 7 +/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN11_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) +/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN12_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S)) +#define RTC_GPIO_PIN12_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN12_INT_TYPE_S 7 +/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN12_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) +/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN13_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S)) +#define RTC_GPIO_PIN13_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN13_INT_TYPE_S 7 +/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN13_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) +/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN14_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S)) +#define RTC_GPIO_PIN14_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN14_INT_TYPE_S 7 +/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN14_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) +/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN15_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S)) +#define RTC_GPIO_PIN15_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN15_INT_TYPE_S 7 +/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN15_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) +/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN16_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S)) +#define RTC_GPIO_PIN16_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN16_INT_TYPE_S 7 +/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN16_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) +/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN17_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S)) +#define RTC_GPIO_PIN17_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN17_INT_TYPE_S 7 +/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN17_PAD_DRIVER_S 2 + +#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70) +/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_IO_DEBUG_12M_NO_GATING_S 25 +/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL4 0x0000001F +#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S)) +#define RTC_IO_DEBUG_SEL4_V 0x1F +#define RTC_IO_DEBUG_SEL4_S 20 +/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL3 0x0000001F +#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S)) +#define RTC_IO_DEBUG_SEL3_V 0x1F +#define RTC_IO_DEBUG_SEL3_S 15 +/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL2 0x0000001F +#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S)) +#define RTC_IO_DEBUG_SEL2_V 0x1F +#define RTC_IO_DEBUG_SEL2_S 10 +/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL1 0x0000001F +#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S)) +#define RTC_IO_DEBUG_SEL1_V 0x1F +#define RTC_IO_DEBUG_SEL1_S 5 +/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL0 0x0000001F +#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S)) +#define RTC_IO_DEBUG_SEL0_V 0x1F +#define RTC_IO_DEBUG_SEL0_S 0 +#define RTC_IO_DEBUG_SEL0_8M 1 +#define RTC_IO_DEBUG_SEL0_32K_XTAL 4 +#define RTC_IO_DEBUG_SEL0_150K_OSC 5 + +#define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) +/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */ +/*description: select the digital pad hold value.*/ +#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_IO_DIG_PAD_HOLD_M ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S)) +#define RTC_IO_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_IO_DIG_PAD_HOLD_S 0 + +#define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78) +/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Power on hall sensor and connect to VP and VN*/ +#define RTC_IO_XPD_HALL (BIT(31)) +#define RTC_IO_XPD_HALL_M (BIT(31)) +#define RTC_IO_XPD_HALL_V 0x1 +#define RTC_IO_XPD_HALL_S 31 +/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: Reverse phase of hall sensor*/ +#define RTC_IO_HALL_PHASE (BIT(30)) +#define RTC_IO_HALL_PHASE_M (BIT(30)) +#define RTC_IO_HALL_PHASE_V 0x1 +#define RTC_IO_HALL_PHASE_S 30 + +#define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c) +/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE1_HOLD (BIT(31)) +#define RTC_IO_SENSE1_HOLD_M (BIT(31)) +#define RTC_IO_SENSE1_HOLD_V 0x1 +#define RTC_IO_SENSE1_HOLD_S 31 +/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE2_HOLD (BIT(30)) +#define RTC_IO_SENSE2_HOLD_M (BIT(30)) +#define RTC_IO_SENSE2_HOLD_V 0x1 +#define RTC_IO_SENSE2_HOLD_S 30 +/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE3_HOLD (BIT(29)) +#define RTC_IO_SENSE3_HOLD_M (BIT(29)) +#define RTC_IO_SENSE3_HOLD_V 0x1 +#define RTC_IO_SENSE3_HOLD_S 29 +/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE4_HOLD (BIT(28)) +#define RTC_IO_SENSE4_HOLD_M (BIT(28)) +#define RTC_IO_SENSE4_HOLD_V 0x1 +#define RTC_IO_SENSE4_HOLD_S 28 +/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE1_MUX_SEL (BIT(27)) +#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27)) +#define RTC_IO_SENSE1_MUX_SEL_V 0x1 +#define RTC_IO_SENSE1_MUX_SEL_S 27 +/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE2_MUX_SEL (BIT(26)) +#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26)) +#define RTC_IO_SENSE2_MUX_SEL_V 0x1 +#define RTC_IO_SENSE2_MUX_SEL_S 26 +/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE3_MUX_SEL (BIT(25)) +#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25)) +#define RTC_IO_SENSE3_MUX_SEL_V 0x1 +#define RTC_IO_SENSE3_MUX_SEL_S 25 +/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE4_MUX_SEL (BIT(24)) +#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24)) +#define RTC_IO_SENSE4_MUX_SEL_V 0x1 +#define RTC_IO_SENSE4_MUX_SEL_S 24 +/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE1_FUN_SEL 0x00000003 +#define RTC_IO_SENSE1_FUN_SEL_M ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S)) +#define RTC_IO_SENSE1_FUN_SEL_V 0x3 +#define RTC_IO_SENSE1_FUN_SEL_S 22 +/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE1_SLP_SEL (BIT(21)) +#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21)) +#define RTC_IO_SENSE1_SLP_SEL_V 0x1 +#define RTC_IO_SENSE1_SLP_SEL_S 21 +/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE1_SLP_IE (BIT(20)) +#define RTC_IO_SENSE1_SLP_IE_M (BIT(20)) +#define RTC_IO_SENSE1_SLP_IE_V 0x1 +#define RTC_IO_SENSE1_SLP_IE_S 20 +/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE1_FUN_IE (BIT(19)) +#define RTC_IO_SENSE1_FUN_IE_M (BIT(19)) +#define RTC_IO_SENSE1_FUN_IE_V 0x1 +#define RTC_IO_SENSE1_FUN_IE_S 19 +/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE2_FUN_SEL 0x00000003 +#define RTC_IO_SENSE2_FUN_SEL_M ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S)) +#define RTC_IO_SENSE2_FUN_SEL_V 0x3 +#define RTC_IO_SENSE2_FUN_SEL_S 17 +/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE2_SLP_SEL (BIT(16)) +#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16)) +#define RTC_IO_SENSE2_SLP_SEL_V 0x1 +#define RTC_IO_SENSE2_SLP_SEL_S 16 +/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE2_SLP_IE (BIT(15)) +#define RTC_IO_SENSE2_SLP_IE_M (BIT(15)) +#define RTC_IO_SENSE2_SLP_IE_V 0x1 +#define RTC_IO_SENSE2_SLP_IE_S 15 +/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE2_FUN_IE (BIT(14)) +#define RTC_IO_SENSE2_FUN_IE_M (BIT(14)) +#define RTC_IO_SENSE2_FUN_IE_V 0x1 +#define RTC_IO_SENSE2_FUN_IE_S 14 +/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE3_FUN_SEL 0x00000003 +#define RTC_IO_SENSE3_FUN_SEL_M ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S)) +#define RTC_IO_SENSE3_FUN_SEL_V 0x3 +#define RTC_IO_SENSE3_FUN_SEL_S 12 +/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE3_SLP_SEL (BIT(11)) +#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11)) +#define RTC_IO_SENSE3_SLP_SEL_V 0x1 +#define RTC_IO_SENSE3_SLP_SEL_S 11 +/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE3_SLP_IE (BIT(10)) +#define RTC_IO_SENSE3_SLP_IE_M (BIT(10)) +#define RTC_IO_SENSE3_SLP_IE_V 0x1 +#define RTC_IO_SENSE3_SLP_IE_S 10 +/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE3_FUN_IE (BIT(9)) +#define RTC_IO_SENSE3_FUN_IE_M (BIT(9)) +#define RTC_IO_SENSE3_FUN_IE_V 0x1 +#define RTC_IO_SENSE3_FUN_IE_S 9 +/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE4_FUN_SEL 0x00000003 +#define RTC_IO_SENSE4_FUN_SEL_M ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S)) +#define RTC_IO_SENSE4_FUN_SEL_V 0x3 +#define RTC_IO_SENSE4_FUN_SEL_S 7 +/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE4_SLP_SEL (BIT(6)) +#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6)) +#define RTC_IO_SENSE4_SLP_SEL_V 0x1 +#define RTC_IO_SENSE4_SLP_SEL_S 6 +/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE4_SLP_IE (BIT(5)) +#define RTC_IO_SENSE4_SLP_IE_M (BIT(5)) +#define RTC_IO_SENSE4_SLP_IE_V 0x1 +#define RTC_IO_SENSE4_SLP_IE_S 5 +/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE4_FUN_IE (BIT(4)) +#define RTC_IO_SENSE4_FUN_IE_M (BIT(4)) +#define RTC_IO_SENSE4_FUN_IE_V 0x1 +#define RTC_IO_SENSE4_FUN_IE_S 4 + +#define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80) +/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_ADC1_HOLD (BIT(31)) +#define RTC_IO_ADC1_HOLD_M (BIT(31)) +#define RTC_IO_ADC1_HOLD_V 0x1 +#define RTC_IO_ADC1_HOLD_S 31 +/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_ADC2_HOLD (BIT(30)) +#define RTC_IO_ADC2_HOLD_M (BIT(30)) +#define RTC_IO_ADC2_HOLD_V 0x1 +#define RTC_IO_ADC2_HOLD_S 30 +/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_ADC1_MUX_SEL (BIT(29)) +#define RTC_IO_ADC1_MUX_SEL_M (BIT(29)) +#define RTC_IO_ADC1_MUX_SEL_V 0x1 +#define RTC_IO_ADC1_MUX_SEL_S 29 +/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_ADC2_MUX_SEL (BIT(28)) +#define RTC_IO_ADC2_MUX_SEL_M (BIT(28)) +#define RTC_IO_ADC2_MUX_SEL_V 0x1 +#define RTC_IO_ADC2_MUX_SEL_S 28 +/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_ADC1_FUN_SEL 0x00000003 +#define RTC_IO_ADC1_FUN_SEL_M ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S)) +#define RTC_IO_ADC1_FUN_SEL_V 0x3 +#define RTC_IO_ADC1_FUN_SEL_S 26 +/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_ADC1_SLP_SEL (BIT(25)) +#define RTC_IO_ADC1_SLP_SEL_M (BIT(25)) +#define RTC_IO_ADC1_SLP_SEL_V 0x1 +#define RTC_IO_ADC1_SLP_SEL_S 25 +/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_ADC1_SLP_IE (BIT(24)) +#define RTC_IO_ADC1_SLP_IE_M (BIT(24)) +#define RTC_IO_ADC1_SLP_IE_V 0x1 +#define RTC_IO_ADC1_SLP_IE_S 24 +/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_ADC1_FUN_IE (BIT(23)) +#define RTC_IO_ADC1_FUN_IE_M (BIT(23)) +#define RTC_IO_ADC1_FUN_IE_V 0x1 +#define RTC_IO_ADC1_FUN_IE_S 23 +/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_ADC2_FUN_SEL 0x00000003 +#define RTC_IO_ADC2_FUN_SEL_M ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S)) +#define RTC_IO_ADC2_FUN_SEL_V 0x3 +#define RTC_IO_ADC2_FUN_SEL_S 21 +/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_ADC2_SLP_SEL (BIT(20)) +#define RTC_IO_ADC2_SLP_SEL_M (BIT(20)) +#define RTC_IO_ADC2_SLP_SEL_V 0x1 +#define RTC_IO_ADC2_SLP_SEL_S 20 +/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_ADC2_SLP_IE (BIT(19)) +#define RTC_IO_ADC2_SLP_IE_M (BIT(19)) +#define RTC_IO_ADC2_SLP_IE_V 0x1 +#define RTC_IO_ADC2_SLP_IE_S 19 +/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_ADC2_FUN_IE (BIT(18)) +#define RTC_IO_ADC2_FUN_IE_M (BIT(18)) +#define RTC_IO_ADC2_FUN_IE_V 0x1 +#define RTC_IO_ADC2_FUN_IE_S 18 + +#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84) +/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_PDAC1_DRV 0x00000003 +#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S)) +#define RTC_IO_PDAC1_DRV_V 0x3 +#define RTC_IO_PDAC1_DRV_S 30 +/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_PDAC1_HOLD (BIT(29)) +#define RTC_IO_PDAC1_HOLD_M (BIT(29)) +#define RTC_IO_PDAC1_HOLD_V 0x1 +#define RTC_IO_PDAC1_HOLD_S 29 +/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_PDAC1_RDE (BIT(28)) +#define RTC_IO_PDAC1_RDE_M (BIT(28)) +#define RTC_IO_PDAC1_RDE_V 0x1 +#define RTC_IO_PDAC1_RDE_S 28 +/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_PDAC1_RUE (BIT(27)) +#define RTC_IO_PDAC1_RUE_M (BIT(27)) +#define RTC_IO_PDAC1_RUE_V 0x1 +#define RTC_IO_PDAC1_RUE_S 27 +/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: PAD DAC1 control code.*/ +#define RTC_IO_PDAC1_DAC 0x000000FF +#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S)) +#define RTC_IO_PDAC1_DAC_V 0xFF +#define RTC_IO_PDAC1_DAC_S 19 +/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC1_XPD_DAC (BIT(18)) +#define RTC_IO_PDAC1_XPD_DAC_M (BIT(18)) +#define RTC_IO_PDAC1_XPD_DAC_V 0x1 +#define RTC_IO_PDAC1_XPD_DAC_S 18 +/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_PDAC1_MUX_SEL (BIT(17)) +#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17)) +#define RTC_IO_PDAC1_MUX_SEL_V 0x1 +#define RTC_IO_PDAC1_MUX_SEL_S 17 +/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_PDAC1_FUN_SEL 0x00000003 +#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S)) +#define RTC_IO_PDAC1_FUN_SEL_V 0x3 +#define RTC_IO_PDAC1_FUN_SEL_S 15 +/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_PDAC1_SLP_SEL (BIT(14)) +#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14)) +#define RTC_IO_PDAC1_SLP_SEL_V 0x1 +#define RTC_IO_PDAC1_SLP_SEL_S 14 +/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_PDAC1_SLP_IE (BIT(13)) +#define RTC_IO_PDAC1_SLP_IE_M (BIT(13)) +#define RTC_IO_PDAC1_SLP_IE_V 0x1 +#define RTC_IO_PDAC1_SLP_IE_S 13 +/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_PDAC1_SLP_OE (BIT(12)) +#define RTC_IO_PDAC1_SLP_OE_M (BIT(12)) +#define RTC_IO_PDAC1_SLP_OE_V 0x1 +#define RTC_IO_PDAC1_SLP_OE_S 12 +/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_PDAC1_FUN_IE (BIT(11)) +#define RTC_IO_PDAC1_FUN_IE_M (BIT(11)) +#define RTC_IO_PDAC1_FUN_IE_V 0x1 +#define RTC_IO_PDAC1_FUN_IE_S 11 +/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10 + +#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88) +/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_PDAC2_DRV 0x00000003 +#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S)) +#define RTC_IO_PDAC2_DRV_V 0x3 +#define RTC_IO_PDAC2_DRV_S 30 +/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_PDAC2_HOLD (BIT(29)) +#define RTC_IO_PDAC2_HOLD_M (BIT(29)) +#define RTC_IO_PDAC2_HOLD_V 0x1 +#define RTC_IO_PDAC2_HOLD_S 29 +/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_PDAC2_RDE (BIT(28)) +#define RTC_IO_PDAC2_RDE_M (BIT(28)) +#define RTC_IO_PDAC2_RDE_V 0x1 +#define RTC_IO_PDAC2_RDE_S 28 +/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_PDAC2_RUE (BIT(27)) +#define RTC_IO_PDAC2_RUE_M (BIT(27)) +#define RTC_IO_PDAC2_RUE_V 0x1 +#define RTC_IO_PDAC2_RUE_S 27 +/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: PAD DAC2 control code.*/ +#define RTC_IO_PDAC2_DAC 0x000000FF +#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S)) +#define RTC_IO_PDAC2_DAC_V 0xFF +#define RTC_IO_PDAC2_DAC_S 19 +/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC2_XPD_DAC (BIT(18)) +#define RTC_IO_PDAC2_XPD_DAC_M (BIT(18)) +#define RTC_IO_PDAC2_XPD_DAC_V 0x1 +#define RTC_IO_PDAC2_XPD_DAC_S 18 +/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_PDAC2_MUX_SEL (BIT(17)) +#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17)) +#define RTC_IO_PDAC2_MUX_SEL_V 0x1 +#define RTC_IO_PDAC2_MUX_SEL_S 17 +/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_PDAC2_FUN_SEL 0x00000003 +#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S)) +#define RTC_IO_PDAC2_FUN_SEL_V 0x3 +#define RTC_IO_PDAC2_FUN_SEL_S 15 +/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_PDAC2_SLP_SEL (BIT(14)) +#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14)) +#define RTC_IO_PDAC2_SLP_SEL_V 0x1 +#define RTC_IO_PDAC2_SLP_SEL_S 14 +/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_PDAC2_SLP_IE (BIT(13)) +#define RTC_IO_PDAC2_SLP_IE_M (BIT(13)) +#define RTC_IO_PDAC2_SLP_IE_V 0x1 +#define RTC_IO_PDAC2_SLP_IE_S 13 +/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_PDAC2_SLP_OE (BIT(12)) +#define RTC_IO_PDAC2_SLP_OE_M (BIT(12)) +#define RTC_IO_PDAC2_SLP_OE_V 0x1 +#define RTC_IO_PDAC2_SLP_OE_S 12 +/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_PDAC2_FUN_IE (BIT(11)) +#define RTC_IO_PDAC2_FUN_IE_M (BIT(11)) +#define RTC_IO_PDAC2_FUN_IE_V 0x1 +#define RTC_IO_PDAC2_FUN_IE_S 11 +/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Power on DAC2. Usually we need to tristate PDAC2 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10 + +#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) +/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_X32N_DRV 0x00000003 +#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S)) +#define RTC_IO_X32N_DRV_V 0x3 +#define RTC_IO_X32N_DRV_S 30 +/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_X32N_HOLD (BIT(29)) +#define RTC_IO_X32N_HOLD_M (BIT(29)) +#define RTC_IO_X32N_HOLD_V 0x1 +#define RTC_IO_X32N_HOLD_S 29 +/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_X32N_RDE (BIT(28)) +#define RTC_IO_X32N_RDE_M (BIT(28)) +#define RTC_IO_X32N_RDE_V 0x1 +#define RTC_IO_X32N_RDE_S 28 +/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_X32N_RUE (BIT(27)) +#define RTC_IO_X32N_RUE_M (BIT(27)) +#define RTC_IO_X32N_RUE_V 0x1 +#define RTC_IO_X32N_RUE_S 27 +/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_X32P_DRV 0x00000003 +#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S)) +#define RTC_IO_X32P_DRV_V 0x3 +#define RTC_IO_X32P_DRV_S 25 +/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_X32P_HOLD (BIT(24)) +#define RTC_IO_X32P_HOLD_M (BIT(24)) +#define RTC_IO_X32P_HOLD_V 0x1 +#define RTC_IO_X32P_HOLD_S 24 +/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_X32P_RDE (BIT(23)) +#define RTC_IO_X32P_RDE_M (BIT(23)) +#define RTC_IO_X32P_RDE_V 0x1 +#define RTC_IO_X32P_RDE_S 23 +/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_X32P_RUE (BIT(22)) +#define RTC_IO_X32P_RUE_M (BIT(22)) +#define RTC_IO_X32P_RUE_V 0x1 +#define RTC_IO_X32P_RUE_S 22 +/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */ +/*description: 32K XTAL bias current DAC.*/ +#define RTC_IO_DAC_XTAL_32K 0x00000003 +#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S)) +#define RTC_IO_DAC_XTAL_32K_V 0x3 +#define RTC_IO_DAC_XTAL_32K_S 20 +/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Power up 32kHz crystal oscillator*/ +#define RTC_IO_XPD_XTAL_32K (BIT(19)) +#define RTC_IO_XPD_XTAL_32K_M (BIT(19)) +#define RTC_IO_XPD_XTAL_32K_V 0x1 +#define RTC_IO_XPD_XTAL_32K_S 19 +/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_X32N_MUX_SEL (BIT(18)) +#define RTC_IO_X32N_MUX_SEL_M (BIT(18)) +#define RTC_IO_X32N_MUX_SEL_V 0x1 +#define RTC_IO_X32N_MUX_SEL_S 18 +/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_X32P_MUX_SEL (BIT(17)) +#define RTC_IO_X32P_MUX_SEL_M (BIT(17)) +#define RTC_IO_X32P_MUX_SEL_V 0x1 +#define RTC_IO_X32P_MUX_SEL_S 17 +/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_X32N_FUN_SEL 0x00000003 +#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S)) +#define RTC_IO_X32N_FUN_SEL_V 0x3 +#define RTC_IO_X32N_FUN_SEL_S 15 +/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_X32N_SLP_SEL (BIT(14)) +#define RTC_IO_X32N_SLP_SEL_M (BIT(14)) +#define RTC_IO_X32N_SLP_SEL_V 0x1 +#define RTC_IO_X32N_SLP_SEL_S 14 +/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_X32N_SLP_IE (BIT(13)) +#define RTC_IO_X32N_SLP_IE_M (BIT(13)) +#define RTC_IO_X32N_SLP_IE_V 0x1 +#define RTC_IO_X32N_SLP_IE_S 13 +/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_X32N_SLP_OE (BIT(12)) +#define RTC_IO_X32N_SLP_OE_M (BIT(12)) +#define RTC_IO_X32N_SLP_OE_V 0x1 +#define RTC_IO_X32N_SLP_OE_S 12 +/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_X32N_FUN_IE (BIT(11)) +#define RTC_IO_X32N_FUN_IE_M (BIT(11)) +#define RTC_IO_X32N_FUN_IE_V 0x1 +#define RTC_IO_X32N_FUN_IE_S 11 +/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_X32P_FUN_SEL 0x00000003 +#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S)) +#define RTC_IO_X32P_FUN_SEL_V 0x3 +#define RTC_IO_X32P_FUN_SEL_S 9 +/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_X32P_SLP_SEL (BIT(8)) +#define RTC_IO_X32P_SLP_SEL_M (BIT(8)) +#define RTC_IO_X32P_SLP_SEL_V 0x1 +#define RTC_IO_X32P_SLP_SEL_S 8 +/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_X32P_SLP_IE (BIT(7)) +#define RTC_IO_X32P_SLP_IE_M (BIT(7)) +#define RTC_IO_X32P_SLP_IE_V 0x1 +#define RTC_IO_X32P_SLP_IE_S 7 +/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_X32P_SLP_OE (BIT(6)) +#define RTC_IO_X32P_SLP_OE_M (BIT(6)) +#define RTC_IO_X32P_SLP_OE_V 0x1 +#define RTC_IO_X32P_SLP_OE_S 6 +/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_X32P_FUN_IE (BIT(5)) +#define RTC_IO_X32P_FUN_IE_M (BIT(5)) +#define RTC_IO_X32P_FUN_IE_V 0x1 +#define RTC_IO_X32P_FUN_IE_S 5 +/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */ +/*description: 32K XTAL resistor bias control.*/ +#define RTC_IO_DRES_XTAL_32K 0x00000003 +#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S)) +#define RTC_IO_DRES_XTAL_32K_V 0x3 +#define RTC_IO_DRES_XTAL_32K_S 3 +/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */ +/*description: 32K XTAL self-bias reference control.*/ +#define RTC_IO_DBIAS_XTAL_32K 0x00000003 +#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S)) +#define RTC_IO_DBIAS_XTAL_32K_V 0x3 +#define RTC_IO_DBIAS_XTAL_32K_S 1 + +#define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90) +/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: touch sensor bias power on.*/ +#define RTC_IO_TOUCH_XPD_BIAS (BIT(31)) +#define RTC_IO_TOUCH_XPD_BIAS_M (BIT(31)) +#define RTC_IO_TOUCH_XPD_BIAS_V 0x1 +#define RTC_IO_TOUCH_XPD_BIAS_S 31 +/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */ +/*description: touch sensor saw wave top voltage.*/ +#define RTC_IO_TOUCH_DREFH 0x00000003 +#define RTC_IO_TOUCH_DREFH_M ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S)) +#define RTC_IO_TOUCH_DREFH_V 0x3 +#define RTC_IO_TOUCH_DREFH_S 29 +/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: touch sensor saw wave bottom voltage.*/ +#define RTC_IO_TOUCH_DREFL 0x00000003 +#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S)) +#define RTC_IO_TOUCH_DREFL_V 0x3 +#define RTC_IO_TOUCH_DREFL_S 27 +/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */ +/*description: touch sensor saw wave voltage range.*/ +#define RTC_IO_TOUCH_DRANGE 0x00000003 +#define RTC_IO_TOUCH_DRANGE_M ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S)) +#define RTC_IO_TOUCH_DRANGE_V 0x3 +#define RTC_IO_TOUCH_DRANGE_S 25 +/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */ +/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When + BIAS_SLEEP this setting is available*/ +#define RTC_IO_TOUCH_DCUR 0x00000003 +#define RTC_IO_TOUCH_DCUR_M ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S)) +#define RTC_IO_TOUCH_DCUR_V 0x3 +#define RTC_IO_TOUCH_DCUR_S 23 + +#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94) +/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD0_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD0_HOLD_S 31 +/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD0_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S)) +#define RTC_IO_TOUCH_PAD0_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD0_DRV_S 29 +/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RDE_S 28 +/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RUE_S 27 +/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD0_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S)) +#define RTC_IO_TOUCH_PAD0_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD0_DAC_S 23 +/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD0_START (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_V 0x1 +#define RTC_IO_TOUCH_PAD0_START_S 22 +/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD0_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD0_XPD_S 20 +/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/ +#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98) +/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD1_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD1_HOLD_S 31 +/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD1_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S)) +#define RTC_IO_TOUCH_PAD1_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD1_DRV_S 29 +/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RDE_S 28 +/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RUE_S 27 +/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD1_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S)) +#define RTC_IO_TOUCH_PAD1_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD1_DAC_S 23 +/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD1_START (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_V 0x1 +#define RTC_IO_TOUCH_PAD1_START_S 22 +/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD1_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD1_XPD_S 20 +/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/ +#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c) +/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD2_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD2_HOLD_S 31 +/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD2_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S)) +#define RTC_IO_TOUCH_PAD2_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD2_DRV_S 29 +/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RDE_S 28 +/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RUE_S 27 +/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD2_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S)) +#define RTC_IO_TOUCH_PAD2_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD2_DAC_S 23 +/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD2_START (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_V 0x1 +#define RTC_IO_TOUCH_PAD2_START_S 22 +/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD2_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD2_XPD_S 20 +/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/ +#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0) +/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD3_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD3_HOLD_S 31 +/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD3_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S)) +#define RTC_IO_TOUCH_PAD3_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD3_DRV_S 29 +/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RDE_S 28 +/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RUE_S 27 +/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD3_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S)) +#define RTC_IO_TOUCH_PAD3_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD3_DAC_S 23 +/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD3_START (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_V 0x1 +#define RTC_IO_TOUCH_PAD3_START_S 22 +/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD3_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD3_XPD_S 20 +/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/ +#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4) +/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD4_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD4_HOLD_S 31 +/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD4_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S)) +#define RTC_IO_TOUCH_PAD4_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD4_DRV_S 29 +/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RDE_S 28 +/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RUE_S 27 +/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD4_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S)) +#define RTC_IO_TOUCH_PAD4_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD4_DAC_S 23 +/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD4_START (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_V 0x1 +#define RTC_IO_TOUCH_PAD4_START_S 22 +/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD4_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD4_XPD_S 20 +/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/ +#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8) +/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD5_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD5_HOLD_S 31 +/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD5_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S)) +#define RTC_IO_TOUCH_PAD5_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD5_DRV_S 29 +/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RDE_S 28 +/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RUE_S 27 +/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD5_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S)) +#define RTC_IO_TOUCH_PAD5_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD5_DAC_S 23 +/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD5_START (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_V 0x1 +#define RTC_IO_TOUCH_PAD5_START_S 22 +/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD5_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD5_XPD_S 20 +/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/ +#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac) +/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD6_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD6_HOLD_S 31 +/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD6_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S)) +#define RTC_IO_TOUCH_PAD6_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD6_DRV_S 29 +/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RDE_S 28 +/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RUE_S 27 +/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD6_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S)) +#define RTC_IO_TOUCH_PAD6_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD6_DAC_S 23 +/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD6_START (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_V 0x1 +#define RTC_IO_TOUCH_PAD6_START_S 22 +/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD6_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD6_XPD_S 20 +/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/ +#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0) +/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD7_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD7_HOLD_S 31 +/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD7_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S)) +#define RTC_IO_TOUCH_PAD7_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD7_DRV_S 29 +/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RDE_S 28 +/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RUE_S 27 +/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD7_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S)) +#define RTC_IO_TOUCH_PAD7_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD7_DAC_S 23 +/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD7_START (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_V 0x1 +#define RTC_IO_TOUCH_PAD7_START_S 22 +/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD7_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD7_XPD_S 20 +/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/ +#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4) +/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD8_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S)) +#define RTC_IO_TOUCH_PAD8_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD8_DAC_S 23 +/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD8_START (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_V 0x1 +#define RTC_IO_TOUCH_PAD8_START_S 22 +/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD8_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD8_XPD_S 20 +/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ +#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19)) +#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19)) +#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19 + +#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8) +/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD9_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S)) +#define RTC_IO_TOUCH_PAD9_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD9_DAC_S 23 +/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD9_START (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_V 0x1 +#define RTC_IO_TOUCH_PAD9_START_S 22 +/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD9_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD9_XPD_S 20 +/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ +#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19)) +#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19)) +#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19 + +#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) +/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ +#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F +#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) +#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F +#define RTC_IO_EXT_WAKEUP0_SEL_S 27 + +#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) +/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select + GPIO2 ...Ò17Ó select GPIO17*/ +#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F +#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S)) +#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F +#define RTC_IO_XTL_EXT_CTR_SEL_S 27 + +#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4) +/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/ +#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S)) +#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SDA_SEL_S 30 +/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/ +#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S)) +#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SCL_SEL_S 28 +/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */ +/*description: */ +#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F +#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S)) +#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F +#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 + +#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8) +/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */ +/*description: date*/ +#define RTC_IO_IO_DATE 0x0FFFFFFF +#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S)) +#define RTC_IO_IO_DATE_V 0xFFFFFFF +#define RTC_IO_IO_DATE_S 0 +#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160 + + + + +#endif /*_SOC_RTC_IO_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/rtc_io_struct.h b/tools/sdk/include/soc/include/soc/rtc_io_struct.h new file mode 100644 index 00000000000..d82f1bd8c04 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/rtc_io_struct.h @@ -0,0 +1,293 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_IO_STRUCT_H_ +#define _SOC_RTC_IO_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t reserved0: 14; + uint32_t data:18; /*GPIO0~17 output value*/ + }; + uint32_t val; + } out; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 output value write 1 to set*/ + }; + uint32_t val; + } out_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 output value write 1 to clear*/ + }; + uint32_t val; + } out_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t enable:18; /*GPIO0~17 output enable*/ + }; + uint32_t val; + } enable; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 output enable write 1 to set*/ + }; + uint32_t val; + } enable_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 output enable write 1 to clear*/ + }; + uint32_t val; + } enable_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t status:18; /*GPIO0~17 interrupt status*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 interrupt status write 1 to set*/ + }; + uint32_t val; + } status_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 interrupt status write 1 to clear*/ + }; + uint32_t val; + } status_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t in:18; /*GPIO0~17 input value*/ + }; + uint32_t val; + } in_val; + union { + struct { + uint32_t reserved0: 2; + uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + uint32_t reserved3: 4; + uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + uint32_t reserved11: 21; + }; + uint32_t val; + } pin[18]; + union { + struct { + uint32_t sel0: 5; + uint32_t sel1: 5; + uint32_t sel2: 5; + uint32_t sel3: 5; + uint32_t sel4: 5; + uint32_t no_gating_12m: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } debug_sel; + uint32_t dig_pad_hold; /*select the digital pad hold value.*/ + union { + struct { + uint32_t reserved0: 30; + uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/ + uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ + }; + uint32_t val; + } hall_sens; + union { + struct { + uint32_t reserved0: 4; + uint32_t sense4_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense4_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense4_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense4_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense3_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense3_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense3_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense3_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense2_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense2_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense2_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense2_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense1_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense1_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense1_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense1_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense4_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense3_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense2_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense1_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense4_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense3_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense2_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense1_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } sensor_pads; + union { + struct { + uint32_t reserved0: 18; + uint32_t adc2_fun_ie: 1; /*the input enable of the pad*/ + uint32_t adc2_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t adc2_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t adc2_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t adc1_fun_ie: 1; /*the input enable of the pad*/ + uint32_t adc1_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t adc1_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t adc1_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t adc2_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t adc1_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t adc2_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t adc1_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } adc_pad; + union { + struct { + uint32_t reserved0: 10; + uint32_t dac_xpd_force: 1; /*Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ + uint32_t fun_ie: 1; /*the input enable of the pad*/ + uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd_dac: 1; /*Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ + uint32_t dac: 8; /*PAD DAC1 control code.*/ + uint32_t rue: 1; /*the pull up enable of the pad*/ + uint32_t rde: 1; /*the pull down enable of the pad*/ + uint32_t hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t drv: 2; /*the driver strength of the pad*/ + }; + uint32_t val; + } pad_dac[2]; + union { + struct { + uint32_t reserved0: 1; + uint32_t dbias_xtal_32k: 2; /*32K XTAL self-bias reference control.*/ + uint32_t dres_xtal_32k: 2; /*32K XTAL resistor bias control.*/ + uint32_t x32p_fun_ie: 1; /*the input enable of the pad*/ + uint32_t x32p_slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t x32p_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t x32p_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t x32p_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t x32n_fun_ie: 1; /*the input enable of the pad*/ + uint32_t x32n_slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t x32n_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t x32n_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t x32n_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t x32p_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t x32n_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd_xtal_32k: 1; /*Power up 32kHz crystal oscillator*/ + uint32_t dac_xtal_32k: 2; /*32K XTAL bias current DAC.*/ + uint32_t x32p_rue: 1; /*the pull up enable of the pad*/ + uint32_t x32p_rde: 1; /*the pull down enable of the pad*/ + uint32_t x32p_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t x32p_drv: 2; /*the driver strength of the pad*/ + uint32_t x32n_rue: 1; /*the pull up enable of the pad*/ + uint32_t x32n_rde: 1; /*the pull down enable of the pad*/ + uint32_t x32n_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t x32n_drv: 2; /*the driver strength of the pad*/ + }; + uint32_t val; + } xtal_32k_pad; + union { + struct { + uint32_t reserved0: 23; + uint32_t dcur: 2; /*touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available*/ + uint32_t drange: 2; /*touch sensor saw wave voltage range.*/ + uint32_t drefl: 2; /*touch sensor saw wave bottom voltage.*/ + uint32_t drefh: 2; /*touch sensor saw wave top voltage.*/ + uint32_t xpd_bias: 1; /*touch sensor bias power on.*/ + }; + uint32_t val; + } touch_cfg; + union { + struct { + uint32_t reserved0: 12; + uint32_t to_gpio: 1; /*connect the rtc pad input to digital pad input �0� is availbale GPIO4*/ + uint32_t fun_ie: 1; /*the input enable of the pad*/ + uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd: 1; /*touch sensor power on.*/ + uint32_t tie_opt: 1; /*default touch sensor tie option. 0: tie low 1: tie high.*/ + uint32_t start: 1; /*start touch sensor.*/ + uint32_t dac: 3; /*touch sensor slope control. 3-bit for each touch panel default 100.*/ + uint32_t reserved26: 1; + uint32_t rue: 1; /*the pull up enable of the pad*/ + uint32_t rde: 1; /*the pull down enable of the pad*/ + uint32_t drv: 2; /*the driver strength of the pad*/ + uint32_t hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } touch_pad[10]; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; /*select the wakeup source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/ + }; + uint32_t val; + } ext_wakeup0; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; /*select the external xtl power source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/ + }; + uint32_t val; + } xtl_ext_ctr; + union { + struct { + uint32_t reserved0: 23; + uint32_t debug_bit_sel: 5; + uint32_t scl_sel: 2; /*�0� using TOUCH_PAD[0] as i2c clk �1� using TOUCH_PAD[2] as i2c clk*/ + uint32_t sda_sel: 2; /*�0� using TOUCH_PAD[1] as i2c sda �1� using TOUCH_PAD[3] as i2c sda*/ + }; + uint32_t val; + } sar_i2c_io; + union { + struct { + uint32_t date: 28; /*date*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_io_dev_t; +extern rtc_io_dev_t RTCIO; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_RTC_IO_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/sdio_slave_pins.h b/tools/sdk/include/soc/include/soc/sdio_slave_pins.h new file mode 100644 index 00000000000..97c8bec07fd --- /dev/null +++ b/tools/sdk/include/soc/include/soc/sdio_slave_pins.h @@ -0,0 +1,34 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_SDIO_SLAVE_PINS_H_ +#define _SOC_SDIO_SLAVE_PINS_H_ + +#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK 6 +#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD 11 +#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0 7 +#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1 8 +#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2 9 +#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3 10 +#define SDIO_SLAVE_SLOT0_FUNC 0 + +#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK 14 +#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD 15 +#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0 2 +#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1 4 +#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2 12 +#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3 13 +#define SDIO_SLAVE_SLOT1_FUNC 4 + +#endif /* _SOC_SDIO_SLAVE_PINS_H_ */ \ No newline at end of file diff --git a/tools/sdk/include/soc/include/soc/sdmmc_pins.h b/tools/sdk/include/soc/include/soc/sdmmc_pins.h new file mode 100644 index 00000000000..c0b328239ad --- /dev/null +++ b/tools/sdk/include/soc/include/soc/sdmmc_pins.h @@ -0,0 +1,38 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_SDMMC_PINS_H_ +#define _SOC_SDMMC_PINS_H_ + +#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK 6 +#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD 11 +#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0 7 +#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1 8 +#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2 9 +#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3 10 +#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4 16 +#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5 17 +#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6 5 +#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7 18 +#define SDMMC_SLOT0_FUNC 0 + +#define SDMMC_SLOT1_IOMUX_PIN_NUM_CLK 14 +#define SDMMC_SLOT1_IOMUX_PIN_NUM_CMD 15 +#define SDMMC_SLOT1_IOMUX_PIN_NUM_D0 2 +#define SDMMC_SLOT1_IOMUX_PIN_NUM_D1 4 +#define SDMMC_SLOT1_IOMUX_PIN_NUM_D2 12 +#define SDMMC_SLOT1_IOMUX_PIN_NUM_D3 13 +#define SDMMC_SLOT1_FUNC 4 + +#endif /* _SOC_SDMMC_PINS_H_ */ \ No newline at end of file diff --git a/tools/sdk/include/soc/include/soc/sdmmc_reg.h b/tools/sdk/include/soc/include/soc/sdmmc_reg.h new file mode 100644 index 00000000000..0e92f682244 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/sdmmc_reg.h @@ -0,0 +1,97 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SDMMC_REG_H_ +#define _SOC_SDMMC_REG_H_ +#include "soc.h" + +#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00) +#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04) +#define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08) +#define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c) +#define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10) +#define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14) +#define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18) +#define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c) +#define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20) +#define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24) +#define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28) +#define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c) +#define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30) +#define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34) +#define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38) +#define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c) + +#define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40) +#define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44) +#define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48) +#define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c) +#define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50) +#define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54) +#define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58) +#define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c) +#define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60) +#define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64) +#define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68) +#define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c) +#define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70) +#define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74) +#define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78) +#define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80) +#define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84) +#define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88) +#define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c) +#define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c) +#define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90) +#define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94) +#define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98) +#define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c) +#define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0) +#define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4) +#define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100) +#define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104) +#define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108) +#define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c) +#define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110) + +#define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800) + +#define SDMMC_INTMASK_IO_SLOT1 BIT(17) +#define SDMMC_INTMASK_IO_SLOT0 BIT(16) +#define SDMMC_INTMASK_EBE BIT(15) +#define SDMMC_INTMASK_ACD BIT(14) +#define SDMMC_INTMASK_SBE BIT(13) +#define SDMMC_INTMASK_BCI BIT(13) +#define SDMMC_INTMASK_HLE BIT(12) +#define SDMMC_INTMASK_FRUN BIT(11) +#define SDMMC_INTMASK_HTO BIT(10) +#define SDMMC_INTMASK_DTO BIT(9) +#define SDMMC_INTMASK_RTO BIT(8) +#define SDMMC_INTMASK_DCRC BIT(7) +#define SDMMC_INTMASK_RCRC BIT(6) +#define SDMMC_INTMASK_RXDR BIT(5) +#define SDMMC_INTMASK_TXDR BIT(4) +#define SDMMC_INTMASK_DATA_OVER BIT(3) +#define SDMMC_INTMASK_CMD_DONE BIT(2) +#define SDMMC_INTMASK_RESP_ERR BIT(1) +#define SDMMC_INTMASK_CD BIT(0) + +#define SDMMC_IDMAC_INTMASK_AI BIT(9) +#define SDMMC_IDMAC_INTMASK_NI BIT(8) +#define SDMMC_IDMAC_INTMASK_CES BIT(5) +#define SDMMC_IDMAC_INTMASK_DU BIT(4) +#define SDMMC_IDMAC_INTMASK_FBE BIT(2) +#define SDMMC_IDMAC_INTMASK_RI BIT(1) +#define SDMMC_IDMAC_INTMASK_TI BIT(0) + +#endif /* _SOC_SDMMC_REG_H_ */ diff --git a/tools/sdk/include/soc/include/soc/sdmmc_struct.h b/tools/sdk/include/soc/include/soc/sdmmc_struct.h new file mode 100644 index 00000000000..17b8b3f24f7 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/sdmmc_struct.h @@ -0,0 +1,393 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SDMMC_STRUCT_H_ +#define _SOC_SDMMC_STRUCT_H_ + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t reserved1: 1; + uint32_t disable_int_on_completion: 1; + uint32_t last_descriptor: 1; + uint32_t first_descriptor: 1; + uint32_t second_address_chained: 1; + uint32_t end_of_ring: 1; + uint32_t reserved2: 24; + uint32_t card_error_summary: 1; + uint32_t owned_by_idmac: 1; + uint32_t buffer1_size: 13; + uint32_t buffer2_size: 13; + uint32_t reserved3: 6; + void* buffer1_ptr; + union { + void* buffer2_ptr; + void* next_desc_ptr; + }; +} sdmmc_desc_t; + +#define SDMMC_DMA_MAX_BUF_LEN 4096 + +_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure"); + + +typedef struct { + uint32_t cmd_index: 6; ///< Command index + uint32_t response_expect: 1; ///< set if response is expected + uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected + uint32_t check_response_crc: 1; ///< set if controller should check response CRC + uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected + uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected) + uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected) + uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer + uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete + uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer + uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1) + uint32_t card_num: 5; ///< card number + uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers + uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device + uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device + uint32_t enable_boot: 1; ///< set for mandatory boot mode + uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern + uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot) + uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation + uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only) + uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register + uint32_t reserved: 1; + uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared. +} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values + +_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure"); + + +typedef volatile struct { + union { + struct { + uint32_t controller_reset: 1; + uint32_t fifo_reset: 1; + uint32_t dma_reset: 1; + uint32_t reserved1: 1; + uint32_t int_enable: 1; + uint32_t dma_enable: 1; + uint32_t read_wait: 1; + uint32_t send_irq_response: 1; + uint32_t abort_read_data: 1; + uint32_t send_ccsd: 1; + uint32_t send_auto_stop_ccsd: 1; + uint32_t ceata_device_interrupt_status: 1; + uint32_t reserved2: 4; + uint32_t card_voltage_a: 4; + uint32_t card_voltage_b: 4; + uint32_t enable_od_pullup: 1; + uint32_t use_internal_dma: 1; + uint32_t reserved3: 6; + }; + uint32_t val; + } ctrl; + + uint32_t pwren; ///< 1: enable power to card, 0: disable power to card + + union { + struct { + uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). + uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). + uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). + uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). + }; + uint32_t val; + } clkdiv; + + union { + struct { + uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3 + uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3 + uint32_t reserved: 28; + }; + uint32_t val; + } clksrc; + + union { + struct { + uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock + uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating + }; + uint32_t val; + } clkena; + + union { + struct { + uint32_t response: 8; ///< response timeout, in card output clock cycles + uint32_t data: 24; ///< data read timeout, in card output clock cycles + }; + uint32_t val; + } tmout; + + union { + struct { + uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode + uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored) + }; + uint32_t val; + } ctype; + + uint32_t blksiz: 16; ///< block size, default 0x200 + uint32_t : 16; + + uint32_t bytcnt; ///< number of bytes to be transferred + + union { + struct { + uint32_t cd: 1; ///< Card detect interrupt enable + uint32_t re: 1; ///< Response error interrupt enable + uint32_t cmd_done: 1; ///< Command done interrupt enable + uint32_t dto: 1; ///< Data transfer over interrupt enable + uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable + uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable + uint32_t rcrc: 1; ///< Response CRC error interrupt enable + uint32_t dcrc: 1; ///< Data CRC error interrupt enable + uint32_t rto: 1; ///< Response timeout interrupt enable + uint32_t drto: 1; ///< Data read timeout interrupt enable + uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable + uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable + uint32_t hle: 1; ///< Hardware locked write error interrupt enable + uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable + uint32_t acd: 1; ///< Auto command done interrupt enable + uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable + uint32_t sdio: 16; ///< SDIO interrupt enable + }; + uint32_t val; + } intmask; + + uint32_t cmdarg; ///< Command argument to be passed to card + + sdmmc_hw_cmd_t cmd; + + uint32_t resp[4]; ///< Response from card + + union { + struct { + uint32_t cd: 1; ///< Card detect interrupt masked status + uint32_t re: 1; ///< Response error interrupt masked status + uint32_t cmd_done: 1; ///< Command done interrupt masked status + uint32_t dto: 1; ///< Data transfer over interrupt masked status + uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status + uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status + uint32_t rcrc: 1; ///< Response CRC error interrupt masked status + uint32_t dcrc: 1; ///< Data CRC error interrupt masked status + uint32_t rto: 1; ///< Response timeout interrupt masked status + uint32_t drto: 1; ///< Data read timeout interrupt masked status + uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status + uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status + uint32_t hle: 1; ///< Hardware locked write error interrupt masked status + uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status + uint32_t acd: 1; ///< Auto command done interrupt masked status + uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status + uint32_t sdio: 16; ///< SDIO interrupt masked status + }; + uint32_t val; + } mintsts; + + union { + struct { + uint32_t cd: 1; ///< Card detect raw interrupt status + uint32_t re: 1; ///< Response error raw interrupt status + uint32_t cmd_done: 1; ///< Command done raw interrupt status + uint32_t dto: 1; ///< Data transfer over raw interrupt status + uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status + uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status + uint32_t rcrc: 1; ///< Response CRC error raw interrupt status + uint32_t dcrc: 1; ///< Data CRC error raw interrupt status + uint32_t rto: 1; ///< Response timeout raw interrupt status + uint32_t drto: 1; ///< Data read timeout raw interrupt status + uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status + uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status + uint32_t hle: 1; ///< Hardware locked write error raw interrupt status + uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status + uint32_t acd: 1; ///< Auto command done raw interrupt status + uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status + uint32_t sdio: 16; ///< SDIO raw interrupt status + }; + uint32_t val; + } rintsts; ///< interrupts can be cleared by writing this register + + union { + struct { + uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level + uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level + uint32_t fifo_empty: 1; ///< FIFO is empty + uint32_t fifo_full: 1; ///< FIFO is full + uint32_t cmd_fsm_state: 4; ///< command FSM state + uint32_t data3_status: 1; ///< this bit reads 1 if card is present + uint32_t data_busy: 1; ///< this bit reads 1 if card is busy + uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy + uint32_t response_index: 6; ///< index of the previous response + uint32_t fifo_count: 13; ///< number of filled locations in the FIFO + uint32_t dma_ack: 1; ///< DMA acknowledge signal + uint32_t dma_req: 1; ///< DMA request signal + }; + uint32_t val; + } status; + + union { + struct { + uint32_t tx_watermark: 12; ///< FIFO TX watermark level + uint32_t reserved1: 4; + uint32_t rx_watermark: 12; ///< FIFO RX watermark level + uint32_t dw_dma_mts: 3; + uint32_t reserved2: 1; + }; + uint32_t val; + } fifoth; + + union { + struct { + uint32_t cards: 2; ///< bit N reads 0 if card N is present + uint32_t reserved: 30; + }; + uint32_t val; + } cdetect; + + union { + struct { + uint32_t cards: 2; ///< bit N reads 1 if card N is write protected + uint32_t reserved: 30; + }; + uint32_t val; + } wrtprt; + + uint32_t gpio; ///< unused + uint32_t tcbcnt; ///< transferred (to card) byte count + uint32_t tbbcnt; ///< transferred from host to FIFO byte count + + union { + struct { + uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms + uint32_t reserved: 8; + }; + } debnce; + + uint32_t usrid; ///< user ID + uint32_t verid; ///< IP block version + uint32_t hcon; ///< compile-time IP configuration + union { + struct { + uint32_t voltage: 16; ///< voltage control for slots; no-op on ESP32. + uint32_t ddr: 16; ///< bit N enables DDR mode for card N + }; + } uhs; ///< UHS related settings + + union { + struct { + uint32_t cards: 2; ///< bit N resets card N, active low + uint32_t reserved: 30; + }; + } rst_n; + + uint32_t reserved_7c; + + union { + struct { + uint32_t sw_reset: 1; ///< set to reset DMA controller + uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers + uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors + uint32_t enable: 1; ///< set to enable IDMAC + uint32_t pbl: 3; ///< programmable burst length + uint32_t reserved: 21; + }; + uint32_t val; + } bmod; + + uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state + sdmmc_desc_t* dbaddr; ///< descriptor list base + + union { + struct { + uint32_t ti: 1; ///< transmit interrupt status + uint32_t ri: 1; ///< receive interrupt status + uint32_t fbe: 1; ///< fatal bus error + uint32_t reserved1: 1; + uint32_t du: 1; ///< descriptor unavailable + uint32_t ces: 1; ///< card error summary + uint32_t reserved2: 2; + uint32_t nis: 1; ///< normal interrupt summary + uint32_t fbe_code: 3; ///< code of fatal bus error + uint32_t fsm: 4; ///< DMAC FSM state + uint32_t reserved3: 15; + }; + uint32_t val; + } idsts; + + union { + struct { + uint32_t ti: 1; ///< transmit interrupt enable + uint32_t ri: 1; ///< receive interrupt enable + uint32_t fbe: 1; ///< fatal bus error interrupt enable + uint32_t reserved1: 1; + uint32_t du: 1; ///< descriptor unavailable interrupt enable + uint32_t ces: 1; ///< card error interrupt enable + uint32_t reserved2: 2; + uint32_t ni: 1; ///< normal interrupt interrupt enable + uint32_t ai: 1; ///< abnormal interrupt enable + uint32_t reserved3: 22; + }; + uint32_t val; + } idinten; + + uint32_t dscaddr; ///< current host descriptor address + uint32_t dscaddrl; ///< unused + uint32_t dscaddru; ///< unused + uint32_t bufaddrl; ///< unused + uint32_t bufaddru; ///< unused + uint32_t reserved_a8[22]; + union { + struct { + uint32_t read_thr_en : 1; ///< initiate transfer only if FIFO has more space than the read threshold + uint32_t busy_clr_int_en : 1; ///< enable generation of busy clear interrupts + uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes + uint32_t reserved1 : 13; + uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes + }; + uint32_t val; + } cardthrctl; + uint32_t back_end_power; + uint32_t uhs_reg_ext; + uint32_t emmc_ddr_reg; + uint32_t enable_shift; + uint32_t reserved_114[443]; + union { + struct { + uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270) + uint32_t phase_din: 3; ///< phase of data input clock + uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral + uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz + uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz + uint32_t div_factor_m: 4; ///< should be equal to div_factor_p + }; + uint32_t val; + } clock; +} sdmmc_dev_t; +extern sdmmc_dev_t SDMMC; + +_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure"); + +#ifdef __cplusplus +} +#endif + +#endif //_SOC_SDMMC_STRUCT_H_ diff --git a/tools/sdk/include/soc/include/soc/sens_reg.h b/tools/sdk/include/soc/include/soc/sens_reg.h new file mode 100644 index 00000000000..34834376e89 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/sens_reg.h @@ -0,0 +1,1068 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SENS_REG_H_ +#define _SOC_SENS_REG_H_ + + +#include "soc.h" +#define SENS_SAR_READ_CTRL_REG (DR_REG_SENS_BASE + 0x0000) +/* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: Invert SAR ADC1 data*/ +#define SENS_SAR1_DATA_INV (BIT(28)) +#define SENS_SAR1_DATA_INV_M (BIT(28)) +#define SENS_SAR1_DATA_INV_V 0x1 +#define SENS_SAR1_DATA_INV_S 28 +/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL*/ +#define SENS_SAR1_DIG_FORCE (BIT(27)) +#define SENS_SAR1_DIG_FORCE_M (BIT(27)) +#define SENS_SAR1_DIG_FORCE_V 0x1 +#define SENS_SAR1_DIG_FORCE_S 27 +/* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: */ +#define SENS_SAR1_SAMPLE_NUM 0x000000FF +#define SENS_SAR1_SAMPLE_NUM_M ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S)) +#define SENS_SAR1_SAMPLE_NUM_V 0xFF +#define SENS_SAR1_SAMPLE_NUM_S 19 +/* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define SENS_SAR1_CLK_GATED (BIT(18)) +#define SENS_SAR1_CLK_GATED_M (BIT(18)) +#define SENS_SAR1_CLK_GATED_V 0x1 +#define SENS_SAR1_CLK_GATED_S 18 +/* SENS_SAR1_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */ +/*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width + 11: for 12-bit width*/ +#define SENS_SAR1_SAMPLE_BIT 0x00000003 +#define SENS_SAR1_SAMPLE_BIT_M ((SENS_SAR1_SAMPLE_BIT_V)<<(SENS_SAR1_SAMPLE_BIT_S)) +#define SENS_SAR1_SAMPLE_BIT_V 0x3 +#define SENS_SAR1_SAMPLE_BIT_S 16 +/* SENS_SAR1_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */ +/*description: sample cycles for SAR ADC1*/ +#define SENS_SAR1_SAMPLE_CYCLE 0x000000FF +#define SENS_SAR1_SAMPLE_CYCLE_M ((SENS_SAR1_SAMPLE_CYCLE_V)<<(SENS_SAR1_SAMPLE_CYCLE_S)) +#define SENS_SAR1_SAMPLE_CYCLE_V 0xFF +#define SENS_SAR1_SAMPLE_CYCLE_S 8 +/* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: clock divider*/ +#define SENS_SAR1_CLK_DIV 0x000000FF +#define SENS_SAR1_CLK_DIV_M ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S)) +#define SENS_SAR1_CLK_DIV_V 0xFF +#define SENS_SAR1_CLK_DIV_S 0 + +#define SENS_SAR_READ_STATUS1_REG (DR_REG_SENS_BASE + 0x0004) +/* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SENS_SAR1_READER_STATUS 0xFFFFFFFF +#define SENS_SAR1_READER_STATUS_M ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S)) +#define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF +#define SENS_SAR1_READER_STATUS_S 0 + +#define SENS_SAR_MEAS_WAIT1_REG (DR_REG_SENS_BASE + 0x0008) +/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ +/*description: */ +#define SENS_SAR_AMP_WAIT2 0x0000FFFF +#define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S)) +#define SENS_SAR_AMP_WAIT2_V 0xFFFF +#define SENS_SAR_AMP_WAIT2_S 16 +/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ +/*description: */ +#define SENS_SAR_AMP_WAIT1 0x0000FFFF +#define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S)) +#define SENS_SAR_AMP_WAIT1_V 0xFFFF +#define SENS_SAR_AMP_WAIT1_S 0 + +#define SENS_SAR_MEAS_WAIT2_REG (DR_REG_SENS_BASE + 0x000c) +/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */ +/*description: */ +#define SENS_SAR2_RSTB_WAIT 0x000000FF +#define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S)) +#define SENS_SAR2_RSTB_WAIT_V 0xFF +#define SENS_SAR2_RSTB_WAIT_S 20 +/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define SENS_FORCE_XPD_SAR 0x00000003 +#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S)) +#define SENS_FORCE_XPD_SAR_V 0x3 +#define SENS_FORCE_XPD_SAR_S 18 +#define SENS_FORCE_XPD_SAR_SW_M (BIT1) +#define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down +#define SENS_FORCE_XPD_SAR_PD 2 // Force power down +#define SENS_FORCE_XPD_SAR_PU 3 // Force power up +/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define SENS_FORCE_XPD_AMP 0x00000003 +#define SENS_FORCE_XPD_AMP_M ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S)) +#define SENS_FORCE_XPD_AMP_V 0x3 +#define SENS_FORCE_XPD_AMP_S 16 +#define SENS_FORCE_XPD_AMP_FSM 0 // Use FSM to control power down +#define SENS_FORCE_XPD_AMP_PD 2 // Force power down +#define SENS_FORCE_XPD_AMP_PU 3 // Force power up +/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ +/*description: */ +#define SENS_SAR_AMP_WAIT3 0x0000FFFF +#define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S)) +#define SENS_SAR_AMP_WAIT3_V 0xFFFF +#define SENS_SAR_AMP_WAIT3_S 0 + +#define SENS_SAR_MEAS_CTRL_REG (DR_REG_SENS_BASE + 0x0010) +/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ +/*description: */ +#define SENS_SAR2_XPD_WAIT 0x000000FF +#define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S)) +#define SENS_SAR2_XPD_WAIT_V 0xFF +#define SENS_SAR2_XPD_WAIT_S 24 +/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[23:20] ;default: 4'b0000 ; */ +/*description: */ +#define SENS_SAR_RSTB_FSM 0x0000000F +#define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S)) +#define SENS_SAR_RSTB_FSM_V 0xF +#define SENS_SAR_RSTB_FSM_S 20 +/* SENS_XPD_SAR_FSM : R/W ;bitpos:[19:16] ;default: 4'b0111 ; */ +/*description: */ +#define SENS_XPD_SAR_FSM 0x0000000F +#define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S)) +#define SENS_XPD_SAR_FSM_V 0xF +#define SENS_XPD_SAR_FSM_S 16 +/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S)) +#define SENS_AMP_SHORT_REF_GND_FSM_V 0xF +#define SENS_AMP_SHORT_REF_GND_FSM_S 12 +/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[11:8] ;default: 4'b0011 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S)) +#define SENS_AMP_SHORT_REF_FSM_V 0xF +#define SENS_AMP_SHORT_REF_FSM_S 8 +/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[7:4] ;default: 4'b1000 ; */ +/*description: */ +#define SENS_AMP_RST_FB_FSM 0x0000000F +#define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S)) +#define SENS_AMP_RST_FB_FSM_V 0xF +#define SENS_AMP_RST_FB_FSM_S 4 +/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[3:0] ;default: 4'b1111 ; */ +/*description: */ +#define SENS_XPD_SAR_AMP_FSM 0x0000000F +#define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S)) +#define SENS_XPD_SAR_AMP_FSM_V 0xF +#define SENS_XPD_SAR_AMP_FSM_S 0 + +#define SENS_SAR_READ_STATUS2_REG (DR_REG_SENS_BASE + 0x0014) +/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SENS_SAR2_READER_STATUS 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S)) +#define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_S 0 + +#define SENS_ULP_CP_SLEEP_CYC0_REG (DR_REG_SENS_BASE + 0x0018) +/* SENS_SLEEP_CYCLES_S0 : R/W ;bitpos:[31:0] ;default: 32'd200 ; */ +/*description: sleep cycles for ULP-coprocessor timer*/ +#define SENS_SLEEP_CYCLES_S0 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S0_M ((SENS_SLEEP_CYCLES_S0_V)<<(SENS_SLEEP_CYCLES_S0_S)) +#define SENS_SLEEP_CYCLES_S0_V 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S0_S 0 + +#define SENS_ULP_CP_SLEEP_CYC1_REG (DR_REG_SENS_BASE + 0x001c) +/* SENS_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */ +/*description: */ +#define SENS_SLEEP_CYCLES_S1 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S1_M ((SENS_SLEEP_CYCLES_S1_V)<<(SENS_SLEEP_CYCLES_S1_S)) +#define SENS_SLEEP_CYCLES_S1_V 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S1_S 0 + +#define SENS_ULP_CP_SLEEP_CYC2_REG (DR_REG_SENS_BASE + 0x0020) +/* SENS_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */ +/*description: */ +#define SENS_SLEEP_CYCLES_S2 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S2_M ((SENS_SLEEP_CYCLES_S2_V)<<(SENS_SLEEP_CYCLES_S2_S)) +#define SENS_SLEEP_CYCLES_S2_V 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S2_S 0 + +#define SENS_ULP_CP_SLEEP_CYC3_REG (DR_REG_SENS_BASE + 0x0024) +/* SENS_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */ +/*description: */ +#define SENS_SLEEP_CYCLES_S3 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S3_M ((SENS_SLEEP_CYCLES_S3_V)<<(SENS_SLEEP_CYCLES_S3_S)) +#define SENS_SLEEP_CYCLES_S3_V 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S3_S 0 + +#define SENS_ULP_CP_SLEEP_CYC4_REG (DR_REG_SENS_BASE + 0x0028) +/* SENS_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */ +/*description: */ +#define SENS_SLEEP_CYCLES_S4 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S4_M ((SENS_SLEEP_CYCLES_S4_V)<<(SENS_SLEEP_CYCLES_S4_S)) +#define SENS_SLEEP_CYCLES_S4_V 0xFFFFFFFF +#define SENS_SLEEP_CYCLES_S4_S 0 + +#define SENS_SAR_START_FORCE_REG (DR_REG_SENS_BASE + 0x002c) +/* SENS_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: N/A*/ +#define SENS_SAR2_PWDET_EN (BIT(24)) +#define SENS_SAR2_PWDET_EN_M (BIT(24)) +#define SENS_SAR2_PWDET_EN_V 0x1 +#define SENS_SAR2_PWDET_EN_S 24 +/* SENS_SAR1_STOP : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: stop SAR ADC1 conversion*/ +#define SENS_SAR1_STOP (BIT(23)) +#define SENS_SAR1_STOP_M (BIT(23)) +#define SENS_SAR1_STOP_V 0x1 +#define SENS_SAR1_STOP_S 23 +/* SENS_SAR2_STOP : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: stop SAR ADC2 conversion*/ +#define SENS_SAR2_STOP (BIT(22)) +#define SENS_SAR2_STOP_M (BIT(22)) +#define SENS_SAR2_STOP_V 0x1 +#define SENS_SAR2_STOP_S 22 +/* SENS_PC_INIT : R/W ;bitpos:[21:11] ;default: 11'b0 ; */ +/*description: initialized PC for ULP-coprocessor*/ +#define SENS_PC_INIT 0x000007FF +#define SENS_PC_INIT_M ((SENS_PC_INIT_V)<<(SENS_PC_INIT_S)) +#define SENS_PC_INIT_V 0x7FF +#define SENS_PC_INIT_S 11 +/* SENS_SARCLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SARCLK_EN (BIT(10)) +#define SENS_SARCLK_EN_M (BIT(10)) +#define SENS_SARCLK_EN_V 0x1 +#define SENS_SARCLK_EN_S 10 +/* SENS_ULP_CP_START_TOP : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top + = 1*/ +#define SENS_ULP_CP_START_TOP (BIT(9)) +#define SENS_ULP_CP_START_TOP_M (BIT(9)) +#define SENS_ULP_CP_START_TOP_V 0x1 +#define SENS_ULP_CP_START_TOP_S 9 +/* SENS_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer*/ +#define SENS_ULP_CP_FORCE_START_TOP (BIT(8)) +#define SENS_ULP_CP_FORCE_START_TOP_M (BIT(8)) +#define SENS_ULP_CP_FORCE_START_TOP_V 0x1 +#define SENS_ULP_CP_FORCE_START_TOP_S 8 +/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[7:5] ;default: 3'b0 ; */ +/*description: SAR2_PWDET_CCT PA power detector capacitance tuning.*/ +#define SENS_SAR2_PWDET_CCT 0x00000007 +#define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S)) +#define SENS_SAR2_PWDET_CCT_V 0x7 +#define SENS_SAR2_PWDET_CCT_S 5 +/* SENS_SAR2_EN_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: SAR2_EN_TEST only active when reg_sar2_dig_force = 0*/ +#define SENS_SAR2_EN_TEST (BIT(4)) +#define SENS_SAR2_EN_TEST_M (BIT(4)) +#define SENS_SAR2_EN_TEST_V 0x1 +#define SENS_SAR2_EN_TEST_S 4 +/* SENS_SAR2_BIT_WIDTH : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ +#define SENS_SAR2_BIT_WIDTH 0x00000003 +#define SENS_SAR2_BIT_WIDTH_M ((SENS_SAR2_BIT_WIDTH_V)<<(SENS_SAR2_BIT_WIDTH_S)) +#define SENS_SAR2_BIT_WIDTH_V 0x3 +#define SENS_SAR2_BIT_WIDTH_S 2 +/* SENS_SAR1_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ +#define SENS_SAR1_BIT_WIDTH 0x00000003 +#define SENS_SAR1_BIT_WIDTH_M ((SENS_SAR1_BIT_WIDTH_V)<<(SENS_SAR1_BIT_WIDTH_S)) +#define SENS_SAR1_BIT_WIDTH_V 0x3 +#define SENS_SAR1_BIT_WIDTH_S 0 + +#define SENS_SAR_MEM_WR_CTRL_REG (DR_REG_SENS_BASE + 0x0030) +/* SENS_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define SENS_RTC_MEM_WR_OFFST_CLR (BIT(22)) +#define SENS_RTC_MEM_WR_OFFST_CLR_M (BIT(22)) +#define SENS_RTC_MEM_WR_OFFST_CLR_V 0x1 +#define SENS_RTC_MEM_WR_OFFST_CLR_S 22 +/* SENS_MEM_WR_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ +/*description: */ +#define SENS_MEM_WR_ADDR_SIZE 0x000007FF +#define SENS_MEM_WR_ADDR_SIZE_M ((SENS_MEM_WR_ADDR_SIZE_V)<<(SENS_MEM_WR_ADDR_SIZE_S)) +#define SENS_MEM_WR_ADDR_SIZE_V 0x7FF +#define SENS_MEM_WR_ADDR_SIZE_S 11 +/* SENS_MEM_WR_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ +/*description: */ +#define SENS_MEM_WR_ADDR_INIT 0x000007FF +#define SENS_MEM_WR_ADDR_INIT_M ((SENS_MEM_WR_ADDR_INIT_V)<<(SENS_MEM_WR_ADDR_INIT_S)) +#define SENS_MEM_WR_ADDR_INIT_V 0x7FF +#define SENS_MEM_WR_ADDR_INIT_S 0 + +#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x0034) +/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ +#define SENS_SAR1_ATTEN 0xFFFFFFFF +#define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S)) +#define SENS_SAR1_ATTEN_V 0xFFFFFFFF +#define SENS_SAR1_ATTEN_S 0 +#define SENS_SAR1_ATTEN_VAL_MASK 0x3 +#define SENS_SAR2_ATTEN_VAL_MASK 0x3 + +#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x0038) +/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ +#define SENS_SAR2_ATTEN 0xFFFFFFFF +#define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S)) +#define SENS_SAR2_ATTEN_V 0xFFFFFFFF +#define SENS_SAR2_ATTEN_S 0 + +#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x003c) +/* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ +/*description: */ +#define SENS_MEAS_STATUS 0x000000FF +#define SENS_MEAS_STATUS_M ((SENS_MEAS_STATUS_V)<<(SENS_MEAS_STATUS_S)) +#define SENS_MEAS_STATUS_V 0xFF +#define SENS_MEAS_STATUS_S 22 +/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR0 0x000007FF +#define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S)) +#define SENS_I2C_SLAVE_ADDR0_V 0x7FF +#define SENS_I2C_SLAVE_ADDR0_S 11 +/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR1 0x000007FF +#define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S)) +#define SENS_I2C_SLAVE_ADDR1_V 0x7FF +#define SENS_I2C_SLAVE_ADDR1_S 0 + +#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x0040) +/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR2 0x000007FF +#define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S)) +#define SENS_I2C_SLAVE_ADDR2_V 0x7FF +#define SENS_I2C_SLAVE_ADDR2_S 11 +/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR3 0x000007FF +#define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S)) +#define SENS_I2C_SLAVE_ADDR3_V 0x7FF +#define SENS_I2C_SLAVE_ADDR3_S 0 + +#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x0044) +/* SENS_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */ +/*description: indicate temperature sensor out ready*/ +#define SENS_TSENS_RDY_OUT (BIT(30)) +#define SENS_TSENS_RDY_OUT_M (BIT(30)) +#define SENS_TSENS_RDY_OUT_V 0x1 +#define SENS_TSENS_RDY_OUT_S 30 +/* SENS_TSENS_OUT : RO ;bitpos:[29:22] ;default: 8'h0 ; */ +/*description: temperature sensor data out*/ +#define SENS_TSENS_OUT 0x000000FF +#define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S)) +#define SENS_TSENS_OUT_V 0xFF +#define SENS_TSENS_OUT_S 22 +/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR4 0x000007FF +#define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S)) +#define SENS_I2C_SLAVE_ADDR4_V 0x7FF +#define SENS_I2C_SLAVE_ADDR4_S 11 +/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR5 0x000007FF +#define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S)) +#define SENS_I2C_SLAVE_ADDR5_V 0x7FF +#define SENS_I2C_SLAVE_ADDR5_S 0 + +#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x0048) +/* SENS_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */ +/*description: indicate I2C done*/ +#define SENS_I2C_DONE (BIT(30)) +#define SENS_I2C_DONE_M (BIT(30)) +#define SENS_I2C_DONE_V 0x1 +#define SENS_I2C_DONE_S 30 +/* SENS_I2C_RDATA : RO ;bitpos:[29:22] ;default: 8'h0 ; */ +/*description: I2C read data*/ +#define SENS_I2C_RDATA 0x000000FF +#define SENS_I2C_RDATA_M ((SENS_I2C_RDATA_V)<<(SENS_I2C_RDATA_S)) +#define SENS_I2C_RDATA_V 0xFF +#define SENS_I2C_RDATA_S 22 +/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR6 0x000007FF +#define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S)) +#define SENS_I2C_SLAVE_ADDR6_V 0x7FF +#define SENS_I2C_SLAVE_ADDR6_S 11 +/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR7 0x000007FF +#define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S)) +#define SENS_I2C_SLAVE_ADDR7_V 0x7FF +#define SENS_I2C_SLAVE_ADDR7_S 0 + +#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x004c) +/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: temperature sensor dump out only active when reg_tsens_power_up_force = 1*/ +#define SENS_TSENS_DUMP_OUT (BIT(26)) +#define SENS_TSENS_DUMP_OUT_M (BIT(26)) +#define SENS_TSENS_DUMP_OUT_V 0x1 +#define SENS_TSENS_DUMP_OUT_S 26 +/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: dump out & power up controlled by SW 0: by FSM*/ +#define SENS_TSENS_POWER_UP_FORCE (BIT(25)) +#define SENS_TSENS_POWER_UP_FORCE_M (BIT(25)) +#define SENS_TSENS_POWER_UP_FORCE_V 0x1 +#define SENS_TSENS_POWER_UP_FORCE_S 25 +/* SENS_TSENS_POWER_UP : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: temperature sensor power up*/ +#define SENS_TSENS_POWER_UP (BIT(24)) +#define SENS_TSENS_POWER_UP_M (BIT(24)) +#define SENS_TSENS_POWER_UP_V 0x1 +#define SENS_TSENS_POWER_UP_S 24 +/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[23:16] ;default: 8'd6 ; */ +/*description: temperature sensor clock divider*/ +#define SENS_TSENS_CLK_DIV 0x000000FF +#define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S)) +#define SENS_TSENS_CLK_DIV_V 0xFF +#define SENS_TSENS_CLK_DIV_S 16 +/* SENS_TSENS_IN_INV : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: invert temperature sensor data*/ +#define SENS_TSENS_IN_INV (BIT(15)) +#define SENS_TSENS_IN_INV_M (BIT(15)) +#define SENS_TSENS_IN_INV_V 0x1 +#define SENS_TSENS_IN_INV_S 15 +/* SENS_TSENS_CLK_GATED : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define SENS_TSENS_CLK_GATED (BIT(14)) +#define SENS_TSENS_CLK_GATED_M (BIT(14)) +#define SENS_TSENS_CLK_GATED_V 0x1 +#define SENS_TSENS_CLK_GATED_S 14 +/* SENS_TSENS_CLK_INV : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define SENS_TSENS_CLK_INV (BIT(13)) +#define SENS_TSENS_CLK_INV_M (BIT(13)) +#define SENS_TSENS_CLK_INV_V 0x1 +#define SENS_TSENS_CLK_INV_S 13 +/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SENS_TSENS_XPD_FORCE (BIT(12)) +#define SENS_TSENS_XPD_FORCE_M (BIT(12)) +#define SENS_TSENS_XPD_FORCE_V 0x1 +#define SENS_TSENS_XPD_FORCE_S 12 +/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ +/*description: */ +#define SENS_TSENS_XPD_WAIT 0x00000FFF +#define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S)) +#define SENS_TSENS_XPD_WAIT_V 0xFFF +#define SENS_TSENS_XPD_WAIT_S 0 + +#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x0050) +/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: I2C started by SW 0: I2C started by FSM*/ +#define SENS_SAR_I2C_START_FORCE (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_M (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_V 0x1 +#define SENS_SAR_I2C_START_FORCE_S 29 +/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: start I2C only active when reg_sar_i2c_start_force = 1*/ +#define SENS_SAR_I2C_START (BIT(28)) +#define SENS_SAR_I2C_START_M (BIT(28)) +#define SENS_SAR_I2C_START_V 0x1 +#define SENS_SAR_I2C_START_S 28 +/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/*description: I2C control data only active when reg_sar_i2c_start_force = 1*/ +#define SENS_SAR_I2C_CTRL 0x0FFFFFFF +#define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S)) +#define SENS_SAR_I2C_CTRL_V 0xFFFFFFF +#define SENS_SAR_I2C_CTRL_S 0 + +#define SENS_SAR_MEAS_START1_REG (DR_REG_SENS_BASE + 0x0054) +/* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 + pad enable bitmap is controlled by ULP-coprocessor*/ +#define SENS_SAR1_EN_PAD_FORCE (BIT(31)) +#define SENS_SAR1_EN_PAD_FORCE_M (BIT(31)) +#define SENS_SAR1_EN_PAD_FORCE_V 0x1 +#define SENS_SAR1_EN_PAD_FORCE_S 31 +/* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ +/*description: SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1*/ +#define SENS_SAR1_EN_PAD 0x00000FFF +#define SENS_SAR1_EN_PAD_M ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S)) +#define SENS_SAR1_EN_PAD_V 0xFFF +#define SENS_SAR1_EN_PAD_S 19 +/* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 + controller is started by ULP-coprocessor*/ +#define SENS_MEAS1_START_FORCE (BIT(18)) +#define SENS_MEAS1_START_FORCE_M (BIT(18)) +#define SENS_MEAS1_START_FORCE_V 0x1 +#define SENS_MEAS1_START_FORCE_S 18 +/* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: SAR ADC1 controller (in RTC) starts conversion only active when + reg_meas1_start_force = 1*/ +#define SENS_MEAS1_START_SAR (BIT(17)) +#define SENS_MEAS1_START_SAR_M (BIT(17)) +#define SENS_MEAS1_START_SAR_V 0x1 +#define SENS_MEAS1_START_SAR_S 17 +/* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: SAR ADC1 conversion done indication*/ +#define SENS_MEAS1_DONE_SAR (BIT(16)) +#define SENS_MEAS1_DONE_SAR_M (BIT(16)) +#define SENS_MEAS1_DONE_SAR_V 0x1 +#define SENS_MEAS1_DONE_SAR_S 16 +/* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: SAR ADC1 data*/ +#define SENS_MEAS1_DATA_SAR 0x0000FFFF +#define SENS_MEAS1_DATA_SAR_M ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S)) +#define SENS_MEAS1_DATA_SAR_V 0xFFFF +#define SENS_MEAS1_DATA_SAR_S 0 + +#define SENS_SAR_TOUCH_CTRL1_REG (DR_REG_SENS_BASE + 0x0058) +/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled + by FSM in ULP-coprocessor*/ +#define SENS_HALL_PHASE_FORCE (BIT(27)) +#define SENS_HALL_PHASE_FORCE_M (BIT(27)) +#define SENS_HALL_PHASE_FORCE_V 0x1 +#define SENS_HALL_PHASE_FORCE_S 27 +/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by + FSM in ULP-coprocessor*/ +#define SENS_XPD_HALL_FORCE (BIT(26)) +#define SENS_XPD_HALL_FORCE_M (BIT(26)) +#define SENS_XPD_HALL_FORCE_V 0x1 +#define SENS_XPD_HALL_FORCE_S 26 +/* SENS_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: 1: wakeup interrupt is generated if SET1 is "touched" 0: + wakeup interrupt is generated only if SET1 & SET2 is both "touched"*/ +#define SENS_TOUCH_OUT_1EN (BIT(25)) +#define SENS_TOUCH_OUT_1EN_M (BIT(25)) +#define SENS_TOUCH_OUT_1EN_V 0x1 +#define SENS_TOUCH_OUT_1EN_S 25 +/* SENS_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: when the counter is greater then the threshold the touch + pad is considered as "touched" 0: when the counter is less than the threshold the touch pad is considered as "touched"*/ +#define SENS_TOUCH_OUT_SEL (BIT(24)) +#define SENS_TOUCH_OUT_SEL_M (BIT(24)) +#define SENS_TOUCH_OUT_SEL_V 0x1 +#define SENS_TOUCH_OUT_SEL_S 24 +/* SENS_TOUCH_XPD_WAIT : R/W ;bitpos:[23:16] ;default: 8'h4 ; */ +/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ +#define SENS_TOUCH_XPD_WAIT 0x000000FF +#define SENS_TOUCH_XPD_WAIT_M ((SENS_TOUCH_XPD_WAIT_V)<<(SENS_TOUCH_XPD_WAIT_S)) +#define SENS_TOUCH_XPD_WAIT_V 0xFF +#define SENS_TOUCH_XPD_WAIT_S 16 +/* SENS_TOUCH_MEAS_DELAY : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: the meas length (in 8MHz)*/ +#define SENS_TOUCH_MEAS_DELAY 0x0000FFFF +#define SENS_TOUCH_MEAS_DELAY_M ((SENS_TOUCH_MEAS_DELAY_V)<<(SENS_TOUCH_MEAS_DELAY_S)) +#define SENS_TOUCH_MEAS_DELAY_V 0xFFFF +#define SENS_TOUCH_MEAS_DELAY_S 0 + +#define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x005c) +/* SENS_TOUCH_OUT_TH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 0*/ +#define SENS_TOUCH_OUT_TH0 0x0000FFFF +#define SENS_TOUCH_OUT_TH0_M ((SENS_TOUCH_OUT_TH0_V)<<(SENS_TOUCH_OUT_TH0_S)) +#define SENS_TOUCH_OUT_TH0_V 0xFFFF +#define SENS_TOUCH_OUT_TH0_S 16 +/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 1*/ +#define SENS_TOUCH_OUT_TH1 0x0000FFFF +#define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S)) +#define SENS_TOUCH_OUT_TH1_V 0xFFFF +#define SENS_TOUCH_OUT_TH1_S 0 + +#define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x0060) +/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 2*/ +#define SENS_TOUCH_OUT_TH2 0x0000FFFF +#define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S)) +#define SENS_TOUCH_OUT_TH2_V 0xFFFF +#define SENS_TOUCH_OUT_TH2_S 16 +/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 3*/ +#define SENS_TOUCH_OUT_TH3 0x0000FFFF +#define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S)) +#define SENS_TOUCH_OUT_TH3_V 0xFFFF +#define SENS_TOUCH_OUT_TH3_S 0 + +#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x0064) +/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 4*/ +#define SENS_TOUCH_OUT_TH4 0x0000FFFF +#define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S)) +#define SENS_TOUCH_OUT_TH4_V 0xFFFF +#define SENS_TOUCH_OUT_TH4_S 16 +/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 5*/ +#define SENS_TOUCH_OUT_TH5 0x0000FFFF +#define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S)) +#define SENS_TOUCH_OUT_TH5_V 0xFFFF +#define SENS_TOUCH_OUT_TH5_S 0 + +#define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x0068) +/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 6*/ +#define SENS_TOUCH_OUT_TH6 0x0000FFFF +#define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S)) +#define SENS_TOUCH_OUT_TH6_V 0xFFFF +#define SENS_TOUCH_OUT_TH6_S 16 +/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 7*/ +#define SENS_TOUCH_OUT_TH7 0x0000FFFF +#define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S)) +#define SENS_TOUCH_OUT_TH7_V 0xFFFF +#define SENS_TOUCH_OUT_TH7_S 0 + +#define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x006c) +/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 8*/ +#define SENS_TOUCH_OUT_TH8 0x0000FFFF +#define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S)) +#define SENS_TOUCH_OUT_TH8_V 0xFFFF +#define SENS_TOUCH_OUT_TH8_S 16 +/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 9*/ +#define SENS_TOUCH_OUT_TH9 0x0000FFFF +#define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S)) +#define SENS_TOUCH_OUT_TH9_V 0xFFFF +#define SENS_TOUCH_OUT_TH9_S 0 + +#define SENS_SAR_TOUCH_OUT1_REG (DR_REG_SENS_BASE + 0x0070) +/* SENS_TOUCH_MEAS_OUT0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 0*/ +#define SENS_TOUCH_MEAS_OUT0 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT0_M ((SENS_TOUCH_MEAS_OUT0_V)<<(SENS_TOUCH_MEAS_OUT0_S)) +#define SENS_TOUCH_MEAS_OUT0_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT0_S 16 +/* SENS_TOUCH_MEAS_OUT1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 1*/ +#define SENS_TOUCH_MEAS_OUT1 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT1_M ((SENS_TOUCH_MEAS_OUT1_V)<<(SENS_TOUCH_MEAS_OUT1_S)) +#define SENS_TOUCH_MEAS_OUT1_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT1_S 0 + +#define SENS_SAR_TOUCH_OUT2_REG (DR_REG_SENS_BASE + 0x0074) +/* SENS_TOUCH_MEAS_OUT2 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 2*/ +#define SENS_TOUCH_MEAS_OUT2 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT2_M ((SENS_TOUCH_MEAS_OUT2_V)<<(SENS_TOUCH_MEAS_OUT2_S)) +#define SENS_TOUCH_MEAS_OUT2_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT2_S 16 +/* SENS_TOUCH_MEAS_OUT3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 3*/ +#define SENS_TOUCH_MEAS_OUT3 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT3_M ((SENS_TOUCH_MEAS_OUT3_V)<<(SENS_TOUCH_MEAS_OUT3_S)) +#define SENS_TOUCH_MEAS_OUT3_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT3_S 0 + +#define SENS_SAR_TOUCH_OUT3_REG (DR_REG_SENS_BASE + 0x0078) +/* SENS_TOUCH_MEAS_OUT4 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 4*/ +#define SENS_TOUCH_MEAS_OUT4 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT4_M ((SENS_TOUCH_MEAS_OUT4_V)<<(SENS_TOUCH_MEAS_OUT4_S)) +#define SENS_TOUCH_MEAS_OUT4_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT4_S 16 +/* SENS_TOUCH_MEAS_OUT5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 5*/ +#define SENS_TOUCH_MEAS_OUT5 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT5_M ((SENS_TOUCH_MEAS_OUT5_V)<<(SENS_TOUCH_MEAS_OUT5_S)) +#define SENS_TOUCH_MEAS_OUT5_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT5_S 0 + +#define SENS_SAR_TOUCH_OUT4_REG (DR_REG_SENS_BASE + 0x007c) +/* SENS_TOUCH_MEAS_OUT6 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 6*/ +#define SENS_TOUCH_MEAS_OUT6 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT6_M ((SENS_TOUCH_MEAS_OUT6_V)<<(SENS_TOUCH_MEAS_OUT6_S)) +#define SENS_TOUCH_MEAS_OUT6_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT6_S 16 +/* SENS_TOUCH_MEAS_OUT7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 7*/ +#define SENS_TOUCH_MEAS_OUT7 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT7_M ((SENS_TOUCH_MEAS_OUT7_V)<<(SENS_TOUCH_MEAS_OUT7_S)) +#define SENS_TOUCH_MEAS_OUT7_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT7_S 0 + +#define SENS_SAR_TOUCH_OUT5_REG (DR_REG_SENS_BASE + 0x0080) +/* SENS_TOUCH_MEAS_OUT8 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 8*/ +#define SENS_TOUCH_MEAS_OUT8 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT8_M ((SENS_TOUCH_MEAS_OUT8_V)<<(SENS_TOUCH_MEAS_OUT8_S)) +#define SENS_TOUCH_MEAS_OUT8_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT8_S 16 +/* SENS_TOUCH_MEAS_OUT9 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 9*/ +#define SENS_TOUCH_MEAS_OUT9 0x0000FFFF +#define SENS_TOUCH_MEAS_OUT9_M ((SENS_TOUCH_MEAS_OUT9_V)<<(SENS_TOUCH_MEAS_OUT9_S)) +#define SENS_TOUCH_MEAS_OUT9_V 0xFFFF +#define SENS_TOUCH_MEAS_OUT9_S 0 + +#define SENS_SAR_TOUCH_CTRL2_REG (DR_REG_SENS_BASE + 0x0084) +/* SENS_TOUCH_MEAS_EN_CLR : WO ;bitpos:[30] ;default: 1'h0 ; */ +/*description: to clear reg_touch_meas_en*/ +#define SENS_TOUCH_MEAS_EN_CLR (BIT(30)) +#define SENS_TOUCH_MEAS_EN_CLR_M (BIT(30)) +#define SENS_TOUCH_MEAS_EN_CLR_V 0x1 +#define SENS_TOUCH_MEAS_EN_CLR_S 30 +/* SENS_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[29:14] ;default: 16'h100 ; */ +/*description: sleep cycles for timer*/ +#define SENS_TOUCH_SLEEP_CYCLES 0x0000FFFF +#define SENS_TOUCH_SLEEP_CYCLES_M ((SENS_TOUCH_SLEEP_CYCLES_V)<<(SENS_TOUCH_SLEEP_CYCLES_S)) +#define SENS_TOUCH_SLEEP_CYCLES_V 0xFFFF +#define SENS_TOUCH_SLEEP_CYCLES_S 14 +/* SENS_TOUCH_START_FORCE : R/W ;bitpos:[13] ;default: 1'h0 ; */ +/*description: 1: to start touch fsm by SW 0: to start touch fsm by timer*/ +#define SENS_TOUCH_START_FORCE (BIT(13)) +#define SENS_TOUCH_START_FORCE_M (BIT(13)) +#define SENS_TOUCH_START_FORCE_V 0x1 +#define SENS_TOUCH_START_FORCE_S 13 +/* SENS_TOUCH_START_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: 1: start touch fsm valid when reg_touch_start_force is set*/ +#define SENS_TOUCH_START_EN (BIT(12)) +#define SENS_TOUCH_START_EN_M (BIT(12)) +#define SENS_TOUCH_START_EN_V 0x1 +#define SENS_TOUCH_START_EN_S 12 +/* SENS_TOUCH_START_FSM_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ +/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START + & TOUCH_XPD is controlled by registers*/ +#define SENS_TOUCH_START_FSM_EN (BIT(11)) +#define SENS_TOUCH_START_FSM_EN_M (BIT(11)) +#define SENS_TOUCH_START_FSM_EN_V 0x1 +#define SENS_TOUCH_START_FSM_EN_S 11 +/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[10] ;default: 1'h0 ; */ +/*description: fsm set 1 to indicate touch touch meas is done*/ +#define SENS_TOUCH_MEAS_DONE (BIT(10)) +#define SENS_TOUCH_MEAS_DONE_M (BIT(10)) +#define SENS_TOUCH_MEAS_DONE_V 0x1 +#define SENS_TOUCH_MEAS_DONE_S 10 +/* SENS_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: 10-bit register to indicate which pads are "touched"*/ +#define SENS_TOUCH_MEAS_EN 0x000003FF +#define SENS_TOUCH_MEAS_EN_M ((SENS_TOUCH_MEAS_EN_V)<<(SENS_TOUCH_MEAS_EN_S)) +#define SENS_TOUCH_MEAS_EN_V 0x3FF +#define SENS_TOUCH_MEAS_EN_S 0 + +#define SENS_SAR_TOUCH_ENABLE_REG (DR_REG_SENS_BASE + 0x008c) +/* SENS_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */ +/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is + "touched" only if at least one of touch pad in SET1 is "touched".*/ +#define SENS_TOUCH_PAD_OUTEN1 0x000003FF +#define SENS_TOUCH_PAD_OUTEN1_M ((SENS_TOUCH_PAD_OUTEN1_V)<<(SENS_TOUCH_PAD_OUTEN1_S)) +#define SENS_TOUCH_PAD_OUTEN1_V 0x3FF +#define SENS_TOUCH_PAD_OUTEN1_S 20 +/* SENS_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */ +/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is + "touched" only if at least one of touch pad in SET2 is "touched".*/ +#define SENS_TOUCH_PAD_OUTEN2 0x000003FF +#define SENS_TOUCH_PAD_OUTEN2_M ((SENS_TOUCH_PAD_OUTEN2_V)<<(SENS_TOUCH_PAD_OUTEN2_S)) +#define SENS_TOUCH_PAD_OUTEN2_V 0x3FF +#define SENS_TOUCH_PAD_OUTEN2_S 10 +/* SENS_TOUCH_PAD_WORKEN : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */ +/*description: Bitmap defining the working set during the measurement.*/ +#define SENS_TOUCH_PAD_WORKEN 0x000003FF +#define SENS_TOUCH_PAD_WORKEN_M ((SENS_TOUCH_PAD_WORKEN_V)<<(SENS_TOUCH_PAD_WORKEN_S)) +#define SENS_TOUCH_PAD_WORKEN_V 0x3FF +#define SENS_TOUCH_PAD_WORKEN_S 0 + +#define SENS_SAR_READ_CTRL2_REG (DR_REG_SENS_BASE + 0x0090) +/* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Invert SAR ADC2 data*/ +#define SENS_SAR2_DATA_INV (BIT(29)) +#define SENS_SAR2_DATA_INV_M (BIT(29)) +#define SENS_SAR2_DATA_INV_V 0x1 +#define SENS_SAR2_DATA_INV_S 29 +/* SENS_SAR2_DIG_FORCE : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR + ADC2 controlled by RTC ADC2 CTRL*/ +#define SENS_SAR2_DIG_FORCE (BIT(28)) +#define SENS_SAR2_DIG_FORCE_M (BIT(28)) +#define SENS_SAR2_DIG_FORCE_V 0x1 +#define SENS_SAR2_DIG_FORCE_S 28 +/* SENS_SAR2_PWDET_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SAR2_PWDET_FORCE (BIT(27)) +#define SENS_SAR2_PWDET_FORCE_M (BIT(27)) +#define SENS_SAR2_PWDET_FORCE_V 0x1 +#define SENS_SAR2_PWDET_FORCE_S 27 +/* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: */ +#define SENS_SAR2_SAMPLE_NUM 0x000000FF +#define SENS_SAR2_SAMPLE_NUM_M ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S)) +#define SENS_SAR2_SAMPLE_NUM_V 0xFF +#define SENS_SAR2_SAMPLE_NUM_S 19 +/* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define SENS_SAR2_CLK_GATED (BIT(18)) +#define SENS_SAR2_CLK_GATED_M (BIT(18)) +#define SENS_SAR2_CLK_GATED_V 0x1 +#define SENS_SAR2_CLK_GATED_S 18 +/* SENS_SAR2_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */ +/*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width + 11: for 12-bit width*/ +#define SENS_SAR2_SAMPLE_BIT 0x00000003 +#define SENS_SAR2_SAMPLE_BIT_M ((SENS_SAR2_SAMPLE_BIT_V)<<(SENS_SAR2_SAMPLE_BIT_S)) +#define SENS_SAR2_SAMPLE_BIT_V 0x3 +#define SENS_SAR2_SAMPLE_BIT_S 16 +/* SENS_SAR2_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */ +/*description: sample cycles for SAR ADC2*/ +#define SENS_SAR2_SAMPLE_CYCLE 0x000000FF +#define SENS_SAR2_SAMPLE_CYCLE_M ((SENS_SAR2_SAMPLE_CYCLE_V)<<(SENS_SAR2_SAMPLE_CYCLE_S)) +#define SENS_SAR2_SAMPLE_CYCLE_V 0xFF +#define SENS_SAR2_SAMPLE_CYCLE_S 8 +/* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: clock divider*/ +#define SENS_SAR2_CLK_DIV 0x000000FF +#define SENS_SAR2_CLK_DIV_M ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S)) +#define SENS_SAR2_CLK_DIV_V 0xFF +#define SENS_SAR2_CLK_DIV_S 0 + +#define SENS_SAR_MEAS_START2_REG (DR_REG_SENS_BASE + 0x0094) +/* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 + pad enable bitmap is controlled by ULP-coprocessor*/ +#define SENS_SAR2_EN_PAD_FORCE (BIT(31)) +#define SENS_SAR2_EN_PAD_FORCE_M (BIT(31)) +#define SENS_SAR2_EN_PAD_FORCE_V 0x1 +#define SENS_SAR2_EN_PAD_FORCE_S 31 +/* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ +/*description: SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1*/ +#define SENS_SAR2_EN_PAD 0x00000FFF +#define SENS_SAR2_EN_PAD_M ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S)) +#define SENS_SAR2_EN_PAD_V 0xFFF +#define SENS_SAR2_EN_PAD_S 19 +/* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 + controller is started by ULP-coprocessor*/ +#define SENS_MEAS2_START_FORCE (BIT(18)) +#define SENS_MEAS2_START_FORCE_M (BIT(18)) +#define SENS_MEAS2_START_FORCE_V 0x1 +#define SENS_MEAS2_START_FORCE_S 18 +/* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: SAR ADC2 controller (in RTC) starts conversion only active when + reg_meas2_start_force = 1*/ +#define SENS_MEAS2_START_SAR (BIT(17)) +#define SENS_MEAS2_START_SAR_M (BIT(17)) +#define SENS_MEAS2_START_SAR_V 0x1 +#define SENS_MEAS2_START_SAR_S 17 +/* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: SAR ADC2 conversion done indication*/ +#define SENS_MEAS2_DONE_SAR (BIT(16)) +#define SENS_MEAS2_DONE_SAR_M (BIT(16)) +#define SENS_MEAS2_DONE_SAR_V 0x1 +#define SENS_MEAS2_DONE_SAR_S 16 +/* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: SAR ADC2 data*/ +#define SENS_MEAS2_DATA_SAR 0x0000FFFF +#define SENS_MEAS2_DATA_SAR_M ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S)) +#define SENS_MEAS2_DATA_SAR_V 0xFFFF +#define SENS_MEAS2_DATA_SAR_S 0 + +#define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x0098) +/* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: invert PDAC_CLK*/ +#define SENS_DAC_CLK_INV (BIT(25)) +#define SENS_DAC_CLK_INV_M (BIT(25)) +#define SENS_DAC_CLK_INV_V 0x1 +#define SENS_DAC_CLK_INV_S 25 +/* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: force PDAC_CLK to high*/ +#define SENS_DAC_CLK_FORCE_HIGH (BIT(24)) +#define SENS_DAC_CLK_FORCE_HIGH_M (BIT(24)) +#define SENS_DAC_CLK_FORCE_HIGH_V 0x1 +#define SENS_DAC_CLK_FORCE_HIGH_S 24 +/* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: force PDAC_CLK to low*/ +#define SENS_DAC_CLK_FORCE_LOW (BIT(23)) +#define SENS_DAC_CLK_FORCE_LOW_M (BIT(23)) +#define SENS_DAC_CLK_FORCE_LOW_V 0x1 +#define SENS_DAC_CLK_FORCE_LOW_S 23 +/* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA*/ +#define SENS_DAC_DIG_FORCE (BIT(22)) +#define SENS_DAC_DIG_FORCE_M (BIT(22)) +#define SENS_DAC_DIG_FORCE_V 0x1 +#define SENS_DAC_DIG_FORCE_S 22 +/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ +/*description: */ +#define SENS_DEBUG_BIT_SEL 0x0000001F +#define SENS_DEBUG_BIT_SEL_M ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S)) +#define SENS_DEBUG_BIT_SEL_V 0x1F +#define SENS_DEBUG_BIT_SEL_S 17 +/* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: 1: enable CW generator 0: disable CW generator*/ +#define SENS_SW_TONE_EN (BIT(16)) +#define SENS_SW_TONE_EN_M (BIT(16)) +#define SENS_SW_TONE_EN_V 0x1 +#define SENS_SW_TONE_EN_S 16 +/* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: frequency step for CW generator can be used to adjust the frequency*/ +#define SENS_SW_FSTEP 0x0000FFFF +#define SENS_SW_FSTEP_M ((SENS_SW_FSTEP_V)<<(SENS_SW_FSTEP_S)) +#define SENS_SW_FSTEP_V 0xFFFF +#define SENS_SW_FSTEP_S 0 + +#define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x009c) +/* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: 1: to select CW generator as source to PDAC2_DAC[7:0] 0: to + select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/ +#define SENS_DAC_CW_EN2 (BIT(25)) +#define SENS_DAC_CW_EN2_M (BIT(25)) +#define SENS_DAC_CW_EN2_V 0x1 +#define SENS_DAC_CW_EN2_S 25 +/* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: 1: to select CW generator as source to PDAC1_DAC[7:0] 0: to + select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/ +#define SENS_DAC_CW_EN1 (BIT(24)) +#define SENS_DAC_CW_EN1_M (BIT(24)) +#define SENS_DAC_CW_EN1_V 0x1 +#define SENS_DAC_CW_EN1_S 24 +/* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: 00: do not invert any bits 01: invert all bits 10: invert MSB + 11: invert all bits except MSB*/ +#define SENS_DAC_INV2 0x00000003 +#define SENS_DAC_INV2_M ((SENS_DAC_INV2_V)<<(SENS_DAC_INV2_S)) +#define SENS_DAC_INV2_V 0x3 +#define SENS_DAC_INV2_S 22 +/* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */ +/*description: 00: do not invert any bits 01: invert all bits 10: invert MSB + 11: invert all bits except MSB*/ +#define SENS_DAC_INV1 0x00000003 +#define SENS_DAC_INV1_M ((SENS_DAC_INV1_V)<<(SENS_DAC_INV1_S)) +#define SENS_DAC_INV1_V 0x3 +#define SENS_DAC_INV1_S 20 +/* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ +#define SENS_DAC_SCALE2 0x00000003 +#define SENS_DAC_SCALE2_M ((SENS_DAC_SCALE2_V)<<(SENS_DAC_SCALE2_S)) +#define SENS_DAC_SCALE2_V 0x3 +#define SENS_DAC_SCALE2_S 18 +/* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ +/*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ +#define SENS_DAC_SCALE1 0x00000003 +#define SENS_DAC_SCALE1_M ((SENS_DAC_SCALE1_V)<<(SENS_DAC_SCALE1_S)) +#define SENS_DAC_SCALE1_V 0x3 +#define SENS_DAC_SCALE1_S 16 +/* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: DC offset for DAC2 CW generator*/ +#define SENS_DAC_DC2 0x000000FF +#define SENS_DAC_DC2_M ((SENS_DAC_DC2_V)<<(SENS_DAC_DC2_S)) +#define SENS_DAC_DC2_V 0xFF +#define SENS_DAC_DC2_S 8 +/* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: DC offset for DAC1 CW generator*/ +#define SENS_DAC_DC1 0x000000FF +#define SENS_DAC_DC1_M ((SENS_DAC_DC1_V)<<(SENS_DAC_DC1_S)) +#define SENS_DAC_DC1_V 0xFF +#define SENS_DAC_DC1_S 0 + +#define SENS_SAR_MEAS_CTRL2_REG (DR_REG_SENS_BASE + 0x0a0) +/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[18:17] ;default: 2'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S)) +#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_GND_FORCE_S 17 +#define SENS_AMP_SHORT_REF_GND_FORCE_FSM 0 // Use FSM to control power down +#define SENS_AMP_SHORT_REF_GND_FORCE_PD 2 // Force power down +#define SENS_AMP_SHORT_REF_GND_FORCE_PU 3 // Force power up +/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S)) +#define SENS_AMP_SHORT_REF_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_FORCE_S 15 +#define SENS_AMP_SHORT_REF_FORCE_FSM 0 // Use FSM to control power down +#define SENS_AMP_SHORT_REF_FORCE_PD 2 // Force power down +#define SENS_AMP_SHORT_REF_FORCE_PU 3 // Force power up +/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: */ +#define SENS_AMP_RST_FB_FORCE 0x00000003 +#define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S)) +#define SENS_AMP_RST_FB_FORCE_V 0x3 +#define SENS_AMP_RST_FB_FORCE_S 13 +#define SENS_AMP_RST_FB_FORCE_FSM 0 // Use FSM to control power down +#define SENS_AMP_RST_FB_FORCE_PD 2 // Force power down +#define SENS_AMP_RST_FB_FORCE_PU 3 // Force power up +/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */ +/*description: */ +#define SENS_SAR2_RSTB_FORCE 0x00000003 +#define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S)) +#define SENS_SAR2_RSTB_FORCE_V 0x3 +#define SENS_SAR2_RSTB_FORCE_S 11 +#define SENS_SAR2_RSTB_FORCE_FSM 0 // Use FSM to control power down +#define SENS_SAR2_RSTB_FORCE_PD 2 // Force power down +#define SENS_SAR2_RSTB_FORCE_PU 3 // Force power up +/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SAR_RSTB_FSM_IDLE (BIT(10)) +#define SENS_SAR_RSTB_FSM_IDLE_M (BIT(10)) +#define SENS_SAR_RSTB_FSM_IDLE_V 0x1 +#define SENS_SAR_RSTB_FSM_IDLE_S 10 +/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SENS_XPD_SAR_FSM_IDLE (BIT(9)) +#define SENS_XPD_SAR_FSM_IDLE_M (BIT(9)) +#define SENS_XPD_SAR_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_FSM_IDLE_S 9 +/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(8)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(8)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 8 +/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(7)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(7)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_FSM_IDLE_S 7 +/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_AMP_RST_FB_FSM_IDLE (BIT(6)) +#define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(6)) +#define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 +#define SENS_AMP_RST_FB_FSM_IDLE_S 6 +/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(5)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(5)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_AMP_FSM_IDLE_S 5 +/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(4)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(4)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 +#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 4 +/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ +/*description: */ +#define SENS_SAR1_DAC_XPD_FSM 0x0000000F +#define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S)) +#define SENS_SAR1_DAC_XPD_FSM_V 0xF +#define SENS_SAR1_DAC_XPD_FSM_S 0 + +#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x00F8) +/* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SENS_SAR_NOUSE 0xFFFFFFFF +#define SENS_SAR_NOUSE_M ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S)) +#define SENS_SAR_NOUSE_V 0xFFFFFFFF +#define SENS_SAR_NOUSE_S 0 + +#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x00FC) +/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605180 ; */ +/*description: */ +#define SENS_SAR_DATE 0x0FFFFFFF +#define SENS_SAR_DATE_M ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S)) +#define SENS_SAR_DATE_V 0xFFFFFFF +#define SENS_SAR_DATE_S 0 + + + + +#endif /*_SOC_SENS_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/sens_struct.h b/tools/sdk/include/soc/include/soc/sens_struct.h new file mode 100644 index 00000000000..f572148cd1d --- /dev/null +++ b/tools/sdk/include/soc/include/soc/sens_struct.h @@ -0,0 +1,328 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SENS_STRUCT_H_ +#define _SOC_SENS_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t sar1_clk_div: 8; + uint32_t sar1_sample_cycle: 8; + uint32_t sar1_sample_bit: 2; + uint32_t sar1_clk_gated: 1; + uint32_t sar1_sample_num: 8; + uint32_t sar1_dig_force: 1; /*1: ADC1 is controlled by the digital controller 0: RTC controller*/ + uint32_t sar1_data_inv: 1; + uint32_t reserved29: 3; + }; + uint32_t val; + } sar_read_ctrl; + uint32_t sar_read_status1; /**/ + union { + struct { + uint32_t sar_amp_wait1:16; + uint32_t sar_amp_wait2:16; + }; + uint32_t val; + } sar_meas_wait1; + union { + struct { + uint32_t sar_amp_wait3: 16; + uint32_t force_xpd_amp: 2; + uint32_t force_xpd_sar: 2; + uint32_t sar2_rstb_wait: 8; + uint32_t reserved28: 4; + }; + uint32_t val; + } sar_meas_wait2; + union { + struct { + uint32_t xpd_sar_amp_fsm: 4; + uint32_t amp_rst_fb_fsm: 4; + uint32_t amp_short_ref_fsm: 4; + uint32_t amp_short_ref_gnd_fsm: 4; + uint32_t xpd_sar_fsm: 4; + uint32_t sar_rstb_fsm: 4; + uint32_t sar2_xpd_wait: 8; + }; + uint32_t val; + } sar_meas_ctrl; + uint32_t sar_read_status2; /**/ + uint32_t ulp_cp_sleep_cyc0; /**/ + uint32_t ulp_cp_sleep_cyc1; /**/ + uint32_t ulp_cp_sleep_cyc2; /**/ + uint32_t ulp_cp_sleep_cyc3; /**/ + uint32_t ulp_cp_sleep_cyc4; /**/ + union { + struct { + uint32_t sar1_bit_width: 2; + uint32_t sar2_bit_width: 2; + uint32_t sar2_en_test: 1; + uint32_t sar2_pwdet_cct: 3; + uint32_t ulp_cp_force_start_top: 1; + uint32_t ulp_cp_start_top: 1; + uint32_t sarclk_en: 1; + uint32_t pc_init: 11; + uint32_t sar2_stop: 1; + uint32_t sar1_stop: 1; + uint32_t sar2_pwdet_en: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } sar_start_force; + union { + struct { + uint32_t mem_wr_addr_init: 11; + uint32_t mem_wr_addr_size: 11; + uint32_t rtc_mem_wr_offst_clr: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } sar_mem_wr_ctrl; + uint32_t sar_atten1; /**/ + uint32_t sar_atten2; /**/ + union { + struct { + uint32_t i2c_slave_addr1: 11; + uint32_t i2c_slave_addr0: 11; + uint32_t meas_status: 8; + uint32_t reserved30: 2; + }; + uint32_t val; + } sar_slave_addr1; + union { + struct { + uint32_t i2c_slave_addr3:11; + uint32_t i2c_slave_addr2:11; + uint32_t reserved22: 10; + }; + uint32_t val; + } sar_slave_addr2; + union { + struct { + uint32_t i2c_slave_addr5:11; + uint32_t i2c_slave_addr4:11; + uint32_t tsens_out: 8; + uint32_t tsens_rdy_out: 1; + uint32_t reserved31: 1; + }; + uint32_t val; + } sar_slave_addr3; + union { + struct { + uint32_t i2c_slave_addr7:11; + uint32_t i2c_slave_addr6:11; + uint32_t i2c_rdata: 8; + uint32_t i2c_done: 1; + uint32_t reserved31: 1; + }; + uint32_t val; + } sar_slave_addr4; + union { + struct { + uint32_t tsens_xpd_wait: 12; + uint32_t tsens_xpd_force: 1; + uint32_t tsens_clk_inv: 1; + uint32_t tsens_clk_gated: 1; + uint32_t tsens_in_inv: 1; + uint32_t tsens_clk_div: 8; + uint32_t tsens_power_up: 1; + uint32_t tsens_power_up_force: 1; + uint32_t tsens_dump_out: 1; + uint32_t reserved27: 5; + }; + uint32_t val; + } sar_tctrl; + union { + struct { + uint32_t sar_i2c_ctrl: 28; + uint32_t sar_i2c_start: 1; + uint32_t sar_i2c_start_force: 1; + uint32_t reserved30: 2; + }; + uint32_t val; + } sar_i2c_ctrl; + union { + struct { + uint32_t meas1_data_sar: 16; + uint32_t meas1_done_sar: 1; + uint32_t meas1_start_sar: 1; + uint32_t meas1_start_force: 1; /*1: ADC1 is controlled by the digital or RTC controller 0: Ulp coprocessor*/ + uint32_t sar1_en_pad: 12; + uint32_t sar1_en_pad_force: 1; /*1: Data ports are controlled by the digital or RTC controller 0: Ulp coprocessor*/ + }; + uint32_t val; + } sar_meas_start1; + union { + struct { + uint32_t touch_meas_delay:16; + uint32_t touch_xpd_wait: 8; + uint32_t touch_out_sel: 1; + uint32_t touch_out_1en: 1; + uint32_t xpd_hall_force: 1; /*1: Power of hall sensor is controlled by the digital or RTC controller 0: Ulp coprocessor*/ + uint32_t hall_phase_force: 1; /*1: Phase of hall sensor is controlled by the digital or RTC controller 0: Ulp coprocessor*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } sar_touch_ctrl1; + union { + struct { + uint32_t l_thresh: 16; + uint32_t h_thresh: 16; + }; + uint32_t val; + } touch_thresh[5]; + union { + struct { + uint32_t l_val: 16; + uint32_t h_val: 16; + }; + uint32_t val; + } touch_meas[5]; + union { + struct { + uint32_t touch_meas_en: 10; + uint32_t touch_meas_done: 1; + uint32_t touch_start_fsm_en: 1; + uint32_t touch_start_en: 1; + uint32_t touch_start_force: 1; + uint32_t touch_sleep_cycles:16; + uint32_t touch_meas_en_clr: 1; + uint32_t reserved31: 1; + }; + uint32_t val; + } sar_touch_ctrl2; + uint32_t reserved_88; + union { + struct { + uint32_t touch_pad_worken:10; + uint32_t touch_pad_outen2:10; + uint32_t touch_pad_outen1:10; + uint32_t reserved30: 2; + }; + uint32_t val; + } sar_touch_enable; + union { + struct { + uint32_t sar2_clk_div: 8; + uint32_t sar2_sample_cycle: 8; + uint32_t sar2_sample_bit: 2; + uint32_t sar2_clk_gated: 1; + uint32_t sar2_sample_num: 8; + uint32_t sar2_pwdet_force: 1; /*1: ADC2 is controlled by PWDET 0: digital or RTC controller*/ + uint32_t sar2_dig_force: 1; /*1: ADC2 is controlled by the digital controller 0: RTC controller*/ + uint32_t sar2_data_inv: 1; + uint32_t reserved30: 2; + }; + uint32_t val; + } sar_read_ctrl2; + union { + struct { + uint32_t meas2_data_sar: 16; + uint32_t meas2_done_sar: 1; + uint32_t meas2_start_sar: 1; + uint32_t meas2_start_force: 1; /*1: ADC2 is controlled by the digital or RTC controller 0: Ulp coprocessor*/ + uint32_t sar2_en_pad: 12; + uint32_t sar2_en_pad_force: 1; /*1: Data ports are controlled by the digital or RTC controller 0: Ulp coprocessor*/ + }; + uint32_t val; + } sar_meas_start2; + union { + struct { + uint32_t sw_fstep: 16; + uint32_t sw_tone_en: 1; + uint32_t debug_bit_sel: 5; + uint32_t dac_dig_force: 1; + uint32_t dac_clk_force_low: 1; + uint32_t dac_clk_force_high: 1; + uint32_t dac_clk_inv: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } sar_dac_ctrl1; + union { + struct { + uint32_t dac_dc1: 8; + uint32_t dac_dc2: 8; + uint32_t dac_scale1: 2; + uint32_t dac_scale2: 2; + uint32_t dac_inv1: 2; + uint32_t dac_inv2: 2; + uint32_t dac_cw_en1: 1; + uint32_t dac_cw_en2: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } sar_dac_ctrl2; + union { + struct { + uint32_t sar1_dac_xpd_fsm: 4; + uint32_t sar1_dac_xpd_fsm_idle: 1; + uint32_t xpd_sar_amp_fsm_idle: 1; + uint32_t amp_rst_fb_fsm_idle: 1; + uint32_t amp_short_ref_fsm_idle: 1; + uint32_t amp_short_ref_gnd_fsm_idle: 1; + uint32_t xpd_sar_fsm_idle: 1; + uint32_t sar_rstb_fsm_idle: 1; + uint32_t sar2_rstb_force: 2; + uint32_t amp_rst_fb_force: 2; + uint32_t amp_short_ref_force: 2; + uint32_t amp_short_ref_gnd_force: 2; + uint32_t reserved19: 13; + }; + uint32_t val; + } sar_meas_ctrl2; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t sar_nouse; /**/ + union { + struct { + uint32_t sar_date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } sardate; +} sens_dev_t; +extern sens_dev_t SENS; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_SENS_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/slc_reg.h b/tools/sdk/include/soc/include/soc/slc_reg.h new file mode 100644 index 00000000000..3d4541cccbc --- /dev/null +++ b/tools/sdk/include/soc/include/soc/slc_reg.h @@ -0,0 +1,3244 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SLC_REG_H_ +#define _SOC_SLC_REG_H_ + + +#include "soc.h" +#define SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0) +/* SLC_SLC1_TOKEN_SEL : R/W ;bitpos:[31] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC1_TOKEN_SEL (BIT(31)) +#define SLC_SLC1_TOKEN_SEL_M (BIT(31)) +#define SLC_SLC1_TOKEN_SEL_V 0x1 +#define SLC_SLC1_TOKEN_SEL_S 31 +/* SLC_SLC1_TOKEN_AUTO_CLR : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC1_TOKEN_AUTO_CLR (BIT(30)) +#define SLC_SLC1_TOKEN_AUTO_CLR_M (BIT(30)) +#define SLC_SLC1_TOKEN_AUTO_CLR_V 0x1 +#define SLC_SLC1_TOKEN_AUTO_CLR_S 30 +/* SLC_SLC1_TXDATA_BURST_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_TXDATA_BURST_EN (BIT(29)) +#define SLC_SLC1_TXDATA_BURST_EN_M (BIT(29)) +#define SLC_SLC1_TXDATA_BURST_EN_V 0x1 +#define SLC_SLC1_TXDATA_BURST_EN_S 29 +/* SLC_SLC1_TXDSCR_BURST_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_TXDSCR_BURST_EN (BIT(28)) +#define SLC_SLC1_TXDSCR_BURST_EN_M (BIT(28)) +#define SLC_SLC1_TXDSCR_BURST_EN_V 0x1 +#define SLC_SLC1_TXDSCR_BURST_EN_S 28 +/* SLC_SLC1_TXLINK_AUTO_RET : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_TXLINK_AUTO_RET (BIT(27)) +#define SLC_SLC1_TXLINK_AUTO_RET_M (BIT(27)) +#define SLC_SLC1_TXLINK_AUTO_RET_V 0x1 +#define SLC_SLC1_TXLINK_AUTO_RET_S 27 +/* SLC_SLC1_RXLINK_AUTO_RET : R/W ;bitpos:[26] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_RXLINK_AUTO_RET (BIT(26)) +#define SLC_SLC1_RXLINK_AUTO_RET_M (BIT(26)) +#define SLC_SLC1_RXLINK_AUTO_RET_V 0x1 +#define SLC_SLC1_RXLINK_AUTO_RET_S 26 +/* SLC_SLC1_RXDATA_BURST_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_RXDATA_BURST_EN (BIT(25)) +#define SLC_SLC1_RXDATA_BURST_EN_M (BIT(25)) +#define SLC_SLC1_RXDATA_BURST_EN_V 0x1 +#define SLC_SLC1_RXDATA_BURST_EN_S 25 +/* SLC_SLC1_RXDSCR_BURST_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_RXDSCR_BURST_EN (BIT(24)) +#define SLC_SLC1_RXDSCR_BURST_EN_M (BIT(24)) +#define SLC_SLC1_RXDSCR_BURST_EN_V 0x1 +#define SLC_SLC1_RXDSCR_BURST_EN_S 24 +/* SLC_SLC1_RX_NO_RESTART_CLR : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_NO_RESTART_CLR (BIT(23)) +#define SLC_SLC1_RX_NO_RESTART_CLR_M (BIT(23)) +#define SLC_SLC1_RX_NO_RESTART_CLR_V 0x1 +#define SLC_SLC1_RX_NO_RESTART_CLR_S 23 +/* SLC_SLC1_RX_AUTO_WRBACK : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_AUTO_WRBACK (BIT(22)) +#define SLC_SLC1_RX_AUTO_WRBACK_M (BIT(22)) +#define SLC_SLC1_RX_AUTO_WRBACK_V 0x1 +#define SLC_SLC1_RX_AUTO_WRBACK_S 22 +/* SLC_SLC1_RX_LOOP_TEST : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_RX_LOOP_TEST (BIT(21)) +#define SLC_SLC1_RX_LOOP_TEST_M (BIT(21)) +#define SLC_SLC1_RX_LOOP_TEST_V 0x1 +#define SLC_SLC1_RX_LOOP_TEST_S 21 +/* SLC_SLC1_TX_LOOP_TEST : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_TX_LOOP_TEST (BIT(20)) +#define SLC_SLC1_TX_LOOP_TEST_M (BIT(20)) +#define SLC_SLC1_TX_LOOP_TEST_V 0x1 +#define SLC_SLC1_TX_LOOP_TEST_S 20 +/* SLC_SLC1_WR_RETRY_MASK_EN : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_WR_RETRY_MASK_EN (BIT(19)) +#define SLC_SLC1_WR_RETRY_MASK_EN_M (BIT(19)) +#define SLC_SLC1_WR_RETRY_MASK_EN_V 0x1 +#define SLC_SLC1_WR_RETRY_MASK_EN_S 19 +/* SLC_SLC0_WR_RETRY_MASK_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_MASK_EN (BIT(18)) +#define SLC_SLC0_WR_RETRY_MASK_EN_M (BIT(18)) +#define SLC_SLC0_WR_RETRY_MASK_EN_V 0x1 +#define SLC_SLC0_WR_RETRY_MASK_EN_S 18 +/* SLC_SLC1_RX_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_RST (BIT(17)) +#define SLC_SLC1_RX_RST_M (BIT(17)) +#define SLC_SLC1_RX_RST_V 0x1 +#define SLC_SLC1_RX_RST_S 17 +/* SLC_SLC1_TX_RST : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC1_TX_RST (BIT(16)) +#define SLC_SLC1_TX_RST_M (BIT(16)) +#define SLC_SLC1_TX_RST_V 0x1 +#define SLC_SLC1_TX_RST_S 16 +/* SLC_SLC0_TOKEN_SEL : R/W ;bitpos:[15] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_TOKEN_SEL (BIT(15)) +#define SLC_SLC0_TOKEN_SEL_M (BIT(15)) +#define SLC_SLC0_TOKEN_SEL_V 0x1 +#define SLC_SLC0_TOKEN_SEL_S 15 +/* SLC_SLC0_TOKEN_AUTO_CLR : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_TOKEN_AUTO_CLR (BIT(14)) +#define SLC_SLC0_TOKEN_AUTO_CLR_M (BIT(14)) +#define SLC_SLC0_TOKEN_AUTO_CLR_V 0x1 +#define SLC_SLC0_TOKEN_AUTO_CLR_S 14 +/* SLC_SLC0_TXDATA_BURST_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TXDATA_BURST_EN (BIT(13)) +#define SLC_SLC0_TXDATA_BURST_EN_M (BIT(13)) +#define SLC_SLC0_TXDATA_BURST_EN_V 0x1 +#define SLC_SLC0_TXDATA_BURST_EN_S 13 +/* SLC_SLC0_TXDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TXDSCR_BURST_EN (BIT(12)) +#define SLC_SLC0_TXDSCR_BURST_EN_M (BIT(12)) +#define SLC_SLC0_TXDSCR_BURST_EN_V 0x1 +#define SLC_SLC0_TXDSCR_BURST_EN_S 12 +/* SLC_SLC0_TXLINK_AUTO_RET : R/W ;bitpos:[11] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_AUTO_RET (BIT(11)) +#define SLC_SLC0_TXLINK_AUTO_RET_M (BIT(11)) +#define SLC_SLC0_TXLINK_AUTO_RET_V 0x1 +#define SLC_SLC0_TXLINK_AUTO_RET_S 11 +/* SLC_SLC0_RXLINK_AUTO_RET : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_AUTO_RET (BIT(10)) +#define SLC_SLC0_RXLINK_AUTO_RET_M (BIT(10)) +#define SLC_SLC0_RXLINK_AUTO_RET_V 0x1 +#define SLC_SLC0_RXLINK_AUTO_RET_S 10 +/* SLC_SLC0_RXDATA_BURST_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RXDATA_BURST_EN (BIT(9)) +#define SLC_SLC0_RXDATA_BURST_EN_M (BIT(9)) +#define SLC_SLC0_RXDATA_BURST_EN_V 0x1 +#define SLC_SLC0_RXDATA_BURST_EN_S 9 +/* SLC_SLC0_RXDSCR_BURST_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RXDSCR_BURST_EN (BIT(8)) +#define SLC_SLC0_RXDSCR_BURST_EN_M (BIT(8)) +#define SLC_SLC0_RXDSCR_BURST_EN_V 0x1 +#define SLC_SLC0_RXDSCR_BURST_EN_S 8 +/* SLC_SLC0_RX_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_NO_RESTART_CLR (BIT(7)) +#define SLC_SLC0_RX_NO_RESTART_CLR_M (BIT(7)) +#define SLC_SLC0_RX_NO_RESTART_CLR_V 0x1 +#define SLC_SLC0_RX_NO_RESTART_CLR_S 7 +/* SLC_SLC0_RX_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_AUTO_WRBACK (BIT(6)) +#define SLC_SLC0_RX_AUTO_WRBACK_M (BIT(6)) +#define SLC_SLC0_RX_AUTO_WRBACK_V 0x1 +#define SLC_SLC0_RX_AUTO_WRBACK_S 6 +/* SLC_SLC0_RX_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_LOOP_TEST (BIT(5)) +#define SLC_SLC0_RX_LOOP_TEST_M (BIT(5)) +#define SLC_SLC0_RX_LOOP_TEST_V 0x1 +#define SLC_SLC0_RX_LOOP_TEST_S 5 +/* SLC_SLC0_TX_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TX_LOOP_TEST (BIT(4)) +#define SLC_SLC0_TX_LOOP_TEST_M (BIT(4)) +#define SLC_SLC0_TX_LOOP_TEST_V 0x1 +#define SLC_SLC0_TX_LOOP_TEST_S 4 +/* SLC_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_AHBM_RST (BIT(3)) +#define SLC_AHBM_RST_M (BIT(3)) +#define SLC_AHBM_RST_V 0x1 +#define SLC_AHBM_RST_S 3 +/* SLC_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_AHBM_FIFO_RST (BIT(2)) +#define SLC_AHBM_FIFO_RST_M (BIT(2)) +#define SLC_AHBM_FIFO_RST_V 0x1 +#define SLC_AHBM_FIFO_RST_S 2 +/* SLC_SLC0_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_RST (BIT(1)) +#define SLC_SLC0_RX_RST_M (BIT(1)) +#define SLC_SLC0_RX_RST_V 0x1 +#define SLC_SLC0_RX_RST_S 1 +/* SLC_SLC0_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_RST (BIT(0)) +#define SLC_SLC0_TX_RST_M (BIT(0)) +#define SLC_SLC0_TX_RST_V 0x1 +#define SLC_SLC0_TX_RST_S 0 + +#define SLC_0INT_RAW_REG (DR_REG_SLC_BASE + 0x4) +/* SLC_SLC0_RX_QUICK_EOF_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S 26 +/* SLC_CMD_DTC_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_RAW (BIT(25)) +#define SLC_CMD_DTC_INT_RAW_M (BIT(25)) +#define SLC_CMD_DTC_INT_RAW_V 0x1 +#define SLC_CMD_DTC_INT_RAW_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_RAW_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_RAW_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_RAW_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_RAW_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_RAW_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_RAW_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S 19 +/* SLC_SLC0_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_RAW (BIT(18)) +#define SLC_SLC0_TOHOST_INT_RAW_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_RAW_V 0x1 +#define SLC_SLC0_TOHOST_INT_RAW_S 18 +/* SLC_SLC0_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_RAW (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_RAW_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_RAW_V 0x1 +#define SLC_SLC0_RX_EOF_INT_RAW_S 17 +/* SLC_SLC0_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_RAW (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_RAW_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_RAW_V 0x1 +#define SLC_SLC0_RX_DONE_INT_RAW_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_RAW_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_RAW_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_RAW_S 15 +/* SLC_SLC0_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_RAW (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_RAW_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_RAW_V 0x1 +#define SLC_SLC0_TX_DONE_INT_RAW_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S 12 +/* SLC_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_RAW (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_RAW_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_RAW_V 0x1 +#define SLC_SLC0_TX_OVF_INT_RAW_S 11 +/* SLC_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_RAW (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_RAW_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_RAW_V 0x1 +#define SLC_SLC0_RX_UDF_INT_RAW_S 10 +/* SLC_SLC0_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_RAW (BIT(9)) +#define SLC_SLC0_TX_START_INT_RAW_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_RAW_V 0x1 +#define SLC_SLC0_TX_START_INT_RAW_S 9 +/* SLC_SLC0_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_RAW (BIT(8)) +#define SLC_SLC0_RX_START_INT_RAW_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_RAW_V 0x1 +#define SLC_SLC0_RX_START_INT_RAW_S 8 +/* SLC_FRHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_RAW (BIT(7)) +#define SLC_FRHOST_BIT7_INT_RAW_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT7_INT_RAW_S 7 +/* SLC_FRHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_RAW (BIT(6)) +#define SLC_FRHOST_BIT6_INT_RAW_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT6_INT_RAW_S 6 +/* SLC_FRHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_RAW (BIT(5)) +#define SLC_FRHOST_BIT5_INT_RAW_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT5_INT_RAW_S 5 +/* SLC_FRHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_RAW (BIT(4)) +#define SLC_FRHOST_BIT4_INT_RAW_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT4_INT_RAW_S 4 +/* SLC_FRHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_RAW (BIT(3)) +#define SLC_FRHOST_BIT3_INT_RAW_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT3_INT_RAW_S 3 +/* SLC_FRHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_RAW (BIT(2)) +#define SLC_FRHOST_BIT2_INT_RAW_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT2_INT_RAW_S 2 +/* SLC_FRHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_RAW (BIT(1)) +#define SLC_FRHOST_BIT1_INT_RAW_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT1_INT_RAW_S 1 +/* SLC_FRHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_RAW (BIT(0)) +#define SLC_FRHOST_BIT0_INT_RAW_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT0_INT_RAW_S 0 + +#define SLC_0INT_ST_REG (DR_REG_SLC_BASE + 0x8) +/* SLC_SLC0_RX_QUICK_EOF_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_ST (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ST_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ST_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_ST_S 26 +/* SLC_CMD_DTC_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_ST (BIT(25)) +#define SLC_CMD_DTC_INT_ST_M (BIT(25)) +#define SLC_CMD_DTC_INT_ST_V 0x1 +#define SLC_CMD_DTC_INT_ST_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_ST (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ST_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ST_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_ST_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ST_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ST_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_ST_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_ST (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ST_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ST_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_ST_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ST_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ST_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_ST_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ST_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ST_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_ST_S 19 +/* SLC_SLC0_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_ST (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ST_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ST_V 0x1 +#define SLC_SLC0_TOHOST_INT_ST_S 18 +/* SLC_SLC0_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_ST (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ST_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ST_V 0x1 +#define SLC_SLC0_RX_EOF_INT_ST_S 17 +/* SLC_SLC0_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_ST (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ST_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ST_V 0x1 +#define SLC_SLC0_RX_DONE_INT_ST_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_ST (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ST_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ST_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_ST_S 15 +/* SLC_SLC0_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_ST (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ST_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ST_V 0x1 +#define SLC_SLC0_TX_DONE_INT_ST_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ST_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_ST_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ST_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_ST_S 12 +/* SLC_SLC0_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_ST (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ST_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ST_V 0x1 +#define SLC_SLC0_TX_OVF_INT_ST_S 11 +/* SLC_SLC0_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_ST (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ST_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ST_V 0x1 +#define SLC_SLC0_RX_UDF_INT_ST_S 10 +/* SLC_SLC0_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_ST (BIT(9)) +#define SLC_SLC0_TX_START_INT_ST_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_ST_V 0x1 +#define SLC_SLC0_TX_START_INT_ST_S 9 +/* SLC_SLC0_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_ST (BIT(8)) +#define SLC_SLC0_RX_START_INT_ST_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_ST_V 0x1 +#define SLC_SLC0_RX_START_INT_ST_S 8 +/* SLC_FRHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_ST (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ST_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ST_V 0x1 +#define SLC_FRHOST_BIT7_INT_ST_S 7 +/* SLC_FRHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_ST (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ST_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ST_V 0x1 +#define SLC_FRHOST_BIT6_INT_ST_S 6 +/* SLC_FRHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_ST (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ST_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ST_V 0x1 +#define SLC_FRHOST_BIT5_INT_ST_S 5 +/* SLC_FRHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_ST (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ST_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ST_V 0x1 +#define SLC_FRHOST_BIT4_INT_ST_S 4 +/* SLC_FRHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_ST (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ST_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ST_V 0x1 +#define SLC_FRHOST_BIT3_INT_ST_S 3 +/* SLC_FRHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_ST (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ST_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ST_V 0x1 +#define SLC_FRHOST_BIT2_INT_ST_S 2 +/* SLC_FRHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_ST (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ST_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ST_V 0x1 +#define SLC_FRHOST_BIT1_INT_ST_S 1 +/* SLC_FRHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_ST (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ST_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ST_V 0x1 +#define SLC_FRHOST_BIT0_INT_ST_S 0 + +#define SLC_0INT_ENA_REG (DR_REG_SLC_BASE + 0xC) +/* SLC_SLC0_RX_QUICK_EOF_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S 26 +/* SLC_CMD_DTC_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_ENA (BIT(25)) +#define SLC_CMD_DTC_INT_ENA_M (BIT(25)) +#define SLC_CMD_DTC_INT_ENA_V 0x1 +#define SLC_CMD_DTC_INT_ENA_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ENA_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ENA_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_ENA_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ENA_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ENA_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_ENA_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S 19 +/* SLC_SLC0_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_ENA (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ENA_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ENA_V 0x1 +#define SLC_SLC0_TOHOST_INT_ENA_S 18 +/* SLC_SLC0_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_ENA (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ENA_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ENA_V 0x1 +#define SLC_SLC0_RX_EOF_INT_ENA_S 17 +/* SLC_SLC0_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_ENA (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ENA_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ENA_V 0x1 +#define SLC_SLC0_RX_DONE_INT_ENA_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ENA_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ENA_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_ENA_S 15 +/* SLC_SLC0_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_ENA (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ENA_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ENA_V 0x1 +#define SLC_SLC0_TX_DONE_INT_ENA_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S 12 +/* SLC_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_ENA (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ENA_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ENA_V 0x1 +#define SLC_SLC0_TX_OVF_INT_ENA_S 11 +/* SLC_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_ENA (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ENA_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ENA_V 0x1 +#define SLC_SLC0_RX_UDF_INT_ENA_S 10 +/* SLC_SLC0_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_ENA (BIT(9)) +#define SLC_SLC0_TX_START_INT_ENA_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_ENA_V 0x1 +#define SLC_SLC0_TX_START_INT_ENA_S 9 +/* SLC_SLC0_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_ENA (BIT(8)) +#define SLC_SLC0_RX_START_INT_ENA_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_ENA_V 0x1 +#define SLC_SLC0_RX_START_INT_ENA_S 8 +/* SLC_FRHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_ENA (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ENA_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT7_INT_ENA_S 7 +/* SLC_FRHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_ENA (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ENA_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT6_INT_ENA_S 6 +/* SLC_FRHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_ENA (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ENA_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT5_INT_ENA_S 5 +/* SLC_FRHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_ENA (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ENA_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT4_INT_ENA_S 4 +/* SLC_FRHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_ENA (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ENA_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT3_INT_ENA_S 3 +/* SLC_FRHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_ENA (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ENA_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT2_INT_ENA_S 2 +/* SLC_FRHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_ENA (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ENA_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT1_INT_ENA_S 1 +/* SLC_FRHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_ENA (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ENA_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT0_INT_ENA_S 0 + +#define SLC_0INT_CLR_REG (DR_REG_SLC_BASE + 0x10) +/* SLC_SLC0_RX_QUICK_EOF_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S 26 +/* SLC_CMD_DTC_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_CLR (BIT(25)) +#define SLC_CMD_DTC_INT_CLR_M (BIT(25)) +#define SLC_CMD_DTC_INT_CLR_V 0x1 +#define SLC_CMD_DTC_INT_CLR_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_CLR_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_CLR_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_CLR_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_CLR_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_CLR_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_CLR_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S 19 +/* SLC_SLC0_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_CLR (BIT(18)) +#define SLC_SLC0_TOHOST_INT_CLR_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_CLR_V 0x1 +#define SLC_SLC0_TOHOST_INT_CLR_S 18 +/* SLC_SLC0_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_CLR (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_CLR_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_CLR_V 0x1 +#define SLC_SLC0_RX_EOF_INT_CLR_S 17 +/* SLC_SLC0_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_CLR (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_CLR_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_CLR_V 0x1 +#define SLC_SLC0_RX_DONE_INT_CLR_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_CLR_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_CLR_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_CLR_S 15 +/* SLC_SLC0_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_CLR (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_CLR_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_CLR_V 0x1 +#define SLC_SLC0_TX_DONE_INT_CLR_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S 12 +/* SLC_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_CLR (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_CLR_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_CLR_V 0x1 +#define SLC_SLC0_TX_OVF_INT_CLR_S 11 +/* SLC_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_CLR (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_CLR_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_CLR_V 0x1 +#define SLC_SLC0_RX_UDF_INT_CLR_S 10 +/* SLC_SLC0_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_CLR (BIT(9)) +#define SLC_SLC0_TX_START_INT_CLR_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_CLR_V 0x1 +#define SLC_SLC0_TX_START_INT_CLR_S 9 +/* SLC_SLC0_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_CLR (BIT(8)) +#define SLC_SLC0_RX_START_INT_CLR_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_CLR_V 0x1 +#define SLC_SLC0_RX_START_INT_CLR_S 8 +/* SLC_FRHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_CLR (BIT(7)) +#define SLC_FRHOST_BIT7_INT_CLR_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT7_INT_CLR_S 7 +/* SLC_FRHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_CLR (BIT(6)) +#define SLC_FRHOST_BIT6_INT_CLR_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT6_INT_CLR_S 6 +/* SLC_FRHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_CLR (BIT(5)) +#define SLC_FRHOST_BIT5_INT_CLR_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT5_INT_CLR_S 5 +/* SLC_FRHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_CLR (BIT(4)) +#define SLC_FRHOST_BIT4_INT_CLR_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT4_INT_CLR_S 4 +/* SLC_FRHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_CLR (BIT(3)) +#define SLC_FRHOST_BIT3_INT_CLR_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT3_INT_CLR_S 3 +/* SLC_FRHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_CLR (BIT(2)) +#define SLC_FRHOST_BIT2_INT_CLR_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT2_INT_CLR_S 2 +/* SLC_FRHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_CLR (BIT(1)) +#define SLC_FRHOST_BIT1_INT_CLR_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT1_INT_CLR_S 1 +/* SLC_FRHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_CLR (BIT(0)) +#define SLC_FRHOST_BIT0_INT_CLR_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT0_INT_CLR_S 0 + +#define SLC_1INT_RAW_REG (DR_REG_SLC_BASE + 0x14) +/* SLC_SLC1_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_RAW_M (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_RAW_V 0x1 +#define SLC_SLC1_TX_ERR_EOF_INT_RAW_S 24 +/* SLC_SLC1_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_RAW_M (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_RAW_V 0x1 +#define SLC_SLC1_WR_RETRY_DONE_INT_RAW_S 23 +/* SLC_SLC1_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_RAW_M (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_RAW_V 0x1 +#define SLC_SLC1_HOST_RD_ACK_INT_RAW_S 22 +/* SLC_SLC1_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_M (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_V 0x1 +#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_S 21 +/* SLC_SLC1_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_RAW_M (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_RAW_V 0x1 +#define SLC_SLC1_RX_DSCR_ERR_INT_RAW_S 20 +/* SLC_SLC1_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_RAW_M (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_RAW_V 0x1 +#define SLC_SLC1_TX_DSCR_ERR_INT_RAW_S 19 +/* SLC_SLC1_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOHOST_INT_RAW (BIT(18)) +#define SLC_SLC1_TOHOST_INT_RAW_M (BIT(18)) +#define SLC_SLC1_TOHOST_INT_RAW_V 0x1 +#define SLC_SLC1_TOHOST_INT_RAW_S 18 +/* SLC_SLC1_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_EOF_INT_RAW (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_RAW_M (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_RAW_V 0x1 +#define SLC_SLC1_RX_EOF_INT_RAW_S 17 +/* SLC_SLC1_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DONE_INT_RAW (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_RAW_M (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_RAW_V 0x1 +#define SLC_SLC1_RX_DONE_INT_RAW_S 16 +/* SLC_SLC1_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_RAW_M (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_RAW_V 0x1 +#define SLC_SLC1_TX_SUC_EOF_INT_RAW_S 15 +/* SLC_SLC1_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DONE_INT_RAW (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_RAW_M (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_RAW_V 0x1 +#define SLC_SLC1_TX_DONE_INT_RAW_S 14 +/* SLC_SLC1_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_RAW_M (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_RAW_V 0x1 +#define SLC_SLC1_TOKEN1_1TO0_INT_RAW_S 13 +/* SLC_SLC1_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_RAW_M (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_RAW_V 0x1 +#define SLC_SLC1_TOKEN0_1TO0_INT_RAW_S 12 +/* SLC_SLC1_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_OVF_INT_RAW (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_RAW_M (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_RAW_V 0x1 +#define SLC_SLC1_TX_OVF_INT_RAW_S 11 +/* SLC_SLC1_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_UDF_INT_RAW (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_RAW_M (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_RAW_V 0x1 +#define SLC_SLC1_RX_UDF_INT_RAW_S 10 +/* SLC_SLC1_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_START_INT_RAW (BIT(9)) +#define SLC_SLC1_TX_START_INT_RAW_M (BIT(9)) +#define SLC_SLC1_TX_START_INT_RAW_V 0x1 +#define SLC_SLC1_TX_START_INT_RAW_S 9 +/* SLC_SLC1_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_START_INT_RAW (BIT(8)) +#define SLC_SLC1_RX_START_INT_RAW_M (BIT(8)) +#define SLC_SLC1_RX_START_INT_RAW_V 0x1 +#define SLC_SLC1_RX_START_INT_RAW_S 8 +/* SLC_FRHOST_BIT15_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT15_INT_RAW (BIT(7)) +#define SLC_FRHOST_BIT15_INT_RAW_M (BIT(7)) +#define SLC_FRHOST_BIT15_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT15_INT_RAW_S 7 +/* SLC_FRHOST_BIT14_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT14_INT_RAW (BIT(6)) +#define SLC_FRHOST_BIT14_INT_RAW_M (BIT(6)) +#define SLC_FRHOST_BIT14_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT14_INT_RAW_S 6 +/* SLC_FRHOST_BIT13_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT13_INT_RAW (BIT(5)) +#define SLC_FRHOST_BIT13_INT_RAW_M (BIT(5)) +#define SLC_FRHOST_BIT13_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT13_INT_RAW_S 5 +/* SLC_FRHOST_BIT12_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT12_INT_RAW (BIT(4)) +#define SLC_FRHOST_BIT12_INT_RAW_M (BIT(4)) +#define SLC_FRHOST_BIT12_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT12_INT_RAW_S 4 +/* SLC_FRHOST_BIT11_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT11_INT_RAW (BIT(3)) +#define SLC_FRHOST_BIT11_INT_RAW_M (BIT(3)) +#define SLC_FRHOST_BIT11_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT11_INT_RAW_S 3 +/* SLC_FRHOST_BIT10_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT10_INT_RAW (BIT(2)) +#define SLC_FRHOST_BIT10_INT_RAW_M (BIT(2)) +#define SLC_FRHOST_BIT10_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT10_INT_RAW_S 2 +/* SLC_FRHOST_BIT9_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT9_INT_RAW (BIT(1)) +#define SLC_FRHOST_BIT9_INT_RAW_M (BIT(1)) +#define SLC_FRHOST_BIT9_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT9_INT_RAW_S 1 +/* SLC_FRHOST_BIT8_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT8_INT_RAW (BIT(0)) +#define SLC_FRHOST_BIT8_INT_RAW_M (BIT(0)) +#define SLC_FRHOST_BIT8_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT8_INT_RAW_S 0 + +#define SLC_1INT_ST_REG (DR_REG_SLC_BASE + 0x18) +/* SLC_SLC1_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_ERR_EOF_INT_ST (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_ST_M (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_ST_V 0x1 +#define SLC_SLC1_TX_ERR_EOF_INT_ST_S 24 +/* SLC_SLC1_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_ST_M (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_ST_V 0x1 +#define SLC_SLC1_WR_RETRY_DONE_INT_ST_S 23 +/* SLC_SLC1_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_HOST_RD_ACK_INT_ST (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_ST_M (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_ST_V 0x1 +#define SLC_SLC1_HOST_RD_ACK_INT_ST_S 22 +/* SLC_SLC1_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_M (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_V 0x1 +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_S 21 +/* SLC_SLC1_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_ST_M (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_ST_V 0x1 +#define SLC_SLC1_RX_DSCR_ERR_INT_ST_S 20 +/* SLC_SLC1_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_ST_M (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_ST_V 0x1 +#define SLC_SLC1_TX_DSCR_ERR_INT_ST_S 19 +/* SLC_SLC1_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOHOST_INT_ST (BIT(18)) +#define SLC_SLC1_TOHOST_INT_ST_M (BIT(18)) +#define SLC_SLC1_TOHOST_INT_ST_V 0x1 +#define SLC_SLC1_TOHOST_INT_ST_S 18 +/* SLC_SLC1_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_EOF_INT_ST (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_ST_M (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_ST_V 0x1 +#define SLC_SLC1_RX_EOF_INT_ST_S 17 +/* SLC_SLC1_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DONE_INT_ST (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_ST_M (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_ST_V 0x1 +#define SLC_SLC1_RX_DONE_INT_ST_S 16 +/* SLC_SLC1_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_SUC_EOF_INT_ST (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_ST_M (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_ST_V 0x1 +#define SLC_SLC1_TX_SUC_EOF_INT_ST_S 15 +/* SLC_SLC1_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DONE_INT_ST (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_ST_M (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_ST_V 0x1 +#define SLC_SLC1_TX_DONE_INT_ST_S 14 +/* SLC_SLC1_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_ST_M (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_ST_V 0x1 +#define SLC_SLC1_TOKEN1_1TO0_INT_ST_S 13 +/* SLC_SLC1_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_ST_M (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_ST_V 0x1 +#define SLC_SLC1_TOKEN0_1TO0_INT_ST_S 12 +/* SLC_SLC1_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_OVF_INT_ST (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_ST_M (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_ST_V 0x1 +#define SLC_SLC1_TX_OVF_INT_ST_S 11 +/* SLC_SLC1_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_UDF_INT_ST (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_ST_M (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_ST_V 0x1 +#define SLC_SLC1_RX_UDF_INT_ST_S 10 +/* SLC_SLC1_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_START_INT_ST (BIT(9)) +#define SLC_SLC1_TX_START_INT_ST_M (BIT(9)) +#define SLC_SLC1_TX_START_INT_ST_V 0x1 +#define SLC_SLC1_TX_START_INT_ST_S 9 +/* SLC_SLC1_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_START_INT_ST (BIT(8)) +#define SLC_SLC1_RX_START_INT_ST_M (BIT(8)) +#define SLC_SLC1_RX_START_INT_ST_V 0x1 +#define SLC_SLC1_RX_START_INT_ST_S 8 +/* SLC_FRHOST_BIT15_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT15_INT_ST (BIT(7)) +#define SLC_FRHOST_BIT15_INT_ST_M (BIT(7)) +#define SLC_FRHOST_BIT15_INT_ST_V 0x1 +#define SLC_FRHOST_BIT15_INT_ST_S 7 +/* SLC_FRHOST_BIT14_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT14_INT_ST (BIT(6)) +#define SLC_FRHOST_BIT14_INT_ST_M (BIT(6)) +#define SLC_FRHOST_BIT14_INT_ST_V 0x1 +#define SLC_FRHOST_BIT14_INT_ST_S 6 +/* SLC_FRHOST_BIT13_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT13_INT_ST (BIT(5)) +#define SLC_FRHOST_BIT13_INT_ST_M (BIT(5)) +#define SLC_FRHOST_BIT13_INT_ST_V 0x1 +#define SLC_FRHOST_BIT13_INT_ST_S 5 +/* SLC_FRHOST_BIT12_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT12_INT_ST (BIT(4)) +#define SLC_FRHOST_BIT12_INT_ST_M (BIT(4)) +#define SLC_FRHOST_BIT12_INT_ST_V 0x1 +#define SLC_FRHOST_BIT12_INT_ST_S 4 +/* SLC_FRHOST_BIT11_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT11_INT_ST (BIT(3)) +#define SLC_FRHOST_BIT11_INT_ST_M (BIT(3)) +#define SLC_FRHOST_BIT11_INT_ST_V 0x1 +#define SLC_FRHOST_BIT11_INT_ST_S 3 +/* SLC_FRHOST_BIT10_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT10_INT_ST (BIT(2)) +#define SLC_FRHOST_BIT10_INT_ST_M (BIT(2)) +#define SLC_FRHOST_BIT10_INT_ST_V 0x1 +#define SLC_FRHOST_BIT10_INT_ST_S 2 +/* SLC_FRHOST_BIT9_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT9_INT_ST (BIT(1)) +#define SLC_FRHOST_BIT9_INT_ST_M (BIT(1)) +#define SLC_FRHOST_BIT9_INT_ST_V 0x1 +#define SLC_FRHOST_BIT9_INT_ST_S 1 +/* SLC_FRHOST_BIT8_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT8_INT_ST (BIT(0)) +#define SLC_FRHOST_BIT8_INT_ST_M (BIT(0)) +#define SLC_FRHOST_BIT8_INT_ST_V 0x1 +#define SLC_FRHOST_BIT8_INT_ST_S 0 + +#define SLC_1INT_ENA_REG (DR_REG_SLC_BASE + 0x1C) +/* SLC_SLC1_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_ENA_M (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_ENA_V 0x1 +#define SLC_SLC1_TX_ERR_EOF_INT_ENA_S 24 +/* SLC_SLC1_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_ENA_M (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_ENA_V 0x1 +#define SLC_SLC1_WR_RETRY_DONE_INT_ENA_S 23 +/* SLC_SLC1_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_ENA_M (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_ENA_V 0x1 +#define SLC_SLC1_HOST_RD_ACK_INT_ENA_S 22 +/* SLC_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_M (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_V 0x1 +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_S 21 +/* SLC_SLC1_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_ENA_M (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_ENA_V 0x1 +#define SLC_SLC1_RX_DSCR_ERR_INT_ENA_S 20 +/* SLC_SLC1_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_ENA_M (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_ENA_V 0x1 +#define SLC_SLC1_TX_DSCR_ERR_INT_ENA_S 19 +/* SLC_SLC1_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOHOST_INT_ENA (BIT(18)) +#define SLC_SLC1_TOHOST_INT_ENA_M (BIT(18)) +#define SLC_SLC1_TOHOST_INT_ENA_V 0x1 +#define SLC_SLC1_TOHOST_INT_ENA_S 18 +/* SLC_SLC1_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_EOF_INT_ENA (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_ENA_M (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_ENA_V 0x1 +#define SLC_SLC1_RX_EOF_INT_ENA_S 17 +/* SLC_SLC1_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DONE_INT_ENA (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_ENA_M (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_ENA_V 0x1 +#define SLC_SLC1_RX_DONE_INT_ENA_S 16 +/* SLC_SLC1_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_ENA_M (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_ENA_V 0x1 +#define SLC_SLC1_TX_SUC_EOF_INT_ENA_S 15 +/* SLC_SLC1_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DONE_INT_ENA (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_ENA_M (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_ENA_V 0x1 +#define SLC_SLC1_TX_DONE_INT_ENA_S 14 +/* SLC_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_ENA_M (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_ENA_V 0x1 +#define SLC_SLC1_TOKEN1_1TO0_INT_ENA_S 13 +/* SLC_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_ENA_M (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_ENA_V 0x1 +#define SLC_SLC1_TOKEN0_1TO0_INT_ENA_S 12 +/* SLC_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_OVF_INT_ENA (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_ENA_M (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_ENA_V 0x1 +#define SLC_SLC1_TX_OVF_INT_ENA_S 11 +/* SLC_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_UDF_INT_ENA (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_ENA_M (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_ENA_V 0x1 +#define SLC_SLC1_RX_UDF_INT_ENA_S 10 +/* SLC_SLC1_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_START_INT_ENA (BIT(9)) +#define SLC_SLC1_TX_START_INT_ENA_M (BIT(9)) +#define SLC_SLC1_TX_START_INT_ENA_V 0x1 +#define SLC_SLC1_TX_START_INT_ENA_S 9 +/* SLC_SLC1_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_START_INT_ENA (BIT(8)) +#define SLC_SLC1_RX_START_INT_ENA_M (BIT(8)) +#define SLC_SLC1_RX_START_INT_ENA_V 0x1 +#define SLC_SLC1_RX_START_INT_ENA_S 8 +/* SLC_FRHOST_BIT15_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT15_INT_ENA (BIT(7)) +#define SLC_FRHOST_BIT15_INT_ENA_M (BIT(7)) +#define SLC_FRHOST_BIT15_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT15_INT_ENA_S 7 +/* SLC_FRHOST_BIT14_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT14_INT_ENA (BIT(6)) +#define SLC_FRHOST_BIT14_INT_ENA_M (BIT(6)) +#define SLC_FRHOST_BIT14_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT14_INT_ENA_S 6 +/* SLC_FRHOST_BIT13_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT13_INT_ENA (BIT(5)) +#define SLC_FRHOST_BIT13_INT_ENA_M (BIT(5)) +#define SLC_FRHOST_BIT13_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT13_INT_ENA_S 5 +/* SLC_FRHOST_BIT12_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT12_INT_ENA (BIT(4)) +#define SLC_FRHOST_BIT12_INT_ENA_M (BIT(4)) +#define SLC_FRHOST_BIT12_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT12_INT_ENA_S 4 +/* SLC_FRHOST_BIT11_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT11_INT_ENA (BIT(3)) +#define SLC_FRHOST_BIT11_INT_ENA_M (BIT(3)) +#define SLC_FRHOST_BIT11_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT11_INT_ENA_S 3 +/* SLC_FRHOST_BIT10_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT10_INT_ENA (BIT(2)) +#define SLC_FRHOST_BIT10_INT_ENA_M (BIT(2)) +#define SLC_FRHOST_BIT10_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT10_INT_ENA_S 2 +/* SLC_FRHOST_BIT9_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT9_INT_ENA (BIT(1)) +#define SLC_FRHOST_BIT9_INT_ENA_M (BIT(1)) +#define SLC_FRHOST_BIT9_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT9_INT_ENA_S 1 +/* SLC_FRHOST_BIT8_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT8_INT_ENA (BIT(0)) +#define SLC_FRHOST_BIT8_INT_ENA_M (BIT(0)) +#define SLC_FRHOST_BIT8_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT8_INT_ENA_S 0 + +#define SLC_1INT_CLR_REG (DR_REG_SLC_BASE + 0x20) +/* SLC_SLC1_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_CLR_M (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_CLR_V 0x1 +#define SLC_SLC1_TX_ERR_EOF_INT_CLR_S 24 +/* SLC_SLC1_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_CLR_M (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_CLR_V 0x1 +#define SLC_SLC1_WR_RETRY_DONE_INT_CLR_S 23 +/* SLC_SLC1_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_CLR_M (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_CLR_V 0x1 +#define SLC_SLC1_HOST_RD_ACK_INT_CLR_S 22 +/* SLC_SLC1_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_M (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_V 0x1 +#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_S 21 +/* SLC_SLC1_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_CLR_M (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_CLR_V 0x1 +#define SLC_SLC1_RX_DSCR_ERR_INT_CLR_S 20 +/* SLC_SLC1_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_CLR_M (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_CLR_V 0x1 +#define SLC_SLC1_TX_DSCR_ERR_INT_CLR_S 19 +/* SLC_SLC1_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOHOST_INT_CLR (BIT(18)) +#define SLC_SLC1_TOHOST_INT_CLR_M (BIT(18)) +#define SLC_SLC1_TOHOST_INT_CLR_V 0x1 +#define SLC_SLC1_TOHOST_INT_CLR_S 18 +/* SLC_SLC1_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_EOF_INT_CLR (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_CLR_M (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_CLR_V 0x1 +#define SLC_SLC1_RX_EOF_INT_CLR_S 17 +/* SLC_SLC1_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DONE_INT_CLR (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_CLR_M (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_CLR_V 0x1 +#define SLC_SLC1_RX_DONE_INT_CLR_S 16 +/* SLC_SLC1_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_CLR_M (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_CLR_V 0x1 +#define SLC_SLC1_TX_SUC_EOF_INT_CLR_S 15 +/* SLC_SLC1_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DONE_INT_CLR (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_CLR_M (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_CLR_V 0x1 +#define SLC_SLC1_TX_DONE_INT_CLR_S 14 +/* SLC_SLC1_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_CLR_M (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_CLR_V 0x1 +#define SLC_SLC1_TOKEN1_1TO0_INT_CLR_S 13 +/* SLC_SLC1_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_CLR_M (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_CLR_V 0x1 +#define SLC_SLC1_TOKEN0_1TO0_INT_CLR_S 12 +/* SLC_SLC1_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_OVF_INT_CLR (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_CLR_M (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_CLR_V 0x1 +#define SLC_SLC1_TX_OVF_INT_CLR_S 11 +/* SLC_SLC1_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_UDF_INT_CLR (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_CLR_M (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_CLR_V 0x1 +#define SLC_SLC1_RX_UDF_INT_CLR_S 10 +/* SLC_SLC1_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_START_INT_CLR (BIT(9)) +#define SLC_SLC1_TX_START_INT_CLR_M (BIT(9)) +#define SLC_SLC1_TX_START_INT_CLR_V 0x1 +#define SLC_SLC1_TX_START_INT_CLR_S 9 +/* SLC_SLC1_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_START_INT_CLR (BIT(8)) +#define SLC_SLC1_RX_START_INT_CLR_M (BIT(8)) +#define SLC_SLC1_RX_START_INT_CLR_V 0x1 +#define SLC_SLC1_RX_START_INT_CLR_S 8 +/* SLC_FRHOST_BIT15_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT15_INT_CLR (BIT(7)) +#define SLC_FRHOST_BIT15_INT_CLR_M (BIT(7)) +#define SLC_FRHOST_BIT15_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT15_INT_CLR_S 7 +/* SLC_FRHOST_BIT14_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT14_INT_CLR (BIT(6)) +#define SLC_FRHOST_BIT14_INT_CLR_M (BIT(6)) +#define SLC_FRHOST_BIT14_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT14_INT_CLR_S 6 +/* SLC_FRHOST_BIT13_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT13_INT_CLR (BIT(5)) +#define SLC_FRHOST_BIT13_INT_CLR_M (BIT(5)) +#define SLC_FRHOST_BIT13_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT13_INT_CLR_S 5 +/* SLC_FRHOST_BIT12_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT12_INT_CLR (BIT(4)) +#define SLC_FRHOST_BIT12_INT_CLR_M (BIT(4)) +#define SLC_FRHOST_BIT12_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT12_INT_CLR_S 4 +/* SLC_FRHOST_BIT11_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT11_INT_CLR (BIT(3)) +#define SLC_FRHOST_BIT11_INT_CLR_M (BIT(3)) +#define SLC_FRHOST_BIT11_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT11_INT_CLR_S 3 +/* SLC_FRHOST_BIT10_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT10_INT_CLR (BIT(2)) +#define SLC_FRHOST_BIT10_INT_CLR_M (BIT(2)) +#define SLC_FRHOST_BIT10_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT10_INT_CLR_S 2 +/* SLC_FRHOST_BIT9_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT9_INT_CLR (BIT(1)) +#define SLC_FRHOST_BIT9_INT_CLR_M (BIT(1)) +#define SLC_FRHOST_BIT9_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT9_INT_CLR_S 1 +/* SLC_FRHOST_BIT8_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT8_INT_CLR (BIT(0)) +#define SLC_FRHOST_BIT8_INT_CLR_M (BIT(0)) +#define SLC_FRHOST_BIT8_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT8_INT_CLR_S 0 + +#define SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24) +/* SLC_SLC1_RX_EMPTY : RO ;bitpos:[17] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_RX_EMPTY (BIT(17)) +#define SLC_SLC1_RX_EMPTY_M (BIT(17)) +#define SLC_SLC1_RX_EMPTY_V 0x1 +#define SLC_SLC1_RX_EMPTY_S 17 +/* SLC_SLC1_RX_FULL : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_FULL (BIT(16)) +#define SLC_SLC1_RX_FULL_M (BIT(16)) +#define SLC_SLC1_RX_FULL_V 0x1 +#define SLC_SLC1_RX_FULL_S 16 +/* SLC_SLC0_RX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_EMPTY (BIT(1)) +#define SLC_SLC0_RX_EMPTY_M (BIT(1)) +#define SLC_SLC0_RX_EMPTY_V 0x1 +#define SLC_SLC0_RX_EMPTY_S 1 +/* SLC_SLC0_RX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_FULL (BIT(0)) +#define SLC_SLC0_RX_FULL_M (BIT(0)) +#define SLC_SLC0_RX_FULL_V 0x1 +#define SLC_SLC0_RX_FULL_S 0 + +#define SLC_0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28) +/* SLC_SLC0_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_RXFIFO_PUSH (BIT(16)) +#define SLC_SLC0_RXFIFO_PUSH_M (BIT(16)) +#define SLC_SLC0_RXFIFO_PUSH_V 0x1 +#define SLC_SLC0_RXFIFO_PUSH_S 16 +/* SLC_SLC0_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define SLC_SLC0_RXFIFO_WDATA 0x000001FF +#define SLC_SLC0_RXFIFO_WDATA_M ((SLC_SLC0_RXFIFO_WDATA_V)<<(SLC_SLC0_RXFIFO_WDATA_S)) +#define SLC_SLC0_RXFIFO_WDATA_V 0x1FF +#define SLC_SLC0_RXFIFO_WDATA_S 0 + +#define SLC_1RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x2C) +/* SLC_SLC1_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC1_RXFIFO_PUSH (BIT(16)) +#define SLC_SLC1_RXFIFO_PUSH_M (BIT(16)) +#define SLC_SLC1_RXFIFO_PUSH_V 0x1 +#define SLC_SLC1_RXFIFO_PUSH_S 16 +/* SLC_SLC1_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define SLC_SLC1_RXFIFO_WDATA 0x000001FF +#define SLC_SLC1_RXFIFO_WDATA_M ((SLC_SLC1_RXFIFO_WDATA_V)<<(SLC_SLC1_RXFIFO_WDATA_S)) +#define SLC_SLC1_RXFIFO_WDATA_V 0x1FF +#define SLC_SLC1_RXFIFO_WDATA_S 0 + +#define SLC_TX_STATUS_REG (DR_REG_SLC_BASE + 0x30) +/* SLC_SLC1_TX_EMPTY : RO ;bitpos:[17] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_TX_EMPTY (BIT(17)) +#define SLC_SLC1_TX_EMPTY_M (BIT(17)) +#define SLC_SLC1_TX_EMPTY_V 0x1 +#define SLC_SLC1_TX_EMPTY_S 17 +/* SLC_SLC1_TX_FULL : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_FULL (BIT(16)) +#define SLC_SLC1_TX_FULL_M (BIT(16)) +#define SLC_SLC1_TX_FULL_V 0x1 +#define SLC_SLC1_TX_FULL_S 16 +/* SLC_SLC0_TX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TX_EMPTY (BIT(1)) +#define SLC_SLC0_TX_EMPTY_M (BIT(1)) +#define SLC_SLC0_TX_EMPTY_V 0x1 +#define SLC_SLC0_TX_EMPTY_S 1 +/* SLC_SLC0_TX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_FULL (BIT(0)) +#define SLC_SLC0_TX_FULL_M (BIT(0)) +#define SLC_SLC0_TX_FULL_V 0x1 +#define SLC_SLC0_TX_FULL_S 0 + +#define SLC_0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34) +/* SLC_SLC0_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_TXFIFO_POP (BIT(16)) +#define SLC_SLC0_TXFIFO_POP_M (BIT(16)) +#define SLC_SLC0_TXFIFO_POP_V 0x1 +#define SLC_SLC0_TXFIFO_POP_S 16 +/* SLC_SLC0_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SLC_SLC0_TXFIFO_RDATA 0x000007FF +#define SLC_SLC0_TXFIFO_RDATA_M ((SLC_SLC0_TXFIFO_RDATA_V)<<(SLC_SLC0_TXFIFO_RDATA_S)) +#define SLC_SLC0_TXFIFO_RDATA_V 0x7FF +#define SLC_SLC0_TXFIFO_RDATA_S 0 + +#define SLC_1TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x38) +/* SLC_SLC1_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC1_TXFIFO_POP (BIT(16)) +#define SLC_SLC1_TXFIFO_POP_M (BIT(16)) +#define SLC_SLC1_TXFIFO_POP_V 0x1 +#define SLC_SLC1_TXFIFO_POP_S 16 +/* SLC_SLC1_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SLC_SLC1_TXFIFO_RDATA 0x000007FF +#define SLC_SLC1_TXFIFO_RDATA_M ((SLC_SLC1_TXFIFO_RDATA_V)<<(SLC_SLC1_TXFIFO_RDATA_S)) +#define SLC_SLC1_TXFIFO_RDATA_V 0x7FF +#define SLC_SLC1_TXFIFO_RDATA_S 0 + +#define SLC_0RX_LINK_REG (DR_REG_SLC_BASE + 0x3C) +/* SLC_SLC0_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_PARK (BIT(31)) +#define SLC_SLC0_RXLINK_PARK_M (BIT(31)) +#define SLC_SLC0_RXLINK_PARK_V 0x1 +#define SLC_SLC0_RXLINK_PARK_S 31 +/* SLC_SLC0_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_RESTART (BIT(30)) +#define SLC_SLC0_RXLINK_RESTART_M (BIT(30)) +#define SLC_SLC0_RXLINK_RESTART_V 0x1 +#define SLC_SLC0_RXLINK_RESTART_S 30 +/* SLC_SLC0_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_START (BIT(29)) +#define SLC_SLC0_RXLINK_START_M (BIT(29)) +#define SLC_SLC0_RXLINK_START_V 0x1 +#define SLC_SLC0_RXLINK_START_S 29 +/* SLC_SLC0_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_STOP (BIT(28)) +#define SLC_SLC0_RXLINK_STOP_M (BIT(28)) +#define SLC_SLC0_RXLINK_STOP_V 0x1 +#define SLC_SLC0_RXLINK_STOP_S 28 +/* SLC_SLC0_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_ADDR 0x000FFFFF +#define SLC_SLC0_RXLINK_ADDR_M ((SLC_SLC0_RXLINK_ADDR_V)<<(SLC_SLC0_RXLINK_ADDR_S)) +#define SLC_SLC0_RXLINK_ADDR_V 0xFFFFF +#define SLC_SLC0_RXLINK_ADDR_S 0 + +#define SLC_0TX_LINK_REG (DR_REG_SLC_BASE + 0x40) +/* SLC_SLC0_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_PARK (BIT(31)) +#define SLC_SLC0_TXLINK_PARK_M (BIT(31)) +#define SLC_SLC0_TXLINK_PARK_V 0x1 +#define SLC_SLC0_TXLINK_PARK_S 31 +/* SLC_SLC0_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_RESTART (BIT(30)) +#define SLC_SLC0_TXLINK_RESTART_M (BIT(30)) +#define SLC_SLC0_TXLINK_RESTART_V 0x1 +#define SLC_SLC0_TXLINK_RESTART_S 30 +/* SLC_SLC0_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_START (BIT(29)) +#define SLC_SLC0_TXLINK_START_M (BIT(29)) +#define SLC_SLC0_TXLINK_START_V 0x1 +#define SLC_SLC0_TXLINK_START_S 29 +/* SLC_SLC0_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_STOP (BIT(28)) +#define SLC_SLC0_TXLINK_STOP_M (BIT(28)) +#define SLC_SLC0_TXLINK_STOP_V 0x1 +#define SLC_SLC0_TXLINK_STOP_S 28 +/* SLC_SLC0_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_ADDR 0x000FFFFF +#define SLC_SLC0_TXLINK_ADDR_M ((SLC_SLC0_TXLINK_ADDR_V)<<(SLC_SLC0_TXLINK_ADDR_S)) +#define SLC_SLC0_TXLINK_ADDR_V 0xFFFFF +#define SLC_SLC0_TXLINK_ADDR_S 0 + +#define SLC_1RX_LINK_REG (DR_REG_SLC_BASE + 0x44) +/* SLC_SLC1_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC1_RXLINK_PARK (BIT(31)) +#define SLC_SLC1_RXLINK_PARK_M (BIT(31)) +#define SLC_SLC1_RXLINK_PARK_V 0x1 +#define SLC_SLC1_RXLINK_PARK_S 31 +/* SLC_SLC1_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RXLINK_RESTART (BIT(30)) +#define SLC_SLC1_RXLINK_RESTART_M (BIT(30)) +#define SLC_SLC1_RXLINK_RESTART_V 0x1 +#define SLC_SLC1_RXLINK_RESTART_S 30 +/* SLC_SLC1_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RXLINK_START (BIT(29)) +#define SLC_SLC1_RXLINK_START_M (BIT(29)) +#define SLC_SLC1_RXLINK_START_V 0x1 +#define SLC_SLC1_RXLINK_START_S 29 +/* SLC_SLC1_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RXLINK_STOP (BIT(28)) +#define SLC_SLC1_RXLINK_STOP_M (BIT(28)) +#define SLC_SLC1_RXLINK_STOP_V 0x1 +#define SLC_SLC1_RXLINK_STOP_S 28 +/* SLC_SLC1_BT_PACKET : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_BT_PACKET (BIT(20)) +#define SLC_SLC1_BT_PACKET_M (BIT(20)) +#define SLC_SLC1_BT_PACKET_V 0x1 +#define SLC_SLC1_BT_PACKET_S 20 +/* SLC_SLC1_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC1_RXLINK_ADDR 0x000FFFFF +#define SLC_SLC1_RXLINK_ADDR_M ((SLC_SLC1_RXLINK_ADDR_V)<<(SLC_SLC1_RXLINK_ADDR_S)) +#define SLC_SLC1_RXLINK_ADDR_V 0xFFFFF +#define SLC_SLC1_RXLINK_ADDR_S 0 + +#define SLC_1TX_LINK_REG (DR_REG_SLC_BASE + 0x48) +/* SLC_SLC1_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC1_TXLINK_PARK (BIT(31)) +#define SLC_SLC1_TXLINK_PARK_M (BIT(31)) +#define SLC_SLC1_TXLINK_PARK_V 0x1 +#define SLC_SLC1_TXLINK_PARK_S 31 +/* SLC_SLC1_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TXLINK_RESTART (BIT(30)) +#define SLC_SLC1_TXLINK_RESTART_M (BIT(30)) +#define SLC_SLC1_TXLINK_RESTART_V 0x1 +#define SLC_SLC1_TXLINK_RESTART_S 30 +/* SLC_SLC1_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TXLINK_START (BIT(29)) +#define SLC_SLC1_TXLINK_START_M (BIT(29)) +#define SLC_SLC1_TXLINK_START_V 0x1 +#define SLC_SLC1_TXLINK_START_S 29 +/* SLC_SLC1_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TXLINK_STOP (BIT(28)) +#define SLC_SLC1_TXLINK_STOP_M (BIT(28)) +#define SLC_SLC1_TXLINK_STOP_V 0x1 +#define SLC_SLC1_TXLINK_STOP_S 28 +/* SLC_SLC1_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC1_TXLINK_ADDR 0x000FFFFF +#define SLC_SLC1_TXLINK_ADDR_M ((SLC_SLC1_TXLINK_ADDR_V)<<(SLC_SLC1_TXLINK_ADDR_S)) +#define SLC_SLC1_TXLINK_ADDR_V 0xFFFFF +#define SLC_SLC1_TXLINK_ADDR_S 0 + +#define SLC_INTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x4C) +/* SLC_SLC1_TOHOST_INTVEC : WO ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define SLC_SLC1_TOHOST_INTVEC 0x000000FF +#define SLC_SLC1_TOHOST_INTVEC_M ((SLC_SLC1_TOHOST_INTVEC_V)<<(SLC_SLC1_TOHOST_INTVEC_S)) +#define SLC_SLC1_TOHOST_INTVEC_V 0xFF +#define SLC_SLC1_TOHOST_INTVEC_S 16 +/* SLC_SLC0_TOHOST_INTVEC : WO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INTVEC 0x000000FF +#define SLC_SLC0_TOHOST_INTVEC_M ((SLC_SLC0_TOHOST_INTVEC_V)<<(SLC_SLC0_TOHOST_INTVEC_S)) +#define SLC_SLC0_TOHOST_INTVEC_V 0xFF +#define SLC_SLC0_TOHOST_INTVEC_S 0 + +#define SLC_0TOKEN0_REG (DR_REG_SLC_BASE + 0x50) +/* SLC_SLC0_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0 0x00000FFF +#define SLC_SLC0_TOKEN0_M ((SLC_SLC0_TOKEN0_V)<<(SLC_SLC0_TOKEN0_S)) +#define SLC_SLC0_TOKEN0_V 0xFFF +#define SLC_SLC0_TOKEN0_S 16 +/* SLC_SLC0_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_INC_MORE (BIT(14)) +#define SLC_SLC0_TOKEN0_INC_MORE_M (BIT(14)) +#define SLC_SLC0_TOKEN0_INC_MORE_V 0x1 +#define SLC_SLC0_TOKEN0_INC_MORE_S 14 +/* SLC_SLC0_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_INC (BIT(13)) +#define SLC_SLC0_TOKEN0_INC_M (BIT(13)) +#define SLC_SLC0_TOKEN0_INC_V 0x1 +#define SLC_SLC0_TOKEN0_INC_S 13 +/* SLC_SLC0_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_WR (BIT(12)) +#define SLC_SLC0_TOKEN0_WR_M (BIT(12)) +#define SLC_SLC0_TOKEN0_WR_V 0x1 +#define SLC_SLC0_TOKEN0_WR_S 12 +/* SLC_SLC0_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_WDATA 0x00000FFF +#define SLC_SLC0_TOKEN0_WDATA_M ((SLC_SLC0_TOKEN0_WDATA_V)<<(SLC_SLC0_TOKEN0_WDATA_S)) +#define SLC_SLC0_TOKEN0_WDATA_V 0xFFF +#define SLC_SLC0_TOKEN0_WDATA_S 0 + +#define SLC_0TOKEN1_REG (DR_REG_SLC_BASE + 0x54) +/* SLC_SLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1 0x00000FFF +#define SLC_SLC0_TOKEN1_M ((SLC_SLC0_TOKEN1_V)<<(SLC_SLC0_TOKEN1_S)) +#define SLC_SLC0_TOKEN1_V 0xFFF +#define SLC_SLC0_TOKEN1_S 16 +/* SLC_SLC0_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_INC_MORE (BIT(14)) +#define SLC_SLC0_TOKEN1_INC_MORE_M (BIT(14)) +#define SLC_SLC0_TOKEN1_INC_MORE_V 0x1 +#define SLC_SLC0_TOKEN1_INC_MORE_S 14 +/* SLC_SLC0_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_INC (BIT(13)) +#define SLC_SLC0_TOKEN1_INC_M (BIT(13)) +#define SLC_SLC0_TOKEN1_INC_V 0x1 +#define SLC_SLC0_TOKEN1_INC_S 13 +/* SLC_SLC0_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_WR (BIT(12)) +#define SLC_SLC0_TOKEN1_WR_M (BIT(12)) +#define SLC_SLC0_TOKEN1_WR_V 0x1 +#define SLC_SLC0_TOKEN1_WR_S 12 +/* SLC_SLC0_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_WDATA 0x00000FFF +#define SLC_SLC0_TOKEN1_WDATA_M ((SLC_SLC0_TOKEN1_WDATA_V)<<(SLC_SLC0_TOKEN1_WDATA_S)) +#define SLC_SLC0_TOKEN1_WDATA_V 0xFFF +#define SLC_SLC0_TOKEN1_WDATA_S 0 + +#define SLC_1TOKEN0_REG (DR_REG_SLC_BASE + 0x58) +/* SLC_SLC1_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0 0x00000FFF +#define SLC_SLC1_TOKEN0_M ((SLC_SLC1_TOKEN0_V)<<(SLC_SLC1_TOKEN0_S)) +#define SLC_SLC1_TOKEN0_V 0xFFF +#define SLC_SLC1_TOKEN0_S 16 +/* SLC_SLC1_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_INC_MORE (BIT(14)) +#define SLC_SLC1_TOKEN0_INC_MORE_M (BIT(14)) +#define SLC_SLC1_TOKEN0_INC_MORE_V 0x1 +#define SLC_SLC1_TOKEN0_INC_MORE_S 14 +/* SLC_SLC1_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_INC (BIT(13)) +#define SLC_SLC1_TOKEN0_INC_M (BIT(13)) +#define SLC_SLC1_TOKEN0_INC_V 0x1 +#define SLC_SLC1_TOKEN0_INC_S 13 +/* SLC_SLC1_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_WR (BIT(12)) +#define SLC_SLC1_TOKEN0_WR_M (BIT(12)) +#define SLC_SLC1_TOKEN0_WR_V 0x1 +#define SLC_SLC1_TOKEN0_WR_S 12 +/* SLC_SLC1_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_WDATA 0x00000FFF +#define SLC_SLC1_TOKEN0_WDATA_M ((SLC_SLC1_TOKEN0_WDATA_V)<<(SLC_SLC1_TOKEN0_WDATA_S)) +#define SLC_SLC1_TOKEN0_WDATA_V 0xFFF +#define SLC_SLC1_TOKEN0_WDATA_S 0 + +#define SLC_1TOKEN1_REG (DR_REG_SLC_BASE + 0x5C) +/* SLC_SLC1_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1 0x00000FFF +#define SLC_SLC1_TOKEN1_M ((SLC_SLC1_TOKEN1_V)<<(SLC_SLC1_TOKEN1_S)) +#define SLC_SLC1_TOKEN1_V 0xFFF +#define SLC_SLC1_TOKEN1_S 16 +/* SLC_SLC1_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_INC_MORE (BIT(14)) +#define SLC_SLC1_TOKEN1_INC_MORE_M (BIT(14)) +#define SLC_SLC1_TOKEN1_INC_MORE_V 0x1 +#define SLC_SLC1_TOKEN1_INC_MORE_S 14 +/* SLC_SLC1_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_INC (BIT(13)) +#define SLC_SLC1_TOKEN1_INC_M (BIT(13)) +#define SLC_SLC1_TOKEN1_INC_V 0x1 +#define SLC_SLC1_TOKEN1_INC_S 13 +/* SLC_SLC1_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_WR (BIT(12)) +#define SLC_SLC1_TOKEN1_WR_M (BIT(12)) +#define SLC_SLC1_TOKEN1_WR_V 0x1 +#define SLC_SLC1_TOKEN1_WR_S 12 +/* SLC_SLC1_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_WDATA 0x00000FFF +#define SLC_SLC1_TOKEN1_WDATA_M ((SLC_SLC1_TOKEN1_WDATA_V)<<(SLC_SLC1_TOKEN1_WDATA_S)) +#define SLC_SLC1_TOKEN1_WDATA_V 0xFFF +#define SLC_SLC1_TOKEN1_WDATA_S 0 + +#define SLC_CONF1_REG (DR_REG_SLC_BASE + 0x60) +/* SLC_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CLK_EN (BIT(22)) +#define SLC_CLK_EN_M (BIT(22)) +#define SLC_CLK_EN_V 0x1 +#define SLC_CLK_EN_S 22 +/* SLC_SLC1_RX_STITCH_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_RX_STITCH_EN (BIT(21)) +#define SLC_SLC1_RX_STITCH_EN_M (BIT(21)) +#define SLC_SLC1_RX_STITCH_EN_V 0x1 +#define SLC_SLC1_RX_STITCH_EN_S 21 +/* SLC_SLC1_TX_STITCH_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_TX_STITCH_EN (BIT(20)) +#define SLC_SLC1_TX_STITCH_EN_M (BIT(20)) +#define SLC_SLC1_TX_STITCH_EN_V 0x1 +#define SLC_SLC1_TX_STITCH_EN_S 20 +/* SLC_HOST_INT_LEVEL_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_HOST_INT_LEVEL_SEL (BIT(19)) +#define SLC_HOST_INT_LEVEL_SEL_M (BIT(19)) +#define SLC_HOST_INT_LEVEL_SEL_V 0x1 +#define SLC_HOST_INT_LEVEL_SEL_S 19 +/* SLC_SLC1_RX_CHECK_SUM_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_CHECK_SUM_EN (BIT(18)) +#define SLC_SLC1_RX_CHECK_SUM_EN_M (BIT(18)) +#define SLC_SLC1_RX_CHECK_SUM_EN_V 0x1 +#define SLC_SLC1_RX_CHECK_SUM_EN_S 18 +/* SLC_SLC1_TX_CHECK_SUM_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_CHECK_SUM_EN (BIT(17)) +#define SLC_SLC1_TX_CHECK_SUM_EN_M (BIT(17)) +#define SLC_SLC1_TX_CHECK_SUM_EN_V 0x1 +#define SLC_SLC1_TX_CHECK_SUM_EN_S 17 +/* SLC_SLC1_CHECK_OWNER : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_CHECK_OWNER (BIT(16)) +#define SLC_SLC1_CHECK_OWNER_M (BIT(16)) +#define SLC_SLC1_CHECK_OWNER_V 0x1 +#define SLC_SLC1_CHECK_OWNER_S 16 +/* SLC_SLC0_RX_STITCH_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_STITCH_EN (BIT(6)) +#define SLC_SLC0_RX_STITCH_EN_M (BIT(6)) +#define SLC_SLC0_RX_STITCH_EN_V 0x1 +#define SLC_SLC0_RX_STITCH_EN_S 6 +/* SLC_SLC0_TX_STITCH_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TX_STITCH_EN (BIT(5)) +#define SLC_SLC0_TX_STITCH_EN_M (BIT(5)) +#define SLC_SLC0_TX_STITCH_EN_V 0x1 +#define SLC_SLC0_TX_STITCH_EN_S 5 +/* SLC_SLC0_LEN_AUTO_CLR : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_LEN_AUTO_CLR (BIT(4)) +#define SLC_SLC0_LEN_AUTO_CLR_M (BIT(4)) +#define SLC_SLC0_LEN_AUTO_CLR_V 0x1 +#define SLC_SLC0_LEN_AUTO_CLR_S 4 +/* SLC_CMD_HOLD_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SLC_CMD_HOLD_EN (BIT(3)) +#define SLC_CMD_HOLD_EN_M (BIT(3)) +#define SLC_CMD_HOLD_EN_V 0x1 +#define SLC_CMD_HOLD_EN_S 3 +/* SLC_SLC0_RX_CHECK_SUM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_CHECK_SUM_EN (BIT(2)) +#define SLC_SLC0_RX_CHECK_SUM_EN_M (BIT(2)) +#define SLC_SLC0_RX_CHECK_SUM_EN_V 0x1 +#define SLC_SLC0_RX_CHECK_SUM_EN_S 2 +/* SLC_SLC0_TX_CHECK_SUM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_CHECK_SUM_EN (BIT(1)) +#define SLC_SLC0_TX_CHECK_SUM_EN_M (BIT(1)) +#define SLC_SLC0_TX_CHECK_SUM_EN_V 0x1 +#define SLC_SLC0_TX_CHECK_SUM_EN_S 1 +/* SLC_SLC0_CHECK_OWNER : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_CHECK_OWNER (BIT(0)) +#define SLC_SLC0_CHECK_OWNER_M (BIT(0)) +#define SLC_SLC0_CHECK_OWNER_V 0x1 +#define SLC_SLC0_CHECK_OWNER_S 0 + +#define SLC_0_STATE0_REG (DR_REG_SLC_BASE + 0x64) +/* SLC_SLC0_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_STATE0 0xFFFFFFFF +#define SLC_SLC0_STATE0_M ((SLC_SLC0_STATE0_V)<<(SLC_SLC0_STATE0_S)) +#define SLC_SLC0_STATE0_V 0xFFFFFFFF +#define SLC_SLC0_STATE0_S 0 + +#define SLC_0_STATE1_REG (DR_REG_SLC_BASE + 0x68) +/* SLC_SLC0_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_STATE1 0xFFFFFFFF +#define SLC_SLC0_STATE1_M ((SLC_SLC0_STATE1_V)<<(SLC_SLC0_STATE1_S)) +#define SLC_SLC0_STATE1_V 0xFFFFFFFF +#define SLC_SLC0_STATE1_S 0 + +#define SLC_1_STATE0_REG (DR_REG_SLC_BASE + 0x6C) +/* SLC_SLC1_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC1_STATE0 0xFFFFFFFF +#define SLC_SLC1_STATE0_M ((SLC_SLC1_STATE0_V)<<(SLC_SLC1_STATE0_S)) +#define SLC_SLC1_STATE0_V 0xFFFFFFFF +#define SLC_SLC1_STATE0_S 0 + +#define SLC_1_STATE1_REG (DR_REG_SLC_BASE + 0x70) +/* SLC_SLC1_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC1_STATE1 0xFFFFFFFF +#define SLC_SLC1_STATE1_M ((SLC_SLC1_STATE1_V)<<(SLC_SLC1_STATE1_S)) +#define SLC_SLC1_STATE1_V 0xFFFFFFFF +#define SLC_SLC1_STATE1_S 0 + +#define SLC_BRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x74) +/* SLC_TX_PUSH_IDLE_NUM : R/W ;bitpos:[31:16] ;default: 16'ha ; */ +/*description: */ +#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF +#define SLC_TX_PUSH_IDLE_NUM_M ((SLC_TX_PUSH_IDLE_NUM_V)<<(SLC_TX_PUSH_IDLE_NUM_S)) +#define SLC_TX_PUSH_IDLE_NUM_V 0xFFFF +#define SLC_TX_PUSH_IDLE_NUM_S 16 +/* SLC_SLC1_TX_DUMMY_MODE : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC1_TX_DUMMY_MODE (BIT(14)) +#define SLC_SLC1_TX_DUMMY_MODE_M (BIT(14)) +#define SLC_SLC1_TX_DUMMY_MODE_V 0x1 +#define SLC_SLC1_TX_DUMMY_MODE_S 14 +/* SLC_HDA_MAP_128K : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: */ +#define SLC_HDA_MAP_128K (BIT(13)) +#define SLC_HDA_MAP_128K_M (BIT(13)) +#define SLC_HDA_MAP_128K_V 0x1 +#define SLC_HDA_MAP_128K_S 13 +/* SLC_SLC0_TX_DUMMY_MODE : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_TX_DUMMY_MODE (BIT(12)) +#define SLC_SLC0_TX_DUMMY_MODE_M (BIT(12)) +#define SLC_SLC0_TX_DUMMY_MODE_V 0x1 +#define SLC_SLC0_TX_DUMMY_MODE_S 12 +/* SLC_FIFO_MAP_ENA : R/W ;bitpos:[11:8] ;default: 4'h7 ; */ +/*description: */ +#define SLC_FIFO_MAP_ENA 0x0000000F +#define SLC_FIFO_MAP_ENA_M ((SLC_FIFO_MAP_ENA_V)<<(SLC_FIFO_MAP_ENA_S)) +#define SLC_FIFO_MAP_ENA_V 0xF +#define SLC_FIFO_MAP_ENA_S 8 +/* SLC_TXEOF_ENA : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: */ +#define SLC_TXEOF_ENA 0x0000003F +#define SLC_TXEOF_ENA_M ((SLC_TXEOF_ENA_V)<<(SLC_TXEOF_ENA_S)) +#define SLC_TXEOF_ENA_V 0x3F +#define SLC_TXEOF_ENA_S 0 + +#define SLC_0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x78) +/* SLC_SLC0_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_TO_EOF_DES_ADDR_M ((SLC_SLC0_TO_EOF_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_DES_ADDR_S)) +#define SLC_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TO_EOF_DES_ADDR_S 0 + +#define SLC_0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x7C) +/* SLC_SLC0_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_SUC_EOF_DES_ADDR_S)) +#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S 0 + +#define SLC_0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x80) +/* SLC_SLC0_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_BFR_DES_ADDR_S)) +#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S 0 + +#define SLC_1_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x84) +/* SLC_SLC1_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC1_TO_EOF_DES_ADDR 0xFFFFFFFF +#define SLC_SLC1_TO_EOF_DES_ADDR_M ((SLC_SLC1_TO_EOF_DES_ADDR_V)<<(SLC_SLC1_TO_EOF_DES_ADDR_S)) +#define SLC_SLC1_TO_EOF_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC1_TO_EOF_DES_ADDR_S 0 + +#define SLC_1_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x88) +/* SLC_SLC1_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC1_TX_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SLC_SLC1_TX_SUC_EOF_DES_ADDR_M ((SLC_SLC1_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC1_TX_SUC_EOF_DES_ADDR_S)) +#define SLC_SLC1_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC1_TX_SUC_EOF_DES_ADDR_S 0 + +#define SLC_1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x8C) +/* SLC_SLC1_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC1_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SLC_SLC1_TO_EOF_BFR_DES_ADDR_M ((SLC_SLC1_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC1_TO_EOF_BFR_DES_ADDR_S)) +#define SLC_SLC1_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC1_TO_EOF_BFR_DES_ADDR_S 0 + +#define SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0x90) +/* SLC_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SLC_AHB_TESTADDR 0x00000003 +#define SLC_AHB_TESTADDR_M ((SLC_AHB_TESTADDR_V)<<(SLC_AHB_TESTADDR_S)) +#define SLC_AHB_TESTADDR_V 0x3 +#define SLC_AHB_TESTADDR_S 4 +/* SLC_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define SLC_AHB_TESTMODE 0x00000007 +#define SLC_AHB_TESTMODE_M ((SLC_AHB_TESTMODE_V)<<(SLC_AHB_TESTMODE_S)) +#define SLC_AHB_TESTMODE_V 0x7 +#define SLC_AHB_TESTMODE_S 0 + +#define SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0x94) +/* SLC_FUNC2_ACC_STATE : RO ;bitpos:[28:24] ;default: 5'b0 ; */ +/*description: */ +#define SLC_FUNC2_ACC_STATE 0x0000001F +#define SLC_FUNC2_ACC_STATE_M ((SLC_FUNC2_ACC_STATE_V)<<(SLC_FUNC2_ACC_STATE_S)) +#define SLC_FUNC2_ACC_STATE_V 0x1F +#define SLC_FUNC2_ACC_STATE_S 24 +/* SLC_FUNC1_ACC_STATE : RO ;bitpos:[20:16] ;default: 5'b0 ; */ +/*description: */ +#define SLC_FUNC1_ACC_STATE 0x0000001F +#define SLC_FUNC1_ACC_STATE_M ((SLC_FUNC1_ACC_STATE_V)<<(SLC_FUNC1_ACC_STATE_S)) +#define SLC_FUNC1_ACC_STATE_V 0x1F +#define SLC_FUNC1_ACC_STATE_S 16 +/* SLC_BUS_ST : RO ;bitpos:[14:12] ;default: 3'b0 ; */ +/*description: */ +#define SLC_BUS_ST 0x00000007 +#define SLC_BUS_ST_M ((SLC_BUS_ST_V)<<(SLC_BUS_ST_S)) +#define SLC_BUS_ST_V 0x7 +#define SLC_BUS_ST_S 12 +/* SLC_SDIO_WAKEUP : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SDIO_WAKEUP (BIT(8)) +#define SLC_SDIO_WAKEUP_M (BIT(8)) +#define SLC_SDIO_WAKEUP_V 0x1 +#define SLC_SDIO_WAKEUP_S 8 +/* SLC_FUNC_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: */ +#define SLC_FUNC_ST 0x0000000F +#define SLC_FUNC_ST_M ((SLC_FUNC_ST_V)<<(SLC_FUNC_ST_S)) +#define SLC_FUNC_ST_V 0xF +#define SLC_FUNC_ST_S 4 +/* SLC_CMD_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define SLC_CMD_ST 0x00000007 +#define SLC_CMD_ST_M ((SLC_CMD_ST_V)<<(SLC_CMD_ST_S)) +#define SLC_CMD_ST_V 0x7 +#define SLC_CMD_ST_S 0 + +#define SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0x98) +/* SLC_SLC1_RD_RETRY_THRESHOLD : R/W ;bitpos:[31:21] ;default: 11'h80 ; */ +/*description: */ +#define SLC_SLC1_RD_RETRY_THRESHOLD 0x000007FF +#define SLC_SLC1_RD_RETRY_THRESHOLD_M ((SLC_SLC1_RD_RETRY_THRESHOLD_V)<<(SLC_SLC1_RD_RETRY_THRESHOLD_S)) +#define SLC_SLC1_RD_RETRY_THRESHOLD_V 0x7FF +#define SLC_SLC1_RD_RETRY_THRESHOLD_S 21 +/* SLC_SLC1_RX_FILL_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_RX_FILL_EN (BIT(20)) +#define SLC_SLC1_RX_FILL_EN_M (BIT(20)) +#define SLC_SLC1_RX_FILL_EN_V 0x1 +#define SLC_SLC1_RX_FILL_EN_S 20 +/* SLC_SLC1_RX_EOF_MODE : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_RX_EOF_MODE (BIT(19)) +#define SLC_SLC1_RX_EOF_MODE_M (BIT(19)) +#define SLC_SLC1_RX_EOF_MODE_V 0x1 +#define SLC_SLC1_RX_EOF_MODE_S 19 +/* SLC_SLC1_RX_FILL_MODE : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_FILL_MODE (BIT(18)) +#define SLC_SLC1_RX_FILL_MODE_M (BIT(18)) +#define SLC_SLC1_RX_FILL_MODE_V 0x1 +#define SLC_SLC1_RX_FILL_MODE_S 18 +/* SLC_SLC1_INFOR_NO_REPLACE : R/W ;bitpos:[17] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_INFOR_NO_REPLACE (BIT(17)) +#define SLC_SLC1_INFOR_NO_REPLACE_M (BIT(17)) +#define SLC_SLC1_INFOR_NO_REPLACE_V 0x1 +#define SLC_SLC1_INFOR_NO_REPLACE_S 17 +/* SLC_SLC1_TOKEN_NO_REPLACE : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC1_TOKEN_NO_REPLACE (BIT(16)) +#define SLC_SLC1_TOKEN_NO_REPLACE_M (BIT(16)) +#define SLC_SLC1_TOKEN_NO_REPLACE_V 0x1 +#define SLC_SLC1_TOKEN_NO_REPLACE_S 16 +/* SLC_SLC0_RD_RETRY_THRESHOLD : R/W ;bitpos:[15:5] ;default: 11'h80 ; */ +/*description: */ +#define SLC_SLC0_RD_RETRY_THRESHOLD 0x000007FF +#define SLC_SLC0_RD_RETRY_THRESHOLD_M ((SLC_SLC0_RD_RETRY_THRESHOLD_V)<<(SLC_SLC0_RD_RETRY_THRESHOLD_S)) +#define SLC_SLC0_RD_RETRY_THRESHOLD_V 0x7FF +#define SLC_SLC0_RD_RETRY_THRESHOLD_S 5 +/* SLC_SLC0_RX_FILL_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_FILL_EN (BIT(4)) +#define SLC_SLC0_RX_FILL_EN_M (BIT(4)) +#define SLC_SLC0_RX_FILL_EN_V 0x1 +#define SLC_SLC0_RX_FILL_EN_S 4 +/* SLC_SLC0_RX_EOF_MODE : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_MODE (BIT(3)) +#define SLC_SLC0_RX_EOF_MODE_M (BIT(3)) +#define SLC_SLC0_RX_EOF_MODE_V 0x1 +#define SLC_SLC0_RX_EOF_MODE_S 3 +/* SLC_SLC0_RX_FILL_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_FILL_MODE (BIT(2)) +#define SLC_SLC0_RX_FILL_MODE_M (BIT(2)) +#define SLC_SLC0_RX_FILL_MODE_V 0x1 +#define SLC_SLC0_RX_FILL_MODE_S 2 +/* SLC_SLC0_INFOR_NO_REPLACE : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_INFOR_NO_REPLACE (BIT(1)) +#define SLC_SLC0_INFOR_NO_REPLACE_M (BIT(1)) +#define SLC_SLC0_INFOR_NO_REPLACE_V 0x1 +#define SLC_SLC0_INFOR_NO_REPLACE_S 1 +/* SLC_SLC0_TOKEN_NO_REPLACE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN_NO_REPLACE (BIT(0)) +#define SLC_SLC0_TOKEN_NO_REPLACE_M (BIT(0)) +#define SLC_SLC0_TOKEN_NO_REPLACE_V 0x1 +#define SLC_SLC0_TOKEN_NO_REPLACE_S 0 + +#define SLC_0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0x9C) +/* SLC_SLC0_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_DSCR 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_M ((SLC_SLC0_TXLINK_DSCR_V)<<(SLC_SLC0_TXLINK_DSCR_S)) +#define SLC_SLC0_TXLINK_DSCR_V 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_S 0 + +#define SLC_0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xA0) +/* SLC_SLC0_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_BF0_M ((SLC_SLC0_TXLINK_DSCR_BF0_V)<<(SLC_SLC0_TXLINK_DSCR_BF0_S)) +#define SLC_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_BF0_S 0 + +#define SLC_0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xA4) +/* SLC_SLC0_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_BF1_M ((SLC_SLC0_TXLINK_DSCR_BF1_V)<<(SLC_SLC0_TXLINK_DSCR_BF1_S)) +#define SLC_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_BF1_S 0 + +#define SLC_0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xA8) +/* SLC_SLC0_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_DSCR 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_M ((SLC_SLC0_RXLINK_DSCR_V)<<(SLC_SLC0_RXLINK_DSCR_S)) +#define SLC_SLC0_RXLINK_DSCR_V 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_S 0 + +#define SLC_0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xAC) +/* SLC_SLC0_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_BF0_M ((SLC_SLC0_RXLINK_DSCR_BF0_V)<<(SLC_SLC0_RXLINK_DSCR_BF0_S)) +#define SLC_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_BF0_S 0 + +#define SLC_0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xB0) +/* SLC_SLC0_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_BF1_M ((SLC_SLC0_RXLINK_DSCR_BF1_V)<<(SLC_SLC0_RXLINK_DSCR_BF1_S)) +#define SLC_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_BF1_S 0 + +#define SLC_1_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xB4) +/* SLC_SLC1_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC1_TXLINK_DSCR 0xFFFFFFFF +#define SLC_SLC1_TXLINK_DSCR_M ((SLC_SLC1_TXLINK_DSCR_V)<<(SLC_SLC1_TXLINK_DSCR_S)) +#define SLC_SLC1_TXLINK_DSCR_V 0xFFFFFFFF +#define SLC_SLC1_TXLINK_DSCR_S 0 + +#define SLC_1_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xB8) +/* SLC_SLC1_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC1_TXLINK_DSCR_BF0 0xFFFFFFFF +#define SLC_SLC1_TXLINK_DSCR_BF0_M ((SLC_SLC1_TXLINK_DSCR_BF0_V)<<(SLC_SLC1_TXLINK_DSCR_BF0_S)) +#define SLC_SLC1_TXLINK_DSCR_BF0_V 0xFFFFFFFF +#define SLC_SLC1_TXLINK_DSCR_BF0_S 0 + +#define SLC_1_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xBC) +/* SLC_SLC1_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC1_TXLINK_DSCR_BF1 0xFFFFFFFF +#define SLC_SLC1_TXLINK_DSCR_BF1_M ((SLC_SLC1_TXLINK_DSCR_BF1_V)<<(SLC_SLC1_TXLINK_DSCR_BF1_S)) +#define SLC_SLC1_TXLINK_DSCR_BF1_V 0xFFFFFFFF +#define SLC_SLC1_TXLINK_DSCR_BF1_S 0 + +#define SLC_1_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xC0) +/* SLC_SLC1_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC1_RXLINK_DSCR 0xFFFFFFFF +#define SLC_SLC1_RXLINK_DSCR_M ((SLC_SLC1_RXLINK_DSCR_V)<<(SLC_SLC1_RXLINK_DSCR_S)) +#define SLC_SLC1_RXLINK_DSCR_V 0xFFFFFFFF +#define SLC_SLC1_RXLINK_DSCR_S 0 + +#define SLC_1_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xC4) +/* SLC_SLC1_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC1_RXLINK_DSCR_BF0 0xFFFFFFFF +#define SLC_SLC1_RXLINK_DSCR_BF0_M ((SLC_SLC1_RXLINK_DSCR_BF0_V)<<(SLC_SLC1_RXLINK_DSCR_BF0_S)) +#define SLC_SLC1_RXLINK_DSCR_BF0_V 0xFFFFFFFF +#define SLC_SLC1_RXLINK_DSCR_BF0_S 0 + +#define SLC_1_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xC8) +/* SLC_SLC1_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC1_RXLINK_DSCR_BF1 0xFFFFFFFF +#define SLC_SLC1_RXLINK_DSCR_BF1_M ((SLC_SLC1_RXLINK_DSCR_BF1_V)<<(SLC_SLC1_RXLINK_DSCR_BF1_S)) +#define SLC_SLC1_RXLINK_DSCR_BF1_V 0xFFFFFFFF +#define SLC_SLC1_RXLINK_DSCR_BF1_S 0 + +#define SLC_0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xCC) +/* SLC_SLC0_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_ERR_EOF_DES_ADDR_S)) +#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S 0 + +#define SLC_1_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xD0) +/* SLC_SLC1_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC1_TX_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SLC_SLC1_TX_ERR_EOF_DES_ADDR_M ((SLC_SLC1_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC1_TX_ERR_EOF_DES_ADDR_S)) +#define SLC_SLC1_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC1_TX_ERR_EOF_DES_ADDR_S 0 + +#define SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xD4) +/* SLC_SLC1_TOKEN : RO ;bitpos:[27:16] ;default: 12'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN 0x00000FFF +#define SLC_SLC1_TOKEN_M ((SLC_SLC1_TOKEN_V)<<(SLC_SLC1_TOKEN_S)) +#define SLC_SLC1_TOKEN_V 0xFFF +#define SLC_SLC1_TOKEN_S 16 +/* SLC_SLC0_TOKEN : RO ;bitpos:[11:0] ;default: 12'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN 0x00000FFF +#define SLC_SLC0_TOKEN_M ((SLC_SLC0_TOKEN_V)<<(SLC_SLC0_TOKEN_S)) +#define SLC_SLC0_TOKEN_V 0xFFF +#define SLC_SLC0_TOKEN_S 0 + +#define SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xD8) +/* SLC_WR_RETRY_THRESHOLD : R/W ;bitpos:[10:0] ;default: 11'h80 ; */ +/*description: */ +#define SLC_WR_RETRY_THRESHOLD 0x000007FF +#define SLC_WR_RETRY_THRESHOLD_M ((SLC_WR_RETRY_THRESHOLD_V)<<(SLC_WR_RETRY_THRESHOLD_S)) +#define SLC_WR_RETRY_THRESHOLD_V 0x7FF +#define SLC_WR_RETRY_THRESHOLD_S 0 + +#define SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xDC) +/* SLC_CMD_CONTENT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_CMD_CONTENT0 0xFFFFFFFF +#define SLC_CMD_CONTENT0_M ((SLC_CMD_CONTENT0_V)<<(SLC_CMD_CONTENT0_S)) +#define SLC_CMD_CONTENT0_V 0xFFFFFFFF +#define SLC_CMD_CONTENT0_S 0 + +#define SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xE0) +/* SLC_CMD_CONTENT1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_CMD_CONTENT1 0xFFFFFFFF +#define SLC_CMD_CONTENT1_M ((SLC_CMD_CONTENT1_V)<<(SLC_CMD_CONTENT1_S)) +#define SLC_CMD_CONTENT1_V 0xFFFFFFFF +#define SLC_CMD_CONTENT1_S 0 + +#define SLC_0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xE4) +/* SLC_SLC0_TX_NEW_PKT_IND : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_NEW_PKT_IND (BIT(28)) +#define SLC_SLC0_TX_NEW_PKT_IND_M (BIT(28)) +#define SLC_SLC0_TX_NEW_PKT_IND_V 0x1 +#define SLC_SLC0_TX_NEW_PKT_IND_S 28 +/* SLC_SLC0_RX_NEW_PKT_IND : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_NEW_PKT_IND (BIT(27)) +#define SLC_SLC0_RX_NEW_PKT_IND_M (BIT(27)) +#define SLC_SLC0_RX_NEW_PKT_IND_V 0x1 +#define SLC_SLC0_RX_NEW_PKT_IND_S 27 +/* SLC_SLC0_TX_GET_USED_DSCR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_GET_USED_DSCR (BIT(26)) +#define SLC_SLC0_TX_GET_USED_DSCR_M (BIT(26)) +#define SLC_SLC0_TX_GET_USED_DSCR_V 0x1 +#define SLC_SLC0_TX_GET_USED_DSCR_S 26 +/* SLC_SLC0_RX_GET_USED_DSCR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_GET_USED_DSCR (BIT(25)) +#define SLC_SLC0_RX_GET_USED_DSCR_M (BIT(25)) +#define SLC_SLC0_RX_GET_USED_DSCR_V 0x1 +#define SLC_SLC0_RX_GET_USED_DSCR_S 25 +/* SLC_SLC0_TX_PACKET_LOAD_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_PACKET_LOAD_EN (BIT(24)) +#define SLC_SLC0_TX_PACKET_LOAD_EN_M (BIT(24)) +#define SLC_SLC0_TX_PACKET_LOAD_EN_V 0x1 +#define SLC_SLC0_TX_PACKET_LOAD_EN_S 24 +/* SLC_SLC0_RX_PACKET_LOAD_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_PACKET_LOAD_EN (BIT(23)) +#define SLC_SLC0_RX_PACKET_LOAD_EN_M (BIT(23)) +#define SLC_SLC0_RX_PACKET_LOAD_EN_V 0x1 +#define SLC_SLC0_RX_PACKET_LOAD_EN_S 23 +/* SLC_SLC0_LEN_INC_MORE : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_LEN_INC_MORE (BIT(22)) +#define SLC_SLC0_LEN_INC_MORE_M (BIT(22)) +#define SLC_SLC0_LEN_INC_MORE_V 0x1 +#define SLC_SLC0_LEN_INC_MORE_S 22 +/* SLC_SLC0_LEN_INC : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_LEN_INC (BIT(21)) +#define SLC_SLC0_LEN_INC_M (BIT(21)) +#define SLC_SLC0_LEN_INC_V 0x1 +#define SLC_SLC0_LEN_INC_S 21 +/* SLC_SLC0_LEN_WR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_LEN_WR (BIT(20)) +#define SLC_SLC0_LEN_WR_M (BIT(20)) +#define SLC_SLC0_LEN_WR_V 0x1 +#define SLC_SLC0_LEN_WR_S 20 +/* SLC_SLC0_LEN_WDATA : WO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC0_LEN_WDATA 0x000FFFFF +#define SLC_SLC0_LEN_WDATA_M ((SLC_SLC0_LEN_WDATA_V)<<(SLC_SLC0_LEN_WDATA_S)) +#define SLC_SLC0_LEN_WDATA_V 0xFFFFF +#define SLC_SLC0_LEN_WDATA_S 0 + +#define SLC_0_LENGTH_REG (DR_REG_SLC_BASE + 0xE8) +/* SLC_SLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC0_LEN 0x000FFFFF +#define SLC_SLC0_LEN_M ((SLC_SLC0_LEN_V)<<(SLC_SLC0_LEN_S)) +#define SLC_SLC0_LEN_V 0xFFFFF +#define SLC_SLC0_LEN_S 0 + +#define SLC_0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xEC) +/* SLC_SLC0_TX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_H_DSCR_ADDR_S)) +#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S 0 + +#define SLC_0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF0) +/* SLC_SLC0_TX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_E_DSCR_ADDR_S)) +#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S 0 + +#define SLC_0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xF4) +/* SLC_SLC0_RX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_H_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S 0 + +#define SLC_0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF8) +/* SLC_SLC0_RX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_E_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S 0 + +#define SLC_0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0xFC) +/* SLC_SLC0_TX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_START_DSCR_ADDR_S)) +#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S 0 + +#define SLC_0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x100) +/* SLC_SLC0_TX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_END_DSCR_ADDR_S)) +#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S 0 + +#define SLC_0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x104) +/* SLC_SLC0_RX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_START_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S 0 + +#define SLC_0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x108) +/* SLC_SLC0_RX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_END_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S 0 + +#define SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x114) +/* SLC_SLC1_SEQ_POSITION : R/W ;bitpos:[15:8] ;default: 8'h5 ; */ +/*description: */ +#define SLC_SLC1_SEQ_POSITION 0x000000FF +#define SLC_SLC1_SEQ_POSITION_M ((SLC_SLC1_SEQ_POSITION_V)<<(SLC_SLC1_SEQ_POSITION_S)) +#define SLC_SLC1_SEQ_POSITION_V 0xFF +#define SLC_SLC1_SEQ_POSITION_S 8 +/* SLC_SLC0_SEQ_POSITION : R/W ;bitpos:[7:0] ;default: 8'h9 ; */ +/*description: */ +#define SLC_SLC0_SEQ_POSITION 0x000000FF +#define SLC_SLC0_SEQ_POSITION_M ((SLC_SLC0_SEQ_POSITION_V)<<(SLC_SLC0_SEQ_POSITION_S)) +#define SLC_SLC0_SEQ_POSITION_V 0xFF +#define SLC_SLC0_SEQ_POSITION_S 0 + +#define SLC_0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x118) +/* SLC_SLC0_RX_DSCR_REC_LIM : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_REC_LIM 0x000003FF +#define SLC_SLC0_RX_DSCR_REC_LIM_M ((SLC_SLC0_RX_DSCR_REC_LIM_V)<<(SLC_SLC0_RX_DSCR_REC_LIM_S)) +#define SLC_SLC0_RX_DSCR_REC_LIM_V 0x3FF +#define SLC_SLC0_RX_DSCR_REC_LIM_S 0 + +#define SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x11C) +/* SLC_DAT3_CRC_ERR_CNT : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define SLC_DAT3_CRC_ERR_CNT 0x000000FF +#define SLC_DAT3_CRC_ERR_CNT_M ((SLC_DAT3_CRC_ERR_CNT_V)<<(SLC_DAT3_CRC_ERR_CNT_S)) +#define SLC_DAT3_CRC_ERR_CNT_V 0xFF +#define SLC_DAT3_CRC_ERR_CNT_S 24 +/* SLC_DAT2_CRC_ERR_CNT : RO ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define SLC_DAT2_CRC_ERR_CNT 0x000000FF +#define SLC_DAT2_CRC_ERR_CNT_M ((SLC_DAT2_CRC_ERR_CNT_V)<<(SLC_DAT2_CRC_ERR_CNT_S)) +#define SLC_DAT2_CRC_ERR_CNT_V 0xFF +#define SLC_DAT2_CRC_ERR_CNT_S 16 +/* SLC_DAT1_CRC_ERR_CNT : RO ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define SLC_DAT1_CRC_ERR_CNT 0x000000FF +#define SLC_DAT1_CRC_ERR_CNT_M ((SLC_DAT1_CRC_ERR_CNT_V)<<(SLC_DAT1_CRC_ERR_CNT_S)) +#define SLC_DAT1_CRC_ERR_CNT_V 0xFF +#define SLC_DAT1_CRC_ERR_CNT_S 8 +/* SLC_DAT0_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SLC_DAT0_CRC_ERR_CNT 0x000000FF +#define SLC_DAT0_CRC_ERR_CNT_M ((SLC_DAT0_CRC_ERR_CNT_V)<<(SLC_DAT0_CRC_ERR_CNT_S)) +#define SLC_DAT0_CRC_ERR_CNT_V 0xFF +#define SLC_DAT0_CRC_ERR_CNT_S 0 + +#define SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x120) +/* SLC_ERR_CNT_CLR : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SLC_ERR_CNT_CLR (BIT(31)) +#define SLC_ERR_CNT_CLR_M (BIT(31)) +#define SLC_ERR_CNT_CLR_V 0x1 +#define SLC_ERR_CNT_CLR_S 31 +/* SLC_CMD_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SLC_CMD_CRC_ERR_CNT 0x000000FF +#define SLC_CMD_CRC_ERR_CNT_M ((SLC_CMD_CRC_ERR_CNT_V)<<(SLC_CMD_CRC_ERR_CNT_S)) +#define SLC_CMD_CRC_ERR_CNT_V 0xFF +#define SLC_CMD_CRC_ERR_CNT_S 0 + +#define SLC_0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x124) +/* SLC_SLC0_EOF_START_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_EOF_START_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_EOF_START_DES_ADDR_M ((SLC_SLC0_EOF_START_DES_ADDR_V)<<(SLC_SLC0_EOF_START_DES_ADDR_S)) +#define SLC_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_EOF_START_DES_ADDR_S 0 + +#define SLC_0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x128) +/* SLC_SLC0_RX_PUSH_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PUSH_DSCR_ADDR_M ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V)<<(SLC_SLC0_RX_PUSH_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PUSH_DSCR_ADDR_S 0 + +#define SLC_0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x12C) +/* SLC_SLC0_RX_DONE_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_DONE_DSCR_ADDR_M ((SLC_SLC0_RX_DONE_DSCR_ADDR_V)<<(SLC_SLC0_RX_DONE_DSCR_ADDR_S)) +#define SLC_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_DONE_DSCR_ADDR_S 0 + +#define SLC_0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x130) +/* SLC_SLC0_SUB_PAC_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V)<<(SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S)) +#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S 0 + +#define SLC_0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x134) +/* SLC_SLC0_RX_GET_EOF_OCC : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_GET_EOF_OCC (BIT(16)) +#define SLC_SLC0_RX_GET_EOF_OCC_M (BIT(16)) +#define SLC_SLC0_RX_GET_EOF_OCC_V 0x1 +#define SLC_SLC0_RX_GET_EOF_OCC_S 16 +/* SLC_SLC0_RX_DSCR_CNT_LAT : RO ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_CNT_LAT 0x000003FF +#define SLC_SLC0_RX_DSCR_CNT_LAT_M ((SLC_SLC0_RX_DSCR_CNT_LAT_V)<<(SLC_SLC0_RX_DSCR_CNT_LAT_S)) +#define SLC_SLC0_RX_DSCR_CNT_LAT_V 0x3FF +#define SLC_SLC0_RX_DSCR_CNT_LAT_S 0 + +#define SLC_0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x138) +/* SLC_SLC0_LEN_LIM : R/W ;bitpos:[19:0] ;default: 20'h5400 ; */ +/*description: */ +#define SLC_SLC0_LEN_LIM 0x000FFFFF +#define SLC_SLC0_LEN_LIM_M ((SLC_SLC0_LEN_LIM_V)<<(SLC_SLC0_LEN_LIM_S)) +#define SLC_SLC0_LEN_LIM_V 0xFFFFF +#define SLC_SLC0_LEN_LIM_S 0 + +#define SLC_0INT_ST1_REG (DR_REG_SLC_BASE + 0x13C) +/* SLC_SLC0_RX_QUICK_EOF_INT_ST1 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S 26 +/* SLC_CMD_DTC_INT_ST1 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_ST1 (BIT(25)) +#define SLC_CMD_DTC_INT_ST1_M (BIT(25)) +#define SLC_CMD_DTC_INT_ST1_V 0x1 +#define SLC_CMD_DTC_INT_ST1_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ST1_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ST1_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_ST1_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ST1_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ST1_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_ST1_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S 19 +/* SLC_SLC0_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_ST1 (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ST1_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ST1_V 0x1 +#define SLC_SLC0_TOHOST_INT_ST1_S 18 +/* SLC_SLC0_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_ST1 (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ST1_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ST1_V 0x1 +#define SLC_SLC0_RX_EOF_INT_ST1_S 17 +/* SLC_SLC0_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_ST1 (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ST1_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ST1_V 0x1 +#define SLC_SLC0_RX_DONE_INT_ST1_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ST1_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ST1_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_ST1_S 15 +/* SLC_SLC0_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_ST1 (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ST1_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ST1_V 0x1 +#define SLC_SLC0_TX_DONE_INT_ST1_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S 12 +/* SLC_SLC0_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_ST1 (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ST1_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ST1_V 0x1 +#define SLC_SLC0_TX_OVF_INT_ST1_S 11 +/* SLC_SLC0_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_ST1 (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ST1_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ST1_V 0x1 +#define SLC_SLC0_RX_UDF_INT_ST1_S 10 +/* SLC_SLC0_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_ST1 (BIT(9)) +#define SLC_SLC0_TX_START_INT_ST1_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_ST1_V 0x1 +#define SLC_SLC0_TX_START_INT_ST1_S 9 +/* SLC_SLC0_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_ST1 (BIT(8)) +#define SLC_SLC0_RX_START_INT_ST1_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_ST1_V 0x1 +#define SLC_SLC0_RX_START_INT_ST1_S 8 +/* SLC_FRHOST_BIT7_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_ST1 (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ST1_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT7_INT_ST1_S 7 +/* SLC_FRHOST_BIT6_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_ST1 (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ST1_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT6_INT_ST1_S 6 +/* SLC_FRHOST_BIT5_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_ST1 (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ST1_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT5_INT_ST1_S 5 +/* SLC_FRHOST_BIT4_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_ST1 (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ST1_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT4_INT_ST1_S 4 +/* SLC_FRHOST_BIT3_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_ST1 (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ST1_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT3_INT_ST1_S 3 +/* SLC_FRHOST_BIT2_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_ST1 (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ST1_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT2_INT_ST1_S 2 +/* SLC_FRHOST_BIT1_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_ST1 (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ST1_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT1_INT_ST1_S 1 +/* SLC_FRHOST_BIT0_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_ST1 (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ST1_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT0_INT_ST1_S 0 + +#define SLC_0INT_ENA1_REG (DR_REG_SLC_BASE + 0x140) +/* SLC_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S 26 +/* SLC_CMD_DTC_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_ENA1 (BIT(25)) +#define SLC_CMD_DTC_INT_ENA1_M (BIT(25)) +#define SLC_CMD_DTC_INT_ENA1_V 0x1 +#define SLC_CMD_DTC_INT_ENA1_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S 19 +/* SLC_SLC0_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_ENA1 (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ENA1_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ENA1_V 0x1 +#define SLC_SLC0_TOHOST_INT_ENA1_S 18 +/* SLC_SLC0_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_ENA1 (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ENA1_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_EOF_INT_ENA1_S 17 +/* SLC_SLC0_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_ENA1 (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ENA1_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_DONE_INT_ENA1_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S 15 +/* SLC_SLC0_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_ENA1 (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ENA1_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_DONE_INT_ENA1_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S 12 +/* SLC_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_ENA1 (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ENA1_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_OVF_INT_ENA1_S 11 +/* SLC_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_ENA1 (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ENA1_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_UDF_INT_ENA1_S 10 +/* SLC_SLC0_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_ENA1 (BIT(9)) +#define SLC_SLC0_TX_START_INT_ENA1_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_START_INT_ENA1_S 9 +/* SLC_SLC0_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_ENA1 (BIT(8)) +#define SLC_SLC0_RX_START_INT_ENA1_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_START_INT_ENA1_S 8 +/* SLC_FRHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_ENA1 (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ENA1_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT7_INT_ENA1_S 7 +/* SLC_FRHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_ENA1 (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ENA1_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT6_INT_ENA1_S 6 +/* SLC_FRHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_ENA1 (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ENA1_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT5_INT_ENA1_S 5 +/* SLC_FRHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_ENA1 (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ENA1_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT4_INT_ENA1_S 4 +/* SLC_FRHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_ENA1 (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ENA1_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT3_INT_ENA1_S 3 +/* SLC_FRHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_ENA1 (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ENA1_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT2_INT_ENA1_S 2 +/* SLC_FRHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_ENA1 (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ENA1_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT1_INT_ENA1_S 1 +/* SLC_FRHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_ENA1 (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ENA1_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT0_INT_ENA1_S 0 + +#define SLC_1INT_ST1_REG (DR_REG_SLC_BASE + 0x144) +/* SLC_SLC1_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_ST1_M (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_ST1_V 0x1 +#define SLC_SLC1_TX_ERR_EOF_INT_ST1_S 24 +/* SLC_SLC1_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_ST1_M (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_ST1_V 0x1 +#define SLC_SLC1_WR_RETRY_DONE_INT_ST1_S 23 +/* SLC_SLC1_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_ST1_M (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_ST1_V 0x1 +#define SLC_SLC1_HOST_RD_ACK_INT_ST1_S 22 +/* SLC_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_M (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_V 0x1 +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_S 21 +/* SLC_SLC1_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_ST1_M (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_ST1_V 0x1 +#define SLC_SLC1_RX_DSCR_ERR_INT_ST1_S 20 +/* SLC_SLC1_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_ST1_M (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_ST1_V 0x1 +#define SLC_SLC1_TX_DSCR_ERR_INT_ST1_S 19 +/* SLC_SLC1_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOHOST_INT_ST1 (BIT(18)) +#define SLC_SLC1_TOHOST_INT_ST1_M (BIT(18)) +#define SLC_SLC1_TOHOST_INT_ST1_V 0x1 +#define SLC_SLC1_TOHOST_INT_ST1_S 18 +/* SLC_SLC1_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_EOF_INT_ST1 (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_ST1_M (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_ST1_V 0x1 +#define SLC_SLC1_RX_EOF_INT_ST1_S 17 +/* SLC_SLC1_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DONE_INT_ST1 (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_ST1_M (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_ST1_V 0x1 +#define SLC_SLC1_RX_DONE_INT_ST1_S 16 +/* SLC_SLC1_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_ST1_M (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_ST1_V 0x1 +#define SLC_SLC1_TX_SUC_EOF_INT_ST1_S 15 +/* SLC_SLC1_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DONE_INT_ST1 (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_ST1_M (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_ST1_V 0x1 +#define SLC_SLC1_TX_DONE_INT_ST1_S 14 +/* SLC_SLC1_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_ST1_M (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_ST1_V 0x1 +#define SLC_SLC1_TOKEN1_1TO0_INT_ST1_S 13 +/* SLC_SLC1_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_ST1_M (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_ST1_V 0x1 +#define SLC_SLC1_TOKEN0_1TO0_INT_ST1_S 12 +/* SLC_SLC1_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_OVF_INT_ST1 (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_ST1_M (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_ST1_V 0x1 +#define SLC_SLC1_TX_OVF_INT_ST1_S 11 +/* SLC_SLC1_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_UDF_INT_ST1 (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_ST1_M (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_ST1_V 0x1 +#define SLC_SLC1_RX_UDF_INT_ST1_S 10 +/* SLC_SLC1_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_START_INT_ST1 (BIT(9)) +#define SLC_SLC1_TX_START_INT_ST1_M (BIT(9)) +#define SLC_SLC1_TX_START_INT_ST1_V 0x1 +#define SLC_SLC1_TX_START_INT_ST1_S 9 +/* SLC_SLC1_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_START_INT_ST1 (BIT(8)) +#define SLC_SLC1_RX_START_INT_ST1_M (BIT(8)) +#define SLC_SLC1_RX_START_INT_ST1_V 0x1 +#define SLC_SLC1_RX_START_INT_ST1_S 8 +/* SLC_FRHOST_BIT15_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT15_INT_ST1 (BIT(7)) +#define SLC_FRHOST_BIT15_INT_ST1_M (BIT(7)) +#define SLC_FRHOST_BIT15_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT15_INT_ST1_S 7 +/* SLC_FRHOST_BIT14_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT14_INT_ST1 (BIT(6)) +#define SLC_FRHOST_BIT14_INT_ST1_M (BIT(6)) +#define SLC_FRHOST_BIT14_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT14_INT_ST1_S 6 +/* SLC_FRHOST_BIT13_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT13_INT_ST1 (BIT(5)) +#define SLC_FRHOST_BIT13_INT_ST1_M (BIT(5)) +#define SLC_FRHOST_BIT13_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT13_INT_ST1_S 5 +/* SLC_FRHOST_BIT12_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT12_INT_ST1 (BIT(4)) +#define SLC_FRHOST_BIT12_INT_ST1_M (BIT(4)) +#define SLC_FRHOST_BIT12_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT12_INT_ST1_S 4 +/* SLC_FRHOST_BIT11_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT11_INT_ST1 (BIT(3)) +#define SLC_FRHOST_BIT11_INT_ST1_M (BIT(3)) +#define SLC_FRHOST_BIT11_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT11_INT_ST1_S 3 +/* SLC_FRHOST_BIT10_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT10_INT_ST1 (BIT(2)) +#define SLC_FRHOST_BIT10_INT_ST1_M (BIT(2)) +#define SLC_FRHOST_BIT10_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT10_INT_ST1_S 2 +/* SLC_FRHOST_BIT9_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT9_INT_ST1 (BIT(1)) +#define SLC_FRHOST_BIT9_INT_ST1_M (BIT(1)) +#define SLC_FRHOST_BIT9_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT9_INT_ST1_S 1 +/* SLC_FRHOST_BIT8_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT8_INT_ST1 (BIT(0)) +#define SLC_FRHOST_BIT8_INT_ST1_M (BIT(0)) +#define SLC_FRHOST_BIT8_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT8_INT_ST1_S 0 + +#define SLC_1INT_ENA1_REG (DR_REG_SLC_BASE + 0x148) +/* SLC_SLC1_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_ENA1_M (BIT(24)) +#define SLC_SLC1_TX_ERR_EOF_INT_ENA1_V 0x1 +#define SLC_SLC1_TX_ERR_EOF_INT_ENA1_S 24 +/* SLC_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_M (BIT(23)) +#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_V 0x1 +#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_S 23 +/* SLC_SLC1_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_ENA1_M (BIT(22)) +#define SLC_SLC1_HOST_RD_ACK_INT_ENA1_V 0x1 +#define SLC_SLC1_HOST_RD_ACK_INT_ENA1_S 22 +/* SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_M (BIT(21)) +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_V 0x1 +#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_S 21 +/* SLC_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_M (BIT(20)) +#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_V 0x1 +#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_S 20 +/* SLC_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_M (BIT(19)) +#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_V 0x1 +#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_S 19 +/* SLC_SLC1_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOHOST_INT_ENA1 (BIT(18)) +#define SLC_SLC1_TOHOST_INT_ENA1_M (BIT(18)) +#define SLC_SLC1_TOHOST_INT_ENA1_V 0x1 +#define SLC_SLC1_TOHOST_INT_ENA1_S 18 +/* SLC_SLC1_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_EOF_INT_ENA1 (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_ENA1_M (BIT(17)) +#define SLC_SLC1_RX_EOF_INT_ENA1_V 0x1 +#define SLC_SLC1_RX_EOF_INT_ENA1_S 17 +/* SLC_SLC1_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_DONE_INT_ENA1 (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_ENA1_M (BIT(16)) +#define SLC_SLC1_RX_DONE_INT_ENA1_V 0x1 +#define SLC_SLC1_RX_DONE_INT_ENA1_S 16 +/* SLC_SLC1_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_ENA1_M (BIT(15)) +#define SLC_SLC1_TX_SUC_EOF_INT_ENA1_V 0x1 +#define SLC_SLC1_TX_SUC_EOF_INT_ENA1_S 15 +/* SLC_SLC1_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_DONE_INT_ENA1 (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_ENA1_M (BIT(14)) +#define SLC_SLC1_TX_DONE_INT_ENA1_V 0x1 +#define SLC_SLC1_TX_DONE_INT_ENA1_S 14 +/* SLC_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_M (BIT(13)) +#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x1 +#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_S 13 +/* SLC_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_M (BIT(12)) +#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x1 +#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_S 12 +/* SLC_SLC1_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_OVF_INT_ENA1 (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_ENA1_M (BIT(11)) +#define SLC_SLC1_TX_OVF_INT_ENA1_V 0x1 +#define SLC_SLC1_TX_OVF_INT_ENA1_S 11 +/* SLC_SLC1_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_UDF_INT_ENA1 (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_ENA1_M (BIT(10)) +#define SLC_SLC1_RX_UDF_INT_ENA1_V 0x1 +#define SLC_SLC1_RX_UDF_INT_ENA1_S 10 +/* SLC_SLC1_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_TX_START_INT_ENA1 (BIT(9)) +#define SLC_SLC1_TX_START_INT_ENA1_M (BIT(9)) +#define SLC_SLC1_TX_START_INT_ENA1_V 0x1 +#define SLC_SLC1_TX_START_INT_ENA1_S 9 +/* SLC_SLC1_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC1_RX_START_INT_ENA1 (BIT(8)) +#define SLC_SLC1_RX_START_INT_ENA1_M (BIT(8)) +#define SLC_SLC1_RX_START_INT_ENA1_V 0x1 +#define SLC_SLC1_RX_START_INT_ENA1_S 8 +/* SLC_FRHOST_BIT15_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT15_INT_ENA1 (BIT(7)) +#define SLC_FRHOST_BIT15_INT_ENA1_M (BIT(7)) +#define SLC_FRHOST_BIT15_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT15_INT_ENA1_S 7 +/* SLC_FRHOST_BIT14_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT14_INT_ENA1 (BIT(6)) +#define SLC_FRHOST_BIT14_INT_ENA1_M (BIT(6)) +#define SLC_FRHOST_BIT14_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT14_INT_ENA1_S 6 +/* SLC_FRHOST_BIT13_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT13_INT_ENA1 (BIT(5)) +#define SLC_FRHOST_BIT13_INT_ENA1_M (BIT(5)) +#define SLC_FRHOST_BIT13_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT13_INT_ENA1_S 5 +/* SLC_FRHOST_BIT12_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT12_INT_ENA1 (BIT(4)) +#define SLC_FRHOST_BIT12_INT_ENA1_M (BIT(4)) +#define SLC_FRHOST_BIT12_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT12_INT_ENA1_S 4 +/* SLC_FRHOST_BIT11_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT11_INT_ENA1 (BIT(3)) +#define SLC_FRHOST_BIT11_INT_ENA1_M (BIT(3)) +#define SLC_FRHOST_BIT11_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT11_INT_ENA1_S 3 +/* SLC_FRHOST_BIT10_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT10_INT_ENA1 (BIT(2)) +#define SLC_FRHOST_BIT10_INT_ENA1_M (BIT(2)) +#define SLC_FRHOST_BIT10_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT10_INT_ENA1_S 2 +/* SLC_FRHOST_BIT9_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT9_INT_ENA1 (BIT(1)) +#define SLC_FRHOST_BIT9_INT_ENA1_M (BIT(1)) +#define SLC_FRHOST_BIT9_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT9_INT_ENA1_S 1 +/* SLC_FRHOST_BIT8_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT8_INT_ENA1 (BIT(0)) +#define SLC_FRHOST_BIT8_INT_ENA1_M (BIT(0)) +#define SLC_FRHOST_BIT8_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT8_INT_ENA1_S 0 + +#define SLC_DATE_REG (DR_REG_SLC_BASE + 0x1F8) +/* SLC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022500 ; */ +/*description: */ +#define SLC_DATE 0xFFFFFFFF +#define SLC_DATE_M ((SLC_DATE_V)<<(SLC_DATE_S)) +#define SLC_DATE_V 0xFFFFFFFF +#define SLC_DATE_S 0 + +#define SLC_ID_REG (DR_REG_SLC_BASE + 0x1FC) +/* SLC_ID : R/W ;bitpos:[31:0] ;default: 32'h0100 ; */ +/*description: */ +#define SLC_ID 0xFFFFFFFF +#define SLC_ID_M ((SLC_ID_V)<<(SLC_ID_S)) +#define SLC_ID_V 0xFFFFFFFF +#define SLC_ID_S 0 + + + + +#endif /*_SOC_SLC_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/slc_struct.h b/tools/sdk/include/soc/include/soc/slc_struct.h new file mode 100644 index 00000000000..55506a5b436 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/slc_struct.h @@ -0,0 +1,860 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SLC_STRUCT_H_ +#define _SOC_SLC_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t slc0_tx_rst: 1; + uint32_t slc0_rx_rst: 1; + uint32_t ahbm_fifo_rst: 1; + uint32_t ahbm_rst: 1; + uint32_t slc0_tx_loop_test: 1; + uint32_t slc0_rx_loop_test: 1; + uint32_t slc0_rx_auto_wrback: 1; + uint32_t slc0_rx_no_restart_clr: 1; + uint32_t slc0_rxdscr_burst_en: 1; + uint32_t slc0_rxdata_burst_en: 1; + uint32_t slc0_rxlink_auto_ret: 1; + uint32_t slc0_txlink_auto_ret: 1; + uint32_t slc0_txdscr_burst_en: 1; + uint32_t slc0_txdata_burst_en: 1; + uint32_t slc0_token_auto_clr: 1; + uint32_t slc0_token_sel: 1; + uint32_t slc1_tx_rst: 1; + uint32_t slc1_rx_rst: 1; + uint32_t slc0_wr_retry_mask_en: 1; + uint32_t slc1_wr_retry_mask_en: 1; + uint32_t slc1_tx_loop_test: 1; + uint32_t slc1_rx_loop_test: 1; + uint32_t slc1_rx_auto_wrback: 1; + uint32_t slc1_rx_no_restart_clr: 1; + uint32_t slc1_rxdscr_burst_en: 1; + uint32_t slc1_rxdata_burst_en: 1; + uint32_t slc1_rxlink_auto_ret: 1; + uint32_t slc1_txlink_auto_ret: 1; + uint32_t slc1_txdscr_burst_en: 1; + uint32_t slc1_txdata_burst_en: 1; + uint32_t slc1_token_auto_clr: 1; + uint32_t slc1_token_sel: 1; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t cmd_dtc: 1; + uint32_t rx_quick_eof: 1; + uint32_t reserved27: 5; + }; + uint32_t val; + } slc0_int_raw; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t cmd_dtc: 1; + uint32_t rx_quick_eof: 1; + uint32_t reserved27: 5; + }; + uint32_t val; + } slc0_int_st; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t cmd_dtc: 1; + uint32_t rx_quick_eof: 1; + uint32_t reserved27: 5; + }; + uint32_t val; + } slc0_int_ena; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t cmd_dtc: 1; + uint32_t rx_quick_eof: 1; + uint32_t reserved27: 5; + }; + uint32_t val; + } slc0_int_clr; + union { + struct { + uint32_t frhost_bit8: 1; + uint32_t frhost_bit9: 1; + uint32_t frhost_bit10: 1; + uint32_t frhost_bit11: 1; + uint32_t frhost_bit12: 1; + uint32_t frhost_bit13: 1; + uint32_t frhost_bit14: 1; + uint32_t frhost_bit15: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } slc1_int_raw; + union { + struct { + uint32_t frhost_bit8: 1; + uint32_t frhost_bit9: 1; + uint32_t frhost_bit10: 1; + uint32_t frhost_bit11: 1; + uint32_t frhost_bit12: 1; + uint32_t frhost_bit13: 1; + uint32_t frhost_bit14: 1; + uint32_t frhost_bit15: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } slc1_int_st; + union { + struct { + uint32_t frhost_bit8: 1; + uint32_t frhost_bit9: 1; + uint32_t frhost_bit10: 1; + uint32_t frhost_bit11: 1; + uint32_t frhost_bit12: 1; + uint32_t frhost_bit13: 1; + uint32_t frhost_bit14: 1; + uint32_t frhost_bit15: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } slc1_int_ena; + union { + struct { + uint32_t frhost_bit8: 1; + uint32_t frhost_bit9: 1; + uint32_t frhost_bit10: 1; + uint32_t frhost_bit11: 1; + uint32_t frhost_bit12: 1; + uint32_t frhost_bit13: 1; + uint32_t frhost_bit14: 1; + uint32_t frhost_bit15: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } slc1_int_clr; + union { + struct { + uint32_t slc0_rx_full: 1; + uint32_t slc0_rx_empty: 1; + uint32_t reserved2: 14; + uint32_t slc1_rx_full: 1; + uint32_t slc1_rx_empty: 1; + uint32_t reserved18:14; + }; + uint32_t val; + } rx_status; + union { + struct { + uint32_t rxfifo_wdata: 9; + uint32_t reserved9: 7; + uint32_t rxfifo_push: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } slc0_rxfifo_push; + union { + struct { + uint32_t rxfifo_wdata: 9; + uint32_t reserved9: 7; + uint32_t rxfifo_push: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } slc1_rxfifo_push; + union { + struct { + uint32_t slc0_tx_full: 1; + uint32_t slc0_tx_empty: 1; + uint32_t reserved2: 14; + uint32_t slc1_tx_full: 1; + uint32_t slc1_tx_empty: 1; + uint32_t reserved18:14; + }; + uint32_t val; + } tx_status; + union { + struct { + uint32_t txfifo_rdata: 11; + uint32_t reserved11: 5; + uint32_t txfifo_pop: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } slc0_txfifo_pop; + union { + struct { + uint32_t txfifo_rdata: 11; + uint32_t reserved11: 5; + uint32_t txfifo_pop: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } slc1_txfifo_pop; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } slc0_rx_link; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } slc0_tx_link; + union { + struct { + uint32_t addr: 20; + uint32_t bt_packet: 1; + uint32_t reserved21: 7; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } slc1_rx_link; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } slc1_tx_link; + union { + struct { + uint32_t slc0_intvec: 8; + uint32_t reserved8: 8; + uint32_t slc1_intvec: 8; + uint32_t reserved24: 8; + }; + uint32_t val; + } intvec_tohost; + union { + struct { + uint32_t wdata: 12; + uint32_t wr: 1; + uint32_t inc: 1; + uint32_t inc_more: 1; + uint32_t reserved15: 1; + uint32_t token0: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_token0; + union { + struct { + uint32_t wdata: 12; + uint32_t wr: 1; + uint32_t inc: 1; + uint32_t inc_more: 1; + uint32_t reserved15: 1; + uint32_t token1: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_token1; + union { + struct { + uint32_t wdata: 12; + uint32_t wr: 1; + uint32_t inc: 1; + uint32_t inc_more: 1; + uint32_t reserved15: 1; + uint32_t token0: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc1_token0; + union { + struct { + uint32_t wdata: 12; + uint32_t wr: 1; + uint32_t inc: 1; + uint32_t inc_more: 1; + uint32_t reserved15: 1; + uint32_t token1: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc1_token1; + union { + struct { + uint32_t slc0_check_owner: 1; + uint32_t slc0_tx_check_sum_en: 1; + uint32_t slc0_rx_check_sum_en: 1; + uint32_t cmd_hold_en: 1; + uint32_t slc0_len_auto_clr: 1; + uint32_t slc0_tx_stitch_en: 1; + uint32_t slc0_rx_stitch_en: 1; + uint32_t reserved7: 9; + uint32_t slc1_check_owner: 1; + uint32_t slc1_tx_check_sum_en: 1; + uint32_t slc1_rx_check_sum_en: 1; + uint32_t host_int_level_sel: 1; + uint32_t slc1_tx_stitch_en: 1; + uint32_t slc1_rx_stitch_en: 1; + uint32_t clk_en: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } conf1; + uint32_t slc0_state0; /**/ + uint32_t slc0_state1; /**/ + uint32_t slc1_state0; /**/ + uint32_t slc1_state1; /**/ + union { + struct { + uint32_t txeof_ena: 6; + uint32_t reserved6: 2; + uint32_t fifo_map_ena: 4; + uint32_t slc0_tx_dummy_mode: 1; + uint32_t hda_map_128k: 1; + uint32_t slc1_tx_dummy_mode: 1; + uint32_t reserved15: 1; + uint32_t tx_push_idle_num:16; + }; + uint32_t val; + } bridge_conf; + uint32_t slc0_to_eof_des_addr; /**/ + uint32_t slc0_tx_eof_des_addr; /**/ + uint32_t slc0_to_eof_bfr_des_addr; /**/ + uint32_t slc1_to_eof_des_addr; /**/ + uint32_t slc1_tx_eof_des_addr; /**/ + uint32_t slc1_to_eof_bfr_des_addr; /**/ + union { + struct { + uint32_t mode: 3; + uint32_t reserved3: 1; + uint32_t addr: 2; + uint32_t reserved6: 26; + }; + uint32_t val; + } ahb_test; + union { + struct { + uint32_t cmd_st: 3; + uint32_t reserved3: 1; + uint32_t func_st: 4; + uint32_t sdio_wakeup: 1; + uint32_t reserved9: 3; + uint32_t bus_st: 3; + uint32_t reserved15: 1; + uint32_t func1_acc_state: 5; + uint32_t reserved21: 3; + uint32_t func2_acc_state: 5; + uint32_t reserved29: 3; + }; + uint32_t val; + } sdio_st; + union { + struct { + uint32_t slc0_token_no_replace: 1; + uint32_t slc0_infor_no_replace: 1; + uint32_t slc0_rx_fill_mode: 1; + uint32_t slc0_rx_eof_mode: 1; + uint32_t slc0_rx_fill_en: 1; + uint32_t slc0_rd_retry_threshold:11; + uint32_t slc1_token_no_replace: 1; + uint32_t slc1_infor_no_replace: 1; + uint32_t slc1_rx_fill_mode: 1; + uint32_t slc1_rx_eof_mode: 1; + uint32_t slc1_rx_fill_en: 1; + uint32_t slc1_rd_retry_threshold:11; + }; + uint32_t val; + } rx_dscr_conf; + uint32_t slc0_txlink_dscr; /**/ + uint32_t slc0_txlink_dscr_bf0; /**/ + uint32_t slc0_txlink_dscr_bf1; /**/ + uint32_t slc0_rxlink_dscr; /**/ + uint32_t slc0_rxlink_dscr_bf0; /**/ + uint32_t slc0_rxlink_dscr_bf1; /**/ + uint32_t slc1_txlink_dscr; /**/ + uint32_t slc1_txlink_dscr_bf0; /**/ + uint32_t slc1_txlink_dscr_bf1; /**/ + uint32_t slc1_rxlink_dscr; /**/ + uint32_t slc1_rxlink_dscr_bf0; /**/ + uint32_t slc1_rxlink_dscr_bf1; /**/ + uint32_t slc0_tx_erreof_des_addr; /**/ + uint32_t slc1_tx_erreof_des_addr; /**/ + union { + struct { + uint32_t slc0_token:12; + uint32_t reserved12: 4; + uint32_t slc1_token:12; + uint32_t reserved28: 4; + }; + uint32_t val; + } token_lat; + union { + struct { + uint32_t wr_retry_threshold:11; + uint32_t reserved11: 21; + }; + uint32_t val; + } tx_dscr_conf; + uint32_t cmd_infor0; /**/ + uint32_t cmd_infor1; /**/ + union { + struct { + uint32_t len_wdata: 20; + uint32_t len_wr: 1; + uint32_t len_inc: 1; + uint32_t len_inc_more: 1; + uint32_t rx_packet_load_en: 1; + uint32_t tx_packet_load_en: 1; + uint32_t rx_get_used_dscr: 1; + uint32_t tx_get_used_dscr: 1; + uint32_t rx_new_pkt_ind: 1; + uint32_t tx_new_pkt_ind: 1; + uint32_t reserved29: 3; + }; + uint32_t val; + } slc0_len_conf; + union { + struct { + uint32_t len: 20; + uint32_t reserved20:12; + }; + uint32_t val; + } slc0_length; + uint32_t slc0_txpkt_h_dscr; /**/ + uint32_t slc0_txpkt_e_dscr; /**/ + uint32_t slc0_rxpkt_h_dscr; /**/ + uint32_t slc0_rxpkt_e_dscr; /**/ + uint32_t slc0_txpktu_h_dscr; /**/ + uint32_t slc0_txpktu_e_dscr; /**/ + uint32_t slc0_rxpktu_h_dscr; /**/ + uint32_t slc0_rxpktu_e_dscr; /**/ + uint32_t reserved_10c; + uint32_t reserved_110; + union { + struct { + uint32_t slc0_position: 8; + uint32_t slc1_position: 8; + uint32_t reserved16: 16; + }; + uint32_t val; + } seq_position; + union { + struct { + uint32_t rx_dscr_rec_lim: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } slc0_dscr_rec_conf; + union { + struct { + uint32_t dat0_crc_err_cnt: 8; + uint32_t dat1_crc_err_cnt: 8; + uint32_t dat2_crc_err_cnt: 8; + uint32_t dat3_crc_err_cnt: 8; + }; + uint32_t val; + } sdio_crc_st0; + union { + struct { + uint32_t cmd_crc_err_cnt: 8; + uint32_t reserved8: 23; + uint32_t err_cnt_clr: 1; + }; + uint32_t val; + } sdio_crc_st1; + uint32_t slc0_eof_start_des; /**/ + uint32_t slc0_push_dscr_addr; /**/ + uint32_t slc0_done_dscr_addr; /**/ + uint32_t slc0_sub_start_des; /**/ + union { + struct { + uint32_t rx_dscr_cnt_lat: 10; + uint32_t reserved10: 6; + uint32_t rx_get_eof_occ: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } slc0_dscr_cnt; + union { + struct { + uint32_t len_lim: 20; + uint32_t reserved20:12; + }; + uint32_t val; + } slc0_len_lim_conf; + union { + struct { + uint32_t frhost_bit01: 1; + uint32_t frhost_bit11: 1; + uint32_t frhost_bit21: 1; + uint32_t frhost_bit31: 1; + uint32_t frhost_bit41: 1; + uint32_t frhost_bit51: 1; + uint32_t frhost_bit61: 1; + uint32_t frhost_bit71: 1; + uint32_t rx_start1: 1; + uint32_t tx_start1: 1; + uint32_t rx_udf1: 1; + uint32_t tx_ovf1: 1; + uint32_t token0_1to01: 1; + uint32_t token1_1to01: 1; + uint32_t tx_done1: 1; + uint32_t tx_suc_eof1: 1; + uint32_t rx_done1: 1; + uint32_t rx_eof1: 1; + uint32_t tohost1: 1; + uint32_t tx_dscr_err1: 1; + uint32_t rx_dscr_err1: 1; + uint32_t tx_dscr_empty1: 1; + uint32_t host_rd_ack1: 1; + uint32_t wr_retry_done1: 1; + uint32_t tx_err_eof1: 1; + uint32_t cmd_dtc1: 1; + uint32_t rx_quick_eof1: 1; + uint32_t reserved27: 5; + }; + uint32_t val; + } slc0_int_st1; + union { + struct { + uint32_t frhost_bit01: 1; + uint32_t frhost_bit11: 1; + uint32_t frhost_bit21: 1; + uint32_t frhost_bit31: 1; + uint32_t frhost_bit41: 1; + uint32_t frhost_bit51: 1; + uint32_t frhost_bit61: 1; + uint32_t frhost_bit71: 1; + uint32_t rx_start1: 1; + uint32_t tx_start1: 1; + uint32_t rx_udf1: 1; + uint32_t tx_ovf1: 1; + uint32_t token0_1to01: 1; + uint32_t token1_1to01: 1; + uint32_t tx_done1: 1; + uint32_t tx_suc_eof1: 1; + uint32_t rx_done1: 1; + uint32_t rx_eof1: 1; + uint32_t tohost1: 1; + uint32_t tx_dscr_err1: 1; + uint32_t rx_dscr_err1: 1; + uint32_t tx_dscr_empty1: 1; + uint32_t host_rd_ack1: 1; + uint32_t wr_retry_done1: 1; + uint32_t tx_err_eof1: 1; + uint32_t cmd_dtc1: 1; + uint32_t rx_quick_eof1: 1; + uint32_t reserved27: 5; + }; + uint32_t val; + } slc0_int_ena1; + union { + struct { + uint32_t frhost_bit81: 1; + uint32_t frhost_bit91: 1; + uint32_t frhost_bit101: 1; + uint32_t frhost_bit111: 1; + uint32_t frhost_bit121: 1; + uint32_t frhost_bit131: 1; + uint32_t frhost_bit141: 1; + uint32_t frhost_bit151: 1; + uint32_t rx_start1: 1; + uint32_t tx_start1: 1; + uint32_t rx_udf1: 1; + uint32_t tx_ovf1: 1; + uint32_t token0_1to01: 1; + uint32_t token1_1to01: 1; + uint32_t tx_done1: 1; + uint32_t tx_suc_eof1: 1; + uint32_t rx_done1: 1; + uint32_t rx_eof1: 1; + uint32_t tohost1: 1; + uint32_t tx_dscr_err1: 1; + uint32_t rx_dscr_err1: 1; + uint32_t tx_dscr_empty1: 1; + uint32_t host_rd_ack1: 1; + uint32_t wr_retry_done1: 1; + uint32_t tx_err_eof1: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } slc1_int_st1; + union { + struct { + uint32_t frhost_bit81: 1; + uint32_t frhost_bit91: 1; + uint32_t frhost_bit101: 1; + uint32_t frhost_bit111: 1; + uint32_t frhost_bit121: 1; + uint32_t frhost_bit131: 1; + uint32_t frhost_bit141: 1; + uint32_t frhost_bit151: 1; + uint32_t rx_start1: 1; + uint32_t tx_start1: 1; + uint32_t rx_udf1: 1; + uint32_t tx_ovf1: 1; + uint32_t token0_1to01: 1; + uint32_t token1_1to01: 1; + uint32_t tx_done1: 1; + uint32_t tx_suc_eof1: 1; + uint32_t rx_done1: 1; + uint32_t rx_eof1: 1; + uint32_t tohost1: 1; + uint32_t tx_dscr_err1: 1; + uint32_t rx_dscr_err1: 1; + uint32_t tx_dscr_empty1: 1; + uint32_t host_rd_ack1: 1; + uint32_t wr_retry_done1: 1; + uint32_t tx_err_eof1: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } slc1_int_ena1; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t date; /**/ + uint32_t id; /**/ +} slc_dev_t; +extern slc_dev_t SLC; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_SLC_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/soc.h b/tools/sdk/include/soc/include/soc/soc.h new file mode 100644 index 00000000000..2aa3cc50205 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/soc.h @@ -0,0 +1,457 @@ +// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_SOC_H_ +#define _ESP32_SOC_H_ + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +//Register Bits{{ +#define BIT31 0x80000000 +#define BIT30 0x40000000 +#define BIT29 0x20000000 +#define BIT28 0x10000000 +#define BIT27 0x08000000 +#define BIT26 0x04000000 +#define BIT25 0x02000000 +#define BIT24 0x01000000 +#define BIT23 0x00800000 +#define BIT22 0x00400000 +#define BIT21 0x00200000 +#define BIT20 0x00100000 +#define BIT19 0x00080000 +#define BIT18 0x00040000 +#define BIT17 0x00020000 +#define BIT16 0x00010000 +#define BIT15 0x00008000 +#define BIT14 0x00004000 +#define BIT13 0x00002000 +#define BIT12 0x00001000 +#define BIT11 0x00000800 +#define BIT10 0x00000400 +#define BIT9 0x00000200 +#define BIT8 0x00000100 +#define BIT7 0x00000080 +#define BIT6 0x00000040 +#define BIT5 0x00000020 +#define BIT4 0x00000010 +#define BIT3 0x00000008 +#define BIT2 0x00000004 +#define BIT1 0x00000002 +#define BIT0 0x00000001 +//}} + +#define PRO_CPU_NUM (0) +#define APP_CPU_NUM (1) + +/* Overall memory map */ +#define SOC_IROM_LOW 0x400D0000 +#define SOC_IROM_HIGH 0x40400000 +#define SOC_DROM_LOW 0x3F400000 +#define SOC_DROM_HIGH 0x3F800000 +#define SOC_DRAM_LOW 0x3FAE0000 +#define SOC_DRAM_HIGH 0x40000000 +#define SOC_RTC_IRAM_LOW 0x400C0000 +#define SOC_RTC_IRAM_HIGH 0x400C2000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50002000 +#define SOC_EXTRAM_DATA_LOW 0x3F800000 +#define SOC_EXTRAM_DATA_HIGH 0x3FC00000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + + +#define DR_REG_DPORT_BASE 0x3ff00000 +#define DR_REG_AES_BASE 0x3ff01000 +#define DR_REG_RSA_BASE 0x3ff02000 +#define DR_REG_SHA_BASE 0x3ff03000 +#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000 +#define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000 +#define DR_REG_DPORT_END 0x3ff13FFC +#define DR_REG_UART_BASE 0x3ff40000 +#define DR_REG_SPI1_BASE 0x3ff42000 +#define DR_REG_SPI0_BASE 0x3ff43000 +#define DR_REG_GPIO_BASE 0x3ff44000 +#define DR_REG_GPIO_SD_BASE 0x3ff44f00 +#define DR_REG_FE2_BASE 0x3ff45000 +#define DR_REG_FE_BASE 0x3ff46000 +#define DR_REG_FRC_TIMER_BASE 0x3ff47000 +#define DR_REG_RTCCNTL_BASE 0x3ff48000 +#define DR_REG_RTCIO_BASE 0x3ff48400 +#define DR_REG_SENS_BASE 0x3ff48800 +#define DR_REG_RTC_I2C_BASE 0x3ff48C00 +#define DR_REG_IO_MUX_BASE 0x3ff49000 +#define DR_REG_HINF_BASE 0x3ff4B000 +#define DR_REG_UHCI1_BASE 0x3ff4C000 +#define DR_REG_I2S_BASE 0x3ff4F000 +#define DR_REG_UART1_BASE 0x3ff50000 +#define DR_REG_BT_BASE 0x3ff51000 +#define DR_REG_I2C_EXT_BASE 0x3ff53000 +#define DR_REG_UHCI0_BASE 0x3ff54000 +#define DR_REG_SLCHOST_BASE 0x3ff55000 +#define DR_REG_RMT_BASE 0x3ff56000 +#define DR_REG_PCNT_BASE 0x3ff57000 +#define DR_REG_SLC_BASE 0x3ff58000 +#define DR_REG_LEDC_BASE 0x3ff59000 +#define DR_REG_EFUSE_BASE 0x3ff5A000 +#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 +#define DR_REG_NRX_BASE 0x3ff5CC00 +#define DR_REG_BB_BASE 0x3ff5D000 +#define DR_REG_PWM_BASE 0x3ff5E000 +#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 +#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 +#define DR_REG_RTCMEM0_BASE 0x3ff61000 +#define DR_REG_RTCMEM1_BASE 0x3ff62000 +#define DR_REG_RTCMEM2_BASE 0x3ff63000 +#define DR_REG_SPI2_BASE 0x3ff64000 +#define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_SYSCON_BASE 0x3ff66000 +#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x3ff67000 +#define DR_REG_SDMMC_BASE 0x3ff68000 +#define DR_REG_EMAC_BASE 0x3ff69000 +#define DR_REG_CAN_BASE 0x3ff6B000 +#define DR_REG_PWM1_BASE 0x3ff6C000 +#define DR_REG_I2S1_BASE 0x3ff6D000 +#define DR_REG_UART2_BASE 0x3ff6E000 +#define DR_REG_PWM2_BASE 0x3ff6F000 +#define DR_REG_PWM3_BASE 0x3ff70000 +#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ +#define BIT(nr) (1UL << (nr)) +#define BIT64(nr) (1ULL << (nr)) +#else +#define BIT(nr) (1 << (nr)) +#endif + +#ifndef __ASSEMBLER__ + +#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) + +#if !defined( BOOTLOADER_BUILD ) && defined( CONFIG_ESP32_DPORT_WORKAROUND ) && defined( ESP_PLATFORM ) +#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP)); +#else +#define ASSERT_IF_DPORT_REG(_r, OP) +#endif + +//write value to register +#define REG_WRITE(_r, _v) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_WRITE); \ + (*(volatile uint32_t *)(_r)) = (_v); \ + }) + +//read value from register +#define REG_READ(_r) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_READ); \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \ + (*(volatile uint32_t*)(_r) |= (_b)); \ + }) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \ + (*(volatile uint32_t*)(_r) &= ~(_b)); \ + }) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \ + (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \ + }) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \ + (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \ + }) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) ({ \ + ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + }) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) ({ \ + ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + }) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) ({ \ + ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + }) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \ + ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \ + (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \ + }) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM ( 26*1000000 ) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz +#define REF_CLK_FREQ ( 1000000 ) +#define UART_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 26 // CPU is 80MHz +//}} + +/* Overall memory map */ +#define SOC_DROM_LOW 0x3F400000 +#define SOC_DROM_HIGH 0x3F800000 +#define SOC_IROM_LOW 0x400D0000 +#define SOC_IROM_HIGH 0x40400000 +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40070000 +#define SOC_CACHE_PRO_LOW 0x40070000 +#define SOC_CACHE_PRO_HIGH 0x40078000 +#define SOC_CACHE_APP_LOW 0x40078000 +#define SOC_CACHE_APP_HIGH 0x40080000 +#define SOC_IRAM_LOW 0x40080000 +#define SOC_IRAM_HIGH 0x400A0000 +#define SOC_RTC_IRAM_LOW 0x400C0000 +#define SOC_RTC_IRAM_HIGH 0x400C2000 +#define SOC_RTC_DRAM_LOW 0x3FF80000 +#define SOC_RTC_DRAM_HIGH 0x3FF82000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50002000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x400A0000 +#define SOC_DIRAM_IRAM_HIGH 0x400BFFFC +#define SOC_DIRAM_DRAM_LOW 0x3FFE0000 +#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x3FFAE000 +#define SOC_DMA_HIGH 0x40000000 + +// Region of memory that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x3FF90000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x3FF90000 +#define SOC_MEM_INTERNAL_HIGH 0x400C2000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x3ffe3f20 + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/ +#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ +#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/ +#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/ +#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/ +#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ +#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/ +#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/ +#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ +#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ +#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/ +#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/ +#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/ +#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/ +#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ +#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ +#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ +#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/ +#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ +#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ +#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ +#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/ +#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/ +#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/ +#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ +#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ +#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ +#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ +#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/ +#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ +#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/ +#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/ +#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/ +#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/ +#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/ +#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/ +#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/ +#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/ +#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/ +#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/ +#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/ +#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/ +#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/ +#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/ +#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/ +#define ETS_CAN_INTR_SOURCE 45/**< interrupt of can, level*/ +#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/ +#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/ +#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/ +#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/ +#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/ +#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/ +#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/ +#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/ +#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/ +#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/ +#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/ +#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/ +#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ +#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ +#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ +#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ +#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ +#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ +#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ +#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ +#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/ +#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/ +#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/ + +//interrupt cpu using table, Please see the core-isa.h +/************************************************************************************************************* + * Intr num Level Type PRO CPU usage APP CPU uasge + * 0 1 extern level WMAC Reserved + * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA + * 2 1 extern level + * 3 1 extern level + * 4 1 extern level WBB + * 5 1 extern level BT/BLE Controller BT/BLE Controller + * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) + * 7 1 software BT/BLE VHCI BT/BLE VHCI + * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) + * 9 1 extern level + * 10 1 extern edge + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved Reserved + * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level TG1_WDT + * 25 4 extern level CACHEERR + * 26 5 extern level + * 27 3 extern level Reserved Reserved + * 28 4 extern edge DPORT ACCESS DPORT ACCESS + * 29 3 software Reserved Reserved + * 30 4 extern edge Reserved Reserved + * 31 5 extern level + ************************************************************************************************************* + */ + +//CPU0 Interrupt number reserved, not touch this. +#define ETS_WMAC_INUM 0 +#define ETS_BT_HOST_INUM 1 +#define ETS_WBB_INUM 4 +#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ +#define ETS_FRC1_INUM 22 +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_DPORT_INUM 28 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 6 + +#endif /* _ESP32_SOC_H_ */ diff --git a/tools/sdk/include/soc/include/soc/soc_ulp.h b/tools/sdk/include/soc/include/soc/soc_ulp.h new file mode 100644 index 00000000000..e8c20d2b565 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/soc_ulp.h @@ -0,0 +1,46 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +// This file contains various convenience macros to be used in ULP programs. + +// Helper macros to calculate bit field width from mask, using the preprocessor. +// Used later in READ_RTC_FIELD and WRITE_RTC_FIELD. +#define IS_BIT_SET(m, i) (((m) >> (i)) & 1) +#define MASK_TO_WIDTH_HELPER1(m, i) IS_BIT_SET(m, i) +#define MASK_TO_WIDTH_HELPER2(m, i) (MASK_TO_WIDTH_HELPER1(m, i) + MASK_TO_WIDTH_HELPER1(m, i + 1)) +#define MASK_TO_WIDTH_HELPER4(m, i) (MASK_TO_WIDTH_HELPER2(m, i) + MASK_TO_WIDTH_HELPER2(m, i + 2)) +#define MASK_TO_WIDTH_HELPER8(m, i) (MASK_TO_WIDTH_HELPER4(m, i) + MASK_TO_WIDTH_HELPER4(m, i + 4)) +#define MASK_TO_WIDTH_HELPER16(m, i) (MASK_TO_WIDTH_HELPER8(m, i) + MASK_TO_WIDTH_HELPER8(m, i + 8)) +#define MASK_TO_WIDTH_HELPER32(m, i) (MASK_TO_WIDTH_HELPER16(m, i) + MASK_TO_WIDTH_HELPER16(m, i + 16)) + +// Peripheral register access macros, build around REG_RD and REG_WR instructions. +// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros. + +// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16 +#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \ + REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit) + +// Write immediate value into rtc_reg[low_bit + bit_width - 1 : low_bit], bit_width <= 8 +#define WRITE_RTC_REG(rtc_reg, low_bit, bit_width, value) \ + REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value) & 0xff) + +// Read from a field in rtc_reg into R0, up to 16 bits +#define READ_RTC_FIELD(rtc_reg, field) \ + READ_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER16(field ## _V, 0)) + +// Write immediate value into a field in rtc_reg, up to 8 bits +#define WRITE_RTC_FIELD(rtc_reg, field, value) \ + WRITE_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER8(field ## _V, 0), ((value) & field ## _V)) + diff --git a/tools/sdk/include/soc/include/soc/spi_pins.h b/tools/sdk/include/soc/include/soc/spi_pins.h new file mode 100644 index 00000000000..eb7af858273 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/spi_pins.h @@ -0,0 +1,39 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_SPI_PINS_H_ +#define _SOC_SPI_PINS_H_ + +#define SPI_IOMUX_PIN_NUM_MISO 7 +#define SPI_IOMUX_PIN_NUM_MOSI 8 +#define SPI_IOMUX_PIN_NUM_CLK 6 +#define SPI_IOMUX_PIN_NUM_CS 11 +#define SPI_IOMUX_PIN_NUM_WP 10 +#define SPI_IOMUX_PIN_NUM_HD 9 + +#define HSPI_IOMUX_PIN_NUM_MISO 12 +#define HSPI_IOMUX_PIN_NUM_MOSI 13 +#define HSPI_IOMUX_PIN_NUM_CLK 14 +#define HSPI_IOMUX_PIN_NUM_CS 15 +#define HSPI_IOMUX_PIN_NUM_WP 2 +#define HSPI_IOMUX_PIN_NUM_HD 4 + +#define VSPI_IOMUX_PIN_NUM_MISO 19 +#define VSPI_IOMUX_PIN_NUM_MOSI 23 +#define VSPI_IOMUX_PIN_NUM_CLK 18 +#define VSPI_IOMUX_PIN_NUM_CS 5 +#define VSPI_IOMUX_PIN_NUM_WP 22 +#define VSPI_IOMUX_PIN_NUM_HD 21 + +#endif /* _SOC_SPI_PINS_H_ */ \ No newline at end of file diff --git a/tools/sdk/include/soc/include/soc/spi_reg.h b/tools/sdk/include/soc/include/soc/spi_reg.h new file mode 100644 index 00000000000..fac2965c786 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/spi_reg.h @@ -0,0 +1,1713 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + + +#include "soc.h" +#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 ))) + +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) +/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_READ (BIT(31)) +#define SPI_FLASH_READ_M (BIT(31)) +#define SPI_FLASH_READ_V 0x1 +#define SPI_FLASH_READ_S 31 +/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the + bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_WREN (BIT(30)) +#define SPI_FLASH_WREN_M (BIT(30)) +#define SPI_FLASH_WREN_V 0x1 +#define SPI_FLASH_WREN_S 30 +/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_WRDI (BIT(29)) +#define SPI_FLASH_WRDI_M (BIT(29)) +#define SPI_FLASH_WRDI_V 0x1 +#define SPI_FLASH_WRDI_S 29 +/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is + set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_RDID (BIT(28)) +#define SPI_FLASH_RDID_M (BIT(28)) +#define SPI_FLASH_RDID_V 0x1 +#define SPI_FLASH_RDID_S 28 +/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_RDSR (BIT(27)) +#define SPI_FLASH_RDSR_M (BIT(27)) +#define SPI_FLASH_RDSR_V 0x1 +#define SPI_FLASH_RDSR_S 27 +/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_WRSR (BIT(26)) +#define SPI_FLASH_WRSR_M (BIT(26)) +#define SPI_FLASH_WRSR_V 0x1 +#define SPI_FLASH_WRSR_S 26 +/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~256 bytes data to be programmed). + Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ +#define SPI_FLASH_PP (BIT(25)) +#define SPI_FLASH_PP_M (BIT(25)) +#define SPI_FLASH_PP_V 0x1 +#define SPI_FLASH_PP_S 25 +/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_SE (BIT(24)) +#define SPI_FLASH_SE_M (BIT(24)) +#define SPI_FLASH_SE_V 0x1 +#define SPI_FLASH_SE_S 24 +/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_BE (BIT(23)) +#define SPI_FLASH_BE_M (BIT(23)) +#define SPI_FLASH_BE_V 0x1 +#define SPI_FLASH_BE_S 23 +/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_CE (BIT(22)) +#define SPI_FLASH_CE_M (BIT(22)) +#define SPI_FLASH_CE_V 0x1 +#define SPI_FLASH_CE_S 22 +/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_DP (BIT(21)) +#define SPI_FLASH_DP_M (BIT(21)) +#define SPI_FLASH_DP_V 0x1 +#define SPI_FLASH_DP_S 21 +/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with reg_resandres bit releases Flash from + the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_RES (BIT(20)) +#define SPI_FLASH_RES_M (BIT(20)) +#define SPI_FLASH_RES_V 0x1 +#define SPI_FLASH_RES_S 20 +/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared + once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_HPM (BIT(19)) +#define SPI_FLASH_HPM_M (BIT(19)) +#define SPI_FLASH_HPM_V 0x1 +#define SPI_FLASH_HPM_S 19 +/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: User define command enable. An operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_USR (BIT(18)) +#define SPI_USR_M (BIT(18)) +#define SPI_USR_V 0x1 +#define SPI_USR_S 18 +/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: program erase suspend bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_PES (BIT(17)) +#define SPI_FLASH_PES_M (BIT(17)) +#define SPI_FLASH_PES_V 0x1 +#define SPI_FLASH_PES_S 17 +/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: program erase resume bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_PER (BIT(16)) +#define SPI_FLASH_PER_M (BIT(16)) +#define SPI_FLASH_PER_V 0x1 +#define SPI_FLASH_PER_S 16 + +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) +//The CSV actually is wrong here. It indicates that the lower 8 bits of this register are reserved. This is not true, +//all 32 bits of SPI_ADDR_REG are usable/used. + +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (BIT(26)) +#define SPI_WR_BIT_ORDER_V 0x1 +#define SPI_WR_BIT_ORDER_S 26 +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/ +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (BIT(25)) +#define SPI_RD_BIT_ORDER_V 0x1 +#define SPI_RD_BIT_ORDER_S 25 +/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 4 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_QIO (BIT(24)) +#define SPI_FREAD_QIO_M (BIT(24)) +#define SPI_FREAD_QIO_V 0x1 +#define SPI_FREAD_QIO_S 24 +/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 2 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_DIO (BIT(23)) +#define SPI_FREAD_DIO_M (BIT(23)) +#define SPI_FREAD_DIO_V 0x1 +#define SPI_FREAD_DIO_S 23 +/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: two bytes data will be written to status register when it is + set. 1: enable 0: disable.*/ +#define SPI_WRSR_2B (BIT(22)) +#define SPI_WRSR_2B_M (BIT(22)) +#define SPI_WRSR_2B_V 0x1 +#define SPI_WRSR_2B_S 22 +/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ +#define SPI_WP_REG (BIT(21)) +#define SPI_WP_REG_M (BIT(21)) +#define SPI_WP_REG_V 0x1 +#define SPI_WP_REG_S 21 +/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_QUAD (BIT(20)) +#define SPI_FREAD_QUAD_M (BIT(20)) +#define SPI_FREAD_QUAD_V 0x1 +#define SPI_FREAD_QUAD_S 20 +/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: The Device ID is read out to SPI_RD_STATUS register, this bit + combine with spi_flash_res bit. 1: enable 0: disable.*/ +#define SPI_RESANDRES (BIT(15)) +#define SPI_RESANDRES_M (BIT(15)) +#define SPI_RESANDRES_V 0x1 +#define SPI_RESANDRES_S 15 +/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (BIT(14)) +#define SPI_FREAD_DUAL_V 0x1 +#define SPI_FREAD_DUAL_S 14 +/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout + and spi_fread_dout. 1: enable 0: disable.*/ +#define SPI_FASTRD_MODE (BIT(13)) +#define SPI_FASTRD_MODE_M (BIT(13)) +#define SPI_FASTRD_MODE_V 0x1 +#define SPI_FASTRD_MODE_S 13 +/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ +#define SPI_WAIT_FLASH_IDLE_EN (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_V 0x1 +#define SPI_WAIT_FLASH_IDLE_EN_S 12 +/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1 enable crc32 when writing encrypted data to flash. + 1: enable 0:disable*/ +#define SPI_TX_CRC_EN (BIT(11)) +#define SPI_TX_CRC_EN_M (BIT(11)) +#define SPI_TX_CRC_EN_V 0x1 +#define SPI_TX_CRC_EN_S 11 +/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: For SPI1 initialize crc32 module before writing encrypted data + to flash. Active low.*/ +#define SPI_FCS_CRC_EN (BIT(10)) +#define SPI_FCS_CRC_EN_M (BIT(10)) +#define SPI_FCS_CRC_EN_V 0x1 +#define SPI_FCS_CRC_EN_S 10 + +#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC) +/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */ +/*description: SPI cs signal is delayed by spi clock cycles*/ +#define SPI_CS_HOLD_DELAY 0x0000000F +#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) +#define SPI_CS_HOLD_DELAY_V 0xF +#define SPI_CS_HOLD_DELAY_S 28 +/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */ +/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ +#define SPI_CS_HOLD_DELAY_RES 0x00000FFF +#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S)) +#define SPI_CS_HOLD_DELAY_RES_V 0xFFF +#define SPI_CS_HOLD_DELAY_RES_S 16 + +#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10) +/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */ +/*description: In the slave mode,it is the status for master to read out.*/ +#define SPI_STATUS_EXT 0x000000FF +#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S)) +#define SPI_STATUS_EXT_V 0xFF +#define SPI_STATUS_EXT_S 24 +/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ +#define SPI_WB_MODE 0x000000FF +#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S)) +#define SPI_WB_MODE_V 0xFF +#define SPI_WB_MODE_S 16 +/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: In the slave mode, it is the status for master to read out.*/ +#define SPI_STATUS 0x0000FFFF +#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S)) +#define SPI_STATUS_V 0xFFFF +#define SPI_STATUS_S 0 + +#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14) +/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: spi_cs signal is delayed by system clock cycles*/ +#define SPI_CS_DELAY_NUM 0x0000000F +#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) +#define SPI_CS_DELAY_NUM_V 0xF +#define SPI_CS_DELAY_NUM_S 28 +/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ +/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_CS_DELAY_MODE 0x00000003 +#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) +#define SPI_CS_DELAY_MODE_V 0x3 +#define SPI_CS_DELAY_MODE_S 26 +/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */ +/*description: MOSI signals are delayed by system clock cycles*/ +#define SPI_MOSI_DELAY_NUM 0x00000007 +#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S)) +#define SPI_MOSI_DELAY_NUM_V 0x7 +#define SPI_MOSI_DELAY_NUM_S 23 +/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_MOSI_DELAY_MODE 0x00000003 +#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S)) +#define SPI_MOSI_DELAY_MODE_V 0x3 +#define SPI_MOSI_DELAY_MODE_S 21 +/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: MISO signals are delayed by system clock cycles*/ +#define SPI_MISO_DELAY_NUM 0x00000007 +#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S)) +#define SPI_MISO_DELAY_NUM_V 0x7 +#define SPI_MISO_DELAY_NUM_S 18 +/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_MISO_DELAY_MODE 0x00000003 +#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S)) +#define SPI_MISO_DELAY_MODE_V 0x3 +#define SPI_MISO_DELAY_MODE_S 16 +/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: modify spi clock duty ratio when the value is lager than 8, + the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ +#define SPI_CK_OUT_HIGH_MODE 0x0000000F +#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S)) +#define SPI_CK_OUT_HIGH_MODE_V 0xF +#define SPI_CK_OUT_HIGH_MODE_S 12 +/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: modify spi clock duty ratio when the value is lager than 8, + the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ +#define SPI_CK_OUT_LOW_MODE 0x0000000F +#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S)) +#define SPI_CK_OUT_LOW_MODE_V 0xF +#define SPI_CK_OUT_LOW_MODE_S 8 +/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */ +/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ +#define SPI_HOLD_TIME 0x0000000F +#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S)) +#define SPI_HOLD_TIME_V 0xF +#define SPI_HOLD_TIME_S 4 +/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */ +/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined + with spi_cs_setup bit.*/ +#define SPI_SETUP_TIME 0x0000000F +#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S)) +#define SPI_SETUP_TIME_V 0xF +#define SPI_SETUP_TIME_S 0 + +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18) +/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is + divided from system clock.*/ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_V 0x1 +#define SPI_CLK_EQU_SYSCLK_S 31 +/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ +/*description: In the master mode it is pre-divider of spi_clk.*/ +#define SPI_CLKDIV_PRE 0x00001FFF +#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) +#define SPI_CLKDIV_PRE_V 0x1FFF +#define SPI_CLKDIV_PRE_S 18 +/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ +/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency + is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) +#define SPI_CLKCNT_N_V 0x3F +#define SPI_CLKCNT_N_S 12 +/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ +/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In + the slave mode it must be 0.*/ +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) +#define SPI_CLKCNT_H_V 0x3F +#define SPI_CLKCNT_H_S 6 +/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ +/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave + mode it must be 0.*/ +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) +#define SPI_CLKCNT_L_V 0x3F +#define SPI_CLKCNT_L_S 0 + +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C) +/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation.*/ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (BIT(31)) +#define SPI_USR_COMMAND_V 0x1 +#define SPI_USR_COMMAND_S 31 +/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation.*/ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (BIT(30)) +#define SPI_USR_ADDR_V 0x1 +#define SPI_USR_ADDR_S 30 +/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation.*/ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (BIT(29)) +#define SPI_USR_DUMMY_V 0x1 +#define SPI_USR_DUMMY_S 29 +/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation.*/ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (BIT(28)) +#define SPI_USR_MISO_V 0x1 +#define SPI_USR_MISO_S 28 +/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation.*/ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (BIT(27)) +#define SPI_USR_MOSI_V 0x1 +#define SPI_USR_MOSI_S 27 +/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable.*/ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_USR_DUMMY_IDLE_V 0x1 +#define SPI_USR_DUMMY_IDLE_S 26 +/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable.*/ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_V 0x1 +#define SPI_USR_MOSI_HIGHPART_S 25 +/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable.*/ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_USR_MISO_HIGHPART_V 0x1 +#define SPI_USR_MISO_HIGHPART_S 24 +/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_PREP_HOLD (BIT(23)) +#define SPI_USR_PREP_HOLD_M (BIT(23)) +#define SPI_USR_PREP_HOLD_V 0x1 +#define SPI_USR_PREP_HOLD_S 23 +/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_CMD_HOLD (BIT(22)) +#define SPI_USR_CMD_HOLD_M (BIT(22)) +#define SPI_USR_CMD_HOLD_V 0x1 +#define SPI_USR_CMD_HOLD_S 22 +/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_ADDR_HOLD (BIT(21)) +#define SPI_USR_ADDR_HOLD_M (BIT(21)) +#define SPI_USR_ADDR_HOLD_V 0x1 +#define SPI_USR_ADDR_HOLD_S 21 +/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DUMMY_HOLD (BIT(20)) +#define SPI_USR_DUMMY_HOLD_M (BIT(20)) +#define SPI_USR_DUMMY_HOLD_V 0x1 +#define SPI_USR_DUMMY_HOLD_S 20 +/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DIN_HOLD (BIT(19)) +#define SPI_USR_DIN_HOLD_M (BIT(19)) +#define SPI_USR_DIN_HOLD_V 0x1 +#define SPI_USR_DIN_HOLD_S 19 +/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DOUT_HOLD (BIT(18)) +#define SPI_USR_DOUT_HOLD_M (BIT(18)) +#define SPI_USR_DOUT_HOLD_V 0x1 +#define SPI_USR_DOUT_HOLD_S 18 +/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: It is combined with hold bits to set the polarity of spi hold + line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ +#define SPI_USR_HOLD_POL (BIT(17)) +#define SPI_USR_HOLD_POL_M (BIT(17)) +#define SPI_USR_HOLD_POL_V 0x1 +#define SPI_USR_HOLD_POL_S 17 +/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set the bit to enable 3-line half duplex communication mosi + and miso signals share the same pin. 1: enable 0: disable.*/ +#define SPI_SIO (BIT(16)) +#define SPI_SIO_M (BIT(16)) +#define SPI_SIO_V 0x1 +#define SPI_SIO_S 16 +/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 4 signals.*/ +#define SPI_FWRITE_QIO (BIT(15)) +#define SPI_FWRITE_QIO_M (BIT(15)) +#define SPI_FWRITE_QIO_V 0x1 +#define SPI_FWRITE_QIO_S 15 +/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 2 signals.*/ +#define SPI_FWRITE_DIO (BIT(14)) +#define SPI_FWRITE_DIO_M (BIT(14)) +#define SPI_FWRITE_DIO_V 0x1 +#define SPI_FWRITE_DIO_S 14 +/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals*/ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (BIT(13)) +#define SPI_FWRITE_QUAD_V 0x1 +#define SPI_FWRITE_QUAD_S 13 +/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals*/ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (BIT(12)) +#define SPI_FWRITE_DUAL_V 0x1 +#define SPI_FWRITE_DUAL_S 12 +/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ +#define SPI_WR_BYTE_ORDER (BIT(11)) +#define SPI_WR_BYTE_ORDER_M (BIT(11)) +#define SPI_WR_BYTE_ORDER_V 0x1 +#define SPI_WR_BYTE_ORDER_S 11 +/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/ +#define SPI_RD_BYTE_ORDER (BIT(10)) +#define SPI_RD_BYTE_ORDER_M (BIT(10)) +#define SPI_RD_BYTE_ORDER_V 0x1 +#define SPI_RD_BYTE_ORDER_S 10 +/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ +#define SPI_CK_OUT_EDGE (BIT(7)) +#define SPI_CK_OUT_EDGE_M (BIT(7)) +#define SPI_CK_OUT_EDGE_V 0x1 +#define SPI_CK_OUT_EDGE_S 7 +/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: In the slave mode the bit is same as spi_ck_out_edge in master + mode. It is combined with spi_miso_delay_mode bits.*/ +#define SPI_CK_I_EDGE (BIT(6)) +#define SPI_CK_I_EDGE_M (BIT(6)) +#define SPI_CK_I_EDGE_V 0x1 +#define SPI_CK_I_EDGE_S 6 +/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/ +#define SPI_CS_SETUP (BIT(5)) +#define SPI_CS_SETUP_M (BIT(5)) +#define SPI_CS_SETUP_V 0x1 +#define SPI_CS_SETUP_S 5 +/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/ +#define SPI_CS_HOLD (BIT(4)) +#define SPI_CS_HOLD_M (BIT(4)) +#define SPI_CS_HOLD_V 0x1 +#define SPI_CS_HOLD_S 4 +/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (BIT(0)) +#define SPI_DOUTDIN_V 0x1 +#define SPI_DOUTDIN_S 0 + +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20) +/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ +#define SPI_USR_ADDR_BITLEN 0x0000003F +#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) +#define SPI_USR_ADDR_BITLEN_V 0x3F +#define SPI_USR_ADDR_BITLEN_S 26 +/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ +/*description: The length in spi_clk cycles of dummy phase. The register value + shall be (cycle_num-1).*/ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) +#define SPI_USR_DUMMY_CYCLELEN_V 0xFF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24) +/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) +#define SPI_USR_COMMAND_BITLEN_V 0xF +#define SPI_USR_COMMAND_BITLEN_S 28 +/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command.*/ +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) +#define SPI_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28) +/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/ +#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF +#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) +#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF +#define SPI_USR_MOSI_DBITLEN_S 0 + +#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C) +/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/ +#define SPI_USR_MISO_DBITLEN 0x00FFFFFF +#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) +#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF +#define SPI_USR_MISO_DBITLEN_S 0 + +#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30) +/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: In the slave mode this register are the status register for the + master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ +#define SPI_SLV_WR_ST 0xFFFFFFFF +#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S)) +#define SPI_SLV_WR_ST_V 0xFFFFFFFF +#define SPI_SLV_WR_ST_S 0 + +#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34) +/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: spi cs line keep low when the bit is set.*/ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_V 0x1 +#define SPI_CS_KEEP_ACTIVE_S 30 +/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (BIT(29)) +#define SPI_CK_IDLE_EDGE_V 0x1 +#define SPI_CK_IDLE_EDGE_S 29 +/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ +/*description: In the master mode spi cs line is enable as spi clk it is combined + with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ +#define SPI_MASTER_CK_SEL 0x00000007 +#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S)) +#define SPI_MASTER_CK_SEL_V 0x07 +#define SPI_MASTER_CK_SEL_S 11 +/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */ +/*description: In the master mode the bits are the polarity of spi cs line + the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ +#define SPI_MASTER_CS_POL 0x00000007 +#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) +#define SPI_MASTER_CS_POL_V 0x7 +#define SPI_MASTER_CS_POL_S 6 +/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: 1: spi clk out disable 0: spi clk out enable*/ +#define SPI_CK_DIS (BIT(5)) +#define SPI_CK_DIS_M (BIT(5)) +#define SPI_CK_DIS_V 0x1 +#define SPI_CK_DIS_S 5 +/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (BIT(2)) +#define SPI_CS2_DIS_V 0x1 +#define SPI_CS2_DIS_S 2 +/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (BIT(1)) +#define SPI_CS1_DIS_V 0x1 +#define SPI_CS1_DIS_S 1 +/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (BIT(0)) +#define SPI_CS0_DIS_V 0x1 +#define SPI_CS0_DIS_S 0 + +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38) +/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Software reset enable, reset the spi clock line cs line and data lines.*/ +#define SPI_SYNC_RESET (BIT(31)) +#define SPI_SYNC_RESET_M (BIT(31)) +#define SPI_SYNC_RESET_V 0x1 +#define SPI_SYNC_RESET_S 31 +/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 1: slave mode 0: master mode.*/ +#define SPI_SLAVE_MODE (BIT(30)) +#define SPI_SLAVE_MODE_M (BIT(30)) +#define SPI_SLAVE_MODE_V 0x1 +#define SPI_SLAVE_MODE_S 30 +/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: write and read buffer enable in the slave mode*/ +#define SPI_SLV_WR_RD_BUF_EN (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_V 0x1 +#define SPI_SLV_WR_RD_BUF_EN_S 29 +/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: write and read status enable in the slave mode*/ +#define SPI_SLV_WR_RD_STA_EN (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_M (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_V 0x1 +#define SPI_SLV_WR_RD_STA_EN_S 28 +/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode + commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ +#define SPI_SLV_CMD_DEFINE (BIT(27)) +#define SPI_SLV_CMD_DEFINE_M (BIT(27)) +#define SPI_SLV_CMD_DEFINE_V 0x1 +#define SPI_SLV_CMD_DEFINE_S 27 +/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */ +/*description: The operations counter in both the master mode and the slave + mode. 4: read-status*/ +#define SPI_TRANS_CNT 0x0000000F +#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) +#define SPI_TRANS_CNT_V 0xF +#define SPI_TRANS_CNT_S 23 +/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: In the slave mode it is the state of spi state machine.*/ +#define SPI_SLV_LAST_STATE 0x00000007 +#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S)) +#define SPI_SLV_LAST_STATE_V 0x7 +#define SPI_SLV_LAST_STATE_S 20 +/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */ +/*description: In the slave mode it is the value of command.*/ +#define SPI_SLV_LAST_COMMAND 0x00000007 +#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) +#define SPI_SLV_LAST_COMMAND_V 0x7 +#define SPI_SLV_LAST_COMMAND_S 17 +/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: In the slave mode this bits used to synchronize the input spi + cs signal and eliminate spi cs jitter.*/ +#define SPI_CS_I_MODE 0x00000003 +#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S)) +#define SPI_CS_I_MODE_V 0x3 +#define SPI_CS_I_MODE_S 10 +/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */ +/*description: Interrupt enable bits for the below 5 sources*/ +#define SPI_INT_EN 0x0000001F +#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S)) +#define SPI_INT_EN_V 0x1F +#define SPI_INT_EN_S 5 +/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of any operation in + both the master mode and the slave mode.*/ +#define SPI_TRANS_DONE (BIT(4)) +#define SPI_TRANS_DONE_M (BIT(4)) +#define SPI_TRANS_DONE_V 0x1 +#define SPI_TRANS_DONE_S 4 +/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of write-status operation + in the slave mode.*/ +#define SPI_SLV_WR_STA_DONE (BIT(3)) +#define SPI_SLV_WR_STA_DONE_M (BIT(3)) +#define SPI_SLV_WR_STA_DONE_V 0x1 +#define SPI_SLV_WR_STA_DONE_S 3 +/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of read-status operation + in the slave mode.*/ +#define SPI_SLV_RD_STA_DONE (BIT(2)) +#define SPI_SLV_RD_STA_DONE_M (BIT(2)) +#define SPI_SLV_RD_STA_DONE_V 0x1 +#define SPI_SLV_RD_STA_DONE_S 2 +/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of write-buffer operation + in the slave mode.*/ +#define SPI_SLV_WR_BUF_DONE (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_M (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_V 0x1 +#define SPI_SLV_WR_BUF_DONE_S 1 +/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of read-buffer operation + in the slave mode.*/ +#define SPI_SLV_RD_BUF_DONE (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_M (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_V 0x1 +#define SPI_SLV_RD_BUF_DONE_S 0 + +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C) +/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */ +/*description: In the slave mode it is the length of status bit.*/ +#define SPI_SLV_STATUS_BITLEN 0x0000001F +#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S)) +#define SPI_SLV_STATUS_BITLEN_V 0x1F +#define SPI_SLV_STATUS_BITLEN_S 27 +/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In the slave mode enable fast read status.*/ +#define SPI_SLV_STATUS_FAST_EN (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_M (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_V 0x1 +#define SPI_SLV_STATUS_FAST_EN_S 26 +/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read + register of SPI_RD_STATUS.*/ +#define SPI_SLV_STATUS_READBACK (BIT(25)) +#define SPI_SLV_STATUS_READBACK_M (BIT(25)) +#define SPI_SLV_STATUS_READBACK_V 0x1 +#define SPI_SLV_STATUS_READBACK_S 25 +/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: In the slave mode it is the address length in bits for read-buffer + operation. The register value shall be (bit_num-1).*/ +#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F +#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S)) +#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F +#define SPI_SLV_RD_ADDR_BITLEN_S 10 +/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */ +/*description: In the slave mode it is the address length in bits for write-buffer + operation. The register value shall be (bit_num-1).*/ +#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F +#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S)) +#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F +#define SPI_SLV_WR_ADDR_BITLEN_S 4 +/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for write-status + operations.*/ +#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_WRSTA_DUMMY_EN_S 3 +/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for read-status + operations.*/ +#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_RDSTA_DUMMY_EN_S 2 +/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for write-buffer + operations.*/ +#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_WRBUF_DUMMY_EN_S 1 +/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for read-buffer + operations.*/ +#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_RDBUF_DUMMY_EN_S 0 + +#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40) +/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for write-buffer operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 +/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for read-buffer operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 +/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for write-status operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8 +/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for read-status operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0 + +#define SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44) +/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of write-status command.*/ +#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S)) +#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_WRSTA_CMD_VALUE_S 24 +/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of read-status command.*/ +#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S)) +#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_RDSTA_CMD_VALUE_S 16 +/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of write-buffer command.*/ +#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S)) +#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_WRBUF_CMD_VALUE_S 8 +/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of read-buffer command.*/ +#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S)) +#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_RDBUF_CMD_VALUE_S 0 + +#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48) +/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: In the slave mode it is the length in bits for write-buffer operations. + The register value shall be (bit_num-1).*/ +#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S)) +#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_WRBUF_DBITLEN_S 0 + +#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C) +/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: In the slave mode it is the length in bits for read-buffer operations. + The register value shall be (bit_num-1).*/ +#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S)) +#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_RDBUF_DBITLEN_S 0 + +#define SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50) +/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 spi1 send suspend command before cache read flash + 1: enable 0:disable.*/ +#define SPI_CACHE_FLASH_PES_EN (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_M (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_V 0x1 +#define SPI_CACHE_FLASH_PES_EN_S 3 +/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/ +#define SPI_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_CACHE_FLASH_USR_CMD_S 2 +/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ +#define SPI_CACHE_USR_CMD_4BYTE (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_V 0x1 +#define SPI_CACHE_USR_CMD_4BYTE_S 1 +/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 Cache access enable 1: enable 0:disable.*/ +#define SPI_CACHE_REQ_EN (BIT(0)) +#define SPI_CACHE_REQ_EN_M (BIT(0)) +#define SPI_CACHE_REQ_EN_V 0x1 +#define SPI_CACHE_REQ_EN_S 0 + +#define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54) +/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache write sram for user define command*/ +#define SPI_CACHE_SRAM_USR_WCMD (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_WCMD_S 28 +/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of address + phase. The register value shall be (bit_num-1).*/ +#define SPI_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S)) +#define SPI_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_SRAM_ADDR_BITLEN_S 22 +/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of address + phase. The register value shall be (bit_num-1).*/ +#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF +#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S)) +#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF +#define SPI_SRAM_DUMMY_CYCLELEN_S 14 +/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */ +/*description: For SPI0 In the sram mode it is the byte length of spi read sram data.*/ +#define SPI_SRAM_BYTES_LEN 0x000000FF +#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S)) +#define SPI_SRAM_BYTES_LEN_V 0xFF +#define SPI_SRAM_BYTES_LEN_S 6 +/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/ +#define SPI_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_RCMD_S 5 +/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for read operations.*/ +#define SPI_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_USR_RD_SRAM_DUMMY_S 4 +/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for write operations.*/ +#define SPI_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_USR_WR_SRAM_DUMMY_S 3 +/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ +#define SPI_USR_SRAM_QIO (BIT(2)) +#define SPI_USR_SRAM_QIO_M (BIT(2)) +#define SPI_USR_SRAM_QIO_V 0x1 +#define SPI_USR_SRAM_QIO_S 2 +/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ +#define SPI_USR_SRAM_DIO (BIT(1)) +#define SPI_USR_SRAM_DIO_M (BIT(1)) +#define SPI_USR_SRAM_DIO_V 0x1 +#define SPI_USR_SRAM_DIO_S 1 + +#define SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58) +/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation + will be triggered when the bit is set. The bit will be cleared once the operation done*/ +#define SPI_SRAM_RSTIO (BIT(4)) +#define SPI_SRAM_RSTIO_M (BIT(4)) +#define SPI_SRAM_RSTIO_V 0x1 +#define SPI_SRAM_RSTIO_S 4 +/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will + be send when the bit is set. The bit will be cleared once the operation done.*/ +#define SPI_SRAM_QIO (BIT(1)) +#define SPI_SRAM_QIO_M (BIT(1)) +#define SPI_SRAM_QIO_V 0x1 +#define SPI_SRAM_QIO_S 1 +/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will + be send when the bit is set. The bit will be cleared once the operation done.*/ +#define SPI_SRAM_DIO (BIT(0)) +#define SPI_SRAM_DIO_M (BIT(0)) +#define SPI_SRAM_DIO_V 0x1 +#define SPI_SRAM_DIO_S 0 + +#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C) +/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the length in bits of + command phase for SRAM. The register value shall be (bit_num-1).*/ +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the read command value + of command phase for SRAM.*/ +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60) +/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the in bits of command + phase for SRAM. The register value shall be (bit_num-1).*/ +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the write command value + of command phase for SRAM.*/ +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64) +/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: In the slave mode it is the bit length of read data. The value + is the length - 1.*/ +#define SPI_SLV_RDATA_BIT 0x00FFFFFF +#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S)) +#define SPI_SLV_RDATA_BIT_V 0xFFFFFF +#define SPI_SLV_RDATA_BIT_S 0 + +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80) +/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84) +/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88) +/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C) +/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90) +/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94) +/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98) +/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C) +/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0) +/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4) +/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8) +/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC) +/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0) +/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4) +/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8) +/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC) +/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +#define SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0) +/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: For SPI1 the value of crc32 for 256 bits data.*/ +#define SPI_TX_CRC_DATA 0xFFFFFFFF +#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S)) +#define SPI_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_TX_CRC_DATA_S 0 + +#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0) +/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: page program delay enable.*/ +#define SPI_T_PP_ENA (BIT(31)) +#define SPI_T_PP_ENA_M (BIT(31)) +#define SPI_T_PP_ENA_V 0x1 +#define SPI_T_PP_ENA_S 31 +/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */ +/*description: page program delay time shift .*/ +#define SPI_T_PP_SHIFT 0x0000000F +#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S)) +#define SPI_T_PP_SHIFT_V 0xF +#define SPI_T_PP_SHIFT_S 16 +/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */ +/*description: page program delay time by system clock.*/ +#define SPI_T_PP_TIME 0x00000FFF +#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S)) +#define SPI_T_PP_TIME_V 0xFFF +#define SPI_T_PP_TIME_S 0 + +#define SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4) +/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: erase flash delay enable.*/ +#define SPI_T_ERASE_ENA (BIT(31)) +#define SPI_T_ERASE_ENA_M (BIT(31)) +#define SPI_T_ERASE_ENA_V 0x1 +#define SPI_T_ERASE_ENA_S 31 +/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */ +/*description: erase flash delay time shift.*/ +#define SPI_T_ERASE_SHIFT 0x0000000F +#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S)) +#define SPI_T_ERASE_SHIFT_V 0xF +#define SPI_T_ERASE_SHIFT_S 16 +/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */ +/*description: erase flash delay time by system clock.*/ +#define SPI_T_ERASE_TIME 0x00000FFF +#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S)) +#define SPI_T_ERASE_TIME_V 0xFFF +#define SPI_T_ERASE_TIME_S 0 + +#define SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8) +/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The status of spi state machine .*/ +#define SPI_ST 0x00000007 +#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) +#define SPI_ST_V 0x7 +#define SPI_ST_S 0 + +#define SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC) +/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: This register is for two SPI masters to share the same cs clock + and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/ +#define SPI_INT_HOLD_ENA 0x00000003 +#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) +#define SPI_INT_HOLD_ENA_V 0x3 +#define SPI_INT_HOLD_ENA_S 0 + +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100) +/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: spi dma continue tx/rx data.*/ +#define SPI_DMA_CONTINUE (BIT(16)) +#define SPI_DMA_CONTINUE_M (BIT(16)) +#define SPI_DMA_CONTINUE_V 0x1 +#define SPI_DMA_CONTINUE_S 16 +/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: spi dma write data stop when in continue tx/rx mode.*/ +#define SPI_DMA_TX_STOP (BIT(15)) +#define SPI_DMA_TX_STOP_M (BIT(15)) +#define SPI_DMA_TX_STOP_V 0x1 +#define SPI_DMA_TX_STOP_S 15 +/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: spi dma read data stop when in continue tx/rx mode.*/ +#define SPI_DMA_RX_STOP (BIT(14)) +#define SPI_DMA_RX_STOP_M (BIT(14)) +#define SPI_DMA_RX_STOP_V 0x1 +#define SPI_DMA_RX_STOP_S 14 +/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: spi dma read data from memory in burst mode.*/ +#define SPI_OUT_DATA_BURST_EN (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_M (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_V 0x1 +#define SPI_OUT_DATA_BURST_EN_S 12 +/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: read descriptor use burst mode when write data to memory.*/ +#define SPI_INDSCR_BURST_EN (BIT(11)) +#define SPI_INDSCR_BURST_EN_M (BIT(11)) +#define SPI_INDSCR_BURST_EN_V 0x1 +#define SPI_INDSCR_BURST_EN_S 11 +/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: read descriptor use burst mode when read data for memory.*/ +#define SPI_OUTDSCR_BURST_EN (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_M (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_V 0x1 +#define SPI_OUTDSCR_BURST_EN_S 10 +/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: out eof flag generation mode . 1: when dma pop all data from + fifo 0:when ahb push all data to fifo.*/ +#define SPI_OUT_EOF_MODE (BIT(9)) +#define SPI_OUT_EOF_MODE_M (BIT(9)) +#define SPI_OUT_EOF_MODE_V 0x1 +#define SPI_OUT_EOF_MODE_S 9 +/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: when the link is empty jump to next automatically.*/ +#define SPI_OUT_AUTO_WRBACK (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_M (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_V 0x1 +#define SPI_OUT_AUTO_WRBACK_S 8 +/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set bit to test out link.*/ +#define SPI_OUT_LOOP_TEST (BIT(7)) +#define SPI_OUT_LOOP_TEST_M (BIT(7)) +#define SPI_OUT_LOOP_TEST_V 0x1 +#define SPI_OUT_LOOP_TEST_S 7 +/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set bit to test in link.*/ +#define SPI_IN_LOOP_TEST (BIT(6)) +#define SPI_IN_LOOP_TEST_M (BIT(6)) +#define SPI_IN_LOOP_TEST_V 0x1 +#define SPI_IN_LOOP_TEST_S 6 +/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: reset spi dma ahb master.*/ +#define SPI_AHBM_RST (BIT(5)) +#define SPI_AHBM_RST_M (BIT(5)) +#define SPI_AHBM_RST_V 0x1 +#define SPI_AHBM_RST_S 5 +/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: reset spi dma ahb master fifo pointer.*/ +#define SPI_AHBM_FIFO_RST (BIT(4)) +#define SPI_AHBM_FIFO_RST_M (BIT(4)) +#define SPI_AHBM_FIFO_RST_V 0x1 +#define SPI_AHBM_FIFO_RST_S 4 +/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/ +#define SPI_OUT_RST (BIT(3)) +#define SPI_OUT_RST_M (BIT(3)) +#define SPI_OUT_RST_V 0x1 +#define SPI_OUT_RST_S 3 +/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/ +#define SPI_IN_RST (BIT(2)) +#define SPI_IN_RST_M (BIT(2)) +#define SPI_IN_RST_V 0x1 +#define SPI_IN_RST_S 2 + +#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104) +/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set the bit to mount on new outlink descriptors.*/ +#define SPI_OUTLINK_RESTART (BIT(30)) +#define SPI_OUTLINK_RESTART_M (BIT(30)) +#define SPI_OUTLINK_RESTART_V 0x1 +#define SPI_OUTLINK_RESTART_S 30 +/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set the bit to start to use outlink descriptor.*/ +#define SPI_OUTLINK_START (BIT(29)) +#define SPI_OUTLINK_START_M (BIT(29)) +#define SPI_OUTLINK_START_V 0x1 +#define SPI_OUTLINK_START_S 29 +/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set the bit to stop to use outlink descriptor.*/ +#define SPI_OUTLINK_STOP (BIT(28)) +#define SPI_OUTLINK_STOP_M (BIT(28)) +#define SPI_OUTLINK_STOP_V 0x1 +#define SPI_OUTLINK_STOP_S 28 +/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The address of the first outlink descriptor.*/ +#define SPI_OUTLINK_ADDR 0x000FFFFF +#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S)) +#define SPI_OUTLINK_ADDR_V 0xFFFFF +#define SPI_OUTLINK_ADDR_S 0 + +#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108) +/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set the bit to mount on new inlink descriptors.*/ +#define SPI_INLINK_RESTART (BIT(30)) +#define SPI_INLINK_RESTART_M (BIT(30)) +#define SPI_INLINK_RESTART_V 0x1 +#define SPI_INLINK_RESTART_S 30 +/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set the bit to start to use inlink descriptor.*/ +#define SPI_INLINK_START (BIT(29)) +#define SPI_INLINK_START_M (BIT(29)) +#define SPI_INLINK_START_V 0x1 +#define SPI_INLINK_START_S 29 +/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set the bit to stop to use inlink descriptor.*/ +#define SPI_INLINK_STOP (BIT(28)) +#define SPI_INLINK_STOP_M (BIT(28)) +#define SPI_INLINK_STOP_V 0x1 +#define SPI_INLINK_STOP_S 28 +/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: when the bit is set inlink descriptor returns to the next descriptor + while a packet is wrong*/ +#define SPI_INLINK_AUTO_RET (BIT(20)) +#define SPI_INLINK_AUTO_RET_M (BIT(20)) +#define SPI_INLINK_AUTO_RET_V 0x1 +#define SPI_INLINK_AUTO_RET_S 20 +/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The address of the first inlink descriptor.*/ +#define SPI_INLINK_ADDR 0x000FFFFF +#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S)) +#define SPI_INLINK_ADDR_V 0xFFFFF +#define SPI_INLINK_ADDR_S 0 + +#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C) +/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: spi dma write data status bit.*/ +#define SPI_DMA_TX_EN (BIT(1)) +#define SPI_DMA_TX_EN_M (BIT(1)) +#define SPI_DMA_TX_EN_V 0x1 +#define SPI_DMA_TX_EN_S 1 +/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: spi dma read data status bit.*/ +#define SPI_DMA_RX_EN (BIT(0)) +#define SPI_DMA_RX_EN_M (BIT(0)) +#define SPI_DMA_RX_EN_V 0x1 +#define SPI_DMA_RX_EN_S 0 + +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110) +/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 +/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_ENA (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_M (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_V 0x1 +#define SPI_OUT_EOF_INT_ENA_S 7 +/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for completing usage of a outlink descriptor .*/ +#define SPI_OUT_DONE_INT_ENA (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_M (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_V 0x1 +#define SPI_OUT_DONE_INT_ENA_S 6 +/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_V 0x1 +#define SPI_IN_SUC_EOF_INT_ENA_S 5 +/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_V 0x1 +#define SPI_IN_ERR_EOF_INT_ENA_S 4 +/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_ENA (BIT(3)) +#define SPI_IN_DONE_INT_ENA_M (BIT(3)) +#define SPI_IN_DONE_INT_ENA_V 0x1 +#define SPI_IN_DONE_INT_ENA_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 + +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114) +/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 +/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_RAW (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_M (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_V 0x1 +#define SPI_OUT_EOF_INT_RAW_S 7 +/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_RAW (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_M (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_V 0x1 +#define SPI_OUT_DONE_INT_RAW_S 6 +/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_V 0x1 +#define SPI_IN_SUC_EOF_INT_RAW_S 5 +/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_V 0x1 +#define SPI_IN_ERR_EOF_INT_RAW_S 4 +/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_RAW (BIT(3)) +#define SPI_IN_DONE_INT_RAW_M (BIT(3)) +#define SPI_IN_DONE_INT_RAW_V 0x1 +#define SPI_IN_DONE_INT_RAW_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 + +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118) +/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The status bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ST_S 8 +/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The status bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_ST (BIT(7)) +#define SPI_OUT_EOF_INT_ST_M (BIT(7)) +#define SPI_OUT_EOF_INT_ST_V 0x1 +#define SPI_OUT_EOF_INT_ST_S 7 +/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_ST (BIT(6)) +#define SPI_OUT_DONE_INT_ST_M (BIT(6)) +#define SPI_OUT_DONE_INT_ST_V 0x1 +#define SPI_OUT_DONE_INT_ST_S 6 +/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_ST (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_V 0x1 +#define SPI_IN_SUC_EOF_INT_ST_S 5 +/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_ST (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_V 0x1 +#define SPI_IN_ERR_EOF_INT_ST_S 4 +/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_ST (BIT(3)) +#define SPI_IN_DONE_INT_ST_M (BIT(3)) +#define SPI_IN_DONE_INT_ST_V 0x1 +#define SPI_IN_DONE_INT_ST_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 + +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C) +/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 +/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_CLR (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_M (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_V 0x1 +#define SPI_OUT_EOF_INT_CLR_S 7 +/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_CLR (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_M (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_V 0x1 +#define SPI_OUT_DONE_INT_CLR_S 6 +/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_V 0x1 +#define SPI_IN_SUC_EOF_INT_CLR_S 5 +/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_V 0x1 +#define SPI_IN_ERR_EOF_INT_CLR_S 4 +/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_CLR (BIT(3)) +#define SPI_IN_DONE_INT_CLR_M (BIT(3)) +#define SPI_IN_DONE_INT_CLR_V 0x1 +#define SPI_IN_DONE_INT_CLR_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 + +#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120) +/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The inlink descriptor address when spi dma produce receiving error.*/ +#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 + +#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124) +/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/ +#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 + +#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128) +/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in descriptor pointer.*/ +#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S)) +#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_S 0 + +#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C) +/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of next in descriptor pointer.*/ +#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S)) +#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_S 0 + +#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130) +/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in descriptor data buffer pointer.*/ +#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S)) +#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_S 0 + +#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134) +/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of buffer relative to the outlink descriptor that produce eof.*/ +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 + +#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138) +/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The last outlink descriptor address when spi dma produce to_eof.*/ +#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_S 0 + +#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C) +/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out descriptor pointer.*/ +#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S)) +#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_S 0 + +#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140) +/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of next out descriptor pointer.*/ +#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S)) +#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_S 0 + +#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144) +/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out descriptor data buffer pointer.*/ +#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S)) +#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_S 0 + +#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148) +/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: spi dma read data from memory status.*/ +#define SPI_DMA_OUT_STATUS 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S)) +#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_S 0 + +#define SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C) +/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: spi dma write data to memory status.*/ +#define SPI_DMA_IN_STATUS 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S)) +#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_S 0 + +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC) +/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */ +/*description: SPI register version.*/ +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) +#define SPI_DATE_V 0xFFFFFFF +#define SPI_DATE_S 0 + + + + +#endif /*__SPI_REG_H__ */ + + diff --git a/tools/sdk/include/soc/include/soc/spi_struct.h b/tools/sdk/include/soc/include/soc/spi_struct.h new file mode 100644 index 00000000000..3e36c81c905 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/spi_struct.h @@ -0,0 +1,688 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SPI_STRUCT_H_ +#define _SOC_SPI_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t reserved0: 16; /*reserved*/ + uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ + uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + }; + uint32_t val; + } cmd; + uint32_t addr; /*addr to slave / from master. SPI transfer from the MSB to the LSB. If length > 32 bits, then address continues from MSB of slv_wr_status.*/ + union { + struct { + uint32_t reserved0: 10; /*reserved*/ + uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t wait_flash_idle_en: 1; /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ + uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/ + uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t resandres: 1; /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/ + uint32_t reserved16: 4; /*reserved*/ + uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ + uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ + uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/ + uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ + uint32_t reserved27: 5; /*reserved*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t reserved0: 16; /*reserved*/ + uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ + uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/ + }; + uint32_t val; + } ctrl1; + union { + struct { + uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/ + uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ + uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/ + }; + uint32_t val; + } rd_status; + union { + struct { + uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/ + uint32_t hold_time: 4; /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ + uint32_t ck_out_low_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ + uint32_t ck_out_high_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ + uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/ + uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/ + uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/ + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/ + uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/ + uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ + uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/ + uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/ + uint32_t reserved1: 3; /*reserved*/ + uint32_t cs_hold: 1; /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/ + uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/ + uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/ + uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ + uint32_t reserved8: 2; /*reserved*/ + uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/ + uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ + uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ + uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ + uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/ + uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ + uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/ + uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/ + uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ + uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/ + uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + uint32_t reserved8: 18; /*reserved*/ + uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value: 16; /*The value of command. Output sequence: bit 7-0 and then 15-8.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + uint32_t val; + } user2; + union { + struct { + uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } mosi_dlen; + union { + struct { + uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } miso_dlen; + uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ + union { + struct { + uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ + uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ + uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ + uint32_t reserved3: 2; /*reserved*/ + uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/ + uint32_t master_cs_pol: 3; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ + uint32_t reserved9: 2; /*reserved*/ + uint32_t master_ck_sel: 3; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ + uint32_t reserved14: 15; /*reserved*/ + uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ + uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } pin; + union { + struct { + uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/ + uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/ + uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/ + uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/ + uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ + uint32_t rd_buf_inten: 1; /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/ + uint32_t wr_buf_inten: 1; /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/ + uint32_t rd_sta_inten: 1; /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/ + uint32_t wr_sta_inten: 1; /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/ + uint32_t trans_inten: 1; /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/ + uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/ + uint32_t reserved12: 5; /*reserved*/ + uint32_t last_command: 3; /*In the slave mode it is the value of command.*/ + uint32_t last_state: 3; /*In the slave mode it is the state of spi state machine.*/ + uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/ + uint32_t cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ + uint32_t wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/ + uint32_t wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/ + uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/ + uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/ + }; + uint32_t val; + } slave; + union { + struct { + uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/ + uint32_t wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/ + uint32_t rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/ + uint32_t wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/ + uint32_t wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/ + uint32_t rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/ + uint32_t reserved16: 9; /*reserved*/ + uint32_t status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/ + uint32_t status_fast_en: 1; /*In the slave mode enable fast read status.*/ + uint32_t status_bitlen: 5; /*In the slave mode it is the length of status bit.*/ + }; + uint32_t val; + } slave1; + union { + struct { + uint32_t rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/ + uint32_t wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/ + uint32_t rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/ + uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/ + }; + uint32_t val; + } slave2; + union { + struct { + uint32_t rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/ + uint32_t wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/ + uint32_t rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/ + uint32_t wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/ + }; + uint32_t val; + } slave3; + union { + struct { + uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } slv_wrbuf_dlen; + union { + struct { + uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } slv_rdbuf_dlen; + union { + struct { + uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ + uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ + uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ + uint32_t flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/ + uint32_t reserved4: 28; /*reserved*/ + }; + uint32_t val; + } cache_fctrl; + union { + struct { + uint32_t reserved0: 1; /*reserved*/ + uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ + uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ + uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/ + uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/ + uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/ + uint32_t sram_bytes_len: 8; /*For SPI0 In the sram mode it is the byte length of spi read sram data.*/ + uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ + uint32_t reserved29: 3; /*reserved*/ + }; + uint32_t val; + } cache_sctrl; + union { + struct { + uint32_t dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t rst_io: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/ + uint32_t reserved5:27; /*reserved*/ + }; + uint32_t val; + } sram_cmd; + union { + struct { + uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_drd_cmd; + union { + struct { + uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_dwr_cmd; + union { + struct { + uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } slv_rd_bit; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t data_buf[16]; /*data buffer*/ + uint32_t tx_crc; /*For SPI1 the value of crc32 for 256 bits data.*/ + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + union { + struct { + uint32_t t_pp_time: 12; /*page program delay time by system clock.*/ + uint32_t reserved12: 4; /*reserved*/ + uint32_t t_pp_shift: 4; /*page program delay time shift .*/ + uint32_t reserved20:11; /*reserved*/ + uint32_t t_pp_ena: 1; /*page program delay enable.*/ + }; + uint32_t val; + } ext0; + union { + struct { + uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/ + uint32_t reserved12: 4; /*reserved*/ + uint32_t t_erase_shift: 4; /*erase flash delay time shift.*/ + uint32_t reserved20: 11; /*reserved*/ + uint32_t t_erase_ena: 1; /*erase flash delay enable.*/ + }; + uint32_t val; + } ext1; + union { + struct { + uint32_t st: 3; /*The status of spi state machine .*/ + uint32_t reserved3: 29; /*reserved*/ + }; + uint32_t val; + } ext2; + union { + struct { + uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/ + uint32_t reserved2: 30; /*reserved*/ + }; + uint32_t val; + } ext3; + union { + struct { + uint32_t reserved0: 2; /*reserved*/ + uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ + uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ + uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/ + uint32_t ahbm_rst: 1; /*reset spi dma ahb master.*/ + uint32_t in_loop_test: 1; /*Set bit to test in link.*/ + uint32_t out_loop_test: 1; /*Set bit to test out link.*/ + uint32_t out_auto_wrback: 1; /*when the link is empty jump to next automatically.*/ + uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ + uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ + uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ + uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ + uint32_t reserved13: 1; /*reserved*/ + uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ + uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ + uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ + uint32_t reserved17: 15; /*reserved*/ + }; + uint32_t val; + } dma_conf; + union { + struct { + uint32_t addr: 20; /*The address of the first outlink descriptor.*/ + uint32_t reserved20: 8; /*reserved*/ + uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/ + uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/ + uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } dma_out_link; + union { + struct { + uint32_t addr: 20; /*The address of the first inlink descriptor.*/ + uint32_t auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/ + uint32_t reserved21: 7; /*reserved*/ + uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/ + uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/ + uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } dma_in_link; + union { + struct { + uint32_t rx_en: 1; /*spi dma read data status bit.*/ + uint32_t tx_en: 1; /*spi dma write data status bit.*/ + uint32_t reserved2: 30; /*spi dma read data from memory count.*/ + }; + uint32_t val; + } dma_status; + union { + struct { + uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/ + uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dma_int_ena; + union { + struct { + uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dma_int_raw; + union { + struct { + uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The status bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dma_int_st; + union { + struct { + uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dma_int_clr; + uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/ + uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/ + uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/ + uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/ + uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/ + uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/ + uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/ + uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/ + uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/ + uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/ + uint32_t dma_rx_status; /*spi dma read data from memory status.*/ + uint32_t dma_tx_status; /*spi dma write data to memory status.*/ + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + union { + struct { + uint32_t date: 28; /*SPI register version.*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } date; +} spi_dev_t; +extern spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/ +extern spi_dev_t SPI1; +extern spi_dev_t SPI2; +extern spi_dev_t SPI3; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_SPI_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/syscon_reg.h b/tools/sdk/include/soc/include/soc/syscon_reg.h new file mode 100644 index 00000000000..5012b27e573 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/syscon_reg.h @@ -0,0 +1,294 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SYSCON_REG_H_ +#define _SOC_SYSCON_REG_H_ + +#include "soc.h" +#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0) +/* SYSCON_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_QUICK_CLK_CHNG (BIT(13)) +#define SYSCON_QUICK_CLK_CHNG_M (BIT(13)) +#define SYSCON_QUICK_CLK_CHNG_V 0x1 +#define SYSCON_QUICK_CLK_CHNG_S 13 +/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_RST_TICK_CNT (BIT(12)) +#define SYSCON_RST_TICK_CNT_M (BIT(12)) +#define SYSCON_RST_TICK_CNT_V 0x1 +#define SYSCON_RST_TICK_CNT_S 12 +/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_CLK_EN (BIT(11)) +#define SYSCON_CLK_EN_M (BIT(11)) +#define SYSCON_CLK_EN_V 0x1 +#define SYSCON_CLK_EN_S 11 +/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_CLK_320M_EN (BIT(10)) +#define SYSCON_CLK_320M_EN_M (BIT(10)) +#define SYSCON_CLK_320M_EN_V 0x1 +#define SYSCON_CLK_320M_EN_S 10 +/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define SYSCON_PRE_DIV_CNT 0x000003FF +#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) +#define SYSCON_PRE_DIV_CNT_V 0x3FF +#define SYSCON_PRE_DIV_CNT_S 0 + +#define SYSCON_XTAL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4) +/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ +/*description: */ +#define SYSCON_XTAL_TICK_NUM 0x000000FF +#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) +#define SYSCON_XTAL_TICK_NUM_V 0xFF +#define SYSCON_XTAL_TICK_NUM_S 0 + +#define SYSCON_PLL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x8) +/* SYSCON_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */ +/*description: */ +#define SYSCON_PLL_TICK_NUM 0x000000FF +#define SYSCON_PLL_TICK_NUM_M ((SYSCON_PLL_TICK_NUM_V)<<(SYSCON_PLL_TICK_NUM_S)) +#define SYSCON_PLL_TICK_NUM_V 0xFF +#define SYSCON_PLL_TICK_NUM_S 0 + +#define SYSCON_CK8M_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0xC) +/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */ +/*description: */ +#define SYSCON_CK8M_TICK_NUM 0x000000FF +#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) +#define SYSCON_CK8M_TICK_NUM_V 0xFF +#define SYSCON_CK8M_TICK_NUM_S 0 + +#define SYSCON_SARADC_CTRL_REG (DR_REG_SYSCON_BASE + 0x10) +/* SYSCON_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data + is from GPIO matrix*/ +#define SYSCON_SARADC_DATA_TO_I2S (BIT(26)) +#define SYSCON_SARADC_DATA_TO_I2S_M (BIT(26)) +#define SYSCON_SARADC_DATA_TO_I2S_V 0x1 +#define SYSCON_SARADC_DATA_TO_I2S_S 26 +/* SYSCON_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data + in this case the resolution should not be larger than 11 bits.*/ +#define SYSCON_SARADC_DATA_SAR_SEL (BIT(25)) +#define SYSCON_SARADC_DATA_SAR_SEL_M (BIT(25)) +#define SYSCON_SARADC_DATA_SAR_SEL_V 0x1 +#define SYSCON_SARADC_DATA_SAR_SEL_S 25 +/* SYSCON_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ +#define SYSCON_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) +#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_V 0x1 +#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_S 24 +/* SYSCON_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ +#define SYSCON_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) +#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_V 0x1 +#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_S 23 +/* SYSCON_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define SYSCON_SARADC_SAR2_PATT_LEN 0x0000000F +#define SYSCON_SARADC_SAR2_PATT_LEN_M ((SYSCON_SARADC_SAR2_PATT_LEN_V)<<(SYSCON_SARADC_SAR2_PATT_LEN_S)) +#define SYSCON_SARADC_SAR2_PATT_LEN_V 0xF +#define SYSCON_SARADC_SAR2_PATT_LEN_S 19 +/* SYSCON_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define SYSCON_SARADC_SAR1_PATT_LEN 0x0000000F +#define SYSCON_SARADC_SAR1_PATT_LEN_M ((SYSCON_SARADC_SAR1_PATT_LEN_V)<<(SYSCON_SARADC_SAR1_PATT_LEN_S)) +#define SYSCON_SARADC_SAR1_PATT_LEN_V 0xF +#define SYSCON_SARADC_SAR1_PATT_LEN_S 15 +/* SYSCON_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ +/*description: SAR clock divider*/ +#define SYSCON_SARADC_SAR_CLK_DIV 0x000000FF +#define SYSCON_SARADC_SAR_CLK_DIV_M ((SYSCON_SARADC_SAR_CLK_DIV_V)<<(SYSCON_SARADC_SAR_CLK_DIV_S)) +#define SYSCON_SARADC_SAR_CLK_DIV_V 0xFF +#define SYSCON_SARADC_SAR_CLK_DIV_S 7 +/* SYSCON_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_SARADC_SAR_CLK_GATED (BIT(6)) +#define SYSCON_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define SYSCON_SARADC_SAR_CLK_GATED_V 0x1 +#define SYSCON_SARADC_SAR_CLK_GATED_S 6 +/* SYSCON_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ +#define SYSCON_SARADC_SAR_SEL (BIT(5)) +#define SYSCON_SARADC_SAR_SEL_M (BIT(5)) +#define SYSCON_SARADC_SAR_SEL_V 0x1 +#define SYSCON_SARADC_SAR_SEL_S 5 +/* SYSCON_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: single mode 1: double mode 2: alternate mode*/ +#define SYSCON_SARADC_WORK_MODE 0x00000003 +#define SYSCON_SARADC_WORK_MODE_M ((SYSCON_SARADC_WORK_MODE_V)<<(SYSCON_SARADC_WORK_MODE_S)) +#define SYSCON_SARADC_WORK_MODE_V 0x3 +#define SYSCON_SARADC_WORK_MODE_S 3 +/* SYSCON_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled + by PWDET CTRL*/ +#define SYSCON_SARADC_SAR2_MUX (BIT(2)) +#define SYSCON_SARADC_SAR2_MUX_M (BIT(2)) +#define SYSCON_SARADC_SAR2_MUX_V 0x1 +#define SYSCON_SARADC_SAR2_MUX_S 2 +/* SYSCON_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_SARADC_START (BIT(1)) +#define SYSCON_SARADC_START_M (BIT(1)) +#define SYSCON_SARADC_START_V 0x1 +#define SYSCON_SARADC_START_S 1 +/* SYSCON_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_SARADC_START_FORCE (BIT(0)) +#define SYSCON_SARADC_START_FORCE_M (BIT(0)) +#define SYSCON_SARADC_START_FORCE_V 0x1 +#define SYSCON_SARADC_START_FORCE_S 0 + +#define SYSCON_SARADC_CTRL2_REG (DR_REG_SYSCON_BASE + 0x14) +/* SYSCON_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ +#define SYSCON_SARADC_SAR2_INV (BIT(10)) +#define SYSCON_SARADC_SAR2_INV_M (BIT(10)) +#define SYSCON_SARADC_SAR2_INV_V 0x1 +#define SYSCON_SARADC_SAR2_INV_S 10 +/* SYSCON_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ +#define SYSCON_SARADC_SAR1_INV (BIT(9)) +#define SYSCON_SARADC_SAR1_INV_M (BIT(9)) +#define SYSCON_SARADC_SAR1_INV_V 0x1 +#define SYSCON_SARADC_SAR1_INV_S 9 +/* SYSCON_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ +/*description: max conversion number*/ +#define SYSCON_SARADC_MAX_MEAS_NUM 0x000000FF +#define SYSCON_SARADC_MAX_MEAS_NUM_M ((SYSCON_SARADC_MAX_MEAS_NUM_V)<<(SYSCON_SARADC_MAX_MEAS_NUM_S)) +#define SYSCON_SARADC_MAX_MEAS_NUM_V 0xFF +#define SYSCON_SARADC_MAX_MEAS_NUM_S 1 +/* SYSCON_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define SYSCON_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define SYSCON_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define SYSCON_SARADC_MEAS_NUM_LIMIT_S 0 + +#define SYSCON_SARADC_FSM_REG (DR_REG_SYSCON_BASE + 0x18) +/* SYSCON_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */ +/*description: sample cycles*/ +#define SYSCON_SARADC_SAMPLE_CYCLE 0x000000FF +#define SYSCON_SARADC_SAMPLE_CYCLE_M ((SYSCON_SARADC_SAMPLE_CYCLE_V)<<(SYSCON_SARADC_SAMPLE_CYCLE_S)) +#define SYSCON_SARADC_SAMPLE_CYCLE_V 0xFF +#define SYSCON_SARADC_SAMPLE_CYCLE_S 24 +/* SYSCON_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */ +/*description: */ +#define SYSCON_SARADC_START_WAIT 0x000000FF +#define SYSCON_SARADC_START_WAIT_M ((SYSCON_SARADC_START_WAIT_V)<<(SYSCON_SARADC_START_WAIT_S)) +#define SYSCON_SARADC_START_WAIT_V 0xFF +#define SYSCON_SARADC_START_WAIT_S 16 +/* SYSCON_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */ +/*description: */ +#define SYSCON_SARADC_STANDBY_WAIT 0x000000FF +#define SYSCON_SARADC_STANDBY_WAIT_M ((SYSCON_SARADC_STANDBY_WAIT_V)<<(SYSCON_SARADC_STANDBY_WAIT_S)) +#define SYSCON_SARADC_STANDBY_WAIT_V 0xFF +#define SYSCON_SARADC_STANDBY_WAIT_S 8 +/* SYSCON_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ +/*description: */ +#define SYSCON_SARADC_RSTB_WAIT 0x000000FF +#define SYSCON_SARADC_RSTB_WAIT_M ((SYSCON_SARADC_RSTB_WAIT_V)<<(SYSCON_SARADC_RSTB_WAIT_S)) +#define SYSCON_SARADC_RSTB_WAIT_V 0xFF +#define SYSCON_SARADC_RSTB_WAIT_S 0 + +#define SYSCON_SARADC_SAR1_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x1C) +/* SYSCON_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ +#define SYSCON_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF +#define SYSCON_SARADC_SAR1_PATT_TAB1_M ((SYSCON_SARADC_SAR1_PATT_TAB1_V)<<(SYSCON_SARADC_SAR1_PATT_TAB1_S)) +#define SYSCON_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF +#define SYSCON_SARADC_SAR1_PATT_TAB1_S 0 + +#define SYSCON_SARADC_SAR1_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x20) +/* SYSCON_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ +#define SYSCON_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF +#define SYSCON_SARADC_SAR1_PATT_TAB2_M ((SYSCON_SARADC_SAR1_PATT_TAB2_V)<<(SYSCON_SARADC_SAR1_PATT_TAB2_S)) +#define SYSCON_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF +#define SYSCON_SARADC_SAR1_PATT_TAB2_S 0 + +#define SYSCON_SARADC_SAR1_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x24) +/* SYSCON_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ +#define SYSCON_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF +#define SYSCON_SARADC_SAR1_PATT_TAB3_M ((SYSCON_SARADC_SAR1_PATT_TAB3_V)<<(SYSCON_SARADC_SAR1_PATT_TAB3_S)) +#define SYSCON_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF +#define SYSCON_SARADC_SAR1_PATT_TAB3_S 0 + +#define SYSCON_SARADC_SAR1_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x28) +/* SYSCON_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ +#define SYSCON_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF +#define SYSCON_SARADC_SAR1_PATT_TAB4_M ((SYSCON_SARADC_SAR1_PATT_TAB4_V)<<(SYSCON_SARADC_SAR1_PATT_TAB4_S)) +#define SYSCON_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF +#define SYSCON_SARADC_SAR1_PATT_TAB4_S 0 + +#define SYSCON_SARADC_SAR2_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x2C) +/* SYSCON_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ +#define SYSCON_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF +#define SYSCON_SARADC_SAR2_PATT_TAB1_M ((SYSCON_SARADC_SAR2_PATT_TAB1_V)<<(SYSCON_SARADC_SAR2_PATT_TAB1_S)) +#define SYSCON_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF +#define SYSCON_SARADC_SAR2_PATT_TAB1_S 0 + +#define SYSCON_SARADC_SAR2_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x30) +/* SYSCON_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ +#define SYSCON_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF +#define SYSCON_SARADC_SAR2_PATT_TAB2_M ((SYSCON_SARADC_SAR2_PATT_TAB2_V)<<(SYSCON_SARADC_SAR2_PATT_TAB2_S)) +#define SYSCON_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF +#define SYSCON_SARADC_SAR2_PATT_TAB2_S 0 + +#define SYSCON_SARADC_SAR2_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x34) +/* SYSCON_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ +#define SYSCON_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF +#define SYSCON_SARADC_SAR2_PATT_TAB3_M ((SYSCON_SARADC_SAR2_PATT_TAB3_V)<<(SYSCON_SARADC_SAR2_PATT_TAB3_S)) +#define SYSCON_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF +#define SYSCON_SARADC_SAR2_PATT_TAB3_S 0 + +#define SYSCON_SARADC_SAR2_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x38) +/* SYSCON_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ +#define SYSCON_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF +#define SYSCON_SARADC_SAR2_PATT_TAB4_M ((SYSCON_SARADC_SAR2_PATT_TAB4_V)<<(SYSCON_SARADC_SAR2_PATT_TAB4_S)) +#define SYSCON_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF +#define SYSCON_SARADC_SAR2_PATT_TAB4_S 0 + +#define SYSCON_APLL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x3C) +/* SYSCON_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */ +/*description: */ +#define SYSCON_APLL_TICK_NUM 0x000000FF +#define SYSCON_APLL_TICK_NUM_M ((SYSCON_APLL_TICK_NUM_V)<<(SYSCON_APLL_TICK_NUM_S)) +#define SYSCON_APLL_TICK_NUM_V 0xFF +#define SYSCON_APLL_TICK_NUM_S 0 + +#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x7C) +/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ +/*description: */ +#define SYSCON_DATE 0xFFFFFFFF +#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) +#define SYSCON_DATE_V 0xFFFFFFFF +#define SYSCON_DATE_S 0 + + + + +#endif /*_SOC_SYSCON_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/syscon_struct.h b/tools/sdk/include/soc/include/soc/syscon_struct.h new file mode 100644 index 00000000000..4fb86f42b99 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/syscon_struct.h @@ -0,0 +1,125 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SYSCON_STRUCT_H_ +#define _SOC_SYSCON_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t pre_div: 10; + uint32_t clk_320m_en: 1; + uint32_t clk_en: 1; + uint32_t rst_tick: 1; + uint32_t quick_clk_chng: 1; + uint32_t reserved14: 18; + }; + uint32_t val; + }clk_conf; + union { + struct { + uint32_t xtal_tick: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + }xtal_tick_conf; + union { + struct { + uint32_t pll_tick: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + }pll_tick_conf; + union { + struct { + uint32_t ck8m_tick: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + }ck8m_tick_conf; + union { + struct { + uint32_t start_force: 1; + uint32_t start: 1; + uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/ + uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ + uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ + uint32_t sar_clk_gated: 1; + uint32_t sar_clk_div: 8; /*SAR clock divider*/ + uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ + uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ + uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ + uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ + uint32_t reserved27: 5; + }; + uint32_t val; + }saradc_ctrl; + union { + struct { + uint32_t meas_num_limit: 1; + uint32_t max_meas_num: 8; /*max conversion number*/ + uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ + uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ + uint32_t reserved11: 21; + }; + uint32_t val; + }saradc_ctrl2; + union { + struct { + uint32_t rstb_wait: 8; + uint32_t standby_wait: 8; + uint32_t start_wait: 8; + uint32_t sample_cycle: 8; /*sample cycles*/ + }; + uint32_t val; + }saradc_fsm; + uint32_t saradc_sar1_patt_tab[4]; /*item 0 ~ 3 for ADC1 pattern table*/ + uint32_t saradc_sar2_patt_tab[4]; /*item 0 ~ 3 for ADC2 pattern table*/ + union { + struct { + uint32_t apll_tick: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + }apll_tick_conf; + uint32_t reserved_40; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t date; /**/ +} syscon_dev_t; + +#ifdef __cplusplus +} +#endif +extern syscon_dev_t SYSCON; +#endif /* _SOC_SYSCON_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/timer_group_reg.h b/tools/sdk/include/soc/include/soc/timer_group_reg.h new file mode 100644 index 00000000000..2db2a7e3f1b --- /dev/null +++ b/tools/sdk/include/soc/include/soc/timer_group_reg.h @@ -0,0 +1,668 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __TIMG_REG_H__ +#define __TIMG_REG_H__ +#include "soc.h" + +/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + + +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000) +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) +/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When set timer 0 time-base counter is enabled*/ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (BIT(31)) +#define TIMG_T0_EN_V 0x1 +#define TIMG_T0_EN_S 31 +/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: When set timer 0 time-base counter increment. When cleared timer + 0 time-base counter decrement.*/ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (BIT(30)) +#define TIMG_T0_INCREASE_V 0x1 +#define TIMG_T0_INCREASE_S 30 +/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: When set timer 0 auto-reload at alarming is enabled*/ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (BIT(29)) +#define TIMG_T0_AUTORELOAD_V 0x1 +#define TIMG_T0_AUTORELOAD_S 29 +/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ +/*description: Timer 0 clock (T0_clk) prescale value.*/ +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) +#define TIMG_T0_DIVIDER_V 0xFFFF +#define TIMG_T0_DIVIDER_S 13 +/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: When set edge type interrupt will be generated during alarm*/ +#define TIMG_T0_EDGE_INT_EN (BIT(12)) +#define TIMG_T0_EDGE_INT_EN_M (BIT(12)) +#define TIMG_T0_EDGE_INT_EN_V 0x1 +#define TIMG_T0_EDGE_INT_EN_S 12 +/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: When set level type interrupt will be generated during alarm*/ +#define TIMG_T0_LEVEL_INT_EN (BIT(11)) +#define TIMG_T0_LEVEL_INT_EN_M (BIT(11)) +#define TIMG_T0_LEVEL_INT_EN_V 0x1 +#define TIMG_T0_LEVEL_INT_EN_S 11 +/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: When set alarm is enabled*/ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (BIT(10)) +#define TIMG_T0_ALARM_EN_V 0x1 +#define TIMG_T0_ALARM_EN_S 10 + +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) +/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Register to store timer 0 time-base counter current value lower 32 bits.*/ +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 + +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) +/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Register to store timer 0 time-base counter current value higher 32 bits.*/ +#define TIMG_T0_HI 0xFFFFFFFF +#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) +#define TIMG_T0_HI_V 0xFFFFFFFF +#define TIMG_T0_HI_S 0 + +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) +/* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will trigger a timer 0 time-base counter value + update (timer 0 current value will be stored in registers above)*/ +#define TIMG_T0_UPDATE 0xFFFFFFFF +#define TIMG_T0_UPDATE_M ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S)) +#define TIMG_T0_UPDATE_V 0xFFFFFFFF +#define TIMG_T0_UPDATE_S 0 + +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) +/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 + +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) +/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ +#define TIMG_T0_ALARM_HI 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) +#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_S 0 + +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) +/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Lower 32 bits of the value that will load into timer 0 time-base counter*/ +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 + +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) +/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: higher 32 bits of the value that will load into timer 0 time-base counter*/ +#define TIMG_T0_LOAD_HI 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) +#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_S 0 + +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) +/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will trigger timer 0 time-base counter reload*/ +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 + +#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024) +/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When set timer 1 time-base counter is enabled*/ +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (BIT(31)) +#define TIMG_T1_EN_V 0x1 +#define TIMG_T1_EN_S 31 +/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: When set timer 1 time-base counter increment. When cleared timer + 1 time-base counter decrement.*/ +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (BIT(30)) +#define TIMG_T1_INCREASE_V 0x1 +#define TIMG_T1_INCREASE_S 30 +/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: When set timer 1 auto-reload at alarming is enabled*/ +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (BIT(29)) +#define TIMG_T1_AUTORELOAD_V 0x1 +#define TIMG_T1_AUTORELOAD_S 29 +/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ +/*description: Timer 1 clock (T1_clk) prescale value.*/ +#define TIMG_T1_DIVIDER 0x0000FFFF +#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S)) +#define TIMG_T1_DIVIDER_V 0xFFFF +#define TIMG_T1_DIVIDER_S 13 +/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: When set edge type interrupt will be generated during alarm*/ +#define TIMG_T1_EDGE_INT_EN (BIT(12)) +#define TIMG_T1_EDGE_INT_EN_M (BIT(12)) +#define TIMG_T1_EDGE_INT_EN_V 0x1 +#define TIMG_T1_EDGE_INT_EN_S 12 +/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: When set level type interrupt will be generated during alarm*/ +#define TIMG_T1_LEVEL_INT_EN (BIT(11)) +#define TIMG_T1_LEVEL_INT_EN_M (BIT(11)) +#define TIMG_T1_LEVEL_INT_EN_V 0x1 +#define TIMG_T1_LEVEL_INT_EN_S 11 +/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: When set alarm is enabled*/ +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (BIT(10)) +#define TIMG_T1_ALARM_EN_V 0x1 +#define TIMG_T1_ALARM_EN_S 10 + +#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028) +/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Register to store timer 1 time-base counter current value lower 32 bits.*/ +#define TIMG_T1_LO 0xFFFFFFFF +#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S)) +#define TIMG_T1_LO_V 0xFFFFFFFF +#define TIMG_T1_LO_S 0 + +#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c) +/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Register to store timer 1 time-base counter current value higher 32 bits.*/ +#define TIMG_T1_HI 0xFFFFFFFF +#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S)) +#define TIMG_T1_HI_V 0xFFFFFFFF +#define TIMG_T1_HI_S 0 + +#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030) +/* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will trigger a timer 1 time-base counter value + update (timer 1 current value will be stored in registers above)*/ +#define TIMG_T1_UPDATE 0xFFFFFFFF +#define TIMG_T1_UPDATE_M ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S)) +#define TIMG_T1_UPDATE_V 0xFFFFFFFF +#define TIMG_T1_UPDATE_S 0 + +#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034) +/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Timer 1 time-base counter value lower 32 bits that will trigger the alarm*/ +#define TIMG_T1_ALARM_LO 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S)) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_S 0 + +#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038) +/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Timer 1 time-base counter value higher 32 bits that will trigger the alarm*/ +#define TIMG_T1_ALARM_HI 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S)) +#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_S 0 + +#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c) +/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Lower 32 bits of the value that will load into timer 1 time-base counter*/ +#define TIMG_T1_LOAD_LO 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S)) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_S 0 + +#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040) +/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: higher 32 bits of the value that will load into timer 1 time-base counter*/ +#define TIMG_T1_LOAD_HI 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S)) +#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_S 0 + +#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044) +/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will trigger timer 1 time-base counter reload*/ +#define TIMG_T1_LOAD 0xFFFFFFFF +#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S)) +#define TIMG_T1_LOAD_V 0xFFFFFFFF +#define TIMG_T1_LOAD_S 0 + +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) +/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When set SWDT is enabled*/ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (BIT(31)) +#define TIMG_WDT_EN_V 0x1 +#define TIMG_WDT_EN_S 31 +/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */ +/*description: Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) +#define TIMG_WDT_STG0_V 0x3 +#define TIMG_WDT_STG0_S 29 +/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */ +/*description: Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) +#define TIMG_WDT_STG1_V 0x3 +#define TIMG_WDT_STG1_S 27 +/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */ +/*description: Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) +#define TIMG_WDT_STG2_V 0x3 +#define TIMG_WDT_STG2_S 25 +/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */ +/*description: Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) +#define TIMG_WDT_STG3_V 0x3 +#define TIMG_WDT_STG3_S 23 +/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: When set edge type interrupt generation is enabled*/ +#define TIMG_WDT_EDGE_INT_EN (BIT(22)) +#define TIMG_WDT_EDGE_INT_EN_M (BIT(22)) +#define TIMG_WDT_EDGE_INT_EN_V 0x1 +#define TIMG_WDT_EDGE_INT_EN_S 22 +/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: When set level type interrupt generation is enabled*/ +#define TIMG_WDT_LEVEL_INT_EN (BIT(21)) +#define TIMG_WDT_LEVEL_INT_EN_M (BIT(21)) +#define TIMG_WDT_LEVEL_INT_EN_V 0x1 +#define TIMG_WDT_LEVEL_INT_EN_S 21 +/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ +/*description: length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns + 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ +/*description: length of system reset selection. 0: 100ns 1: 200ns 2: 300ns + 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: When set flash boot protection is enabled*/ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 + +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) +/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ +/*description: SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) +#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF +#define TIMG_WDT_CLK_PRESCALE_S 16 + +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) +/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ +/*description: Stage 0 timeout value in SWDT clock cycles*/ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 + +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) +/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ +/*description: Stage 1 timeout value in SWDT clock cycles*/ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 + +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) +/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ +/*description: Stage 2 timeout value in SWDT clock cycles*/ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 + +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) +/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ +/*description: Stage 3 timeout value in SWDT clock cycles*/ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 + +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) +/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will feed SWDT*/ +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 + +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) +/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: If change its value from default then write protection is on.*/ +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 + +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 +/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ +/*description: */ +#define TIMG_RTC_CALI_MAX 0x00007FFF +#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S)) +#define TIMG_RTC_CALI_MAX_V 0x7FFF +#define TIMG_RTC_CALI_MAX_S 16 +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ +/*description: */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S)) +#define TIMG_RTC_CALI_CLK_SEL_V 0x3 +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S)) +#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF +#define TIMG_RTC_CALI_VALUE_S 7 + +#define TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070) +/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_EN (BIT(31)) +#define TIMG_LACT_EN_M (BIT(31)) +#define TIMG_LACT_EN_V 0x1 +#define TIMG_LACT_EN_S 31 +/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_LACT_INCREASE (BIT(30)) +#define TIMG_LACT_INCREASE_M (BIT(30)) +#define TIMG_LACT_INCREASE_V 0x1 +#define TIMG_LACT_INCREASE_S 30 +/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_LACT_AUTORELOAD (BIT(29)) +#define TIMG_LACT_AUTORELOAD_M (BIT(29)) +#define TIMG_LACT_AUTORELOAD_V 0x1 +#define TIMG_LACT_AUTORELOAD_S 29 +/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ +/*description: */ +#define TIMG_LACT_DIVIDER 0x0000FFFF +#define TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S)) +#define TIMG_LACT_DIVIDER_V 0xFFFF +#define TIMG_LACT_DIVIDER_S 13 +/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_EDGE_INT_EN (BIT(12)) +#define TIMG_LACT_EDGE_INT_EN_M (BIT(12)) +#define TIMG_LACT_EDGE_INT_EN_V 0x1 +#define TIMG_LACT_EDGE_INT_EN_S 12 +/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_LEVEL_INT_EN (BIT(11)) +#define TIMG_LACT_LEVEL_INT_EN_M (BIT(11)) +#define TIMG_LACT_LEVEL_INT_EN_V 0x1 +#define TIMG_LACT_LEVEL_INT_EN_S 11 +/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_ALARM_EN (BIT(10)) +#define TIMG_LACT_ALARM_EN_M (BIT(10)) +#define TIMG_LACT_ALARM_EN_V 0x1 +#define TIMG_LACT_ALARM_EN_S 10 +/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_LACT_LAC_EN (BIT(9)) +#define TIMG_LACT_LAC_EN_M (BIT(9)) +#define TIMG_LACT_LAC_EN_V 0x1 +#define TIMG_LACT_LAC_EN_S 9 +/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_LACT_CPST_EN (BIT(8)) +#define TIMG_LACT_CPST_EN_M (BIT(8)) +#define TIMG_LACT_CPST_EN_V 0x1 +#define TIMG_LACT_CPST_EN_S 8 +/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_RTC_ONLY (BIT(7)) +#define TIMG_LACT_RTC_ONLY_M (BIT(7)) +#define TIMG_LACT_RTC_ONLY_V 0x1 +#define TIMG_LACT_RTC_ONLY_S 7 + +#define TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074) +/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */ +/*description: */ +#define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S)) +#define TIMG_LACT_RTC_STEP_LEN_V 0x3FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_S 6 + +#define TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078) +/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_LO 0xFFFFFFFF +#define TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S)) +#define TIMG_LACT_LO_V 0xFFFFFFFF +#define TIMG_LACT_LO_S 0 + +#define TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c) +/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_HI 0xFFFFFFFF +#define TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S)) +#define TIMG_LACT_HI_V 0xFFFFFFFF +#define TIMG_LACT_HI_S 0 + +#define TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080) +/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_UPDATE 0xFFFFFFFF +#define TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S)) +#define TIMG_LACT_UPDATE_V 0xFFFFFFFF +#define TIMG_LACT_UPDATE_S 0 + +#define TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084) +/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_ALARM_LO 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S)) +#define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_S 0 + +#define TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088) +/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_ALARM_HI 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S)) +#define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_S 0 + +#define TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c) +/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_LOAD_LO 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S)) +#define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_S 0 + +#define TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090) +/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_LOAD_HI 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S)) +#define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_S 0 + +#define TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094) +/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_LOAD 0xFFFFFFFF +#define TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S)) +#define TIMG_LACT_LOAD_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_S 0 + +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098) +/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_INT_ENA (BIT(3)) +#define TIMG_LACT_INT_ENA_M (BIT(3)) +#define TIMG_LACT_INT_ENA_V 0x1 +#define TIMG_LACT_INT_ENA_S 3 +/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Interrupt when an interrupt stage timeout*/ +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (BIT(2)) +#define TIMG_WDT_INT_ENA_V 0x1 +#define TIMG_WDT_INT_ENA_S 2 +/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: interrupt when timer1 alarm*/ +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (BIT(1)) +#define TIMG_T1_INT_ENA_V 0x1 +#define TIMG_T1_INT_ENA_S 1 +/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: interrupt when timer0 alarm*/ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (BIT(0)) +#define TIMG_T0_INT_ENA_V 0x1 +#define TIMG_T0_INT_ENA_S 0 + +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c) +/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_INT_RAW (BIT(3)) +#define TIMG_LACT_INT_RAW_M (BIT(3)) +#define TIMG_LACT_INT_RAW_V 0x1 +#define TIMG_LACT_INT_RAW_S 3 +/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Interrupt when an interrupt stage timeout*/ +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (BIT(2)) +#define TIMG_WDT_INT_RAW_V 0x1 +#define TIMG_WDT_INT_RAW_S 2 +/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: interrupt when timer1 alarm*/ +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (BIT(1)) +#define TIMG_T1_INT_RAW_V 0x1 +#define TIMG_T1_INT_RAW_S 1 +/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: interrupt when timer0 alarm*/ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (BIT(0)) +#define TIMG_T0_INT_RAW_V 0x1 +#define TIMG_T0_INT_RAW_S 0 + +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0) +/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_INT_ST (BIT(3)) +#define TIMG_LACT_INT_ST_M (BIT(3)) +#define TIMG_LACT_INT_ST_V 0x1 +#define TIMG_LACT_INT_ST_S 3 +/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Interrupt when an interrupt stage timeout*/ +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (BIT(2)) +#define TIMG_WDT_INT_ST_V 0x1 +#define TIMG_WDT_INT_ST_S 2 +/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: interrupt when timer1 alarm*/ +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (BIT(1)) +#define TIMG_T1_INT_ST_V 0x1 +#define TIMG_T1_INT_ST_S 1 +/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: interrupt when timer0 alarm*/ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (BIT(0)) +#define TIMG_T0_INT_ST_V 0x1 +#define TIMG_T0_INT_ST_S 0 + +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4) +/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_INT_CLR (BIT(3)) +#define TIMG_LACT_INT_CLR_M (BIT(3)) +#define TIMG_LACT_INT_CLR_V 0x1 +#define TIMG_LACT_INT_CLR_S 3 +/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Interrupt when an interrupt stage timeout*/ +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (BIT(2)) +#define TIMG_WDT_INT_CLR_V 0x1 +#define TIMG_WDT_INT_CLR_S 2 +/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: interrupt when timer1 alarm*/ +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (BIT(1)) +#define TIMG_T1_INT_CLR_V 0x1 +#define TIMG_T1_INT_CLR_S 1 +/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: interrupt when timer0 alarm*/ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (BIT(0)) +#define TIMG_T0_INT_CLR_V 0x1 +#define TIMG_T0_INT_CLR_S 0 + +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) +/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; */ +/*description: Version of this regfile*/ +#define TIMG_NTIMERS_DATE 0x0FFFFFFF +#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) +#define TIMG_NTIMERS_DATE_V 0xFFFFFFF +#define TIMG_NTIMERS_DATE_S 0 + +#define TIMGCLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) +/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Force clock enable for this regfile*/ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (BIT(31)) +#define TIMG_CLK_EN_V 0x1 +#define TIMG_CLK_EN_S 31 + + + + +#endif /*__TIMG_REG_H__ */ + + diff --git a/tools/sdk/include/soc/include/soc/timer_group_struct.h b/tools/sdk/include/soc/include/soc/timer_group_struct.h new file mode 100644 index 00000000000..6d312969d49 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/timer_group_struct.h @@ -0,0 +1,207 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_TIMG_STRUCT_H_ +#define _SOC_TIMG_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + struct{ + union { + struct { + uint32_t reserved0: 10; + uint32_t alarm_en: 1; /*When set alarm is enabled*/ + uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ + uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ + uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ + uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ + uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ + uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ + }; + uint32_t val; + } config; + uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ + uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ + uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ + uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ + uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ + uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/ + } hw_timer[2]; + union { + struct { + uint32_t reserved0: 14; + uint32_t flashboot_mod_en: 1; /*When set flash boot protection is enabled*/ + uint32_t sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + uint32_t cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + uint32_t level_int_en: 1; /*When set level type interrupt generation is enabled*/ + uint32_t edge_int_en: 1; /*When set edge type interrupt generation is enabled*/ + uint32_t stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t en: 1; /*When set SWDT is enabled*/ + }; + uint32_t val; + } wdt_config0; + union { + struct { + uint32_t reserved0: 16; + uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ + }; + uint32_t val; + } wdt_config1; + uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/ + uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/ + uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/ + uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/ + uint32_t wdt_feed; /*Write any value will feed SWDT*/ + uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/ + union { + struct { + uint32_t reserved0: 12; + uint32_t start_cycling: 1; + uint32_t clk_sel: 2; + uint32_t rdy: 1; + uint32_t max: 15; + uint32_t start: 1; + }; + uint32_t val; + } rtc_cali_cfg; + union { + struct { + uint32_t reserved0: 7; + uint32_t value:25; + }; + uint32_t val; + } rtc_cali_cfg1; + union { + struct { + uint32_t reserved0: 7; + uint32_t rtc_only: 1; + uint32_t cpst_en: 1; + uint32_t lac_en: 1; + uint32_t alarm_en: 1; + uint32_t level_int_en: 1; + uint32_t edge_int_en: 1; + uint32_t divider: 16; + uint32_t autoreload: 1; + uint32_t increase: 1; + uint32_t en: 1; + }; + uint32_t val; + } lactconfig; + union { + struct { + uint32_t reserved0: 6; + uint32_t step_len:26; + }; + uint32_t val; + } lactrtc; + uint32_t lactlo; /**/ + uint32_t lacthi; /**/ + uint32_t lactupdate; /**/ + uint32_t lactalarmlo; /**/ + uint32_t lactalarmhi; /**/ + uint32_t lactloadlo; /**/ + uint32_t lactloadhi; /**/ + uint32_t lactload; /**/ + union { + struct { + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4:28; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_st_timers; + union { + struct { + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_clr_timers; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + union { + struct { + uint32_t date:28; /*Version of this regfile*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } timg_date; + union { + struct { + uint32_t reserved0: 31; + uint32_t en: 1; /*Force clock enable for this regfile*/ + }; + uint32_t val; + } clk; +} timg_dev_t; +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_TIMG_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/touch_channel.h b/tools/sdk/include/soc/include/soc/touch_channel.h new file mode 100644 index 00000000000..a9aa838b4e0 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/touch_channel.h @@ -0,0 +1,49 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_TOUCH_CHANNEL_H +#define _SOC_TOUCH_CHANNEL_H + +//Touch channels +#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM0 +#define TOUCH_PAD_NUM0_GPIO_NUM 4 + +#define TOUCH_PAD_GPIO0_CHANNEL TOUCH_PAD_NUM1 +#define TOUCH_PAD_NUM1_GPIO_NUM 0 + +#define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM2 +#define TOUCH_PAD_NUM2_GPIO_NUM 2 + +#define TOUCH_PAD_GPIO15_CHANNEL TOUCH_PAD_NUM3 +#define TOUCH_PAD_NUM3_GPIO_NUM 15 + +#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM4 +#define TOUCH_PAD_NUM4_GPIO_NUM 13 + +#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM5 +#define TOUCH_PAD_NUM5_GPIO_NUM 12 + +#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM6 +#define TOUCH_PAD_NUM6_GPIO_NUM 14 + +#define TOUCH_PAD_GPIO27_CHANNEL TOUCH_PAD_NUM7 +#define TOUCH_PAD_NUM7_GPIO_NUM 27 + +#define TOUCH_PAD_GPIO33_CHANNEL TOUCH_PAD_NUM8 +#define TOUCH_PAD_NUM8_GPIO_NUM 33 + +#define TOUCH_PAD_GPIO32_CHANNEL TOUCH_PAD_NUM9 +#define TOUCH_PAD_NUM9_GPIO_NUM 32 + +#endif diff --git a/tools/sdk/include/soc/include/soc/uart_channel.h b/tools/sdk/include/soc/include/soc/uart_channel.h new file mode 100644 index 00000000000..5b8dc56d5ae --- /dev/null +++ b/tools/sdk/include/soc/include/soc/uart_channel.h @@ -0,0 +1,61 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_UART_CHANNEL_H +#define _SOC_UART_CHANNEL_H + +//UART channels +#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1 +#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3 +#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19 +#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22 + +#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL +#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL +#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL +#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL + +#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10 +#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9 +#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6 +#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11 + +#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL +#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL +#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL +#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL + +#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17 +#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16 +#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8 +#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7 + +#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL +#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL +#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL +#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL + +#endif diff --git a/tools/sdk/include/soc/include/soc/uart_reg.h b/tools/sdk/include/soc/include/soc/uart_reg.h new file mode 100644 index 00000000000..33b6e998edf --- /dev/null +++ b/tools/sdk/include/soc/include/soc/uart_reg.h @@ -0,0 +1,1180 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + + +#include "soc.h" + +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) + +/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: This register stores one byte data read by rx fifo.*/ +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) +#define UART_RXFIFO_RD_BYTE_V 0xFF +#define UART_RXFIFO_RD_BYTE_S 0 + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the configured at_cmd chars.*/ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects + the clash between transmitter and receiver.*/ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_V 0x1 +#define UART_RS485_CLASH_INT_RAW_S 17 +/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects + the data frame error.*/ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + send all the data in fifo.*/ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (BIT(14)) +#define UART_TX_DONE_INT_RAW_V 0x1 +#define UART_TX_DONE_INT_RAW_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + kept the shortest duration after the last data has been send.*/ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter completes + sendding 0 after all the datas in transmitter's fifo are send.*/ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_V 0x1 +#define UART_GLITCH_DET_INT_RAW_S 11 +/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + xon char with uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (BIT(10)) +#define UART_SW_XOFF_INT_RAW_V 0x1 +#define UART_SW_XOFF_INT_RAW_S 10 +/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + xoff char with uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (BIT(9)) +#define UART_SW_XON_INT_RAW_V 0x1 +#define UART_SW_XON_INT_RAW_S 9 +/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver takes + more time than rx_tout_thrhd to receive a byte.*/ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the 0 after the stop bit.*/ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (BIT(7)) +#define UART_BRK_DET_INT_RAW_V 0x1 +#define UART_BRK_DET_INT_RAW_S 7 +/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of ctsn signal.*/ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (BIT(6)) +#define UART_CTS_CHG_INT_RAW_V 0x1 +#define UART_CTS_CHG_INT_RAW_S 6 +/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of dsrn signal.*/ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (BIT(5)) +#define UART_DSR_CHG_INT_RAW_V 0x1 +#define UART_DSR_CHG_INT_RAW_S 5 +/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than the fifo can store.*/ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_V 0x1 +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + data's frame error .*/ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (BIT(3)) +#define UART_FRM_ERR_INT_RAW_V 0x1 +#define UART_FRM_ERR_INT_RAW_S 3 +/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the parity error of data.*/ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_V 0x1 +#define UART_PARITY_ERR_INT_RAW_S 2 +/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when the amount of + data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_V 0x1 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena + is set to 1.*/ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena + is set to 1.*/ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (BIT(17)) +#define UART_RS485_CLASH_INT_ST_V 0x1 +#define UART_RS485_CLASH_INT_ST_S 17 +/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena + is set to 1.*/ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_V 0x1 +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena + is set to 1.*/ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (BIT(14)) +#define UART_TX_DONE_INT_ST_V 0x1 +#define UART_TX_DONE_INT_ST_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_DONE_INT_ST_S 12 +/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena + is set to 1.*/ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (BIT(11)) +#define UART_GLITCH_DET_INT_ST_V 0x1 +#define UART_GLITCH_DET_INT_ST_S 11 +/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (BIT(10)) +#define UART_SW_XOFF_INT_ST_V 0x1 +#define UART_SW_XOFF_INT_ST_S 10 +/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (BIT(9)) +#define UART_SW_XON_INT_ST_V 0x1 +#define UART_SW_XON_INT_ST_S 9 +/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena + is set to 1.*/ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_V 0x1 +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (BIT(7)) +#define UART_BRK_DET_INT_ST_V 0x1 +#define UART_BRK_DET_INT_ST_S 7 +/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (BIT(6)) +#define UART_CTS_CHG_INT_ST_V 0x1 +#define UART_CTS_CHG_INT_ST_S 6 +/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (BIT(5)) +#define UART_DSR_CHG_INT_ST_V 0x1 +#define UART_DSR_CHG_INT_ST_S 5 +/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena + is set to 1.*/ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_V 0x1 +#define UART_RXFIFO_OVF_INT_ST_S 4 +/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (BIT(3)) +#define UART_FRM_ERR_INT_ST_V 0x1 +#define UART_FRM_ERR_INT_ST_S 3 +/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena + is set to 1.*/ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (BIT(2)) +#define UART_PARITY_ERR_INT_ST_V 0x1 +#define UART_PARITY_ERR_INT_ST_S 2 +/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena + is set to 1.*/ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena + is set to 1.*/ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_V 0x1 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the enable bit for at_cmd_char_det_int_st register.*/ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_clash_int_st register.*/ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_V 0x1 +#define UART_RS485_CLASH_INT_ENA_S 17 +/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_done_int_st register.*/ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (BIT(14)) +#define UART_TX_DONE_INT_ENA_V 0x1 +#define UART_TX_DONE_INT_ENA_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_done_int_st register.*/ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the enable bit for glitch_det_int_st register.*/ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_V 0x1 +#define UART_GLITCH_DET_INT_ENA_S 11 +/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xoff_int_st register.*/ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (BIT(10)) +#define UART_SW_XOFF_INT_ENA_V 0x1 +#define UART_SW_XOFF_INT_ENA_S 10 +/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xon_int_st register.*/ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (BIT(9)) +#define UART_SW_XON_INT_ENA_V 0x1 +#define UART_SW_XON_INT_ENA_S 9 +/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_tout_int_st register.*/ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the enable bit for brk_det_int_st register.*/ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (BIT(7)) +#define UART_BRK_DET_INT_ENA_V 0x1 +#define UART_BRK_DET_INT_ENA_S 7 +/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the enable bit for cts_chg_int_st register.*/ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (BIT(6)) +#define UART_CTS_CHG_INT_ENA_V 0x1 +#define UART_CTS_CHG_INT_ENA_S 6 +/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the enable bit for dsr_chg_int_st register.*/ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (BIT(5)) +#define UART_DSR_CHG_INT_ENA_V 0x1 +#define UART_DSR_CHG_INT_ENA_S 5 +/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_ovf_int_st register.*/ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_V 0x1 +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the enable bit for frm_err_int_st register.*/ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (BIT(3)) +#define UART_FRM_ERR_INT_ENA_V 0x1 +#define UART_FRM_ERR_INT_ENA_S 3 +/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the enable bit for parity_err_int_st register.*/ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_V 0x1 +#define UART_PARITY_ERR_INT_ENA_S 2 +/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_full_int_st register.*/ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_full_int_st register.*/ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_V 0x1 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_V 0x1 +#define UART_RS485_CLASH_INT_CLR_S 17 +/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_done_int_raw interrupt.*/ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (BIT(14)) +#define UART_TX_DONE_INT_CLR_V 0x1 +#define UART_TX_DONE_INT_CLR_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_V 0x1 +#define UART_GLITCH_DET_INT_CLR_S 11 +/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (BIT(10)) +#define UART_SW_XOFF_INT_CLR_V 0x1 +#define UART_SW_XOFF_INT_CLR_S 10 +/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (BIT(9)) +#define UART_SW_XON_INT_CLR_V 0x1 +#define UART_SW_XON_INT_CLR_S 9 +/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the brk_det_int_raw interrupt.*/ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (BIT(7)) +#define UART_BRK_DET_INT_CLR_V 0x1 +#define UART_BRK_DET_INT_CLR_S 7 +/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (BIT(6)) +#define UART_CTS_CHG_INT_CLR_V 0x1 +#define UART_CTS_CHG_INT_CLR_S 6 +/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (BIT(5)) +#define UART_DSR_CHG_INT_CLR_V 0x1 +#define UART_DSR_CHG_INT_CLR_S 5 +/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_V 0x1 +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear frm_err_int_raw interrupt.*/ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (BIT(3)) +#define UART_FRM_ERR_INT_CLR_V 0x1 +#define UART_FRM_ERR_INT_CLR_S 3 +/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear parity_err_int_raw interrupt.*/ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_V 0x1 +#define UART_PARITY_ERR_INT_CLR_S 2 +/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_V 0x1 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) +/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: The register value is the decimal part of the frequency divider's factor.*/ +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) +#define UART_CLKDIV_FRAG_V 0xF +#define UART_CLKDIV_FRAG_S 20 +/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */ +/*description: The register value is the integer part of the frequency divider's factor.*/ +#define UART_CLKDIV 0x000FFFFF +#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) +#define UART_CLKDIV_V 0xFFFFF +#define UART_CLKDIV_S 0 + +#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) +/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */ +/*description: when input pulse width is lower then this value igore this pulse.this + register is used in autobaud detect process.*/ +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) +#define UART_GLITCH_FILT_V 0xFF +#define UART_GLITCH_FILT_S 8 +/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the enable bit for detecting baudrate.*/ +#define UART_AUTOBAUD_EN (BIT(0)) +#define UART_AUTOBAUD_EN_M (BIT(0)) +#define UART_AUTOBAUD_EN_V 0x1 +#define UART_AUTOBAUD_EN_S 0 + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) +/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ +/*description: This register represent the level value of the internal uart rxd signal.*/ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (BIT(31)) +#define UART_TXD_V 0x1 +#define UART_TXD_S 31 +/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This register represent the level value of the internal uart cts signal.*/ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (BIT(30)) +#define UART_RTSN_V 0x1 +#define UART_RTSN_S 30 +/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The register represent the level value of the internal uart dsr signal.*/ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (BIT(29)) +#define UART_DTRN_V 0x1 +#define UART_DTRN_S 29 +/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */ +/*description: This register stores the value of transmitter's finite state + machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) +#define UART_ST_UTX_OUT_V 0xF +#define UART_ST_UTX_OUT_S 24 +/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in + transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ +#define UART_TXFIFO_CNT 0x000000FF +#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) +#define UART_TXFIFO_CNT_V 0xFF +#define UART_TXFIFO_CNT_S 16 +/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart rxd signal.*/ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (BIT(15)) +#define UART_RXD_V 0x1 +#define UART_RXD_S 15 +/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart cts signal.*/ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (BIT(14)) +#define UART_CTSN_V 0x1 +#define UART_CTSN_S 14 +/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart dsr signal.*/ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (BIT(13)) +#define UART_DSRN_V 0x1 +#define UART_DSRN_S 13 +/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */ +/*description: This register stores the value of receiver's finite state machine. + 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) +#define UART_ST_URX_OUT_V 0xF +#define UART_ST_URX_OUT_S 8 +/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in + receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ +#define UART_RXFIFO_CNT 0x000000FF +#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) +#define UART_RXFIFO_CNT_V 0xFF +#define UART_RXFIFO_CNT_S 0 + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) +/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/ +#define UART_TICK_REF_ALWAYS_ON (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_M (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_V 0x1 +#define UART_TICK_REF_ALWAYS_ON_S 27 +/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1.receiver stops storing data int fifo when data is wrong. + 0.receiver stores the data even if the received data is wrong.*/ +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (BIT(26)) +#define UART_ERR_WR_MASK_V 0x1 +#define UART_ERR_WR_MASK_S 26 +/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: 1.force clock on for registers.support clock only when write registers*/ +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (BIT(25)) +#define UART_CLK_EN_V 0x1 +#define UART_CLK_EN_S 25 +/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dtr signal.*/ +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (BIT(24)) +#define UART_DTR_INV_V 0x1 +#define UART_DTR_INV_S 24 +/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rts signal.*/ +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (BIT(23)) +#define UART_RTS_INV_V 0x1 +#define UART_RTS_INV_S 23 +/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart txd signal.*/ +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (BIT(22)) +#define UART_TXD_INV_V 0x1 +#define UART_TXD_INV_S 22 +/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dsr signal.*/ +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (BIT(21)) +#define UART_DSR_INV_V 0x1 +#define UART_DSR_INV_S 21 +/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart cts signal.*/ +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (BIT(20)) +#define UART_CTS_INV_V 0x1 +#define UART_CTS_INV_S 20 +/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rxd signal.*/ +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (BIT(19)) +#define UART_RXD_INV_V 0x1 +#define UART_RXD_INV_S 19 +/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: Set this bit to reset uart transmitter's fifo.*/ +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (BIT(18)) +#define UART_TXFIFO_RST_V 0x1 +#define UART_TXFIFO_RST_S 18 +/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: Set this bit to reset uart receiver's fifo.*/ +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (BIT(17)) +#define UART_RXFIFO_RST_V 0x1 +#define UART_RXFIFO_RST_S 17 +/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to enable irda protocol.*/ +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (BIT(16)) +#define UART_IRDA_EN_V 0x1 +#define UART_IRDA_EN_S 16 +/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable transmitter's flow control function.*/ +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (BIT(15)) +#define UART_TX_FLOW_EN_V 0x1 +#define UART_TX_FLOW_EN_S 15 +/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart loopback test mode.*/ +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (BIT(14)) +#define UART_LOOPBACK_V 0x1 +#define UART_LOOPBACK_S 14 +/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to inverse the level value of irda receiver's level.*/ +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (BIT(13)) +#define UART_IRDA_RX_INV_V 0x1 +#define UART_IRDA_RX_INV_S 13 +/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to inverse the level value of irda transmitter's level.*/ +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (BIT(12)) +#define UART_IRDA_TX_INV_V 0x1 +#define UART_IRDA_TX_INV_S 12 +/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit. + 0.set irda transmitter's 11th bit to 0.*/ +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (BIT(11)) +#define UART_IRDA_WCTL_V 0x1 +#define UART_IRDA_WCTL_S 11 +/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the start enable bit for irda transmitter.*/ +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (BIT(10)) +#define UART_IRDA_TX_EN_V 0x1 +#define UART_IRDA_TX_EN_S 10 +/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable irda loopback mode.*/ +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (BIT(9)) +#define UART_IRDA_DPLX_V 0x1 +#define UART_IRDA_DPLX_S 9 +/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enbale transmitter to send 0 when the process + of sending data is done.*/ +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (BIT(8)) +#define UART_TXD_BRK_V 0x1 +#define UART_TXD_BRK_S 8 +/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This register is used to configure the software dtr signal which + is used in software flow control..*/ +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (BIT(7)) +#define UART_SW_DTR_V 0x1 +#define UART_SW_DTR_S 7 +/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This register is used to configure the software rts signal which + is used in software flow control.*/ +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (BIT(6)) +#define UART_SW_RTS_V 0x1 +#define UART_SW_RTS_S 6 +/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ +/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) +#define UART_STOP_BIT_NUM_V 0x3 +#define UART_STOP_BIT_NUM_S 4 +/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ +/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) +#define UART_BIT_NUM_V 0x3 +#define UART_BIT_NUM_S 2 +/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart parity check.*/ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (BIT(1)) +#define UART_PARITY_EN_V 0x1 +#define UART_PARITY_EN_S 1 +/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This register is used to configure the parity check mode. 0:even 1:odd*/ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (BIT(0)) +#define UART_PARITY_V 0x1 +#define UART_PARITY_S 0 + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: This is the enble bit for uart receiver's timeout function.*/ +#define UART_RX_TOUT_EN (BIT(31)) +#define UART_RX_TOUT_EN_M (BIT(31)) +#define UART_RX_TOUT_EN_V 0x1 +#define UART_RX_TOUT_EN_S 31 +/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */ +/*description: This register is used to configure the timeout value for uart + receiver receiving a byte.*/ +#define UART_RX_TOUT_THRHD 0x0000007F +#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) +#define UART_RX_TOUT_THRHD_V 0x7F +#define UART_RX_TOUT_THRHD_S 24 +/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This is the flow enable bit for uart receiver. 1:choose software + flow control with configuring sw_rts signal*/ +#define UART_RX_FLOW_EN (BIT(23)) +#define UART_RX_FLOW_EN_M (BIT(23)) +#define UART_RX_FLOW_EN_V 0x1 +#define UART_RX_FLOW_EN_S 23 +/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */ +/*description: when receiver receives more data than its threshold value. + receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ +#define UART_RX_FLOW_THRHD 0x0000007F +#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) +#define UART_RX_FLOW_THRHD_V 0x7F +#define UART_RX_FLOW_THRHD_S 16 +/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */ +/*description: when the data amount in transmitter fifo is less than its threshold + value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ +#define UART_TXFIFO_EMPTY_THRHD 0x0000007F +#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) +#define UART_TXFIFO_EMPTY_THRHD_V 0x7F +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */ +/*description: When receiver receives more data than its threshold value.receiver + will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ +#define UART_RXFIFO_FULL_THRHD 0x0000007F +#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) +#define UART_RXFIFO_FULL_THRHD_V 0x7F +#define UART_RXFIFO_FULL_THRHD_S 0 + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) +/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the value of the minimum duration time for + the low level pulse. it is used in baudrate-detect process.*/ +#define UART_LOWPULSE_MIN_CNT 0x000FFFFF +#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) +#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) +/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the value of the maxinum duration time + for the high level pulse. it is used in baudrate-detect process.*/ +#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF +#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) +#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) +/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register stores the count of rxd edge change. it is used + in baudrate-detect process.*/ +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) +#define UART_RXD_EDGE_CNT_V 0x3FF +#define UART_RXD_EDGE_CNT_S 0 + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) +/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/ +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (BIT(5)) +#define UART_SEND_XOFF_V 0x1 +#define UART_SEND_XOFF_S 5 +/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/ +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (BIT(4)) +#define UART_SEND_XON_V 0x1 +#define UART_SEND_XON_S 4 +/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/ +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (BIT(3)) +#define UART_FORCE_XOFF_V 0x1 +#define UART_FORCE_XOFF_S 3 +/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/ +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (BIT(2)) +#define UART_FORCE_XON_V 0x1 +#define UART_FORCE_XON_S 2 +/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to remove flow control char from the received data.*/ +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (BIT(1)) +#define UART_XONOFF_DEL_V 0x1 +#define UART_XONOFF_DEL_S 1 +/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable software flow control. it is used with + register sw_xon or sw_xoff .*/ +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (BIT(0)) +#define UART_SW_FLOW_CON_EN_V 0x1 +#define UART_SW_FLOW_CON_EN_S 0 + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) +/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ +/*description: When the input rxd edge changes more than this register value. + the uart is active from light sleeping mode.*/ +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) +#define UART_ACTIVE_THRESHOLD_V 0x3FF +#define UART_ACTIVE_THRESHOLD_S 0 + +#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C) +/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */ +/*description: This register stores the xoff flow control char.*/ +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) +#define UART_XOFF_CHAR_V 0xFF +#define UART_XOFF_CHAR_S 24 +/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */ +/*description: This register stores the xon flow control char.*/ +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) +#define UART_XON_CHAR_V 0xFF +#define UART_XON_CHAR_S 16 +/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */ +/*description: When the data amount in receiver's fifo is less than this register + value. it will send a xon char with uart_sw_flow_con_en set to 1.*/ +#define UART_XOFF_THRESHOLD 0x000000FF +#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) +#define UART_XOFF_THRESHOLD_V 0xFF +#define UART_XOFF_THRESHOLD_S 8 +/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: when the data amount in receiver's fifo is more than this register + value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/ +#define UART_XON_THRESHOLD 0x000000FF +#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) +#define UART_XON_THRESHOLD_V 0xFF +#define UART_XON_THRESHOLD_S 0 + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40) +/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */ +/*description: This register is used to configure the num of 0 send after the + process of sending data is done. it is active when txd_brk is set to 1.*/ +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) +#define UART_TX_BRK_NUM_V 0xFF +#define UART_TX_BRK_NUM_S 20 +/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ +/*description: This register is used to configure the duration time between transfers.*/ +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) +#define UART_TX_IDLE_NUM_V 0x3FF +#define UART_TX_IDLE_NUM_S 10 +/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ +/*description: when receiver takes more time than this register value to receive + a byte data. it will produce frame end signal for uhci to stop receiving data.*/ +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) +#define UART_RX_IDLE_THRHD_V 0x3FF +#define UART_RX_IDLE_THRHD_S 0 + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44) +/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ +/*description: This register is used to delay the transmitter's internal data signal.*/ +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) +#define UART_RS485_TX_DLY_NUM_V 0xF +#define UART_RS485_TX_DLY_NUM_S 6 +/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This register is used to delay the receiver's internal data signal.*/ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (BIT(5)) +#define UART_RS485_RX_DLY_NUM_V 0x1 +#define UART_RS485_RX_DLY_NUM_S 5 +/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: enable rs485's transmitter to send data when rs485's receiver + is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (BIT(4)) +#define UART_RS485RXBY_TX_EN_V 0x1 +#define UART_RS485RXBY_TX_EN_S 4 +/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable loopback transmitter's output data signal + to receiver's input data signal.*/ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (BIT(3)) +#define UART_RS485TX_RX_EN_V 0x1 +#define UART_RS485TX_RX_EN_S 3 +/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (BIT(2)) +#define UART_DL1_EN_V 0x1 +#define UART_DL1_EN_S 2 +/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (BIT(1)) +#define UART_DL0_EN_V 0x1 +#define UART_DL0_EN_S 1 +/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to choose rs485 mode.*/ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (BIT(0)) +#define UART_RS485_EN_V 0x1 +#define UART_RS485_EN_S 0 + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48) +/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/*description: This register is used to configure the idle duration time before + the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ +#define UART_PRE_IDLE_NUM 0x00FFFFFF +#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) +#define UART_PRE_IDLE_NUM_V 0xFFFFFF +#define UART_PRE_IDLE_NUM_S 0 + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c) +/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/*description: This register is used to configure the duration time between + the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/ +#define UART_POST_IDLE_NUM 0x00FFFFFF +#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) +#define UART_POST_IDLE_NUM_V 0xFFFFFF +#define UART_POST_IDLE_NUM_S 0 + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50) +/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */ +/*description: This register is used to configure the duration time between + the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/ +#define UART_RX_GAP_TOUT 0x00FFFFFF +#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) +#define UART_RX_GAP_TOUT_V 0xFFFFFF +#define UART_RX_GAP_TOUT_S 0 + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54) +/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ +/*description: This register is used to configure the num of continous at_cmd + chars received by receiver.*/ +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) +#define UART_CHAR_NUM_V 0xFF +#define UART_CHAR_NUM_S 8 +/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ +/*description: This register is used to configure the content of at_cmd char.*/ +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) +#define UART_AT_CMD_CHAR_V 0xFF +#define UART_AT_CMD_CHAR_S 0 + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58) +/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: refer to txfifo_empty_thrhd 's describtion.*/ +#define UART_TX_MEM_EMPTY_THRHD 0x00000007 +#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S)) +#define UART_TX_MEM_EMPTY_THRHD_V 0x7 +#define UART_TX_MEM_EMPTY_THRHD_S 28 +/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: refer to the rxfifo_full_thrhd's describtion.*/ +#define UART_RX_MEM_FULL_THRHD 0x00000007 +#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S)) +#define UART_RX_MEM_FULL_THRHD_V 0x7 +#define UART_RX_MEM_FULL_THRHD_S 25 +/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ +/*description: refer to the uart_xoff_threshold's describtion.*/ +#define UART_XOFF_THRESHOLD_H2 0x00000003 +#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S)) +#define UART_XOFF_THRESHOLD_H2_V 0x3 +#define UART_XOFF_THRESHOLD_H2_S 23 +/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: refer to the uart_xon_threshold's describtion.*/ +#define UART_XON_THRESHOLD_H2 0x00000003 +#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S)) +#define UART_XON_THRESHOLD_H2_V 0x3 +#define UART_XON_THRESHOLD_H2_S 21 +/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: refer to the rx_tout_thrhd's describtion.*/ +#define UART_RX_TOUT_THRHD_H3 0x00000007 +#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S)) +#define UART_RX_TOUT_THRHD_H3_V 0x7 +#define UART_RX_TOUT_THRHD_H3_S 18 +/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: refer to the rx_flow_thrhd's describtion.*/ +#define UART_RX_FLOW_THRHD_H3 0x00000007 +#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S)) +#define UART_RX_FLOW_THRHD_H3_V 0x7 +#define UART_RX_FLOW_THRHD_H3_S 15 +/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */ +/*description: This register is used to configure the amount of mem allocated + to transmitter's fifo.the default byte num is 128.*/ +#define UART_TX_SIZE 0x0000000F +#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) +#define UART_TX_SIZE_V 0xF +#define UART_TX_SIZE_S 7 +/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */ +/*description: This register is used to configure the amount of mem allocated + to receiver's fifo. the default byte num is 128.*/ +#define UART_RX_SIZE 0x0000000F +#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) +#define UART_RX_SIZE_V 0xF +#define UART_RX_SIZE_S 3 +/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to power down mem.when reg_mem_pd registers in + the 3 uarts are all set to 1 mem will enter low power mode.*/ +#define UART_MEM_PD (BIT(0)) +#define UART_MEM_PD_M (BIT(0)) +#define UART_MEM_PD_V 0x1 +#define UART_MEM_PD_S 0 + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c) +/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: */ +#define UART_MEM_TX_STATUS 0x00FFFFFF +#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S)) +#define UART_MEM_TX_STATUS_V 0xFFFFFF +#define UART_MEM_TX_STATUS_S 0 + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) +/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: This register stores the current uart rx mem read address + and rx mem write address */ +#define UART_MEM_RX_STATUS 0x00FFFFFF +#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S)) +#define UART_MEM_RX_STATUS_V 0xFFFFFF +#define UART_MEM_RX_STATUS_S 0 +/* UART_MEM_RX_RD_ADDR : RO ;bitpos:[12:2] ;default: 11'h0 ; */ +/*description: This register stores the rx mem read address */ +#define UART_MEM_RX_RD_ADDR 0x000007FF +#define UART_MEM_RX_RD_ADDR_M ((UART_MEM_RX_RD_ADDR_V)<<(UART_MEM_RX_RD_ADDR_S)) +#define UART_MEM_RX_RD_ADDR_V (0x7FF) +#define UART_MEM_RX_RD_ADDR_S (2) +/* UART_MEM_RX_WR_ADDR : RO ;bitpos:[23:13] ;default: 11'h0 ; */ +/*description: This register stores the rx mem write address */ +#define UART_MEM_RX_WR_ADDR 0x000007FF +#define UART_MEM_RX_WR_ADDR_M ((UART_MEM_RX_WR_ADDR_V)<<(UART_MEM_RX_WR_ADDR_S)) +#define UART_MEM_RX_WR_ADDR_V (0x7FF) +#define UART_MEM_RX_WR_ADDR_S (13) + +#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) +/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: refer to the txfifo_cnt's describtion.*/ +#define UART_TX_MEM_CNT 0x00000007 +#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S)) +#define UART_TX_MEM_CNT_V 0x7 +#define UART_TX_MEM_CNT_S 3 +/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: refer to the rxfifo_cnt's describtion.*/ +#define UART_RX_MEM_CNT 0x00000007 +#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S)) +#define UART_RX_MEM_CNT_V 0x7 +#define UART_RX_MEM_CNT_S 0 + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68) +/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the count of rxd posedge edge. it is used + in boudrate-detect process.*/ +#define UART_POSEDGE_MIN_CNT 0x000FFFFF +#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) +#define UART_POSEDGE_MIN_CNT_V 0xFFFFF +#define UART_POSEDGE_MIN_CNT_S 0 + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) +/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the count of rxd negedge edge. it is used + in boudrate-detect process.*/ +#define UART_NEGEDGE_MIN_CNT 0x000FFFFF +#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) +#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78) +/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */ +/*description: */ +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C) +/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ +/*description: */ +#define UART_ID 0xFFFFFFFF +#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) +#define UART_ID_V 0xFFFFFFFF +#define UART_ID_S 0 + + + + +#endif /*__UART_REG_H__ */ + + diff --git a/tools/sdk/include/soc/include/soc/uart_struct.h b/tools/sdk/include/soc/include/soc/uart_struct.h new file mode 100644 index 00000000000..4efd6cf9011 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/uart_struct.h @@ -0,0 +1,383 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UART_STRUCT_H_ +#define _SOC_UART_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/ + uint8_t reserved[3]; + }; + uint32_t val; + } fifo; + union { + struct { + uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ + uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ + uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ + uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ + uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ + uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ + uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ + uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ + uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ + uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ + uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ + uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ + uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ + uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ + uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ + uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ + uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ + uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ + uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ + uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ + uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ + uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ + uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ + uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ + uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ + uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ + uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ + uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ + uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ + uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ + uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ + uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ + uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ + uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ + uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/ + uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/ + uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ + uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/ + uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/ + uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/ + uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ + uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/ + uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/ + uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/ + uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ + uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ + uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/ + uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/ + uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ + uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ + uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ + uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ + uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ + uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ + uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ + uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ + uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ + uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ + uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ + uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ + uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ + uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ + uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ + uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ + uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/ + uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } clk_div; + union { + struct { + uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/ + uint32_t reserved1: 7; + uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } auto_baud; + union { + struct { + uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ + uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ + uint32_t reserved12: 1; + uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/ + uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/ + uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/ + uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ + uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ + uint32_t reserved28: 1; + uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ + uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/ + uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/ + uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ + uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ + uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ + uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ + uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ + uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ + uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/ + uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ + uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ + uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ + uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/ + uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/ + uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/ + uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/ + uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/ + uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/ + uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ + uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ + uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ + uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ + uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ + uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ + uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/ + uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/ + uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ + uint32_t reserved7: 1; + uint32_t txfifo_empty_thrhd: 7; /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ + uint32_t reserved15: 1; + uint32_t rx_flow_thrhd: 7; /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/ + uint32_t rx_tout_thrhd: 7; /*This register is used to configure the timeout value for uart receiver receiving a byte.*/ + uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } lowpulse; + union { + struct { + uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } highpulse; + union { + struct { + uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } rxd_cnt; + union { + struct { + uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/ + uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ + uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/ + uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/ + uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/ + uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } flow_conf; + union { + struct { + uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sleep_conf; + union { + struct { + uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/ + uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/ + uint32_t xon_char: 8; /*This register stores the xon flow control char.*/ + uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/ + }; + uint32_t val; + } swfc_conf; + union { + struct { + uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/ + uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ + uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } idle_conf; + union { + struct { + uint32_t en: 1; /*Set this bit to choose rs485 mode.*/ + uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ + uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ + uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ + uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } rs485_conf; + union { + struct { + uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } at_cmd_precnt; + union { + struct { + uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } at_cmd_postcnt; + union { + struct { + uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } at_cmd_gaptout; + union { + struct { + uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/ + uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } at_cmd_char; + union { + struct { + uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/ + uint32_t reserved1: 1; + uint32_t reserved2: 1; + uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/ + uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/ + uint32_t reserved11: 4; + uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/ + uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/ + uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/ + uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/ + uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/ + uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } mem_conf; + union { + struct { + uint32_t status:24; + uint32_t reserved24: 8; + }; + uint32_t val; + } mem_tx_status; + union { + struct { + uint32_t status: 24; + uint32_t reserved24: 8; + }; + struct { + uint32_t reserved0: 2; + uint32_t rd_addr: 11; /*This register stores the rx mem read address.*/ + uint32_t wr_addr: 11; /*This register stores the rx mem write address.*/ + uint32_t reserved: 8; + }; + uint32_t val; + } mem_rx_status; + union { + struct { + uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/ + uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } mem_cnt_status; + union { + struct { + uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } pospulse; + union { + struct { + uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } negpulse; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t date; /**/ + uint32_t id; /**/ +} uart_dev_t; +extern uart_dev_t UART0; +extern uart_dev_t UART1; +extern uart_dev_t UART2; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_UART_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/uhci_reg.h b/tools/sdk/include/soc/include/soc/uhci_reg.h new file mode 100644 index 00000000000..973c6b58929 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/uhci_reg.h @@ -0,0 +1,1260 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UHCI_REG_H_ +#define _SOC_UHCI_REG_H_ + + +#include "soc.h" +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) +/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to enable to use brk char as the end of a data frame.*/ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(23)) +#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(23)) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x1 +#define UHCI_UART_RX_BRK_EOF_EN_S 23 +/* UHCI_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to enable clock-gating for read or write registers.*/ +#define UHCI_CLK_EN (BIT(22)) +#define UHCI_CLK_EN_M (BIT(22)) +#define UHCI_CLK_EN_V 0x1 +#define UHCI_CLK_EN_S 22 +/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Set this bit to enable crc calculation for data frame when bit6 + in the head packet is 1.*/ +#define UHCI_ENCODE_CRC_EN (BIT(21)) +#define UHCI_ENCODE_CRC_EN_M (BIT(21)) +#define UHCI_ENCODE_CRC_EN_V 0x1 +#define UHCI_ENCODE_CRC_EN_S 21 +/* UHCI_LEN_EOF_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to enable to use packet_len in packet head when + the received data is equal to packet_len this means the end of a data frame.*/ +#define UHCI_LEN_EOF_EN (BIT(20)) +#define UHCI_LEN_EOF_EN_M (BIT(20)) +#define UHCI_LEN_EOF_EN_V 0x1 +#define UHCI_LEN_EOF_EN_S 20 +/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to enable to use idle time when the idle time after + data frame is satisfied this means the end of a data frame.*/ +#define UHCI_UART_IDLE_EOF_EN (BIT(19)) +#define UHCI_UART_IDLE_EOF_EN_M (BIT(19)) +#define UHCI_UART_IDLE_EOF_EN_V 0x1 +#define UHCI_UART_IDLE_EOF_EN_S 19 +/* UHCI_CRC_REC_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: Set this bit to enable receiver''s ability of crc calculation + when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/ +#define UHCI_CRC_REC_EN (BIT(18)) +#define UHCI_CRC_REC_EN_M (BIT(18)) +#define UHCI_CRC_REC_EN_V 0x1 +#define UHCI_CRC_REC_EN_S 18 +/* UHCI_HEAD_EN : R/W ;bitpos:[17] ;default: 1'b1 ; */ +/*description: Set this bit to enable to use head packet before the data frame.*/ +#define UHCI_HEAD_EN (BIT(17)) +#define UHCI_HEAD_EN_M (BIT(17)) +#define UHCI_HEAD_EN_V 0x1 +#define UHCI_HEAD_EN_S 17 +/* UHCI_SEPER_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: Set this bit to use special char to separate the data frame.*/ +#define UHCI_SEPER_EN (BIT(16)) +#define UHCI_SEPER_EN_M (BIT(16)) +#define UHCI_SEPER_EN_V 0x1 +#define UHCI_SEPER_EN_S 16 +/* UHCI_MEM_TRANS_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_MEM_TRANS_EN (BIT(15)) +#define UHCI_MEM_TRANS_EN_M (BIT(15)) +#define UHCI_MEM_TRANS_EN_V 0x1 +#define UHCI_MEM_TRANS_EN_S 15 +/* UHCI_OUT_DATA_BURST_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable DMA burst MODE*/ +#define UHCI_OUT_DATA_BURST_EN (BIT(14)) +#define UHCI_OUT_DATA_BURST_EN_M (BIT(14)) +#define UHCI_OUT_DATA_BURST_EN_V 0x1 +#define UHCI_OUT_DATA_BURST_EN_S 14 +/* UHCI_INDSCR_BURST_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to enable DMA out links to use burst mode.*/ +#define UHCI_INDSCR_BURST_EN (BIT(13)) +#define UHCI_INDSCR_BURST_EN_M (BIT(13)) +#define UHCI_INDSCR_BURST_EN_V 0x1 +#define UHCI_INDSCR_BURST_EN_S 13 +/* UHCI_OUTDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable DMA in links to use burst mode.*/ +#define UHCI_OUTDSCR_BURST_EN (BIT(12)) +#define UHCI_OUTDSCR_BURST_EN_M (BIT(12)) +#define UHCI_OUTDSCR_BURST_EN_V 0x1 +#define UHCI_OUTDSCR_BURST_EN_S 12 +/* UHCI_UART2_CE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to use UART2 to transmit or receive data.*/ +#define UHCI_UART2_CE (BIT(11)) +#define UHCI_UART2_CE_M (BIT(11)) +#define UHCI_UART2_CE_V 0x1 +#define UHCI_UART2_CE_S 11 +/* UHCI_UART1_CE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to use UART1 to transmit or receive data.*/ +#define UHCI_UART1_CE (BIT(10)) +#define UHCI_UART1_CE_M (BIT(10)) +#define UHCI_UART1_CE_V 0x1 +#define UHCI_UART1_CE_S 10 +/* UHCI_UART0_CE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to use UART to transmit or receive data.*/ +#define UHCI_UART0_CE (BIT(9)) +#define UHCI_UART0_CE_M (BIT(9)) +#define UHCI_UART0_CE_V 0x1 +#define UHCI_UART0_CE_S 9 +/* UHCI_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Set this bit to produce eof after DMA pops all data clear this + bit to produce eof after DMA pushes all data*/ +#define UHCI_OUT_EOF_MODE (BIT(8)) +#define UHCI_OUT_EOF_MODE_M (BIT(8)) +#define UHCI_OUT_EOF_MODE_V 0x1 +#define UHCI_OUT_EOF_MODE_S 8 +/* UHCI_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: don't use*/ +#define UHCI_OUT_NO_RESTART_CLR (BIT(7)) +#define UHCI_OUT_NO_RESTART_CLR_M (BIT(7)) +#define UHCI_OUT_NO_RESTART_CLR_V 0x1 +#define UHCI_OUT_NO_RESTART_CLR_S 7 +/* UHCI_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: when in link's length is 0 go on to use the next in link automatically.*/ +#define UHCI_OUT_AUTO_WRBACK (BIT(6)) +#define UHCI_OUT_AUTO_WRBACK_M (BIT(6)) +#define UHCI_OUT_AUTO_WRBACK_V 0x1 +#define UHCI_OUT_AUTO_WRBACK_S 6 +/* UHCI_OUT_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable loop test for out links.*/ +#define UHCI_OUT_LOOP_TEST (BIT(5)) +#define UHCI_OUT_LOOP_TEST_M (BIT(5)) +#define UHCI_OUT_LOOP_TEST_V 0x1 +#define UHCI_OUT_LOOP_TEST_S 5 +/* UHCI_IN_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable loop test for in links.*/ +#define UHCI_IN_LOOP_TEST (BIT(4)) +#define UHCI_IN_LOOP_TEST_M (BIT(4)) +#define UHCI_IN_LOOP_TEST_V 0x1 +#define UHCI_IN_LOOP_TEST_S 4 +/* UHCI_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset dma ahb interface.*/ +#define UHCI_AHBM_RST (BIT(3)) +#define UHCI_AHBM_RST_M (BIT(3)) +#define UHCI_AHBM_RST_V 0x1 +#define UHCI_AHBM_RST_S 3 +/* UHCI_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to reset dma ahb fifo.*/ +#define UHCI_AHBM_FIFO_RST (BIT(2)) +#define UHCI_AHBM_FIFO_RST_M (BIT(2)) +#define UHCI_AHBM_FIFO_RST_V 0x1 +#define UHCI_AHBM_FIFO_RST_S 2 +/* UHCI_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to reset out link operations.*/ +#define UHCI_OUT_RST (BIT(1)) +#define UHCI_OUT_RST_M (BIT(1)) +#define UHCI_OUT_RST_V 0x1 +#define UHCI_OUT_RST_S 1 +/* UHCI_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to reset in link operations.*/ +#define UHCI_IN_RST (BIT(0)) +#define UHCI_IN_RST_M (BIT(0)) +#define UHCI_IN_RST_V 0x1 +#define UHCI_IN_RST_S 0 + +#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) +/* UHCI_DMA_INFIFO_FULL_WM_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_M (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_V 0x1 +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_S 16 +/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: When use always_send registers to send a series of short packets + it will produce this interrupt when dma has send the short packet.*/ +#define UHCI_SEND_A_Q_INT_RAW (BIT(15)) +#define UHCI_SEND_A_Q_INT_RAW_M (BIT(15)) +#define UHCI_SEND_A_Q_INT_RAW_V 0x1 +#define UHCI_SEND_A_Q_INT_RAW_S 15 +/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: When use single send registers to send a short packets it will + produce this interrupt when dma has send the short packet.*/ +#define UHCI_SEND_S_Q_INT_RAW (BIT(14)) +#define UHCI_SEND_S_Q_INT_RAW_M (BIT(14)) +#define UHCI_SEND_S_Q_INT_RAW_V 0x1 +#define UHCI_SEND_S_Q_INT_RAW_S 14 +/* UHCI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ +#define UHCI_OUT_TOTAL_EOF_INT_RAW (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_RAW_M (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_RAW_V 0x1 +#define UHCI_OUT_TOTAL_EOF_INT_RAW_S 13 +/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: when there are some errors about eof in outlink descriptor it + will produce uhci_outlink_eof_err_int interrupt.*/ +#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 12 +/* UHCI_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: when there are not enough in links for DMA it will produce uhci_in_dscr_err_int + interrupt.*/ +#define UHCI_IN_DSCR_EMPTY_INT_RAW (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_RAW_M (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_RAW_V 0x1 +#define UHCI_IN_DSCR_EMPTY_INT_RAW_S 11 +/* UHCI_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: when there are some errors about the in link descriptor it will + produce uhci_out_dscr_err_int interrupt.*/ +#define UHCI_OUT_DSCR_ERR_INT_RAW (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_RAW_M (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_RAW_V 0x1 +#define UHCI_OUT_DSCR_ERR_INT_RAW_S 10 +/* UHCI_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: when there are some errors about the out link descriptor it + will produce uhci_in_dscr_err_int interrupt.*/ +#define UHCI_IN_DSCR_ERR_INT_RAW (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_RAW_M (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_RAW_V 0x1 +#define UHCI_IN_DSCR_ERR_INT_RAW_S 9 +/* UHCI_OUT_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int + interrupt.*/ +#define UHCI_OUT_EOF_INT_RAW (BIT(8)) +#define UHCI_OUT_EOF_INT_RAW_M (BIT(8)) +#define UHCI_OUT_EOF_INT_RAW_V 0x1 +#define UHCI_OUT_EOF_INT_RAW_S 8 +/* UHCI_OUT_DONE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: when a out link descriptor is completed it will produce uhci_out_done_int + interrupt.*/ +#define UHCI_OUT_DONE_INT_RAW (BIT(7)) +#define UHCI_OUT_DONE_INT_RAW_M (BIT(7)) +#define UHCI_OUT_DONE_INT_RAW_V 0x1 +#define UHCI_OUT_DONE_INT_RAW_S 7 +/* UHCI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: when there are some errors about eof in in link descriptor it + will produce uhci_in_err_eof_int interrupt.*/ +#define UHCI_IN_ERR_EOF_INT_RAW (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_RAW_M (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_RAW_V 0x1 +#define UHCI_IN_ERR_EOF_INT_RAW_S 6 +/* UHCI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: when a data packet has been received it will produce uhci_in_suc_eof_int + interrupt.*/ +#define UHCI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_RAW_M (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_RAW_V 0x1 +#define UHCI_IN_SUC_EOF_INT_RAW_S 5 +/* UHCI_IN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: when a in link descriptor has been completed it will produce + uhci_in_done_int interrupt.*/ +#define UHCI_IN_DONE_INT_RAW (BIT(4)) +#define UHCI_IN_DONE_INT_RAW_M (BIT(4)) +#define UHCI_IN_DONE_INT_RAW_V 0x1 +#define UHCI_IN_DONE_INT_RAW_S 4 +/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: when DMA takes a lot of time to read a data from RAM it will + produce uhci_tx_hung_int interrupt.*/ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_V 0x1 +#define UHCI_TX_HUNG_INT_RAW_S 3 +/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: when DMA takes a lot of time to receive a data it will produce + uhci_rx_hung_int interrupt.*/ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_V 0x1 +#define UHCI_RX_HUNG_INT_RAW_S 2 +/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (BIT(1)) +#define UHCI_TX_START_INT_RAW_V 0x1 +#define UHCI_TX_START_INT_RAW_S 1 +/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: when a separator char has been send it will produce uhci_rx_start_int + interrupt.*/ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (BIT(0)) +#define UHCI_RX_START_INT_RAW_V 0x1 +#define UHCI_RX_START_INT_RAW_S 0 + +#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) +/* UHCI_DMA_INFIFO_FULL_WM_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_M (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_V 0x1 +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_S 16 +/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_ST (BIT(15)) +#define UHCI_SEND_A_Q_INT_ST_M (BIT(15)) +#define UHCI_SEND_A_Q_INT_ST_V 0x1 +#define UHCI_SEND_A_Q_INT_ST_S 15 +/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_ST (BIT(14)) +#define UHCI_SEND_S_Q_INT_ST_M (BIT(14)) +#define UHCI_SEND_S_Q_INT_ST_V 0x1 +#define UHCI_SEND_S_Q_INT_ST_S 14 +/* UHCI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_TOTAL_EOF_INT_ST (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ST_M (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ST_V 0x1 +#define UHCI_OUT_TOTAL_EOF_INT_ST_S 13 +/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 12 +/* UHCI_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_EMPTY_INT_ST (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ST_M (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ST_V 0x1 +#define UHCI_IN_DSCR_EMPTY_INT_ST_S 11 +/* UHCI_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DSCR_ERR_INT_ST (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ST_M (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ST_V 0x1 +#define UHCI_OUT_DSCR_ERR_INT_ST_S 10 +/* UHCI_IN_DSCR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_ERR_INT_ST (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ST_M (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ST_V 0x1 +#define UHCI_IN_DSCR_ERR_INT_ST_S 9 +/* UHCI_OUT_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_EOF_INT_ST (BIT(8)) +#define UHCI_OUT_EOF_INT_ST_M (BIT(8)) +#define UHCI_OUT_EOF_INT_ST_V 0x1 +#define UHCI_OUT_EOF_INT_ST_S 8 +/* UHCI_OUT_DONE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DONE_INT_ST (BIT(7)) +#define UHCI_OUT_DONE_INT_ST_M (BIT(7)) +#define UHCI_OUT_DONE_INT_ST_V 0x1 +#define UHCI_OUT_DONE_INT_ST_S 7 +/* UHCI_IN_ERR_EOF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_ERR_EOF_INT_ST (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ST_M (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ST_V 0x1 +#define UHCI_IN_ERR_EOF_INT_ST_S 6 +/* UHCI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_SUC_EOF_INT_ST (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ST_M (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ST_V 0x1 +#define UHCI_IN_SUC_EOF_INT_ST_S 5 +/* UHCI_IN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DONE_INT_ST (BIT(4)) +#define UHCI_IN_DONE_INT_ST_M (BIT(4)) +#define UHCI_IN_DONE_INT_ST_V 0x1 +#define UHCI_IN_DONE_INT_ST_S 4 +/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_V 0x1 +#define UHCI_TX_HUNG_INT_ST_S 3 +/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_V 0x1 +#define UHCI_RX_HUNG_INT_ST_S 2 +/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (BIT(1)) +#define UHCI_TX_START_INT_ST_V 0x1 +#define UHCI_TX_START_INT_ST_S 1 +/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (BIT(0)) +#define UHCI_RX_START_INT_ST_V 0x1 +#define UHCI_RX_START_INT_ST_S 0 + +#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC) +/* UHCI_DMA_INFIFO_FULL_WM_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_M (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_V 0x1 +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_S 16 +/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_ENA (BIT(15)) +#define UHCI_SEND_A_Q_INT_ENA_M (BIT(15)) +#define UHCI_SEND_A_Q_INT_ENA_V 0x1 +#define UHCI_SEND_A_Q_INT_ENA_S 15 +/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_ENA (BIT(14)) +#define UHCI_SEND_S_Q_INT_ENA_M (BIT(14)) +#define UHCI_SEND_S_Q_INT_ENA_V 0x1 +#define UHCI_SEND_S_Q_INT_ENA_S 14 +/* UHCI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_TOTAL_EOF_INT_ENA (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ENA_M (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ENA_V 0x1 +#define UHCI_OUT_TOTAL_EOF_INT_ENA_S 13 +/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 12 +/* UHCI_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_EMPTY_INT_ENA (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ENA_M (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ENA_V 0x1 +#define UHCI_IN_DSCR_EMPTY_INT_ENA_S 11 +/* UHCI_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DSCR_ERR_INT_ENA (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ENA_M (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ENA_V 0x1 +#define UHCI_OUT_DSCR_ERR_INT_ENA_S 10 +/* UHCI_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_ERR_INT_ENA (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ENA_M (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ENA_V 0x1 +#define UHCI_IN_DSCR_ERR_INT_ENA_S 9 +/* UHCI_OUT_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_EOF_INT_ENA (BIT(8)) +#define UHCI_OUT_EOF_INT_ENA_M (BIT(8)) +#define UHCI_OUT_EOF_INT_ENA_V 0x1 +#define UHCI_OUT_EOF_INT_ENA_S 8 +/* UHCI_OUT_DONE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DONE_INT_ENA (BIT(7)) +#define UHCI_OUT_DONE_INT_ENA_M (BIT(7)) +#define UHCI_OUT_DONE_INT_ENA_V 0x1 +#define UHCI_OUT_DONE_INT_ENA_S 7 +/* UHCI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_ERR_EOF_INT_ENA (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ENA_M (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ENA_V 0x1 +#define UHCI_IN_ERR_EOF_INT_ENA_S 6 +/* UHCI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ENA_M (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ENA_V 0x1 +#define UHCI_IN_SUC_EOF_INT_ENA_S 5 +/* UHCI_IN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DONE_INT_ENA (BIT(4)) +#define UHCI_IN_DONE_INT_ENA_M (BIT(4)) +#define UHCI_IN_DONE_INT_ENA_V 0x1 +#define UHCI_IN_DONE_INT_ENA_S 4 +/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_V 0x1 +#define UHCI_TX_HUNG_INT_ENA_S 3 +/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_V 0x1 +#define UHCI_RX_HUNG_INT_ENA_S 2 +/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (BIT(1)) +#define UHCI_TX_START_INT_ENA_V 0x1 +#define UHCI_TX_START_INT_ENA_S 1 +/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (BIT(0)) +#define UHCI_RX_START_INT_ENA_V 0x1 +#define UHCI_RX_START_INT_ENA_S 0 + +#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) +/* UHCI_DMA_INFIFO_FULL_WM_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_M (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_V 0x1 +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_S 16 +/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_CLR (BIT(15)) +#define UHCI_SEND_A_Q_INT_CLR_M (BIT(15)) +#define UHCI_SEND_A_Q_INT_CLR_V 0x1 +#define UHCI_SEND_A_Q_INT_CLR_S 15 +/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_CLR (BIT(14)) +#define UHCI_SEND_S_Q_INT_CLR_M (BIT(14)) +#define UHCI_SEND_S_Q_INT_CLR_V 0x1 +#define UHCI_SEND_S_Q_INT_CLR_S 14 +/* UHCI_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_TOTAL_EOF_INT_CLR (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_CLR_M (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_CLR_V 0x1 +#define UHCI_OUT_TOTAL_EOF_INT_CLR_S 13 +/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 12 +/* UHCI_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_EMPTY_INT_CLR (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_CLR_M (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_CLR_V 0x1 +#define UHCI_IN_DSCR_EMPTY_INT_CLR_S 11 +/* UHCI_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DSCR_ERR_INT_CLR (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_CLR_M (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_CLR_V 0x1 +#define UHCI_OUT_DSCR_ERR_INT_CLR_S 10 +/* UHCI_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_ERR_INT_CLR (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_CLR_M (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_CLR_V 0x1 +#define UHCI_IN_DSCR_ERR_INT_CLR_S 9 +/* UHCI_OUT_EOF_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_EOF_INT_CLR (BIT(8)) +#define UHCI_OUT_EOF_INT_CLR_M (BIT(8)) +#define UHCI_OUT_EOF_INT_CLR_V 0x1 +#define UHCI_OUT_EOF_INT_CLR_S 8 +/* UHCI_OUT_DONE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DONE_INT_CLR (BIT(7)) +#define UHCI_OUT_DONE_INT_CLR_M (BIT(7)) +#define UHCI_OUT_DONE_INT_CLR_V 0x1 +#define UHCI_OUT_DONE_INT_CLR_S 7 +/* UHCI_IN_ERR_EOF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_ERR_EOF_INT_CLR (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_CLR_M (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_CLR_V 0x1 +#define UHCI_IN_ERR_EOF_INT_CLR_S 6 +/* UHCI_IN_SUC_EOF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_CLR_M (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_CLR_V 0x1 +#define UHCI_IN_SUC_EOF_INT_CLR_S 5 +/* UHCI_IN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DONE_INT_CLR (BIT(4)) +#define UHCI_IN_DONE_INT_CLR_M (BIT(4)) +#define UHCI_IN_DONE_INT_CLR_V 0x1 +#define UHCI_IN_DONE_INT_CLR_S 4 +/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_V 0x1 +#define UHCI_TX_HUNG_INT_CLR_S 3 +/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_V 0x1 +#define UHCI_RX_HUNG_INT_CLR_S 2 +/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (BIT(1)) +#define UHCI_TX_START_INT_CLR_V 0x1 +#define UHCI_TX_START_INT_CLR_S 1 +/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (BIT(0)) +#define UHCI_RX_START_INT_CLR_V 0x1 +#define UHCI_RX_START_INT_CLR_S 0 + +#define UHCI_DMA_OUT_STATUS_REG(i) (REG_UHCI_BASE(i) + 0x14) +/* UHCI_OUT_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: 1:DMA in link descriptor's fifo is empty.*/ +#define UHCI_OUT_EMPTY (BIT(1)) +#define UHCI_OUT_EMPTY_M (BIT(1)) +#define UHCI_OUT_EMPTY_V 0x1 +#define UHCI_OUT_EMPTY_S 1 +/* UHCI_OUT_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1:DMA out link descriptor's fifo is full.*/ +#define UHCI_OUT_FULL (BIT(0)) +#define UHCI_OUT_FULL_M (BIT(0)) +#define UHCI_OUT_FULL_V 0x1 +#define UHCI_OUT_FULL_S 0 + +#define UHCI_DMA_OUT_PUSH_REG(i) (REG_UHCI_BASE(i) + 0x18) +/* UHCI_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to push data in out link descriptor's fifo.*/ +#define UHCI_OUTFIFO_PUSH (BIT(16)) +#define UHCI_OUTFIFO_PUSH_M (BIT(16)) +#define UHCI_OUTFIFO_PUSH_V 0x1 +#define UHCI_OUTFIFO_PUSH_S 16 +/* UHCI_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This is the data need to be pushed into out link descriptor's fifo.*/ +#define UHCI_OUTFIFO_WDATA 0x000001FF +#define UHCI_OUTFIFO_WDATA_M ((UHCI_OUTFIFO_WDATA_V)<<(UHCI_OUTFIFO_WDATA_S)) +#define UHCI_OUTFIFO_WDATA_V 0x1FF +#define UHCI_OUTFIFO_WDATA_S 0 + +#define UHCI_DMA_IN_STATUS_REG(i) (REG_UHCI_BASE(i) + 0x1C) +/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: This register stores the errors caused in out link descriptor's data packet.*/ +#define UHCI_RX_ERR_CAUSE 0x00000007 +#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S)) +#define UHCI_RX_ERR_CAUSE_V 0x7 +#define UHCI_RX_ERR_CAUSE_S 4 +/* UHCI_IN_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_IN_EMPTY (BIT(1)) +#define UHCI_IN_EMPTY_M (BIT(1)) +#define UHCI_IN_EMPTY_V 0x1 +#define UHCI_IN_EMPTY_S 1 +/* UHCI_IN_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_FULL (BIT(0)) +#define UHCI_IN_FULL_M (BIT(0)) +#define UHCI_IN_FULL_V 0x1 +#define UHCI_IN_FULL_S 0 + +#define UHCI_DMA_IN_POP_REG(i) (REG_UHCI_BASE(i) + 0x20) +/* UHCI_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to pop data in in link descriptor's fifo.*/ +#define UHCI_INFIFO_POP (BIT(16)) +#define UHCI_INFIFO_POP_M (BIT(16)) +#define UHCI_INFIFO_POP_V 0x1 +#define UHCI_INFIFO_POP_S 16 +/* UHCI_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: This register stores the data pop from in link descriptor's fifo.*/ +#define UHCI_INFIFO_RDATA 0x00000FFF +#define UHCI_INFIFO_RDATA_M ((UHCI_INFIFO_RDATA_V)<<(UHCI_INFIFO_RDATA_S)) +#define UHCI_INFIFO_RDATA_V 0xFFF +#define UHCI_INFIFO_RDATA_S 0 + +#define UHCI_DMA_OUT_LINK_REG(i) (REG_UHCI_BASE(i) + 0x24) +/* UHCI_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: 1£º the out link descriptor's fsm is in idle state. 0:the out + link descriptor's fsm is working.*/ +#define UHCI_OUTLINK_PARK (BIT(31)) +#define UHCI_OUTLINK_PARK_M (BIT(31)) +#define UHCI_OUTLINK_PARK_V 0x1 +#define UHCI_OUTLINK_PARK_S 31 +/* UHCI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to mount on new out link descriptors*/ +#define UHCI_OUTLINK_RESTART (BIT(30)) +#define UHCI_OUTLINK_RESTART_M (BIT(30)) +#define UHCI_OUTLINK_RESTART_V 0x1 +#define UHCI_OUTLINK_RESTART_S 30 +/* UHCI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the out link descriptors.*/ +#define UHCI_OUTLINK_START (BIT(29)) +#define UHCI_OUTLINK_START_M (BIT(29)) +#define UHCI_OUTLINK_START_V 0x1 +#define UHCI_OUTLINK_START_S 29 +/* UHCI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the out link descriptors.*/ +#define UHCI_OUTLINK_STOP (BIT(28)) +#define UHCI_OUTLINK_STOP_M (BIT(28)) +#define UHCI_OUTLINK_STOP_V 0x1 +#define UHCI_OUTLINK_STOP_S 28 +/* UHCI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the least 20 bits of the first out link + descriptor's address.*/ +#define UHCI_OUTLINK_ADDR 0x000FFFFF +#define UHCI_OUTLINK_ADDR_M ((UHCI_OUTLINK_ADDR_V)<<(UHCI_OUTLINK_ADDR_S)) +#define UHCI_OUTLINK_ADDR_V 0xFFFFF +#define UHCI_OUTLINK_ADDR_S 0 + +#define UHCI_DMA_IN_LINK_REG(i) (REG_UHCI_BASE(i) + 0x28) +/* UHCI_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: 1:the in link descriptor's fsm is in idle state. 0:the in link + descriptor's fsm is working*/ +#define UHCI_INLINK_PARK (BIT(31)) +#define UHCI_INLINK_PARK_M (BIT(31)) +#define UHCI_INLINK_PARK_V 0x1 +#define UHCI_INLINK_PARK_S 31 +/* UHCI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to mount on new in link descriptors*/ +#define UHCI_INLINK_RESTART (BIT(30)) +#define UHCI_INLINK_RESTART_M (BIT(30)) +#define UHCI_INLINK_RESTART_V 0x1 +#define UHCI_INLINK_RESTART_S 30 +/* UHCI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the in link descriptors.*/ +#define UHCI_INLINK_START (BIT(29)) +#define UHCI_INLINK_START_M (BIT(29)) +#define UHCI_INLINK_START_V 0x1 +#define UHCI_INLINK_START_S 29 +/* UHCI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the in link descriptors.*/ +#define UHCI_INLINK_STOP (BIT(28)) +#define UHCI_INLINK_STOP_M (BIT(28)) +#define UHCI_INLINK_STOP_V 0x1 +#define UHCI_INLINK_STOP_S 28 +/* UHCI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: 1:when a packet is wrong in link descriptor returns to the descriptor + which is lately used.*/ +#define UHCI_INLINK_AUTO_RET (BIT(20)) +#define UHCI_INLINK_AUTO_RET_M (BIT(20)) +#define UHCI_INLINK_AUTO_RET_V 0x1 +#define UHCI_INLINK_AUTO_RET_S 20 +/* UHCI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the least 20 bits of the first in link descriptor's + address.*/ +#define UHCI_INLINK_ADDR 0x000FFFFF +#define UHCI_INLINK_ADDR_M ((UHCI_INLINK_ADDR_V)<<(UHCI_INLINK_ADDR_S)) +#define UHCI_INLINK_ADDR_V 0xFFFFF +#define UHCI_INLINK_ADDR_S 0 + +#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x2C) +/* UHCI_DMA_INFIFO_FULL_THRS : R/W ;bitpos:[20:9] ;default: 12'b0 ; */ +/*description: when data amount in link descriptor's fifo is more than this + register value it will produce uhci_dma_infifo_full_wm_int interrupt.*/ +#define UHCI_DMA_INFIFO_FULL_THRS 0x00000FFF +#define UHCI_DMA_INFIFO_FULL_THRS_M ((UHCI_DMA_INFIFO_FULL_THRS_V)<<(UHCI_DMA_INFIFO_FULL_THRS_S)) +#define UHCI_DMA_INFIFO_FULL_THRS_V 0xFFF +#define UHCI_DMA_INFIFO_FULL_THRS_S 9 +/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to start inserting the packet header.*/ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (BIT(8)) +#define UHCI_SW_START_V 0x1 +#define UHCI_SW_START_S 8 +/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable software way to add packet header.*/ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (BIT(7)) +#define UHCI_WAIT_SW_START_V 0x1 +#define UHCI_WAIT_SW_START_S 7 +/* UHCI_CHECK_OWNER : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to check the owner bit in link descriptor.*/ +#define UHCI_CHECK_OWNER (BIT(6)) +#define UHCI_CHECK_OWNER_M (BIT(6)) +#define UHCI_CHECK_OWNER_V 0x1 +#define UHCI_CHECK_OWNER_S 6 +/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: Set this bit to enable hardware replace ack num in packet header automatically.*/ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_V 0x1 +#define UHCI_TX_ACK_NUM_RE_S 5 +/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: Set this bit to enable hardware replace check_sum in packet header + automatically.*/ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_V 0x1 +#define UHCI_TX_CHECK_SUM_RE_S 4 +/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to save packet header .*/ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (BIT(3)) +#define UHCI_SAVE_HEAD_V 0x1 +#define UHCI_SAVE_HEAD_S 3 +/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to disable crc calculation.*/ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (BIT(2)) +#define UHCI_CRC_DISABLE_V 0x1 +#define UHCI_CRC_DISABLE_S 2 +/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Set this bit to enable decoder to check seq num in packet header.*/ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (BIT(1)) +#define UHCI_CHECK_SEQ_EN_V 0x1 +#define UHCI_CHECK_SEQ_EN_S 1 +/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Set this bit to enable decoder to check check_sum in packet header.*/ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (BIT(0)) +#define UHCI_CHECK_SUM_EN_V 0x1 +#define UHCI_CHECK_SUM_EN_S 0 + +#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x30) +/* UHCI_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_STATE0 0xFFFFFFFF +#define UHCI_STATE0_M ((UHCI_STATE0_V)<<(UHCI_STATE0_S)) +#define UHCI_STATE0_V 0xFFFFFFFF +#define UHCI_STATE0_S 0 + +#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x34) +/* UHCI_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_STATE1 0xFFFFFFFF +#define UHCI_STATE1_M ((UHCI_STATE1_V)<<(UHCI_STATE1_S)) +#define UHCI_STATE1_V 0xFFFFFFFF +#define UHCI_STATE1_S 0 + +#define UHCI_DMA_OUT_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x38) +/* UHCI_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of out link descriptoir when + eof bit in this descriptor is 1.*/ +#define UHCI_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define UHCI_OUT_EOF_DES_ADDR_M ((UHCI_OUT_EOF_DES_ADDR_V)<<(UHCI_OUT_EOF_DES_ADDR_S)) +#define UHCI_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define UHCI_OUT_EOF_DES_ADDR_S 0 + +#define UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x3C) +/* UHCI_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of in link descriptor when eof + bit in this descriptor is 1.*/ +#define UHCI_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define UHCI_IN_SUC_EOF_DES_ADDR_M ((UHCI_IN_SUC_EOF_DES_ADDR_V)<<(UHCI_IN_SUC_EOF_DES_ADDR_S)) +#define UHCI_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define UHCI_IN_SUC_EOF_DES_ADDR_S 0 + +#define UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x40) +/* UHCI_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of in link descriptor when there + are some errors in this descriptor.*/ +#define UHCI_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define UHCI_IN_ERR_EOF_DES_ADDR_M ((UHCI_IN_ERR_EOF_DES_ADDR_V)<<(UHCI_IN_ERR_EOF_DES_ADDR_S)) +#define UHCI_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define UHCI_IN_ERR_EOF_DES_ADDR_S 0 + +#define UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x44) +/* UHCI_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of out link descriptor when + there are some errors in this descriptor.*/ +#define UHCI_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define UHCI_OUT_EOF_BFR_DES_ADDR_M ((UHCI_OUT_EOF_BFR_DES_ADDR_V)<<(UHCI_OUT_EOF_BFR_DES_ADDR_S)) +#define UHCI_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define UHCI_OUT_EOF_BFR_DES_ADDR_S 0 + +#define UHCI_AHB_TEST_REG(i) (REG_UHCI_BASE(i) + 0x48) +/* UHCI_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: The two bits represent ahb bus address bit[20:19]*/ +#define UHCI_AHB_TESTADDR 0x00000003 +#define UHCI_AHB_TESTADDR_M ((UHCI_AHB_TESTADDR_V)<<(UHCI_AHB_TESTADDR_S)) +#define UHCI_AHB_TESTADDR_V 0x3 +#define UHCI_AHB_TESTADDR_S 4 +/* UHCI_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) + or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ +#define UHCI_AHB_TESTMODE 0x00000007 +#define UHCI_AHB_TESTMODE_M ((UHCI_AHB_TESTMODE_V)<<(UHCI_AHB_TESTMODE_S)) +#define UHCI_AHB_TESTMODE_V 0x7 +#define UHCI_AHB_TESTMODE_S 0 + +#define UHCI_DMA_IN_DSCR_REG(i) (REG_UHCI_BASE(i) + 0x4C) +/* UHCI_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in link descriptor's third dword*/ +#define UHCI_INLINK_DSCR 0xFFFFFFFF +#define UHCI_INLINK_DSCR_M ((UHCI_INLINK_DSCR_V)<<(UHCI_INLINK_DSCR_S)) +#define UHCI_INLINK_DSCR_V 0xFFFFFFFF +#define UHCI_INLINK_DSCR_S 0 + +#define UHCI_DMA_IN_DSCR_BF0_REG(i) (REG_UHCI_BASE(i) + 0x50) +/* UHCI_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in link descriptor's first dword*/ +#define UHCI_INLINK_DSCR_BF0 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF0_M ((UHCI_INLINK_DSCR_BF0_V)<<(UHCI_INLINK_DSCR_BF0_S)) +#define UHCI_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF0_S 0 + +#define UHCI_DMA_IN_DSCR_BF1_REG(i) (REG_UHCI_BASE(i) + 0x54) +/* UHCI_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in link descriptor's second dword*/ +#define UHCI_INLINK_DSCR_BF1 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF1_M ((UHCI_INLINK_DSCR_BF1_V)<<(UHCI_INLINK_DSCR_BF1_S)) +#define UHCI_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF1_S 0 + +#define UHCI_DMA_OUT_DSCR_REG(i) (REG_UHCI_BASE(i) + 0x58) +/* UHCI_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out link descriptor's third dword*/ +#define UHCI_OUTLINK_DSCR 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_M ((UHCI_OUTLINK_DSCR_V)<<(UHCI_OUTLINK_DSCR_S)) +#define UHCI_OUTLINK_DSCR_V 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_S 0 + +#define UHCI_DMA_OUT_DSCR_BF0_REG(i) (REG_UHCI_BASE(i) + 0x5C) +/* UHCI_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out link descriptor's first dword*/ +#define UHCI_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF0_M ((UHCI_OUTLINK_DSCR_BF0_V)<<(UHCI_OUTLINK_DSCR_BF0_S)) +#define UHCI_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF0_S 0 + +#define UHCI_DMA_OUT_DSCR_BF1_REG(i) (REG_UHCI_BASE(i) + 0x60) +/* UHCI_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out link descriptor's second dword*/ +#define UHCI_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF1_M ((UHCI_OUTLINK_DSCR_BF1_V)<<(UHCI_OUTLINK_DSCR_BF1_S)) +#define UHCI_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF1_S 0 + +#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x64) +/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable flow control char 0x13 replace when DMA sends data.*/ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (BIT(7)) +#define UHCI_RX_13_ESC_EN_V 0x1 +#define UHCI_RX_13_ESC_EN_S 7 +/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to enable flow control char 0x11 replace when DMA sends data.*/ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (BIT(6)) +#define UHCI_RX_11_ESC_EN_V 0x1 +#define UHCI_RX_11_ESC_EN_S 6 +/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: Set this bit to enable 0xdb char replace when DMA sends data.*/ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (BIT(5)) +#define UHCI_RX_DB_ESC_EN_V 0x1 +#define UHCI_RX_DB_ESC_EN_S 5 +/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: Set this bit to enable 0xc0 char replace when DMA sends data.*/ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (BIT(4)) +#define UHCI_RX_C0_ESC_EN_V 0x1 +#define UHCI_RX_C0_ESC_EN_S 4 +/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable flow control char 0x13 decode when DMA receives data.*/ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (BIT(3)) +#define UHCI_TX_13_ESC_EN_V 0x1 +#define UHCI_TX_13_ESC_EN_S 3 +/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable flow control char 0x11 decode when DMA receives data.*/ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (BIT(2)) +#define UHCI_TX_11_ESC_EN_V 0x1 +#define UHCI_TX_11_ESC_EN_S 2 +/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Set this bit to enable 0xdb char decode when DMA receives data.*/ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (BIT(1)) +#define UHCI_TX_DB_ESC_EN_V 0x1 +#define UHCI_TX_DB_ESC_EN_S 1 +/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Set this bit to enable 0xc0 char decode when DMA receives data.*/ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (BIT(0)) +#define UHCI_TX_C0_ESC_EN_V 0x1 +#define UHCI_TX_C0_ESC_EN_S 0 + +#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x68) +/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: This is the enable bit for DMA send data timeout*/ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 +/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */ +/*description: This register stores the timeout value.when DMA takes more time + than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/ +#define UHCI_RXFIFO_TIMEOUT 0x000000FF +#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S)) +#define UHCI_RXFIFO_TIMEOUT_V 0xFF +#define UHCI_RXFIFO_TIMEOUT_S 12 +/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: The enable bit for txfifo receive data timeout*/ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ +/*description: This register stores the timeout value.when DMA takes more time + than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/ +#define UHCI_TXFIFO_TIMEOUT 0x000000FF +#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S)) +#define UHCI_TXFIFO_TIMEOUT_V 0xFF +#define UHCI_TXFIFO_TIMEOUT_S 0 + +#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x6C) + +#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x70) +/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the packet header received by DMA*/ +#define UHCI_RX_HEAD 0xFFFFFFFF +#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S)) +#define UHCI_RX_HEAD_V 0xFFFFFFFF +#define UHCI_RX_HEAD_S 0 + +#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x74) +/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable continuously send the same short packet*/ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_V 0x1 +#define UHCI_ALWAYS_SEND_EN_S 7 +/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: The bits are used to choose which short packet*/ +#define UHCI_ALWAYS_SEND_NUM 0x00000007 +#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S)) +#define UHCI_ALWAYS_SEND_NUM_V 0x7 +#define UHCI_ALWAYS_SEND_NUM_S 4 +/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable send a short packet*/ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (BIT(3)) +#define UHCI_SINGLE_SEND_EN_V 0x1 +#define UHCI_SINGLE_SEND_EN_S 3 +/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: The bits are used to choose which short packet*/ +#define UHCI_SINGLE_SEND_NUM 0x00000007 +#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S)) +#define UHCI_SINGLE_SEND_NUM_V 0x7 +#define UHCI_SINGLE_SEND_NUM_S 0 + +#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x78) +/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S)) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_S 0 + +#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x7C) +/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S)) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_S 0 + +#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x80) +/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S)) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_S 0 + +#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x84) +/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S)) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_S 0 + +#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x88) +/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S)) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_S 0 + +#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x8C) +/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S)) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_S 0 + +#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x90) +/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S)) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_S 0 + +#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x94) +/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S)) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_S 0 + +#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x98) +/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S)) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_S 0 + +#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x9C) +/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S)) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_S 0 + +#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0xA0) +/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S)) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_S 0 + +#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0xA4) +/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S)) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_S 0 + +#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0xA8) +/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S)) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_S 0 + +#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0xAC) +/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S)) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_S 0 + +#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0xB0) +/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */ +/*description: This register stores the second char used to replace seperator + char in data . 0xdc 0xdb replace 0xc0 by default.*/ +#define UHCI_SEPER_ESC_CHAR1 0x000000FF +#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S)) +#define UHCI_SEPER_ESC_CHAR1_V 0xFF +#define UHCI_SEPER_ESC_CHAR1_S 16 +/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: This register stores thee first char used to replace seperator char in data.*/ +#define UHCI_SEPER_ESC_CHAR0 0x000000FF +#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S)) +#define UHCI_SEPER_ESC_CHAR0_V 0xFF +#define UHCI_SEPER_ESC_CHAR0_S 8 +/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ +/*description: This register stores the seperator char seperator char is used + to seperate the data frame.*/ +#define UHCI_SEPER_CHAR 0x000000FF +#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S)) +#define UHCI_SEPER_CHAR_V 0xFF +#define UHCI_SEPER_CHAR_S 0 + +#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0xB4) +/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */ +/*description: This register stores the second char used to replace the reg_esc_seq0 in data*/ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FF +#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S)) +#define UHCI_ESC_SEQ0_CHAR1_V 0xFF +#define UHCI_ESC_SEQ0_CHAR1_S 16 +/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: This register stores the first char used to replace reg_esc_seq0 in data.*/ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FF +#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S)) +#define UHCI_ESC_SEQ0_CHAR0_V 0xFF +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */ +/*description: This register stores the first substitute char used to replace + the seperator char.*/ +#define UHCI_ESC_SEQ0 0x000000FF +#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S)) +#define UHCI_ESC_SEQ0_V 0xFF +#define UHCI_ESC_SEQ0_S 0 + +#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0xB8) +/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */ +/*description: This register stores the second char used to replace the reg_esc_seq1 in data.*/ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FF +#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S)) +#define UHCI_ESC_SEQ1_CHAR1_V 0xFF +#define UHCI_ESC_SEQ1_CHAR1_S 16 +/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: This register stores the first char used to replace the reg_esc_seq1 in data.*/ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FF +#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S)) +#define UHCI_ESC_SEQ1_CHAR0_V 0xFF +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */ +/*description: This register stores the flow control char to turn on the flow_control*/ +#define UHCI_ESC_SEQ1 0x000000FF +#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S)) +#define UHCI_ESC_SEQ1_V 0xFF +#define UHCI_ESC_SEQ1_S 0 + +#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0xBC) +/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */ +/*description: This register stores the second char used to replace the reg_esc_seq2 in data.*/ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FF +#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S)) +#define UHCI_ESC_SEQ2_CHAR1_V 0xFF +#define UHCI_ESC_SEQ2_CHAR1_S 16 +/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: This register stores the first char used to replace the reg_esc_seq2 in data.*/ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FF +#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S)) +#define UHCI_ESC_SEQ2_CHAR0_V 0xFF +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */ +/*description: This register stores the flow_control char to turn off the flow_control*/ +#define UHCI_ESC_SEQ2 0x000000FF +#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S)) +#define UHCI_ESC_SEQ2_V 0xFF +#define UHCI_ESC_SEQ2_S 0 + +#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0xC0) +/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */ +/*description: when the amount of packet payload is greater than this value + the process of receiving data is done.*/ +#define UHCI_PKT_THRS 0x00001FFF +#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S)) +#define UHCI_PKT_THRS_V 0x1FFF +#define UHCI_PKT_THRS_S 0 + +#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0xFC) +/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h16041001 ; */ +/*description: version information*/ +#define UHCI_DATE 0xFFFFFFFF +#define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S)) +#define UHCI_DATE_V 0xFFFFFFFF +#define UHCI_DATE_S 0 + + + + +#endif /*_SOC_UHCI_REG_H_ */ + + diff --git a/tools/sdk/include/soc/include/soc/uhci_struct.h b/tools/sdk/include/soc/include/soc/uhci_struct.h new file mode 100644 index 00000000000..543af215c44 --- /dev/null +++ b/tools/sdk/include/soc/include/soc/uhci_struct.h @@ -0,0 +1,349 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UHCI_STRUCT_H_ +#define _SOC_UHCI_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/ + uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/ + uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/ + uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/ + uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/ + uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/ + uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/ + uint32_t out_no_restart_clr: 1; /*don't use*/ + uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/ + uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/ + uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/ + uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/ + uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/ + uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/ + uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/ + uint32_t mem_trans_en: 1; + uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/ + uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/ + uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/ + uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/ + uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/ + uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/ + uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/ + uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rx_start: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/ + uint32_t tx_start: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ + uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/ + uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/ + uint32_t in_done: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/ + uint32_t in_suc_eof: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/ + uint32_t in_err_eof: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/ + uint32_t out_done: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/ + uint32_t out_eof: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/ + uint32_t in_dscr_err: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/ + uint32_t out_dscr_err: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/ + uint32_t in_dscr_empty: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/ + uint32_t outlink_eof_err: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/ + uint32_t out_total_eof: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ + uint32_t send_s_q: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/ + uint32_t send_a_q: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/ + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t outlink_eof_err: 1; + uint32_t out_total_eof: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t outlink_eof_err: 1; + uint32_t out_total_eof: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t outlink_eof_err: 1; + uint32_t out_total_eof: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t full: 1; /*1:DMA out link descriptor's fifo is full.*/ + uint32_t empty: 1; /*1:DMA in link descriptor's fifo is empty.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } dma_out_status; + union { + struct { + uint32_t fifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/ + uint32_t reserved9: 7; + uint32_t fifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/ + uint32_t reserved17:15; + }; + uint32_t val; + } dma_out_push; + union { + struct { + uint32_t full: 1; + uint32_t empty: 1; + uint32_t reserved2: 2; + uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/ + uint32_t reserved7: 25; + }; + uint32_t val; + } dma_in_status; + union { + struct { + uint32_t fifo_rdata: 12; /*This register stores the data pop from in link descriptor's fifo.*/ + uint32_t reserved12: 4; + uint32_t fifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } dma_in_pop; + union { + struct { + uint32_t addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/ + uint32_t reserved20: 8; + uint32_t stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/ + uint32_t start: 1; /*Set this bit to start dealing with the out link descriptors.*/ + uint32_t restart: 1; /*Set this bit to mount on new out link descriptors*/ + uint32_t park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/ + }; + uint32_t val; + } dma_out_link; + union { + struct { + uint32_t addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/ + uint32_t auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/ + uint32_t reserved21: 7; + uint32_t stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/ + uint32_t start: 1; /*Set this bit to start dealing with the in link descriptors.*/ + uint32_t restart: 1; /*Set this bit to mount on new in link descriptors*/ + uint32_t park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/ + }; + uint32_t val; + } dma_in_link; + union { + struct { + uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/ + uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/ + uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/ + uint32_t save_head: 1; /*Set this bit to save packet header .*/ + uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/ + uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/ + uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/ + uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/ + uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/ + uint32_t dma_in_fifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/ + uint32_t reserved21: 11; + }; + uint32_t val; + } conf1; + uint32_t state0; /**/ + uint32_t state1; /**/ + uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/ + uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/ + uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/ + uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/ + union { + struct { + uint32_t test_mode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ + uint32_t reserved3: 1; + uint32_t test_addr: 2; /*The two bits represent ahb bus address bit[20:19]*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } ahb_test; + uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/ + uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/ + uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/ + uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/ + uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/ + uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/ + union { + struct { + uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/ + uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/ + uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/ + uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/ + uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/ + uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/ + uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/ + uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } escape_conf; + union { + struct { + uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/ + uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/ + uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/ + uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/ + uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/ + uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } hung_conf; + uint32_t ack_num; /**/ + uint32_t rx_head; /*This register stores the packet header received by DMA*/ + union { + struct { + uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/ + uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/ + uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/ + uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } quick_sent; + struct{ + uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ + } q_data[7]; + union { + struct { + uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/ + uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/ + uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf0; + union { + struct { + uint32_t seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/ + uint32_t seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/ + uint32_t seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf1; + union { + struct { + uint32_t seq1: 8; /*This register stores the flow control char to turn on the flow_control*/ + uint32_t seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/ + uint32_t seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf2; + union { + struct { + uint32_t seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/ + uint32_t seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/ + uint32_t seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf3; + union { + struct { + uint32_t thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/ + uint32_t reserved13:19; + }; + uint32_t val; + } pkt_thres; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /*version information*/ +} uhci_dev_t; +extern uhci_dev_t UHCI0; +extern uhci_dev_t UHCI1; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_UHCI_STRUCT_H_ */ diff --git a/tools/sdk/include/soc/include/soc/wdev_reg.h b/tools/sdk/include/soc/include/soc/wdev_reg.h new file mode 100644 index 00000000000..f3217cb0d6f --- /dev/null +++ b/tools/sdk/include/soc/include/soc/wdev_reg.h @@ -0,0 +1,20 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc.h" + +/* Hardware random number generator register */ +#define WDEV_RND_REG 0x60035144 diff --git a/tools/sdk/include/soc/rtc_clk_common.h b/tools/sdk/include/soc/rtc_clk_common.h new file mode 100644 index 00000000000..b1efa175d3e --- /dev/null +++ b/tools/sdk/include/soc/rtc_clk_common.h @@ -0,0 +1,38 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define MHZ (1000000) + +void rtc_clk_cpu_freq_to_xtal(int freq, int div); + +/* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in + * lower and upper 16-bit halves. These are the routines to work with such a + * representation. + */ +static inline bool clk_val_is_valid(uint32_t val) { + return (val & 0xffff) == ((val >> 16) & 0xffff) && + val != 0 && + val != UINT32_MAX; +} + +static inline uint32_t reg_val_to_clk_val(uint32_t val) { + return val & UINT16_MAX; +} + +static inline uint32_t clk_val_to_reg_val(uint32_t val) { + return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16); +} + diff --git a/tools/sdk/include/soc/soc/cpu.h b/tools/sdk/include/soc/soc/cpu.h index f28feb59fa2..190786a433b 100644 --- a/tools/sdk/include/soc/soc/cpu.h +++ b/tools/sdk/include/soc/soc/cpu.h @@ -110,4 +110,25 @@ void esp_cpu_reset(int cpu_id); */ bool esp_cpu_in_ocd_debug_mode(); +/** + * @brief Convert the PC register value to its true address + * + * The address of the current instruction is not stored as an exact uint32_t + * representation in PC register. This function will convert the value stored in + * the PC register to a uint32_t address. + * + * @param pc_raw The PC as stored in register format. + * + * @return Address in uint32_t format + */ +static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc) +{ + if (pc & 0x80000000) { + //Top two bits of a0 (return address) specify window increment. Overwrite to map to address space. + pc = (pc & 0x3fffffff) | 0x40000000; + } + //Minus 3 to get PC of previous instruction (i.e. instruction executed before return address) + return pc - 3; +} + #endif diff --git a/tools/sdk/include/soc/soc/soc.h b/tools/sdk/include/soc/soc/soc.h index d1d468303cc..2aa3cc50205 100644 --- a/tools/sdk/include/soc/soc/soc.h +++ b/tools/sdk/include/soc/soc/soc.h @@ -322,6 +322,9 @@ #define SOC_MEM_INTERNAL_LOW 0x3FF90000 #define SOC_MEM_INTERNAL_HIGH 0x400C2000 +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x3ffe3f20 + //Interrupt hardware source table //This table is decided by hardware, don't touch this. #define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/ diff --git a/tools/sdk/include/soc/soc/soc_memory_layout.h b/tools/sdk/include/soc/soc/soc_memory_layout.h index 9bca1120ab3..caae8e384be 100644 --- a/tools/sdk/include/soc/soc/soc_memory_layout.h +++ b/tools/sdk/include/soc/soc/soc_memory_layout.h @@ -206,3 +206,39 @@ inline static bool IRAM_ATTR esp_ptr_in_diram_dram(const void *p) { inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) { return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH); } + +inline static bool IRAM_ATTR esp_stack_ptr_is_sane(uint32_t sp) +{ + //Check if stack ptr is in between SOC_DRAM_LOW and SOC_DRAM_HIGH, and 16 byte aligned. + return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0)); +} + +inline static bool IRAM_ATTR esp_ptr_in_rtc_iram_fast(const void *p) { + return ((intptr_t)p >= SOC_RTC_IRAM_LOW && (intptr_t)p < SOC_RTC_IRAM_HIGH); +} + +inline static bool IRAM_ATTR esp_ptr_in_rtc_dram_fast(const void *p) { + return ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH); +} + +inline static bool IRAM_ATTR esp_ptr_in_rtc_slow(const void *p) { + return ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH); +} + +/* Convert a D/IRAM DRAM pointer to equivalent word address in IRAM + + - Address must be word aligned + - Address must pass esp_ptr_in_diram_dram() test, or result will be invalid pointer +*/ +inline static void * IRAM_ATTR esp_ptr_diram_dram_to_iram(const void *p) { + return (void *) ( SOC_DIRAM_IRAM_LOW + ((intptr_t)p - SOC_DIRAM_DRAM_LOW) ); +} + +/* Convert a D/IRAM IRAM pointer to equivalent word address in DRAM + + - Address must be word aligned + - Address must pass esp_ptr_in_diram_iram() test, or result will be invalid pointer +*/ +inline static void * IRAM_ATTR esp_ptr_diram_iram_to_dram(const void *p) { + return (void *) ( SOC_DIRAM_DRAM_LOW + ((intptr_t)p - SOC_DIRAM_IRAM_LOW) ); +} diff --git a/tools/sdk/include/soc/soc_log.h b/tools/sdk/include/soc/soc_log.h new file mode 100644 index 00000000000..4fdffd7b502 --- /dev/null +++ b/tools/sdk/include/soc/soc_log.h @@ -0,0 +1,40 @@ +// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file soc_log.h + * @brief SOC library logging functions + * + * To make SOC library compatible with environments which don't use ESP-IDF, + * this header file provides wrappers for logging functions. + */ + +#ifdef ESP_PLATFORM +#include "esp_log.h" +#define SOC_LOGE(tag, fmt, ...) ESP_EARLY_LOGE(tag, fmt, ##__VA_ARGS__) +#define SOC_LOGW(tag, fmt, ...) ESP_EARLY_LOGW(tag, fmt, ##__VA_ARGS__) +#define SOC_LOGI(tag, fmt, ...) ESP_EARLY_LOGI(tag, fmt, ##__VA_ARGS__) +#define SOC_LOGD(tag, fmt, ...) ESP_EARLY_LOGD(tag, fmt, ##__VA_ARGS__) +#define SOC_LOGV(tag, fmt, ...) ESP_EARLY_LOGV(tag, fmt, ##__VA_ARGS__) + +#else +#include "rom/ets_sys.h" +#define SOC_LOGE(tag, fmt, ...) ets_printf("%s(err): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGW(tag, fmt, ...) ets_printf("%s(warn): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGI(tag, fmt, ...) ets_printf("%s(info): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGD(tag, fmt, ...) ets_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGV(tag, fmt, ...) ets_printf("%s: " fmt, tag, ##__VA_ARGS__) +#endif //ESP_PLATFORM diff --git a/tools/sdk/include/tcp_transport/esp_transport.h b/tools/sdk/include/tcp_transport/esp_transport.h index e163a010cd9..1499e41fa3d 100644 --- a/tools/sdk/include/tcp_transport/esp_transport.h +++ b/tools/sdk/include/tcp_transport/esp_transport.h @@ -16,11 +16,21 @@ #define _ESP_TRANSPORT_H_ #include +#include #ifdef __cplusplus extern "C" { #endif +/** +* @brief Keep alive parameters structure +*/ +typedef struct esp_transport_keepalive { + bool keep_alive_enable; /*!< Enable keep-alive timeout */ + int keep_alive_idle; /*!< Keep-alive idle time (second) */ + int keep_alive_interval; /*!< Keep-alive interval time (second) */ + int keep_alive_count; /*!< Keep-alive packet retry send count */ +} esp_transport_keep_alive_t; typedef struct esp_transport_list_t* esp_transport_list_handle_t; typedef struct esp_transport_item_t* esp_transport_handle_t; @@ -298,6 +308,22 @@ esp_err_t esp_transport_set_async_connect_func(esp_transport_handle_t t, connect */ esp_err_t esp_transport_set_parent_transport_func(esp_transport_handle_t t, payload_transfer_func _parent_transport); +/** + * @brief Set keep-alive configuration + * + * @param[in] t The transport handle + * @param[in] keep_alive_cfg The keep-alive config + */ +void esp_transport_set_keep_alive(esp_transport_handle_t t, esp_transport_keep_alive_t *keep_alive_cfg); + +/** + * @brief Get keep-alive config of this transport + * + * @param[in] t The transport handle + * + * @return The keep-alive configuration + */ +void *esp_transport_get_keep_alive(esp_transport_handle_t t); #ifdef __cplusplus } #endif diff --git a/tools/sdk/include/tcp_transport/esp_transport_ssl.h b/tools/sdk/include/tcp_transport/esp_transport_ssl.h index 0f83c1d6e49..fedd1c46b2d 100644 --- a/tools/sdk/include/tcp_transport/esp_transport_ssl.h +++ b/tools/sdk/include/tcp_transport/esp_transport_ssl.h @@ -78,6 +78,14 @@ void esp_transport_ssl_set_client_key_data(esp_transport_handle_t t, const char */ void esp_transport_ssl_skip_common_name_check(esp_transport_handle_t t); +/** + * @brief Set keep-alive status in current ssl context + * + * @param[in] t ssl transport + * @param[in] keep_alive_cfg The handle for keep-alive configuration + */ +void esp_transport_ssl_set_keep_alive(esp_transport_handle_t t, esp_transport_keep_alive_t *keep_alive_cfg); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/include/tcp_transport/esp_transport_tcp.h b/tools/sdk/include/tcp_transport/esp_transport_tcp.h index 57ad453309f..b78ecc1d1ed 100644 --- a/tools/sdk/include/tcp_transport/esp_transport_tcp.h +++ b/tools/sdk/include/tcp_transport/esp_transport_tcp.h @@ -21,6 +21,14 @@ extern "C" { #endif +/** + * @brief Set TCP keep-alive configuration + * + * @param[in] t The transport handle + * @param[in] keep_alive_cfg The keep-alive config + */ +void esp_transport_tcp_set_keep_alive(esp_transport_handle_t t, esp_transport_keep_alive_t *keep_alive_cfg); + /** * @brief Create TCP transport, the transport handle must be release esp_transport_destroy callback * diff --git a/tools/sdk/include/unity/priv/setjmp.h b/tools/sdk/include/unity/priv/setjmp.h new file mode 100644 index 00000000000..94162bd992d --- /dev/null +++ b/tools/sdk/include/unity/priv/setjmp.h @@ -0,0 +1,14 @@ +#include_next +#include "esp_panic.h" + +/* + * This is the middle layer of setjmp to be used with the unity. + */ + +/** Insert backtrace before longjmp (TEST_ABORT). + * + * Currently we only do long jump before test is ignored or failed. + * If this is also called when test pass, we may need to add some check before + * backtrace is called. + */ +#define longjmp(buf, val) do {esp_backtrace_print(100); longjmp(buf, val);} while(0) diff --git a/tools/sdk/ld/esp32.project.ld b/tools/sdk/ld/esp32.project.ld index 21a3fc43712..676923563f9 100644 --- a/tools/sdk/ld/esp32.project.ld +++ b/tools/sdk/ld/esp32.project.ld @@ -539,7 +539,7 @@ SECTIONS *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libphy.a *libgcov.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-strndup_r.* *libsoc.a:rtc_clk.*) .rodata EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libphy.a *libgcov.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-strndup_r.* *libsoc.a:rtc_clk.*) .rodata.*) + *(EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libphy.a *libgcov.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strrchr.* *libsoc.a:rtc_clk.*) .rodata EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libphy.a *libgcov.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strrchr.* *libsoc.a:rtc_clk.*) .rodata.*) *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ *(.gnu.linkonce.r.*) @@ -599,13 +599,21 @@ SECTIONS _stext = .; _text_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libhal.a *librtc.a *libgcc.a:lib2funcs.* *libgcov.a *libesp_ringbuf.a *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libfreertos.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-strndup_r.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_pm.* *libsoc.a:cpu_util.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libspi_flash.a:spi_flash_rom_patch.* *libxtensa-debug-module.a:eri.*) .literal EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libhal.a *librtc.a *libgcc.a:lib2funcs.* *libgcov.a *libesp_ringbuf.a *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libfreertos.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-strndup_r.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_pm.* *libsoc.a:cpu_util.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libspi_flash.a:spi_flash_rom_patch.* *libxtensa-debug-module.a:eri.*) .literal.* .phyiram .phyiram.* EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libhal.a *librtc.a *libgcc.a:lib2funcs.* *libgcov.a *libesp_ringbuf.a *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libfreertos.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-strndup_r.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_pm.* *libsoc.a:cpu_util.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libspi_flash.a:spi_flash_rom_patch.* *libxtensa-debug-module.a:eri.*) .text EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libhal.a *librtc.a *libgcc.a:lib2funcs.* *libgcov.a *libesp_ringbuf.a *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libfreertos.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-strndup_r.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_pm.* *libsoc.a:cpu_util.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libspi_flash.a:spi_flash_rom_patch.* *libxtensa-debug-module.a:eri.*) .text.* .wifi0iram .wifi0iram.* .wifirxiram .wifirxiram.*) + *(EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libhal.a *librtc.a *libgcc.a:lib2funcs.* *libgcov.a *libesp_ringbuf.a *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libfreertos.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strrchr.* *libsoc.a:rtc_time.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_periph.* *libsoc.a:rtc_init.* *libsoc.a:rtc_wdt.* *libsoc.a:cpu_util.* *libspi_flash.a:spi_flash_rom_patch.* *libxtensa-debug-module.a:eri.*) .literal EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libhal.a *librtc.a *libgcc.a:lib2funcs.* *libgcov.a *libesp_ringbuf.a *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libfreertos.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strrchr.* *libsoc.a:rtc_time.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_periph.* *libsoc.a:rtc_init.* *libsoc.a:rtc_wdt.* *libsoc.a:cpu_util.* *libspi_flash.a:spi_flash_rom_patch.* *libxtensa-debug-module.a:eri.*) .literal.* .phyiram .phyiram.* EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libhal.a *librtc.a *libgcc.a:lib2funcs.* *libgcov.a *libesp_ringbuf.a *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libfreertos.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strrchr.* *libsoc.a:rtc_time.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_periph.* *libsoc.a:rtc_init.* *libsoc.a:rtc_wdt.* *libsoc.a:cpu_util.* *libspi_flash.a:spi_flash_rom_patch.* *libxtensa-debug-module.a:eri.*) .text EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libhal.a *librtc.a *libgcc.a:lib2funcs.* *libgcov.a *libesp_ringbuf.a *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libfreertos.a *libheap.a:multi_heap_poisoning.* *libheap.a:multi_heap.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-strrchr.* *libsoc.a:rtc_time.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_periph.* *libsoc.a:rtc_init.* *libsoc.a:rtc_wdt.* *libsoc.a:cpu_util.* *libspi_flash.a:spi_flash_rom_patch.* *libxtensa-debug-module.a:eri.*) .text.* .wifi0iram .wifi0iram.* .wifirxiram .wifirxiram.*) *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ *(.fini.literal) *(.fini) *(.gnu.version) + + /** CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + _text_end = ABSOLUTE(.); _etext = .; diff --git a/tools/sdk/ld/esp32.rom.ld b/tools/sdk/ld/esp32.rom.ld index 57114cc0935..603c25b7dcf 100644 --- a/tools/sdk/ld/esp32.rom.ld +++ b/tools/sdk/ld/esp32.rom.ld @@ -124,6 +124,7 @@ PROVIDE ( jd_prepare = 0x40060fa8 ); PROVIDE ( ke_env = 0x3ffb93cc ); PROVIDE ( ke_handler_search = 0x4001a430 ); PROVIDE ( ke_task_env = 0x3ffb81d4 ); +PROVIDE ( ke_event_env = 0x3ffb81a4 ); PROVIDE ( lb_default_handler = 0x3ff982b8 ); PROVIDE ( lb_default_state_tab_p_get = 0x4001c198 ); PROVIDE ( lb_env = 0x3ffb9424 ); @@ -1632,5 +1633,22 @@ PROVIDE ( prbs_64bytes = 0x3ff98992 ); PROVIDE ( nvds_env = 0x3ffb8364 ); PROVIDE ( nvds_magic_number = 0x3ff9912a ); PROVIDE ( TASK_DESC_LLD = 0x3ff98b58 ); +PROVIDE ( ld_acl_clk_isr = 0x40030cf8 ); +PROVIDE ( ld_acl_evt_canceled_cbk = 0x40033944 ); +PROVIDE ( ld_acl_evt_stop_cbk = 0x40033870 ); +PROVIDE ( ld_acl_evt_start_cbk = 0x40030ab0 ); +PROVIDE ( ld_acl_test_mode_update = 0x40032050 ); +PROVIDE ( ld_acl_resched = 0x40033814 ); +PROVIDE ( ld_acl_rx_isr = 0x40033aa8 ); +PROVIDE ( lc_acl_disc_ind_handler = 0x4002f270 ); +PROVIDE ( lc_pca_sscan_start_req_handler = 0x40029b34 ); +PROVIDE ( lmp_feats_req_ext_handler = 0x4002ccb0 ); +PROVIDE ( ld_pscan_em_init = 0x4003e5e8 ); +PROVIDE ( ld_acl_rsw_start = 0x40032e90 ); +PROVIDE ( ld_acl_sniff_enter = 0x40031244 ); +PROVIDE ( ld_acl_sniff_trans_sched = 0x40033734 ); +PROVIDE ( lc_pwr_decr_ind_handler = 0x4002859c ); +PROVIDE ( lc_pwr_incr_ind_handler = 0x400284a8 ); +PROVIDE ( lc_pwr_max_ind_handler = 0x40028690 ); /* Above are static data, but can be used, not generated by script >>>>> btdm data */ diff --git a/tools/sdk/lib/libapp_trace.a b/tools/sdk/lib/libapp_trace.a index a023944c238..977202ae8a8 100644 Binary files a/tools/sdk/lib/libapp_trace.a and b/tools/sdk/lib/libapp_trace.a differ diff --git a/tools/sdk/lib/libapp_update.a b/tools/sdk/lib/libapp_update.a index 5ade2b8c8c8..236c7365cec 100644 Binary files a/tools/sdk/lib/libapp_update.a and b/tools/sdk/lib/libapp_update.a differ diff --git a/tools/sdk/lib/libasio.a b/tools/sdk/lib/libasio.a index 2ba16c08b8a..ac401272b65 100644 Binary files a/tools/sdk/lib/libasio.a and b/tools/sdk/lib/libasio.a differ diff --git a/tools/sdk/lib/libbootloader_support.a b/tools/sdk/lib/libbootloader_support.a index 6923ccd947b..21809e2b2dd 100644 Binary files a/tools/sdk/lib/libbootloader_support.a and b/tools/sdk/lib/libbootloader_support.a differ diff --git a/tools/sdk/lib/libbt.a b/tools/sdk/lib/libbt.a index 3758f32ecd8..e1642ec4a0a 100644 Binary files a/tools/sdk/lib/libbt.a and b/tools/sdk/lib/libbt.a differ diff --git a/tools/sdk/lib/libbtdm_app.a b/tools/sdk/lib/libbtdm_app.a index de74c65b813..838eecd498c 100644 Binary files a/tools/sdk/lib/libbtdm_app.a and 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b/tools/sdk/lib/libxtensa-debug-module.a index 49b51de6aae..c7b084cfa22 100644 Binary files a/tools/sdk/lib/libxtensa-debug-module.a and b/tools/sdk/lib/libxtensa-debug-module.a differ diff --git a/tools/sdk/sdkconfig b/tools/sdk/sdkconfig index 70001fc49ef..c6cebf31d3f 100644 --- a/tools/sdk/sdkconfig +++ b/tools/sdk/sdkconfig @@ -221,7 +221,6 @@ CONFIG_BTDM_CONTROLLER_FULL_SCAN_SUPPORTED=y CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED=y CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM=100 CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD=20 -CONFIG_BTDM_COEX_BT_OPTIONS= CONFIG_BLUEDROID_ENABLED=y CONFIG_BLUEDROID_PINNED_TO_CORE_0=y CONFIG_BLUEDROID_PINNED_TO_CORE_1= @@ -282,6 +281,11 @@ CONFIG_SPI_SLAVE_ISR_IN_IRAM=y # CONFIG_CAN_ISR_IN_IRAM= +# +# UART configuration +# +CONFIG_UART_ISR_IN_IRAM= + # # eFuse Bit Manager # @@ -440,6 +444,7 @@ CONFIG_ESP32_XTAL_FREQ=0 CONFIG_DISABLE_BASIC_ROM_CONSOLE= CONFIG_ESP_TIMER_PROFILING= CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS= +CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS= CONFIG_ESP_ERR_TO_NAME_LOOKUP=y CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5 @@ -489,11 +494,17 @@ CONFIG_NT99141_SUPPORT=y CONFIG_OV2640_SUPPORT=y CONFIG_OV3660_SUPPORT=y CONFIG_OV5640_SUPPORT=y +CONFIG_GC2145_SUPPORT=y +CONFIG_GC032A_SUPPORT=y +CONFIG_GC0308_SUPPORT=y CONFIG_SCCB_HARDWARE_I2C_PORT0= CONFIG_SCCB_HARDWARE_I2C_PORT1=y +CONFIG_GC_SENSOR_WINDOWING_MODE= +CONFIG_GC_SENSOR_SUBSAMPLE_MODE=y CONFIG_CAMERA_CORE0= CONFIG_CAMERA_CORE1=y CONFIG_CAMERA_NO_AFFINITY= +CONFIG_CAMERA_DMA_BUFFER_SIZE_MAX=32768 # # ADC-Calibration @@ -937,6 +948,7 @@ CONFIG_UNITY_ENABLE_DOUBLE=y CONFIG_UNITY_ENABLE_COLOR= CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y CONFIG_UNITY_ENABLE_FIXTURE= +CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL= # # Virtual file system