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IDF release/v4.4 ce1fde4b3b
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platform.txt

+4-4
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tools/platformio-build-esp32.py

+1-1
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@@ -323,7 +323,7 @@
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"UNITY_INCLUDE_CONFIG_H",
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"WITH_POSIX",
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"_GNU_SOURCE",
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("IDF_VER", '\\"v4.4.1-593-g6d85d53cee\\"'),
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("IDF_VER", '\\"v4.4.2-1-gce1fde4b3b\\"'),
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"ESP_PLATFORM",
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"_POSIX_READER_WRITER_LOCKS",
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"ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32c3.py

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@@ -318,7 +318,7 @@
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"UNITY_INCLUDE_CONFIG_H",
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"WITH_POSIX",
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"_GNU_SOURCE",
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("IDF_VER", '\\"v4.4.1-593-g6d85d53cee\\"'),
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("IDF_VER", '\\"v4.4.2-1-gce1fde4b3b\\"'),
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"ESP_PLATFORM",
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"_POSIX_READER_WRITER_LOCKS",
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"ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32s2.py

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@@ -306,7 +306,7 @@
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"UNITY_INCLUDE_CONFIG_H",
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"WITH_POSIX",
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"_GNU_SOURCE",
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("IDF_VER", '\\"v4.4.1-593-g6d85d53cee\\"'),
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("IDF_VER", '\\"v4.4.2-1-gce1fde4b3b\\"'),
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"ESP_PLATFORM",
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"_POSIX_READER_WRITER_LOCKS",
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"ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32s3.py

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@@ -322,7 +322,7 @@
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"UNITY_INCLUDE_CONFIG_H",
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"WITH_POSIX",
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"_GNU_SOURCE",
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("IDF_VER", '\\"v4.4.1-593-g6d85d53cee\\"'),
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("IDF_VER", '\\"v4.4.2-1-gce1fde4b3b\\"'),
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"ESP_PLATFORM",
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"_POSIX_READER_WRITER_LOCKS",
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"ARDUINO_ARCH_ESP32",

tools/sdk/esp32/dio_qspi/include/sdkconfig.h

+3-1
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@@ -83,6 +83,8 @@
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#define CONFIG_ARDUHAL_ESP_LOG 1
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#define CONFIG_ARDUHAL_PARTITION_SCHEME_DEFAULT 1
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#define CONFIG_ARDUHAL_PARTITION_SCHEME "default"
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#define CONFIG_USE_AFE 1
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#define CONFIG_AFE_INTERFACE_V1 1
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#define CONFIG_COMPILER_OPTIMIZATION_SIZE 1
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#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1
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#define CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL 2
@@ -750,5 +752,5 @@
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#define CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED
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#define CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
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#define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
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#define CONFIG_ARDUINO_IDF_COMMIT "6d85d53cee"
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#define CONFIG_ARDUINO_IDF_COMMIT "ce1fde4b3b"
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#define CONFIG_ARDUINO_IDF_BRANCH "release/v4.4"

tools/sdk/esp32/dout_qspi/include/sdkconfig.h

+3-1
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@@ -83,6 +83,8 @@
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#define CONFIG_ARDUHAL_ESP_LOG 1
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#define CONFIG_ARDUHAL_PARTITION_SCHEME_DEFAULT 1
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#define CONFIG_ARDUHAL_PARTITION_SCHEME "default"
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#define CONFIG_USE_AFE 1
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#define CONFIG_AFE_INTERFACE_V1 1
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#define CONFIG_COMPILER_OPTIMIZATION_SIZE 1
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#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1
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#define CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL 2
@@ -750,5 +752,5 @@
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#define CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED
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#define CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
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#define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
753-
#define CONFIG_ARDUINO_IDF_COMMIT "6d85d53cee"
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#define CONFIG_ARDUINO_IDF_COMMIT "ce1fde4b3b"
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#define CONFIG_ARDUINO_IDF_BRANCH "release/v4.4"

tools/sdk/esp32/include/esp-dsp/modules/common/include/dsp_common.h

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@@ -57,10 +57,14 @@ int dsp_power_of_two(int x);
5757
#endif
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// esp_cpu_get_ccount function is implemented in IDF 4.1 and later
60+
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0)
61+
#define dsp_get_cpu_cycle_count esp_cpu_get_cycle_count
62+
#else
6063
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 1, 0)
6164
#define dsp_get_cpu_cycle_count esp_cpu_get_ccount
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#else
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#define dsp_get_cpu_cycle_count xthal_get_ccount
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#endif
68+
#endif // ESP_IDF_VERSION
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#endif // _dsp_common_H_
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
1-
//Generated by mkmodel
1+
//Generated by mkmodel_py
22
#pragma once
33
#include <string.h>
44
#include "dl_lib_coefgetter_if.h"
55
#include "dl_lib_matrix.h"
66
#include "dl_lib_matrixq.h"
7+
#include "dl_lib_matrixq8.h"
78

8-
extern const model_coeff_getter_t get_coeff_customized_word_wn5;
9+
extern const model_coeff_getter_t get_coeff_customized_word_wn5;

tools/sdk/esp32/include/esp-sr/include/esp32/dl_lib_convq8_queue.h

+22
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@@ -246,6 +246,28 @@ void dl_dilation_layerq8_mc_steps(dl_convq8_queue_t **in, dl_convq8_queue_t **ou
246246

247247
void dl_convq8_queue_mc_bzero(dl_convq8_queue_t **cqm, int nch);
248248

249+
250+
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dl_convq8_queue_t *dl_convq8_queue_alloc_from_psram(int n, int c);
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qtp_t *dl_dilation_layerq16_8(dl_convq_queue_t *in, dl_convq8_queue_t *out, int rate, int size,
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dl_matrix2dq_t* filter_kernel, dl_matrix2dq_t* filter_bias,
255+
dl_matrix2dq_t* gate_kernel, dl_matrix2dq_t* gate_bias, int prenum);
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qtp_t *dl_dilation_layerq8(dl_convq8_queue_t *in, dl_convq8_queue_t *out, int rate, int size,
259+
dl_matrix2dq8_t* filter_kernel, dl_matrix2dq_t* filter_bias,
260+
dl_matrix2dq8_t* gate_kernel, dl_matrix2dq_t* gate_bias, int prenum);
261+
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dl_matrix2dq8_t *dl_convq8_lstm_layer(const dl_convq8_queue_t *in, dl_convq8_queue_t *out, dl_matrix2dq8_t *state_c,
263+
dl_matrix2dq8_t *state_h, const dl_matrix2dq8_t *in_weight, const dl_matrix2dq8_t *h_weight,
264+
const dl_matrix2dq_t *bias, int prenum);
265+
266+
qtp_t *dl_atrous_conv1dq8_16_s3(dl_convq8_queue_t *in, dl_convq_queue_t *out, int rate, int size,
267+
dl_matrix2dq8_t* kernel, dl_matrix2dq_t* bias, int prenum);
268+
249269
void print_convq8(dl_convq8_queue_t *cq, int offset);
250270
void print_convq(dl_convq_queue_t *cq, int offset);
271+
272+
void lstmq8_free(void);
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#endif
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@@ -0,0 +1,101 @@
1+
#pragma once
2+
#include "stdint.h"
3+
#include "esp_wn_iface.h"
4+
#include "esp_wn_models.h"
5+
#include "esp_vad.h"
6+
7+
//AFE: Audio Front-End
8+
//SR: Speech Recognition
9+
//afe_sr/AFE_SR: the audio front-end for speech recognition
10+
11+
//Set AFE_SR mode
12+
typedef enum {
13+
SR_MODE_LOW_COST = 0,
14+
SR_MODE_HIGH_PERF = 1
15+
} afe_sr_mode_t;
16+
17+
typedef enum {
18+
AFE_MEMORY_ALLOC_MORE_INTERNAL = 1, // malloc with more internal ram
19+
AFE_MEMORY_ALLOC_INTERNAL_PSRAM_BALANCE = 2, // malloc with internal ram and psram in balance
20+
AFE_MEMORY_ALLOC_MORE_PSRAM = 3 // malloc with more psram
21+
} afe_memory_alloc_mode_t;
22+
23+
typedef enum {
24+
AFE_MN_PEAK_AGC_MODE_1 = -5, // The peak amplitude of audio fed to multinet is -5dB
25+
AFE_MN_PEAK_AGC_MODE_2 = -4, // The peak amplitude of audio fed to multinet is -4dB
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AFE_MN_PEAK_AGC_MODE_3 = -3, // The peak amplitude of audio fed to multinet is -3dB
27+
AFE_MN_PEAK_NO_AGC = 0, // There is no agc gain
28+
} afe_mn_peak_agc_mode_t;
29+
30+
typedef struct {
31+
int total_ch_num; // total channel num. It must be: total_ch_num = mic_num + ref_num
32+
int mic_num; // mic channel num
33+
int ref_num; // reference channel num
34+
} afe_pcm_config_t;
35+
36+
typedef struct {
37+
bool aec_init;
38+
bool se_init;
39+
bool vad_init;
40+
bool wakenet_init;
41+
bool voice_communication_init;
42+
bool voice_communication_agc_init; // AGC swich for voice communication
43+
int voice_communication_agc_gain; // AGC gain(dB) for voice communication
44+
vad_mode_t vad_mode; // The value can be: VAD_MODE_0, VAD_MODE_1, VAD_MODE_2, VAD_MODE_3, VAD_MODE_4
45+
char *wakenet_model_name; // The model name of wakenet
46+
det_mode_t wakenet_mode;
47+
afe_sr_mode_t afe_mode;
48+
int afe_perferred_core;
49+
int afe_perferred_priority;
50+
int afe_ringbuf_size;
51+
afe_memory_alloc_mode_t memory_alloc_mode;
52+
afe_mn_peak_agc_mode_t agc_mode; // The agc mode for ASR
53+
afe_pcm_config_t pcm_config; // Config the channel num of original data which is fed to the afe feed function.
54+
} afe_config_t;
55+
56+
57+
#if CONFIG_IDF_TARGET_ESP32
58+
#define AFE_CONFIG_DEFAULT() { \
59+
.aec_init = true, \
60+
.se_init = true, \
61+
.vad_init = true, \
62+
.wakenet_init = true, \
63+
.voice_communication_init = false, \
64+
.voice_communication_agc_init = false, \
65+
.voice_communication_agc_gain = 15, \
66+
.vad_mode = VAD_MODE_3, \
67+
.wakenet_model_name = NULL, \
68+
.wakenet_mode = DET_MODE_90, \
69+
.afe_mode = SR_MODE_HIGH_PERF, \
70+
.afe_perferred_core = 0, \
71+
.afe_perferred_priority = 5, \
72+
.afe_ringbuf_size = 50, \
73+
.memory_alloc_mode = AFE_MEMORY_ALLOC_INTERNAL_PSRAM_BALANCE, \
74+
.agc_mode = AFE_MN_PEAK_AGC_MODE_2, \
75+
.pcm_config.total_ch_num = 2, \
76+
.pcm_config.mic_num = 1, \
77+
.pcm_config.ref_num = 1, \
78+
}
79+
#elif CONFIG_IDF_TARGET_ESP32S3
80+
#define AFE_CONFIG_DEFAULT() { \
81+
.aec_init = true, \
82+
.se_init = true, \
83+
.vad_init = true, \
84+
.wakenet_init = true, \
85+
.voice_communication_init = false, \
86+
.voice_communication_agc_init = false, \
87+
.voice_communication_agc_gain = 15, \
88+
.vad_mode = VAD_MODE_3, \
89+
.wakenet_model_name = NULL, \
90+
.wakenet_mode = DET_MODE_2CH_90, \
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.afe_mode = SR_MODE_LOW_COST, \
92+
.afe_perferred_core = 0, \
93+
.afe_perferred_priority = 5, \
94+
.afe_ringbuf_size = 50, \
95+
.memory_alloc_mode = AFE_MEMORY_ALLOC_MORE_PSRAM, \
96+
.agc_mode = AFE_MN_PEAK_AGC_MODE_2, \
97+
.pcm_config.total_ch_num = 3, \
98+
.pcm_config.mic_num = 2, \
99+
.pcm_config.ref_num = 1, \
100+
}
101+
#endif

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