@@ -1480,7 +1480,9 @@ i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda)
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* */
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// 24Nov17 only supports Master Mode
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i2c_t * i2cInit (uint8_t i2c_num , int8_t sda , int8_t scl , uint32_t frequency ) {
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+ #ifdef ENABLE_I2C_DEBUG_BUFFER
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log_v ("num=%d sda=%d scl=%d freq=%d" ,i2c_num , sda , scl , frequency );
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+ #endif
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if (i2c_num > 1 ) {
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return NULL ;
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}
@@ -1674,8 +1676,9 @@ i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed)
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clk_speed = apb /(period * 2 );
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log_d ("APB Freq too fast, Increasing i2c Freq to %d Hz" ,clk_speed );
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}
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+ #ifdef ENABLE_I2C_DEBUG_BUFFER
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log_v ("freq=%dHz" ,clk_speed );
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-
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+ #endif
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uint32_t halfPeriod = period /2 ;
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uint32_t quarterPeriod = period /4 ;
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@@ -1689,14 +1692,17 @@ i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed)
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available when a Fifo interrupt is triggered. This allows enough room in the Fifo so that
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interrupt latency does not cause a Fifo overflow/underflow event.
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*/
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+ #ifdef ENABLE_I2C_DEBUG_BUFFER
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log_v ("cpu Freq=%dMhz, i2c Freq=%dHz" ,getCpuFrequencyMhz (),clk_speed );
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+ #endif
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uint32_t fifo_delta = (INTERRUPT_CYCLE_OVERHEAD /((getCpuFrequencyMhz ()* 1000000 / clk_speed )* 10 ))+ 1 ;
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if (fifo_delta > 24 ) fifo_delta = 24 ;
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f .rx_fifo_full_thrhd = 32 - fifo_delta ;
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f .tx_fifo_empty_thrhd = fifo_delta ;
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i2c -> dev -> fifo_conf .val = f .val ; // set thresholds
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+ #ifdef ENABLE_I2C_DEBUG_BUFFER
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log_v ("Fifo delta=%d" ,fifo_delta );
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-
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+ #endif
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//the clock num during SCL is low level
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i2c -> dev -> scl_low_period .period = period ;
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//the clock num during SCL is high level
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