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Commit 3f63013

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francisvmfrancisvm
committedDec 14, 2017
[CodeGen] Print global addresses as @foo in both MIR and debug output
Work towards the unification of MIR and debug output by printing `@foo` instead of `<ga:@foo>`. Also print target flags in the MIR format since most of them are used on global address operands. Only debug syntax is affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320682 91177308-0d34-0410-b5e6-96231b3b80d8
·
1.40.11.38.3
1 parent d398775 commit 3f63013

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11 files changed

+172
-136
lines changed

11 files changed

+172
-136
lines changed
 

‎include/llvm/CodeGen/MachineOperand.h

+2
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,8 @@ class MachineOperand {
239239
/// called to check this.
240240
static void printSubregIdx(raw_ostream &OS, uint64_t Index,
241241
const TargetRegisterInfo *TRI);
242+
/// Print operand target flags.
243+
static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
242244

243245
/// Print the MachineOperand to \p os.
244246
/// Providing a valid \p TRI and \p IntrinsicInfo results in a more

‎lib/CodeGen/MIRPrinter.cpp

+3-64
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,6 @@ class MIPrinter {
161161
void printIRValueReference(const Value &V);
162162
void printStackObjectReference(int FrameIndex);
163163
void printOffset(int64_t Offset);
164-
void printTargetFlags(const MachineOperand &Op);
165164
void print(const MachineInstr &MI, unsigned OpIdx,
166165
const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
167166
LLT TypeToPrint, bool PrintDef = true);
@@ -778,72 +777,15 @@ void MIPrinter::printOffset(int64_t Offset) {
778777
OS << " + " << Offset;
779778
}
780779

781-
static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
782-
auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
783-
for (const auto &I : Flags) {
784-
if (I.first == TF) {
785-
return I.second;
786-
}
787-
}
788-
return nullptr;
789-
}
790-
791-
void MIPrinter::printTargetFlags(const MachineOperand &Op) {
792-
if (!Op.getTargetFlags())
793-
return;
794-
const auto *TII = Op.getParent()->getMF()->getSubtarget().getInstrInfo();
795-
assert(TII && "expected instruction info");
796-
auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
797-
OS << "target-flags(";
798-
const bool HasDirectFlags = Flags.first;
799-
const bool HasBitmaskFlags = Flags.second;
800-
if (!HasDirectFlags && !HasBitmaskFlags) {
801-
OS << "<unknown>) ";
802-
return;
803-
}
804-
if (HasDirectFlags) {
805-
if (const auto *Name = getTargetFlagName(TII, Flags.first))
806-
OS << Name;
807-
else
808-
OS << "<unknown target flag>";
809-
}
810-
if (!HasBitmaskFlags) {
811-
OS << ") ";
812-
return;
813-
}
814-
bool IsCommaNeeded = HasDirectFlags;
815-
unsigned BitMask = Flags.second;
816-
auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
817-
for (const auto &Mask : BitMasks) {
818-
// Check if the flag's bitmask has the bits of the current mask set.
819-
if ((BitMask & Mask.first) == Mask.first) {
820-
if (IsCommaNeeded)
821-
OS << ", ";
822-
IsCommaNeeded = true;
823-
OS << Mask.second;
824-
// Clear the bits which were serialized from the flag's bitmask.
825-
BitMask &= ~(Mask.first);
826-
}
827-
}
828-
if (BitMask) {
829-
// When the resulting flag's bitmask isn't zero, we know that we didn't
830-
// serialize all of the bit flags.
831-
if (IsCommaNeeded)
832-
OS << ", ";
833-
OS << "<unknown bitmask target flag>";
834-
}
835-
OS << ") ";
836-
}
837-
838780
void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
839781
const TargetRegisterInfo *TRI,
840782
bool ShouldPrintRegisterTies, LLT TypeToPrint,
841783
bool PrintDef) {
842784
const MachineOperand &Op = MI.getOperand(OpIdx);
843-
printTargetFlags(Op);
844785
switch (Op.getType()) {
845786
case MachineOperand::MO_Immediate:
846787
if (MI.isOperandSubregIdx(OpIdx)) {
788+
MachineOperand::printTargetFlags(OS, Op);
847789
MachineOperand::printSubregIdx(OS, Op.getImm(), TRI);
848790
break;
849791
}
@@ -854,7 +796,8 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
854796
case MachineOperand::MO_ConstantPoolIndex:
855797
case MachineOperand::MO_TargetIndex:
856798
case MachineOperand::MO_JumpTableIndex:
857-
case MachineOperand::MO_ExternalSymbol: {
799+
case MachineOperand::MO_ExternalSymbol:
800+
case MachineOperand::MO_GlobalAddress: {
858801
unsigned TiedOperandIdx = 0;
859802
if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
860803
TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
@@ -869,10 +812,6 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
869812
case MachineOperand::MO_FrameIndex:
870813
printStackObjectReference(Op.getIndex());
871814
break;
872-
case MachineOperand::MO_GlobalAddress:
873-
Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
874-
printOffset(Op.getOffset());
875-
break;
876815
case MachineOperand::MO_BlockAddress:
877816
OS << "blockaddress(";
878817
Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,

‎lib/CodeGen/MachineOperand.cpp

+64-6
Original file line numberDiff line numberDiff line change
@@ -401,6 +401,16 @@ static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
401401
return nullptr;
402402
}
403403

404+
static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
405+
auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
406+
for (const auto &I : Flags) {
407+
if (I.first == TF) {
408+
return I.second;
409+
}
410+
}
411+
return nullptr;
412+
}
413+
404414
void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
405415
const TargetRegisterInfo *TRI) {
406416
OS << "%subreg.";
@@ -410,6 +420,58 @@ void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
410420
OS << Index;
411421
}
412422

423+
void MachineOperand::printTargetFlags(raw_ostream &OS,
424+
const MachineOperand &Op) {
425+
if (!Op.getTargetFlags())
426+
return;
427+
const MachineFunction *MF = getMFIfAvailable(Op);
428+
if (!MF)
429+
return;
430+
431+
const auto *TII = MF->getSubtarget().getInstrInfo();
432+
assert(TII && "expected instruction info");
433+
auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
434+
OS << "target-flags(";
435+
const bool HasDirectFlags = Flags.first;
436+
const bool HasBitmaskFlags = Flags.second;
437+
if (!HasDirectFlags && !HasBitmaskFlags) {
438+
OS << "<unknown>) ";
439+
return;
440+
}
441+
if (HasDirectFlags) {
442+
if (const auto *Name = getTargetFlagName(TII, Flags.first))
443+
OS << Name;
444+
else
445+
OS << "<unknown target flag>";
446+
}
447+
if (!HasBitmaskFlags) {
448+
OS << ") ";
449+
return;
450+
}
451+
bool IsCommaNeeded = HasDirectFlags;
452+
unsigned BitMask = Flags.second;
453+
auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
454+
for (const auto &Mask : BitMasks) {
455+
// Check if the flag's bitmask has the bits of the current mask set.
456+
if ((BitMask & Mask.first) == Mask.first) {
457+
if (IsCommaNeeded)
458+
OS << ", ";
459+
IsCommaNeeded = true;
460+
OS << Mask.second;
461+
// Clear the bits which were serialized from the flag's bitmask.
462+
BitMask &= ~(Mask.first);
463+
}
464+
}
465+
if (BitMask) {
466+
// When the resulting flag's bitmask isn't zero, we know that we didn't
467+
// serialize all of the bit flags.
468+
if (IsCommaNeeded)
469+
OS << ", ";
470+
OS << "<unknown bitmask target flag>";
471+
}
472+
OS << ") ";
473+
}
474+
413475
void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
414476
const TargetIntrinsicInfo *IntrinsicInfo) const {
415477
tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
@@ -425,6 +487,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
425487
unsigned TiedOperandIdx,
426488
const TargetRegisterInfo *TRI,
427489
const TargetIntrinsicInfo *IntrinsicInfo) const {
490+
printTargetFlags(OS, *this);
428491
switch (getType()) {
429492
case MachineOperand::MO_Register: {
430493
unsigned Reg = getReg();
@@ -528,11 +591,8 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
528591
OS << printJumpTableEntryReference(getIndex());
529592
break;
530593
case MachineOperand::MO_GlobalAddress:
531-
OS << "<ga:";
532594
getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
533-
if (getOffset())
534-
OS << "+" << getOffset();
535-
OS << '>';
595+
printOffset(OS, getOffset());
536596
break;
537597
case MachineOperand::MO_ExternalSymbol: {
538598
StringRef Name = getSymbolName();
@@ -608,8 +668,6 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
608668
break;
609669
}
610670
}
611-
if (unsigned TF = getTargetFlags())
612-
OS << "[TF=" << TF << ']';
613671
}
614672

615673
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

‎lib/Target/ARM/ARMBaseInstrInfo.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -2882,7 +2882,7 @@ bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
28822882
if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
28832883
return false;
28842884
if (!DefMI.getOperand(1).isImm())
2885-
// Could be t2MOVi32imm <ga:xx>
2885+
// Could be t2MOVi32imm @xx
28862886
return false;
28872887

28882888
if (!MRI->hasOneNonDBGUse(Reg))

‎lib/Target/PowerPC/PPCAsmPrinter.cpp

+21-21
Original file line numberDiff line numberDiff line change
@@ -592,7 +592,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
592592
return;
593593
}
594594
case PPC::LWZtoc: {
595-
// Transform %r3 = LWZtoc <ga:@min1>, %r2
595+
// Transform %r3 = LWZtoc @min1, %r2
596596
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
597597

598598
// Change the opcode to LWZ, and the global address operand to be a
@@ -636,7 +636,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
636636
case PPC::LDtocCPT:
637637
case PPC::LDtocBA:
638638
case PPC::LDtoc: {
639-
// Transform %x3 = LDtoc <ga:@min1>, %x2
639+
// Transform %x3 = LDtoc @min1, %x2
640640
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
641641

642642
// Change the opcode to LD, and the global address operand to be a
@@ -667,7 +667,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
667667
}
668668

669669
case PPC::ADDIStocHA: {
670-
// Transform %xd = ADDIStocHA %x2, <ga:@sym>
670+
// Transform %xd = ADDIStocHA %x2, @sym
671671
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
672672

673673
// Change the opcode to ADDIS8. If the global address is external, has
@@ -714,7 +714,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
714714
return;
715715
}
716716
case PPC::LDtocL: {
717-
// Transform %xd = LDtocL <ga:@sym>, %xs
717+
// Transform %xd = LDtocL @sym, %xs
718718
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
719719

720720
// Change the opcode to LD. If the global address is external, has
@@ -757,7 +757,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
757757
return;
758758
}
759759
case PPC::ADDItocL: {
760-
// Transform %xd = ADDItocL %xs, <ga:@sym>
760+
// Transform %xd = ADDItocL %xs, @sym
761761
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
762762

763763
// Change the opcode to ADDI8. If the global address is external, then
@@ -788,7 +788,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
788788
return;
789789
}
790790
case PPC::ADDISgotTprelHA: {
791-
// Transform: %xd = ADDISgotTprelHA %x2, <ga:@sym>
791+
// Transform: %xd = ADDISgotTprelHA %x2, @sym
792792
// Into: %xd = ADDIS8 %x2, sym@got@tlsgd@ha
793793
assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
794794
const MachineOperand &MO = MI->getOperand(2);
@@ -805,7 +805,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
805805
}
806806
case PPC::LDgotTprelL:
807807
case PPC::LDgotTprelL32: {
808-
// Transform %xd = LDgotTprelL <ga:@sym>, %xs
808+
// Transform %xd = LDgotTprelL @sym, %xs
809809
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
810810

811811
// Change the opcode to LD.
@@ -866,7 +866,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
866866
return;
867867
}
868868
case PPC::ADDIStlsgdHA: {
869-
// Transform: %xd = ADDIStlsgdHA %x2, <ga:@sym>
869+
// Transform: %xd = ADDIStlsgdHA %x2, @sym
870870
// Into: %xd = ADDIS8 %x2, sym@got@tlsgd@ha
871871
assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
872872
const MachineOperand &MO = MI->getOperand(2);
@@ -882,10 +882,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
882882
return;
883883
}
884884
case PPC::ADDItlsgdL:
885-
// Transform: %xd = ADDItlsgdL %xs, <ga:@sym>
885+
// Transform: %xd = ADDItlsgdL %xs, @sym
886886
// Into: %xd = ADDI8 %xs, sym@got@tlsgd@l
887887
case PPC::ADDItlsgdL32: {
888-
// Transform: %rd = ADDItlsgdL32 %rs, <ga:@sym>
888+
// Transform: %rd = ADDItlsgdL32 %rs, @sym
889889
// Into: %rd = ADDI %rs, sym@got@tlsgd
890890
const MachineOperand &MO = MI->getOperand(2);
891891
const GlobalValue *GValue = MO.getGlobal();
@@ -902,16 +902,16 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
902902
return;
903903
}
904904
case PPC::GETtlsADDR:
905-
// Transform: %x3 = GETtlsADDR %x3, <ga:@sym>
905+
// Transform: %x3 = GETtlsADDR %x3, @sym
906906
// Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd)
907907
case PPC::GETtlsADDR32: {
908-
// Transform: %r3 = GETtlsADDR32 %r3, <ga:@sym>
908+
// Transform: %r3 = GETtlsADDR32 %r3, @sym
909909
// Into: BL_TLS __tls_get_addr(sym at tlsgd)@PLT
910910
EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSGD);
911911
return;
912912
}
913913
case PPC::ADDIStlsldHA: {
914-
// Transform: %xd = ADDIStlsldHA %x2, <ga:@sym>
914+
// Transform: %xd = ADDIStlsldHA %x2, @sym
915915
// Into: %xd = ADDIS8 %x2, sym@got@tlsld@ha
916916
assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
917917
const MachineOperand &MO = MI->getOperand(2);
@@ -927,10 +927,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
927927
return;
928928
}
929929
case PPC::ADDItlsldL:
930-
// Transform: %xd = ADDItlsldL %xs, <ga:@sym>
930+
// Transform: %xd = ADDItlsldL %xs, @sym
931931
// Into: %xd = ADDI8 %xs, sym@got@tlsld@l
932932
case PPC::ADDItlsldL32: {
933-
// Transform: %rd = ADDItlsldL32 %rs, <ga:@sym>
933+
// Transform: %rd = ADDItlsldL32 %rs, @sym
934934
// Into: %rd = ADDI %rs, sym@got@tlsld
935935
const MachineOperand &MO = MI->getOperand(2);
936936
const GlobalValue *GValue = MO.getGlobal();
@@ -947,19 +947,19 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
947947
return;
948948
}
949949
case PPC::GETtlsldADDR:
950-
// Transform: %x3 = GETtlsldADDR %x3, <ga:@sym>
950+
// Transform: %x3 = GETtlsldADDR %x3, @sym
951951
// Into: BL8_NOP_TLS __tls_get_addr(sym at tlsld)
952952
case PPC::GETtlsldADDR32: {
953-
// Transform: %r3 = GETtlsldADDR32 %r3, <ga:@sym>
953+
// Transform: %r3 = GETtlsldADDR32 %r3, @sym
954954
// Into: BL_TLS __tls_get_addr(sym at tlsld)@PLT
955955
EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSLD);
956956
return;
957957
}
958958
case PPC::ADDISdtprelHA:
959-
// Transform: %xd = ADDISdtprelHA %xs, <ga:@sym>
959+
// Transform: %xd = ADDISdtprelHA %xs, @sym
960960
// Into: %xd = ADDIS8 %xs, sym@dtprel@ha
961961
case PPC::ADDISdtprelHA32: {
962-
// Transform: %rd = ADDISdtprelHA32 %rs, <ga:@sym>
962+
// Transform: %rd = ADDISdtprelHA32 %rs, @sym
963963
// Into: %rd = ADDIS %rs, sym@dtprel@ha
964964
const MachineOperand &MO = MI->getOperand(2);
965965
const GlobalValue *GValue = MO.getGlobal();
@@ -976,10 +976,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
976976
return;
977977
}
978978
case PPC::ADDIdtprelL:
979-
// Transform: %xd = ADDIdtprelL %xs, <ga:@sym>
979+
// Transform: %xd = ADDIdtprelL %xs, @sym
980980
// Into: %xd = ADDI8 %xs, sym@dtprel@l
981981
case PPC::ADDIdtprelL32: {
982-
// Transform: %rd = ADDIdtprelL32 %rs, <ga:@sym>
982+
// Transform: %rd = ADDIdtprelL32 %rs, @sym
983983
// Into: %rd = ADDI %rs, sym@dtprel@l
984984
const MachineOperand &MO = MI->getOperand(2);
985985
const GlobalValue *GValue = MO.getGlobal();

‎lib/Target/PowerPC/PPCISelDAGToDAG.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -4518,9 +4518,9 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
45184518

45194519
// The first source operand is a TargetGlobalAddress or a TargetJumpTable.
45204520
// If it must be toc-referenced according to PPCSubTarget, we generate:
4521-
// LDtocL(<ga:@sym>, ADDIStocHA(%x2, <ga:@sym>))
4521+
// LDtocL(@sym, ADDIStocHA(%x2, @sym))
45224522
// Otherwise we generate:
4523-
// ADDItocL(ADDIStocHA(%x2, <ga:@sym>), <ga:@sym>)
4523+
// ADDItocL(ADDIStocHA(%x2, @sym), @sym)
45244524
SDValue GA = N->getOperand(0);
45254525
SDValue TOCbase = N->getOperand(1);
45264526
SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,

‎lib/Target/PowerPC/PPCInstrInfo.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -2316,7 +2316,7 @@ PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
23162316
// For a method return value, we check the ZExt/SExt flags in attribute.
23172317
// We assume the following code sequence for method call.
23182318
// ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
2319-
// BL8_NOP <ga:@func>,...
2319+
// BL8_NOP @func,...
23202320
// ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
23212321
// %5 = COPY %x3; G8RC:%5
23222322
if (SrcReg == PPC::X3) {

‎test/CodeGen/AArch64/loh.mir

+36-36
Original file line numberDiff line numberDiff line change
@@ -22,14 +22,14 @@ tracksRegLiveness: true
2222
body: |
2323
bb.0:
2424
; CHECK: Adding MCLOH_AdrpAdrp:
25-
; CHECK-NEXT: %x1 = ADRP <ga:@g3>
26-
; CHECK-NEXT: %x1 = ADRP <ga:@g4>
25+
; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
26+
; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g4
2727
; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
28-
; CHECK-NEXT: %x1 = ADRP <ga:@g2>
29-
; CHECK-NEXT: %x1 = ADRP <ga:@g3>
28+
; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g2
29+
; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
3030
; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
31-
; CHECK-NEXT: %x0 = ADRP <ga:@g0>
32-
; CHECK-NEXT: %x0 = ADRP <ga:@g1>
31+
; CHECK-NEXT: %x0 = ADRP target-flags(aarch64-page) @g0
32+
; CHECK-NEXT: %x0 = ADRP target-flags(aarch64-page) @g1
3333
%x0 = ADRP target-flags(aarch64-page) @g0
3434
%x0 = ADRP target-flags(aarch64-page) @g1
3535
%x1 = ADRP target-flags(aarch64-page) @g2
@@ -38,11 +38,11 @@ body: |
3838
3939
bb.1:
4040
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
41-
; CHECK-NEXT: %x20 = ADRP <ga:@g0>
42-
; CHECK-NEXT: %x3 = ADDXri %x20, <ga:@g0>
41+
; CHECK-NEXT: %x20 = ADRP target-flags(aarch64-page) @g0
42+
; CHECK-NEXT: %x3 = ADDXri %x20, target-flags(aarch64-pageoff) @g0
4343
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
44-
; CHECK-NEXT: %x1 = ADRP <ga:@g0>
45-
; CHECK-NEXT: %x1 = ADDXri %x1, <ga:@g0>
44+
; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g0
45+
; CHECK-NEXT: %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0
4646
%x1 = ADRP target-flags(aarch64-page) @g0
4747
%x9 = SUBXri undef %x11, 5, 0 ; should not affect MCLOH formation
4848
%x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0, 0
@@ -73,23 +73,23 @@ body: |
7373
7474
bb.5:
7575
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
76-
; CHECK-NEXT: %x5 = ADRP <ga:@g2>
77-
; CHECK-NEXT: %s6 = LDRSui %x5, <ga:@g2>
76+
; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g2
77+
; CHECK-NEXT: %s6 = LDRSui %x5, target-flags(aarch64-pageoff) @g2
7878
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
79-
; CHECK-NEXT: %x4 = ADRP <ga:@g2>
80-
; CHECK-NEXT: %x4 = LDRXui %x4, <ga:@g2>
79+
; CHECK-NEXT: %x4 = ADRP target-flags(aarch64-page) @g2
80+
; CHECK-NEXT: %x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
8181
%x4 = ADRP target-flags(aarch64-page) @g2
8282
%x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
8383
%x5 = ADRP target-flags(aarch64-page) @g2
8484
%s6 = LDRSui %x5, target-flags(aarch64-pageoff) @g2
8585
8686
bb.6:
8787
; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
88-
; CHECK-NEXT: %x5 = ADRP <ga:@g2>
89-
; CHECK-NEXT: %x6 = LDRXui %x5, <ga:@g2>
88+
; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
89+
; CHECK-NEXT: %x6 = LDRXui %x5, target-flags(aarch64-pageoff, aarch64-got) @g2
9090
; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
91-
; CHECK-NEXT: %x4 = ADRP <ga:@g2>
92-
; CHECK-NEXT: %x4 = LDRXui %x4, <ga:@g2>
91+
; CHECK-NEXT: %x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
92+
; CHECK-NEXT: %x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
9393
%x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
9494
%x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
9595
%x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
@@ -104,23 +104,23 @@ body: |
104104
105105
bb.8:
106106
; CHECK-NEXT: Adding MCLOH_AdrpAddLdr:
107-
; CHECK-NEXT: %x7 = ADRP <ga:@g3>[TF=1]
108-
; CHECK-NEXT: %x8 = ADDXri %x7, <ga:@g3>
107+
; CHECK-NEXT: %x7 = ADRP target-flags(aarch64-page) @g3
108+
; CHECK-NEXT: %x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3
109109
; CHECK-NEXT: %d1 = LDRDui %x8, 8
110110
%x7 = ADRP target-flags(aarch64-page) @g3
111111
%x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3, 0
112112
%d1 = LDRDui %x8, 8
113113
114114
bb.9:
115115
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
116-
; CHECK-NEXT: %x3 = ADRP <ga:@g3>
117-
; CHECK-NEXT: %x3 = ADDXri %x3, <ga:@g3>
116+
; CHECK-NEXT: %x3 = ADRP target-flags(aarch64-page) @g3
117+
; CHECK-NEXT: %x3 = ADDXri %x3, target-flags(aarch64-pageoff) @g3
118118
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
119-
; CHECK-NEXT: %x5 = ADRP <ga:@g3>
120-
; CHECK-NEXT: %x2 = ADDXri %x5, <ga:@g3>
119+
; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g3
120+
; CHECK-NEXT: %x2 = ADDXri %x5, target-flags(aarch64-pageoff) @g3
121121
; CHECK-NEXT: Adding MCLOH_AdrpAddStr:
122-
; CHECK-NEXT: %x1 = ADRP <ga:@g3>
123-
; CHECK-NEXT: %x1 = ADDXri %x1, <ga:@g3>
122+
; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
123+
; CHECK-NEXT: %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3
124124
; CHECK-NEXT: STRXui %xzr, %x1, 16
125125
%x1 = ADRP target-flags(aarch64-page) @g3
126126
%x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3, 0
@@ -138,11 +138,11 @@ body: |
138138
139139
bb.10:
140140
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
141-
; CHECK-NEXT: %x2 = ADRP <ga:@g3>
142-
; CHECK-NEXT: %x2 = LDRXui %x2, <ga:@g3>
141+
; CHECK-NEXT: %x2 = ADRP target-flags(aarch64-page) @g3
142+
; CHECK-NEXT: %x2 = LDRXui %x2, target-flags(aarch64-pageoff) @g3
143143
; CHECK-NEXT: Adding MCLOH_AdrpLdrGotLdr:
144-
; CHECK-NEXT: %x1 = ADRP <ga:@g4>
145-
; CHECK-NEXT: %x1 = LDRXui %x1, <ga:@g4>
144+
; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
145+
; CHECK-NEXT: %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
146146
; CHECK-NEXT: %x1 = LDRXui %x1, 24
147147
%x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
148148
%x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
@@ -154,11 +154,11 @@ body: |
154154
155155
bb.11:
156156
; CHECK-NEXT: Adding MCLOH_AdrpLdr
157-
; CHECK-NEXT: %x5 = ADRP <ga:@g1>
158-
; CHECK-NEXT: %x5 = LDRXui %x5, <ga:@g1>
157+
; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g1
158+
; CHECK-NEXT: %x5 = LDRXui %x5, target-flags(aarch64-pageoff) @g1
159159
; CHECK-NEXT: Adding MCLOH_AdrpLdrGotStr:
160-
; CHECK-NEXT: %x1 = ADRP <ga:@g4>
161-
; CHECK-NEXT: %x1 = LDRXui %x1, <ga:@g4>
160+
; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
161+
; CHECK-NEXT: %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
162162
; CHECK-NEXT: STRXui %xzr, %x1, 32
163163
%x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
164164
%x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
@@ -171,8 +171,8 @@ body: |
171171
bb.12:
172172
; CHECK-NOT: MCLOH_AdrpAdrp
173173
; CHECK: Adding MCLOH_AdrpAddLdr
174-
; %x9 = ADRP <ga:@g4>
175-
; %x9 = ADDXri %x9, <ga:@g4>
174+
; %x9 = ADRP @g4
175+
; %x9 = ADDXri %x9, @g4
176176
; %x5 = LDRXui %x9, 0
177177
%x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4
178178
%x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0

‎test/CodeGen/ARM/misched-int-basic-thumb2.mir

+1-1
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@
3737
}
3838
#
3939
# CHECK: ********** MI Scheduling **********
40-
# CHECK: SU(2): %2:rgpr = t2MOVi32imm <ga:@g1>; rGPR:%2
40+
# CHECK: SU(2): %2:rgpr = t2MOVi32imm @g1; rGPR:%2
4141
# CHECK_A9: Latency : 2
4242
# CHECK_SWIFT: Latency : 2
4343
# CHECK_R52: Latency : 2

‎test/CodeGen/X86/stack-protector-weight.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -13,20 +13,20 @@
1313
; DARWIN-IR: Successors according to CFG: %bb.[[SUCCESS:[0-9]+]]({{[0-9a-fx/= ]+}}100.00%) %bb.[[FAILURE:[0-9]+]]
1414
; DARWIN-IR: %bb.[[SUCCESS]]:
1515
; DARWIN-IR: %bb.[[FAILURE]]:
16-
; DARWIN-IR: CALL64pcrel32 <ga:@__stack_chk_fail>
16+
; DARWIN-IR: CALL64pcrel32 @__stack_chk_fail
1717

1818
; MSVC-SELDAG: # Machine code for function test_branch_weights:
1919
; MSVC-SELDAG: mem:Volatile LD4[@__security_cookie]
2020
; MSVC-SELDAG: ST4[FixedStack0]
2121
; MSVC-SELDAG: LD4[FixedStack0]
22-
; MSVC-SELDAG: CALLpcrel32 <ga:@__security_check_cookie>
22+
; MSVC-SELDAG: CALLpcrel32 @__security_check_cookie
2323

2424
; MSVC always uses selection DAG now.
2525
; MSVC-IR: # Machine code for function test_branch_weights:
2626
; MSVC-IR: mem:Volatile LD4[@__security_cookie]
2727
; MSVC-IR: ST4[FixedStack0]
2828
; MSVC-IR: LD4[FixedStack0]
29-
; MSVC-IR: CALLpcrel32 <ga:@__security_check_cookie>
29+
; MSVC-IR: CALLpcrel32 @__security_check_cookie
3030

3131
define i32 @test_branch_weights(i32 %n) #0 {
3232
entry:

‎unittests/CodeGen/MachineOperandTest.cpp

+38-1
Original file line numberDiff line numberDiff line change
@@ -7,10 +7,11 @@
77
//
88
//===----------------------------------------------------------------------===//
99

10-
#include "llvm/ADT/ilist_node.h"
1110
#include "llvm/CodeGen/MachineOperand.h"
11+
#include "llvm/ADT/ilist_node.h"
1212
#include "llvm/IR/Constants.h"
1313
#include "llvm/IR/LLVMContext.h"
14+
#include "llvm/IR/Module.h"
1415
#include "llvm/IR/ModuleSlotTracker.h"
1516
#include "llvm/Support/raw_ostream.h"
1617
#include "gtest/gtest.h"
@@ -235,4 +236,40 @@ TEST(MachineOperandTest, PrintExternalSymbol) {
235236
}
236237
}
237238

239+
TEST(MachineOperandTest, PrintGlobalAddress) {
240+
LLVMContext Ctx;
241+
Module M("MachineOperandGVTest", Ctx);
242+
M.getOrInsertGlobal("foo", Type::getInt32Ty(Ctx));
243+
244+
GlobalValue *GV = M.getNamedValue("foo");
245+
246+
// Create a MachineOperand with a global address and a positive offset and
247+
// print it.
248+
MachineOperand MO = MachineOperand::CreateGA(GV, 12);
249+
250+
// Checking some preconditions on the newly created
251+
// MachineOperand.
252+
ASSERT_TRUE(MO.isGlobal());
253+
ASSERT_TRUE(MO.getGlobal() == GV);
254+
ASSERT_TRUE(MO.getOffset() == 12);
255+
256+
std::string str;
257+
// Print a MachineOperand containing a global address and a positive offset.
258+
{
259+
raw_string_ostream OS(str);
260+
MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
261+
ASSERT_TRUE(OS.str() == "@foo + 12");
262+
}
263+
264+
str.clear();
265+
MO.setOffset(-12);
266+
267+
// Print a MachineOperand containing a global address and a negative offset.
268+
{
269+
raw_string_ostream OS(str);
270+
MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
271+
ASSERT_TRUE(OS.str() == "@foo - 12");
272+
}
273+
}
274+
238275
} // end namespace

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