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IBMJimmykIBMJimmyk
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Added Asserts for large TOC offsets
For cases where the TOC offset is unusually large, I put in an assert instead of generating instructions. The reasoning was TOC offsets of this size should never occur so those code paths would never be tested. Also TOC offsets of that size are likely an indication of a problem elsewhere. Also changed addConstantToInteger to just truncate since it is handling 32 bit data which means it is okay for the bits outside the lower 32 bits to be garbage. Signed-off-by: jimmyk <jimmyk@ca.ibm.com>
1 parent 969749b commit cc406a1

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4 files changed

+15
-72
lines changed

4 files changed

+15
-72
lines changed

‎compiler/p/codegen/ControlFlowEvaluator.cpp

+6-27
Original file line numberDiff line numberDiff line change
@@ -3001,15 +3001,8 @@ static void lookupScheme3(TR::Node *node, bool unbalanced, TR::CodeGenerator *cg
30013001
TR_PPCTableOfConstants::setTOCSlot(offset, address);
30023002
if (offset<LOWER_IMMED||offset>UPPER_IMMED)
30033003
{
3004-
if (0x00008000 == cg->hiValue(offset))
3005-
{
3006-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, addrRegister, cg->getTOCBaseRegister(), 0x7FFF);
3007-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, addrRegister, addrRegister, 0x1);
3008-
}
3009-
else
3010-
{
3011-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, addrRegister, cg->getTOCBaseRegister(), cg->hiValue(offset));
3012-
}
3004+
TR_ASSERT_FATAL(0x00008000 != cg->hiValue(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
3005+
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, addrRegister, cg->getTOCBaseRegister(), cg->hiValue(offset));
30133006
generateTrg1MemInstruction(cg,TR::InstOpCode::Op_load, node, addrRegister, new (cg->trHeapMemory()) TR::MemoryReference(addrRegister, LO_VALUE(offset), 8, cg));
30143007
}
30153008
else
@@ -3311,15 +3304,8 @@ static void lookupScheme4(TR::Node *node, TR::CodeGenerator *cg)
33113304
TR_PPCTableOfConstants::setTOCSlot(offset, address);
33123305
if (offset<LOWER_IMMED||offset>UPPER_IMMED)
33133306
{
3314-
if (0x00008000 == cg->hiValue(offset))
3315-
{
3316-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, pivotRegister, cg->getTOCBaseRegister(), 0x7FFF);
3317-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, pivotRegister, pivotRegister, 0x1);
3318-
}
3319-
else
3320-
{
3321-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, pivotRegister, cg->getTOCBaseRegister(), cg->hiValue(offset));
3322-
}
3307+
TR_ASSERT_FATAL(0x00008000 != cg->hiValue(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
3308+
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, pivotRegister, cg->getTOCBaseRegister(), cg->hiValue(offset));
33233309
generateTrg1MemInstruction(cg,TR::InstOpCode::Op_load, node, addrRegister, new (cg->trHeapMemory()) TR::MemoryReference(pivotRegister, LO_VALUE(offset), 8, cg));
33243310
}
33253311
else
@@ -3512,15 +3498,8 @@ TR::Register *OMR::Power::TreeEvaluator::tableEvaluator(TR::Node *node, TR::Code
35123498
cg->itemTracking(offset, table);
35133499
if (offset<LOWER_IMMED||offset>UPPER_IMMED)
35143500
{
3515-
if (0x00008000 == cg->hiValue(offset))
3516-
{
3517-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, reg1, cg->getTOCBaseRegister(), 0x7FFF);
3518-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, reg1, reg1, 0x1);
3519-
}
3520-
else
3521-
{
3522-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, reg1, cg->getTOCBaseRegister(), cg->hiValue(offset));
3523-
}
3501+
TR_ASSERT_FATAL(0x00008000 != cg->hiValue(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
3502+
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, reg1, cg->getTOCBaseRegister(), cg->hiValue(offset));
35243503
generateTrg1MemInstruction(cg,TR::InstOpCode::Op_load, node, reg1, new (cg->trHeapMemory()) TR::MemoryReference(reg1, LO_VALUE(offset), 8, cg));
35253504
}
35263505
else

‎compiler/p/codegen/FPTreeEvaluator.cpp

+4-18
Original file line numberDiff line numberDiff line change
@@ -359,15 +359,8 @@ static TR::Register *fconstHandler(TR::Node *node, TR::CodeGenerator *cg, float
359359
{
360360
srcRegister = cg->allocateRegister();
361361

362-
if (0x00008000 == HI_VALUE(offset))
363-
{
364-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, cg->getTOCBaseRegister(), 0x7FFF);
365-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, srcRegister, 0x1);
366-
}
367-
else
368-
{
369-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, cg->getTOCBaseRegister(), HI_VALUE(offset));
370-
}
362+
TR_ASSERT_FATAL(0x00008000 != HI_VALUE(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
363+
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, cg->getTOCBaseRegister(), HI_VALUE(offset));
371364
generateTrg1MemInstruction(cg, TR::InstOpCode::lfs, node, trgRegister, new (cg->trHeapMemory()) TR::MemoryReference(srcRegister, LO_VALUE(offset), 4, cg));
372365
cg->stopUsingRegister(srcRegister);
373366
}
@@ -443,15 +436,8 @@ TR::Register *OMR::Power::TreeEvaluator::dconstEvaluator(TR::Node *node, TR::Cod
443436
{
444437
srcRegister = cg->allocateRegister();
445438

446-
if (0x00008000 == HI_VALUE(offset))
447-
{
448-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, cg->getTOCBaseRegister(), 0x7FFF);
449-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, srcRegister, 0x1);
450-
}
451-
else
452-
{
453-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, cg->getTOCBaseRegister(), HI_VALUE(offset));
454-
}
439+
TR_ASSERT_FATAL(0x00008000 != HI_VALUE(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
440+
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, cg->getTOCBaseRegister(), HI_VALUE(offset));
455441

456442
TR::MemoryReference *memRef = new (cg->trHeapMemory()) TR::MemoryReference(srcRegister, LO_VALUE(offset), 8, cg);
457443
if (splats)

‎compiler/p/codegen/OMRCodeGenerator.cpp

+3-18
Original file line numberDiff line numberDiff line change
@@ -3239,15 +3239,8 @@ OMR::Power::CodeGenerator::fixedLoadLabelAddressIntoReg(
32393239
self()->itemTracking(offset, label);
32403240
if (offset<LOWER_IMMED||offset>UPPER_IMMED)
32413241
{
3242-
if (0x00008000 == self()->hiValue(offset))
3243-
{
3244-
generateTrg1Src1ImmInstruction(self(), TR::InstOpCode::addis, node, trgReg, self()->getTOCBaseRegister(), 0x7FFF);
3245-
generateTrg1Src1ImmInstruction(self(), TR::InstOpCode::addis, node, trgReg, trgReg, 0x1);
3246-
}
3247-
else
3248-
{
3249-
generateTrg1Src1ImmInstruction(self(), TR::InstOpCode::addis, node, trgReg, self()->getTOCBaseRegister(), self()->hiValue(offset));
3250-
}
3242+
TR_ASSERT_FATAL(0x00008000 != self()->hiValue(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
3243+
generateTrg1Src1ImmInstruction(self(), TR::InstOpCode::addis, node, trgReg, self()->getTOCBaseRegister(), self()->hiValue(offset));
32513244
generateTrg1MemInstruction(self(),TR::InstOpCode::Op_load, node, trgReg, new (self()->trHeapMemory()) TR::MemoryReference(trgReg, LO_VALUE(offset), 8, self()));
32523245
}
32533246
else
@@ -3608,15 +3601,7 @@ TR::Register *addConstantToInteger(TR::Node * node, TR::Register *trgReg, TR::Re
36083601
}
36093602
else
36103603
{
3611-
if (0x00008000 == HI_VALUE(value))
3612-
{
3613-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, trgReg, srcReg, 0x7FFF);
3614-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, trgReg, trgReg, 0x1);
3615-
}
3616-
else
3617-
{
3618-
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, trgReg, srcReg, HI_VALUE(value));
3619-
}
3604+
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, trgReg, srcReg, (int16_t)HI_VALUE(value));
36203605

36213606
if (value & 0xFFFF)
36223607
{

‎compiler/p/codegen/OMRTreeEvaluator.cpp

+2-9
Original file line numberDiff line numberDiff line change
@@ -227,15 +227,8 @@ TR::Instruction *loadConstant(TR::CodeGenerator *cg, TR::Node * node, int64_t va
227227
TR_PPCTableOfConstants::setTOCSlot(offset, value);
228228
if (offset < LOWER_IMMED || offset > UPPER_IMMED)
229229
{
230-
if (0x00008000 == cg->hiValue(offset))
231-
{
232-
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, trgReg, cg->getTOCBaseRegister(), 0x7FFF, cursor);
233-
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, trgReg, trgReg, 0x1, cursor);
234-
}
235-
else
236-
{
237-
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, trgReg, cg->getTOCBaseRegister(), cg->hiValue(offset), cursor);
238-
}
230+
TR_ASSERT_FATAL(0x00008000 != cg->hiValue(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
231+
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, trgReg, cg->getTOCBaseRegister(), cg->hiValue(offset), cursor);
239232
cursor = generateTrg1MemInstruction(cg,TR::InstOpCode::Op_load, node, trgReg, new (cg->trHeapMemory()) TR::MemoryReference(trgReg, LO_VALUE(offset), 8, cg), cursor);
240233
}
241234
else

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