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S390GenerateInstructions.cpp
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/*******************************************************************************
* Copyright IBM Corp. and others 2000
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at https://www.eclipse.org/legal/epl-2.0/
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] https://openjdk.org/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0-only WITH Classpath-exception-2.0 OR GPL-2.0-only WITH OpenJDK-assembly-exception-1.0
*******************************************************************************/
#include "z/codegen/S390GenerateInstructions.hpp"
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "codegen/CodeGenerator.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/Relocation.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/S390Snippets.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/S390Evaluator.hpp"
#include "codegen/UnresolvedDataSnippet.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "infra/Assert.hpp"
#include "infra/List.hpp"
#include "ras/Debug.hpp"
#include "z/codegen/CallSnippet.hpp"
#include "z/codegen/S390Instruction.hpp"
class TR_OpaqueClassBlock;
class TR_OpaqueMethodBlock;
class TR_VirtualGuardSite;
#define INSN_HEAP cg->trHeapMemory()
////////////////////////////////////////////////////////////////////////////////
// Generate methods
////////////////////////////////////////////////////////////////////////////////
TR::Instruction *
generateS390LabelInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::LabelSymbol * sym,
TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390LabelInstruction(op, n, sym, preced, cg);
}
return new (INSN_HEAP) TR::S390LabelInstruction(op, n, sym, cg);
}
TR::Instruction *
generateS390LabelInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::LabelSymbol * sym,
TR::RegisterDependencyConditions * cond, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390LabelInstruction(op, n, sym, cond, preced, cg);
}
return new (INSN_HEAP) TR::S390LabelInstruction(op, n, sym, cond, cg);
}
TR::Instruction *
generateS390LabelInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Snippet * s,
TR::RegisterDependencyConditions * cond, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390LabelInstruction(op, n, s, cond, preced, cg);
}
return new (INSN_HEAP) TR::S390LabelInstruction(op, n, s, cond, cg);
}
TR::Instruction *
generateS390LabelInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Snippet * s, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390LabelInstruction(op, n, s, preced, cg);
}
return new (INSN_HEAP) TR::S390LabelInstruction(op, n, s, cg);
}
////////////////////////////////////////////////////////////////////////////////
// Generate methods
////////////////////////////////////////////////////////////////////////////////
TR::Instruction *
generateS390BranchInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::InstOpCode::S390BranchCondition brCond,
TR::Node * n, TR::LabelSymbol * sym, TR::Instruction * preced)
{
TR::S390BranchInstruction * cursor ;
if (preced)
cursor = new (INSN_HEAP) TR::S390BranchInstruction(op, brCond, n, sym, preced, cg);
else
cursor = new (INSN_HEAP) TR::S390BranchInstruction(op, brCond, n, sym, cg);
return cursor;
}
TR::Instruction* generateS390BranchInstruction(TR::CodeGenerator* cg, TR::InstOpCode::Mnemonic op, TR::Node* node, TR::InstOpCode::S390BranchCondition compareOpCode, TR::Register* targetReg, TR::Instruction* preced)
{
TR::Instruction* returnInstruction = generateS390RegInstruction(cg, op, node, targetReg, preced);
// RR type branch instructions use the first operand register field as a mask value
static_cast<TR::S390RegInstruction*>(returnInstruction)->setBranchCondition(compareOpCode);
return returnInstruction;
}
TR::Instruction *
generateS390BranchInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * targetReg,
TR::LabelSymbol * sym, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390BranchOnCountInstruction(op, n, targetReg, sym, preced, cg);
}
return new (INSN_HEAP) TR::S390BranchOnCountInstruction(op, n, targetReg, sym, cg);
}
TR::Instruction *
generateS390BranchInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * targetReg,
TR::RegisterDependencyConditions *cond, TR::LabelSymbol * sym, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390BranchOnCountInstruction(op, n, targetReg, cond, sym, preced, cg);
}
return new (INSN_HEAP) TR::S390BranchOnCountInstruction(op, n, targetReg, cond, sym, cg);
}
TR::Instruction *
generateS390BranchInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * sourceReg,
TR::Register * targetReg, TR::LabelSymbol * sym, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390BranchOnIndexInstruction(op, n, sourceReg, targetReg, sym, preced, cg);
}
return new (INSN_HEAP) TR::S390BranchOnIndexInstruction(op, n, sourceReg, targetReg, sym, cg);
}
TR::Instruction *
generateS390BranchInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::RegisterPair * sourceReg,
TR::Register * targetReg, TR::LabelSymbol * sym, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390BranchOnIndexInstruction(op, n, sourceReg, targetReg, sym, preced, cg);
}
return new (INSN_HEAP) TR::S390BranchOnIndexInstruction(op, n, sourceReg, targetReg, sym, cg);
}
TR::Instruction *
generateS390BranchInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::InstOpCode::S390BranchCondition brCond,
TR::Node * n, TR::LabelSymbol * sym, TR::RegisterDependencyConditions * cond, TR::Instruction * preced)
{
TR::S390BranchInstruction * cursor ;
if (preced)
cursor = new (INSN_HEAP) TR::S390BranchInstruction(op, brCond, n, sym, cond, preced, cg);
else
cursor = new (INSN_HEAP) TR::S390BranchInstruction(op, brCond, n, sym, cond, cg);
return cursor;
}
TR::Instruction *
generateS390BranchInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::InstOpCode::S390BranchCondition brCond,
TR::Node * n, TR::Snippet * s, TR::RegisterDependencyConditions * cond, TR::Instruction * preced)
{
TR::S390BranchInstruction * cursor ;
if (preced)
cursor = new (INSN_HEAP) TR::S390BranchInstruction(op, brCond, n, s, cond, preced, cg);
else
cursor = new (INSN_HEAP) TR::S390BranchInstruction(op, brCond, n, s, cond, cg);
return cursor;
}
TR::Instruction *
generateS390BranchInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::InstOpCode::S390BranchCondition brCond,
TR::Node * n, TR::Snippet * s, TR::Instruction * preced)
{
TR::S390BranchInstruction * cursor ;
if (preced)
cursor = new (INSN_HEAP) TR::S390BranchInstruction(op, brCond, n, s, preced, cg);
else
cursor = new (INSN_HEAP) TR::S390BranchInstruction(op, brCond, n, s, cg);
return cursor;
}
/**
* Given a compare-only opCode, return its corresponding compare-and-branch-relative opCode
*/
TR::InstOpCode::Mnemonic getReplacementCompareAndBranchOpCode(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic compareOpCode)
{
static char * disableS390CompareAndBranch = feGetEnv("TR_DISABLES390CompareAndBranch");
if (disableS390CompareAndBranch)
return TR::InstOpCode::bad ;
switch(compareOpCode)
{
case TR::InstOpCode::CR:
return TR::InstOpCode::CRJ;
break;
case TR::InstOpCode::CLR:
return TR::InstOpCode::CLRJ;
break;
case TR::InstOpCode::CGR:
return TR::InstOpCode::CGRJ;
break;
case TR::InstOpCode::CLGR:
return TR::InstOpCode::CLGRJ;
break;
case TR::InstOpCode::C:
return TR::InstOpCode::CIJ;
break;
case TR::InstOpCode::CL:
return TR::InstOpCode::CLIJ;
break;
case TR::InstOpCode::CG:
return TR::InstOpCode::CGIJ;
break;
case TR::InstOpCode::CLG:
return TR::InstOpCode::CLGIJ;
break;
default:
return TR::InstOpCode::bad;
break;
}
}
TR::InstOpCode::Mnemonic
getReplacementLongDisplacementOpCode(TR::CodeGenerator* cg, TR::InstOpCode::Mnemonic op, TR::MemoryReference* memRef)
{
if (!memRef->hasTemporaryNegativeOffset() && memRef->isLongDisplacementRequired())
{
auto longDisplacementMnemonic = TR::InstOpCode::getEquivalentLongDisplacementMnemonic(op);
if (longDisplacementMnemonic != TR::InstOpCode::bad)
{
op = longDisplacementMnemonic;
TR::DebugCounter::incStaticDebugCounter(cg->comp(), TR::DebugCounter::debugCounterName(cg->comp(), "z/memref/long-displacement-upgrade/(%s)", cg->comp()->signature()));
}
}
return op;
}
/**
* Generate a compare and a branch instruction. if z10 is available, this will
* attempt to generate a COMPARE AND BRANCH instruction, otherwise the a
* compare with the compareOpCode passed and a TR::InstOpCode::BRC with the passed branch
* condition will be generated.
*
* You are responsible for setting start and end of internal control flow if
* applicable.
*
* You can force the TR::InstOpCode::C* + TR::InstOpCode::BRC to be generated by setting the needsCC
* parameter to true (the default).
*/
TR::Instruction *
generateS390CompareAndBranchInstruction(TR::CodeGenerator * cg,
TR::InstOpCode::Mnemonic compareOpCode,
TR::Node * node,
TR::Register * first ,
TR::Register * second,
TR::InstOpCode::S390BranchCondition bc,
TR::LabelSymbol * branchDestination,
bool needsCC,
bool targetIsFarAndCold)
{
// declare a space for the instruction we'll return (the compare and branch
// instruction, or the branch instruction if z6 support is off).
TR::Instruction * returnInstruction = NULL;
// test to see if this node is suitable for compare and branch, and which
// compare and branch op code to use if so. if we get TR::InstOpCode::bad, it isn't
// suitable for compare and branch, and we'll generate the old fashioned way.
TR::InstOpCode::Mnemonic replacementOpCode = getReplacementCompareAndBranchOpCode(cg, compareOpCode);
// if we do not need the CC, we can try to use a compare and branch instruction.
// compare-and-branch instructions are zEC12 and above
if( !cg->comp()->getOption(TR_DisableCompareAndBranchInstruction) &&
!needsCC &&
replacementOpCode != TR::InstOpCode::bad &&
cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12))
{
// generate a compare and branch.
returnInstruction = (TR::S390RIEInstruction *)generateRIEInstruction(cg, replacementOpCode, node, first, second, branchDestination, bc);
}
// otherwise we'll generate with the compare opcode pased and an TR::InstOpCode::BRC.
else
{
// we'll generate a compare which sets CC in a manner which flags the
// condition we want to check, indicated by the passed-in opcode and condition.
// DXL we may have CC from previouse compare op of the same operands, so we don't need to
TR::Instruction* ccInst = NULL;
if (cg->hasCCInfo()) ccInst = cg->ccInstruction();
TR::Compilation *comp = cg->comp();
TR::InstOpCode opcTmp = TR::InstOpCode(compareOpCode);
TR_Debug * debugObj = cg->getDebug();
if (!needsCC && comp->getOption(TR_EnableEBBCCInfo) &&
cg->isActiveCompareCC(compareOpCode, first, second) &&
performTransformation(comp, "O^O generateS390CompareAndBranchInstruction case 1 remove RR Compare[%s\t %s, %s]: reuse CC from ccInst [%p].", opcTmp.getMnemonicName(), debugObj->getName(first),debugObj->getName(second),ccInst) )
returnInstruction = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, bc, node, branchDestination);
else if ( !needsCC && comp->getOption(TR_EnableEBBCCInfo) &&
cg->isActiveCompareCC(compareOpCode, second, first) &&
performTransformation(comp, "O^O generateS390CompareAndBranchInstruction case 2 remove RR Compare[%s\t %s, %s]: reuse CC from ccInst [%p].", opcTmp.getMnemonicName(), debugObj->getName(first),debugObj->getName(second),ccInst) )
returnInstruction = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, getReverseBranchCondition(bc), node, branchDestination);
else
{
generateRRInstruction(cg, compareOpCode, node, first, second, (TR::RegisterDependencyConditions*) 0);
// generate a branch on condition such that if CC is set as
// directed above, we take the branch.
returnInstruction = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, bc, node, branchDestination);
}
}
return returnInstruction;
}
/**
* Generate a compare and a branch instruction. if z10 is available, this will
* attempt to generate a COMPARE AND BRANCH instruction, otherwise the a
* compare with the compareOpCode passed and a TR::InstOpCode::BRC with the passed branch
* condition will be generated.
*
* When not generating a COMPARE AND BRANCH instruction, a new register may be allocated
* to contain the immediate value, which may need to be added into register dependencies.
*
* You are responsible for setting start and end of internal control flow if
* applicable.
*
* You can force the TR::InstOpCode::C* + TR::InstOpCode::BRC to be generated by setting the needsCC
* parameter to true (the default).
*/
template <typename imm32Or64Bit>
TR::Instruction *
generateS390CompareAndBranchInstruction(TR::CodeGenerator * cg,
TR::InstOpCode::Mnemonic compareOpCode,
TR::Node * node,
TR::Register * first ,
imm32Or64Bit second,
TR::InstOpCode::S390BranchCondition bc,
TR::LabelSymbol * branchDestination,
bool needsCC,
bool targetIsFarAndCold,
TR::Instruction *preced,
TR::RegisterDependencyConditions * cond)
{
// declare a space for the instruction we'll return (the compare and branch
// instruction, or the branch instruction if z6 support is off).
TR::Instruction * cursor = NULL;
TR::InstOpCode::Mnemonic replacementOpCode = TR::InstOpCode::bad;
// test to see if this node is suitable for compare and branch, and which
// compare and branch op code to use if so. if we get TR::InstOpCode::bad, it isn't
// suitable for compare and branch, and we'll generate the old fashioned way.
bool canUseReplacementOpCode = false;
switch(compareOpCode)
{
case TR::InstOpCode::CLR:
case TR::InstOpCode::CLGR:
case TR::InstOpCode::CL:
case TR::InstOpCode::CLG:
if(second == (second & 0xFF))
canUseReplacementOpCode = true;
default:
if ((second >= MIN_IMMEDIATE_BYTE_VAL) && (second <= MAX_IMMEDIATE_BYTE_VAL))
canUseReplacementOpCode = true;
}
if (canUseReplacementOpCode)
replacementOpCode = getReplacementCompareAndBranchOpCode(cg, compareOpCode);
// if we do not need the CC, we can try to use a compare and branch instruction.
// compare-and-branch instructions are zEC12 and above
if( !cg->comp()->getOption(TR_DisableCompareAndBranchInstruction) &&
!needsCC &&
replacementOpCode != TR::InstOpCode::bad &&
cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12))
{
cursor = (TR::S390RIEInstruction *)generateRIEInstruction(cg, replacementOpCode, node, first, (int8_t) second, branchDestination, bc, preced);
}
// otherwise we'll generate with the compare opcode pased and an TR::InstOpCode::BRC.
else
{
// we'll generate a compare which sets CC in a manner which flags the
// condition we want to check, indicated by the passed-in opcode and condition.
cursor = generateS390ImmOp(cg, compareOpCode, node, first, first, second, cond, NULL, preced);
// generate a branch on condition such that if CC is set as
// directed above, we take the branch.
cursor = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, bc, node, branchDestination, cursor);
}
return cursor;
}
TR::Instruction *
generateS390RegInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RegInstruction(op, n, treg, preced, cg);
}
return new (INSN_HEAP) TR::S390RegInstruction(op, n, treg, cg);
}
TR::Instruction *
generateS390RegInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg,
TR::RegisterDependencyConditions * cond, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RegInstruction(op, n, treg, cond, preced, cg);
}
return new (INSN_HEAP) TR::S390RegInstruction(op, n, treg, cond, cg);
}
TR::Instruction *
generateRRInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Register * sreg,
TR::Instruction * preced)
{
TR::Instruction *instr;
if (preced)
instr = new (INSN_HEAP) TR::S390RRInstruction(op, n, treg, sreg, preced, cg);
else
instr = new (INSN_HEAP) TR::S390RRInstruction(op, n, treg, sreg, cg);
return instr;
}
TR::Instruction *
generateRRInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, int8_t secondConstant,
TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RRInstruction(op, n, treg, secondConstant, preced, cg);
}
return new (INSN_HEAP) TR::S390RRInstruction(op, n, treg, secondConstant, cg);
}
TR::Instruction *
generateRRInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, int8_t firstConstant, int8_t secondConstant,
TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RRInstruction(op, n, firstConstant, secondConstant, preced, cg);
}
return new (INSN_HEAP) TR::S390RRInstruction(op, n, firstConstant, secondConstant, cg);
}
TR::Instruction *
generateRRInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, int8_t firstConstant, TR::Register * sreg,
TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RRInstruction(op, n, firstConstant, sreg, preced, cg);
}
return new (INSN_HEAP) TR::S390RRInstruction(op, n, firstConstant, sreg, cg);
}
TR::Instruction *
generateRRInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Register * sreg,
TR::RegisterDependencyConditions * cond, TR::Instruction * preced)
{
TR::Instruction *instr;
if (preced)
instr = new (INSN_HEAP) TR::S390RRInstruction(op, n, treg, sreg, cond, preced, cg);
else
instr = new (INSN_HEAP) TR::S390RRInstruction(op, n, treg, sreg, cond, cg);
return instr;
}
TR::Instruction *
generateRRDInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Register * sreg,
TR::Register * sreg2, TR::Instruction * preced)
{
bool encodeAsRRD = true;
if (preced)
{
return new (INSN_HEAP) TR::S390RRFInstruction(encodeAsRRD, op, n, treg, sreg, sreg2, preced, cg);
}
return new (INSN_HEAP) TR::S390RRFInstruction(encodeAsRRD, op, n, treg, sreg, sreg2, cg);
}
TR::Instruction *
generateRRFInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, uint8_t mask, bool isMask3,
TR::Instruction * preced)
{
return new (INSN_HEAP) TR::S390RRFInstruction(op, n, mask, isMask3, cg);
}
TR::Instruction *
generateRRFInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Register * sreg,
TR::Register * sreg2, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RRFInstruction(op, n, treg, sreg, sreg2, preced, cg);
}
return new (INSN_HEAP) TR::S390RRFInstruction(op, n, treg, sreg, sreg2, cg);
}
TR::Instruction *
generateRRFInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Register * sreg,
uint8_t mask, bool isMask3, TR::Instruction * preced)
{
return new (INSN_HEAP) TR::S390RRFInstruction(op, n, treg, sreg, mask, isMask3, cg);
}
TR::Instruction *
generateRRFInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Register * sreg,
uint8_t mask, bool isMask3, TR::RegisterDependencyConditions * cond, TR::Instruction * preced)
{
return new (INSN_HEAP) TR::S390RRFInstruction(op, n, treg, sreg, mask, isMask3, cond, cg);
}
TR::Instruction *
generateRRFInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Register * sreg,
TR::Register * sreg2, uint8_t mask, TR::Instruction * preced)
{
return new (INSN_HEAP) TR::S390RRFInstruction(op, n, treg, sreg, sreg2, mask, cg);
}
TR::Instruction *
generateRRFInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg,
TR::Register * sreg, uint8_t mask3, uint8_t mask4, TR::Instruction * preced)
{
return new (INSN_HEAP) TR::S390RRFInstruction(op, n, treg, sreg, mask3, mask4, cg);
}
TR::Instruction *
generateRRRInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Register * sreg,
TR::Register * sreg2, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RRRInstruction(op, n, treg, sreg, sreg2, preced, cg);
}
return new (INSN_HEAP) TR::S390RRRInstruction(op, n, treg, sreg, sreg2, cg);
}
/**
* Iterate through conds1 and conds2, checking for a specific merge conflict:
* This function returns true if two dependency conditions exist with the same real register but different virtual registers
* If this function returns true, it can optionally output the two conflicting register dependency objects.
* Otherwise, this function returns false.
* Optionally, the caller can limit the search for conflicts containing only one type of real register.
*/
bool CheckForRegisterDependencyConditionsRealRegisterMergeConflict( TR::RegisterDependencyGroup * conds1,
int conds1_addCursor,
TR::RegisterDependencyGroup * conds2,
int conds2_addCursor,
TR::RegisterDependency ** conflict1,
TR::RegisterDependency ** conflict2,
TR::CodeGenerator *cg,
TR::RealRegister::RegNum checkForThisRealRegister = TR::RealRegister::NoReg)
{
for( int i = 0; i < conds1_addCursor; i++ )
{
TR::RealRegister::RegNum conds1_real = conds1->getRegisterDependency( i )->getRealRegister();
if(( checkForThisRealRegister != TR::RealRegister::NoReg ) && ( conds1_real != checkForThisRealRegister ))
{
continue;
}
for( int j = 0; j < conds2_addCursor; j++ )
{
TR::RealRegister::RegNum conds2_real = conds2->getRegisterDependency( j )->getRealRegister();
if(( checkForThisRealRegister != TR::RealRegister::NoReg ) && ( conds2_real != checkForThisRealRegister ))
{
continue;
}
if(( conds1_real == conds2_real ) &&
( conds1->getRegisterDependency(i)->getRegister() != conds2->getRegisterDependency(j)->getRegister() ))
{
// Conflict found
if( conflict1 && conflict2 )
{
*conflict1 = conds1->getRegisterDependency( i );
*conflict2 = conds2->getRegisterDependency( j );
}
return true;
}
}
}
return false;
}
TR::Instruction *
generateRXInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::MemoryReference * mf,
TR::Instruction * preced)
{
TR::Compilation* comp = cg->comp();
TR_ASSERT(treg->getRealRegister()!=NULL || // Not in RA
op != TR::InstOpCode::L || !n->isExtendedTo64BitAtSource(), "Generating an TR::InstOpCode::L, when LLGF|LGF should be used");
// Handle long displacement if necessary
op = getReplacementLongDisplacementOpCode(cg, op, mf);
TR::Instruction* result = NULL;
auto instructionFormat = TR::InstOpCode(op).getInstructionFormat();
if (instructionFormat == RXa_FORMAT)
{
result = preced != NULL ?
new (INSN_HEAP) TR::S390RXInstruction(op, n, treg, mf, preced, cg) :
new (INSN_HEAP) TR::S390RXInstruction(op, n, treg, mf, cg);
}
else
{
TR_ASSERT_FATAL(instructionFormat == RXYa_FORMAT || instructionFormat == RXYc_FORMAT, "Mnemonic (%s) is incorrectly used as an RXY instruction", TR::InstOpCode::metadata[op].name);
result = preced != NULL ?
new (INSN_HEAP) TR::S390RXYInstruction(op, n, treg, mf, preced, cg) :
new (INSN_HEAP) TR::S390RXYInstruction(op, n, treg, mf, cg);
}
#ifdef J9_PROJECT_SPECIFIC
if (op == TR::InstOpCode::CVB || op == TR::InstOpCode::CVBY || op == TR::InstOpCode::CVBG || op == TR::InstOpCode::EX)
{
// NOP padding needed only for RX instructions which are CVB and EX
const bool isNOPNeeded = op == TR::InstOpCode::CVB || op == TR::InstOpCode::EX;
generateS390DAAExceptionRestoreSnippet(cg, n, result, op, isNOPNeeded);
}
#endif
return result;
}
TR::Instruction*
generateRXInstruction(TR::CodeGenerator* cg, TR::InstOpCode::Mnemonic op, TR::Node* n, uint8_t mask, TR::MemoryReference* mf, TR::Instruction* preced)
{
// Handle long displacement if necessary
op = getReplacementLongDisplacementOpCode(cg, op, mf);
TR::Instruction* result = NULL;
auto instructionFormat = TR::InstOpCode(op).getInstructionFormat();
if (instructionFormat == RXb_FORMAT)
{
TR_ASSERT_FATAL(false, "RX-b format instructions for mnemonic (%s) are currently not implemented", TR::InstOpCode::metadata[op].name);
}
else
{
TR_ASSERT_FATAL(instructionFormat == RXYb_FORMAT, "Mnemonic (%s) is incorrectly used as an RXY instruction", TR::InstOpCode::metadata[op].name);
result = preced != NULL ?
new (INSN_HEAP) TR::S390RXYbInstruction(op, n, mask, mf, preced, cg) :
new (INSN_HEAP) TR::S390RXYbInstruction(op, n, mask, mf, cg);
}
return result;
}
TR::Instruction *
generateRXEInstruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node *n, TR::Register *treg, TR::MemoryReference *mf,
uint8_t mask3, TR::Instruction *preced)
{
TR::Instruction * instr;
if (preced)
instr = new (INSN_HEAP) TR::S390RXEInstruction(op, n, treg, mf, mask3, preced, cg);
else
instr = new (INSN_HEAP) TR::S390RXEInstruction(op, n, treg, mf, mask3, cg);
return instr;
}
TR::Instruction *
generateRXFInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Register * sreg,
TR::MemoryReference * mf, TR::Instruction * preced)
{
TR::Instruction *instr;
if (preced)
instr = new (INSN_HEAP) TR::S390RXFInstruction(op, n, treg, sreg, mf, preced, cg);
else
instr = new (INSN_HEAP) TR::S390RXFInstruction(op, n, treg, sreg, mf, cg);
return instr;
}
TR::Instruction *
generateRIInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RIInstruction(op, n, preced, cg);
}
return new (INSN_HEAP) TR::S390RIInstruction(op, n, cg);
}
TR::Instruction *
generateRIInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RIInstruction(op, n, treg, preced, cg);
}
return new (INSN_HEAP) TR::S390RIInstruction(op, n, treg, cg);
}
TR::Instruction *
generateRIInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, int32_t imm, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RIInstruction(op, n, treg, imm, preced, cg);
}
return new (INSN_HEAP) TR::S390RIInstruction(op, n, treg, imm, cg);
}
TR::Instruction *
generateRIInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, char *data, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RIInstruction(op, n, treg, data, preced, cg);
}
return new (INSN_HEAP) TR::S390RIInstruction(op, n, treg, data, cg);
}
TR::Instruction *
generateRILInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::SymbolReference * sr, void * addr, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, addr, sr, preced, cg);
}
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, addr, sr, cg);
}
TR::Instruction *
generateRILInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::LabelSymbol * label, TR::Instruction * preced)
{
if (preced)
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, label, preced, cg);
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, label, cg);
}
TR::Instruction *
generateRILInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, uint32_t imm, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, imm, preced, cg);
}
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, imm, cg);
}
TR::Instruction *
generateRILInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, int32_t imm, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, imm, preced, cg);
}
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, imm, cg);
}
TR::Instruction *
generateRILInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, void * addr, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, addr, preced, cg);
}
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, addr, cg);
}
TR::Instruction *
generateRILInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, uint32_t mask, void * addr, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RILInstruction(op, n, mask, addr, preced, cg);
}
return new (INSN_HEAP) TR::S390RILInstruction(op, n, mask, addr, cg);
}
TR::Instruction *
generateRILInstruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register *treg, TR::Snippet *ts, TR::Instruction *preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, ts, preced, cg);
}
return new (INSN_HEAP) TR::S390RILInstruction(op, n, treg, ts, cg);
}
TR::Instruction *
generateRSInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, uint32_t imm, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, imm, preced, cg);
}
return new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, imm, cg);
}
TR::Instruction *
generateRSInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, uint32_t imm,
TR::RegisterDependencyConditions * cond, TR::Instruction * preced)
{
if (preced)
{
return new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, imm, cond, preced, cg);
}
return new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, imm, cond, cg);
}
TR::Instruction *
generateRSInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, TR::MemoryReference * mf,
TR::Instruction * preced)
{
// RS and RSY instructions do not have an index register
preced = mf->separateIndexRegister(n, cg, false, preced);
// Handle long displacement if necessary
op = getReplacementLongDisplacementOpCode(cg, op, mf);
TR::Instruction* result = NULL;
auto instructionFormat = TR::InstOpCode(op).getInstructionFormat();
if (instructionFormat == RSa_FORMAT)
{
result = preced != NULL ?
new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, mf, preced, cg) :
new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, mf, cg);
}
else
{
TR_ASSERT_FATAL(instructionFormat == RSYa_FORMAT, "Mnemonic (%s) is incorrectly used as an RSY instruction", TR::InstOpCode::metadata[op].name);
result = preced != NULL ?
new (INSN_HEAP) TR::S390RSYInstruction(op, n, treg, static_cast<uint32_t>(0), mf, preced, cg) :
new (INSN_HEAP) TR::S390RSYInstruction(op, n, treg, static_cast<uint32_t>(0), mf, cg);
}
return result;
}
TR::Instruction *
generateRSInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * treg, uint32_t mask,
TR::MemoryReference * mf, TR::Instruction * preced)
{
// RS and RSY instructions do not have an index register
preced = mf->separateIndexRegister(n, cg, false, preced);
// Handle long displacement if necessary
op = getReplacementLongDisplacementOpCode(cg, op, mf);
TR::Instruction* result = NULL;
auto instructionFormat = TR::InstOpCode(op).getInstructionFormat();
if (instructionFormat == RSb_FORMAT)
{
result = preced != NULL ?
new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, mask, mf, preced, cg) :
new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, mask, mf, cg);
}
else
{
TR_ASSERT_FATAL(instructionFormat == RSYb_FORMAT, "Mnemonic (%s) is incorrectly used as an RSY instruction", TR::InstOpCode::metadata[op].name);
result = preced != NULL ?
new (INSN_HEAP) TR::S390RSYInstruction(op, n, treg, mask, mf, preced, cg) :
new (INSN_HEAP) TR::S390RSYInstruction(op, n, treg, mask, mf, cg);
}
return result;
}
TR::Instruction *
generateRSInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::RegisterPair * treg, TR::RegisterPair * sreg,
TR::MemoryReference * mf, TR::Instruction * preced)
{
// RS and RSY instructions do not have an index register
preced = mf->separateIndexRegister(n, cg, false, preced);
// Handle long displacement if necessary
op = getReplacementLongDisplacementOpCode(cg, op, mf);
TR::Instruction* result = NULL;
auto instructionFormat = TR::InstOpCode(op).getInstructionFormat();
if (instructionFormat == RSa_FORMAT)
{
result = preced != NULL ?
new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, sreg, mf, preced, cg) :
new (INSN_HEAP) TR::S390RSInstruction(op, n, treg, sreg, mf, cg);
}
else
{
TR_ASSERT_FATAL(instructionFormat == RSYa_FORMAT, "Mnemonic (%s) is incorrectly used as an RSY instruction", TR::InstOpCode::metadata[op].name);
result = preced != NULL ?
new (INSN_HEAP) TR::S390RSYInstruction(op, n, treg, sreg, mf, preced, cg) :
new (INSN_HEAP) TR::S390RSYInstruction(op, n, treg, sreg, mf, cg);
}
return result;
}
TR::Instruction *
generateRSInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * freg, TR::Register * lreg,
TR::MemoryReference * mf, TR::Instruction * preced)
{
// RS and RSY instructions do not have an index register
preced = mf->separateIndexRegister(n, cg, false, preced);
// Handle long displacement if necessary
op = getReplacementLongDisplacementOpCode(cg, op, mf);
TR::Instruction* result = NULL;
auto instructionFormat = TR::InstOpCode(op).getInstructionFormat();
if (instructionFormat == RSa_FORMAT)
{
result = preced != NULL ?
new (INSN_HEAP) TR::S390RSInstruction(op, n, freg, lreg, mf, preced, cg) :
new (INSN_HEAP) TR::S390RSInstruction(op, n, freg, lreg, mf, cg);
}
else
{
TR_ASSERT_FATAL(instructionFormat == RSYa_FORMAT, "Mnemonic (%s) is incorrectly used as an RSY instruction", TR::InstOpCode::metadata[op].name);
result = preced != NULL ?
new (INSN_HEAP) TR::S390RSYInstruction(op, n, freg, lreg, mf, preced, cg) :
new (INSN_HEAP) TR::S390RSYInstruction(op, n, freg, lreg, mf, cg);
}
return result;
}
TR::Instruction *
generateRSInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::RegisterPair * regp, TR::MemoryReference * mf,
TR::Instruction * preced)