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ControlFlowEvaluator.cpp
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/*******************************************************************************
*
* (c) Copyright IBM Corp. 2000, 2016
*
* This program and the accompanying materials are made available
* under the terms of the Eclipse Public License v1.0 and
* Apache License v2.0 which accompanies this distribution.
*
* The Eclipse Public License is available at
* http://www.eclipse.org/legal/epl-v10.html
*
* The Apache License v2.0 is available at
* http://www.opensource.org/licenses/apache2.0.php
*
* Contributors:
* Multiple authors (IBM Corp.) - initial implementation and documentation
*******************************************************************************/
#include "arm/codegen/ARMInstruction.hpp"
#include "arm/codegen/ARMOperand2.hpp"
#include "codegen/AheadOfTimeCompile.hpp"
#include "codegen/ARMAOTRelocation.hpp"
#include "codegen/CallSnippet.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/GenerateInstructions.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "compile/VirtualGuard.hpp" // for TR_VirtualGuard
#include "env/CompilerEnv.hpp"
#include "infra/Bit.hpp"
#include "il/Block.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "trj9/env/CHTable.hpp" // for TR_AOTGuardSite, etc
#endif
static void lookupScheme1(TR::CodeGenerator *cg, TR::Node *node, bool unbalanced);
static void lookupScheme2(TR::CodeGenerator *cg, TR::Node *node, bool unbalanced);
static void lookupScheme3(TR::CodeGenerator *cg, TR::Node *node, bool unbalanced);
static void lookupScheme4(TR::CodeGenerator *cg, TR::Node *node);
static bool isGlDepsUnBalanced(TR::CodeGenerator *cg, TR::Node *node);
static void switchDispatch(TR::CodeGenerator *cg, TR::Node *node);
static bool virtualGuardHelper(TR::Node *node, TR::CodeGenerator *cg);
TR::Register *OMR::ARM::TreeEvaluator::gotoEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::LabelSymbol *gotoLabel = node->getBranchDestination()->getNode()->getLabel();
if (node->getNumChildren() > 0)
{
TR::Node *child = node->getFirstChild();
cg->evaluate(child);
generateLabelInstruction(cg, ARMOp_b, node, gotoLabel, generateRegisterDependencyConditions(cg, child, 0));
child->decReferenceCount();
}
else
{
generateLabelInstruction(cg, ARMOp_b, node, gotoLabel);
}
return NULL;
}
// also handles areturn
TR::Register *OMR::ARM::TreeEvaluator::ireturnEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *returnRegister = cg->evaluate(node->getFirstChild());
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(1, 1, cg->trMemory());
addDependency(deps, returnRegister, cg->getProperties().getIntegerReturnRegister(), TR_GPR, cg);
generateAdminInstruction(cg, ARMOp_ret, node, deps);
TR::comp()->setReturnInfo(TR_IntReturn);
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::lreturnEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *returnRegister = cg->evaluate(node->getFirstChild());
TR::Register *lowReg = returnRegister->getLowOrder();
TR::Register *highReg = returnRegister->getHighOrder();
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(2, 2, cg->trMemory());
addDependency(deps, lowReg, cg->getProperties().getLongLowReturnRegister(), TR_GPR, cg);
addDependency(deps, highReg, cg->getProperties().getLongHighReturnRegister(), TR_GPR, cg);
generateAdminInstruction(cg, ARMOp_ret, node, deps);
TR::comp()->setReturnInfo(TR_LongReturn);
return NULL;
}
// areturn handled by ireturnEvaluator
TR::Register *OMR::ARM::TreeEvaluator::returnEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
generateAdminInstruction(cg, ARMOp_ret, node);
TR::comp()->setReturnInfo(TR_VoidReturn);
return NULL;
}
static TR::Instruction *compareIntsForOrder(TR_ARMConditionCode branchType,
TR::Node *node,
TR::CodeGenerator *cg,
TR::SymbolReference *sr = NULL)
{
TR::Node *secondChild = node->getSecondChild();
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg;
uint32_t base, rotate;
TR::LabelSymbol *branchTarget = sr ? NULL : node->getBranchDestination()->getNode()->getLabel();
TR::Instruction *result;
int32_t value = secondChild->getInt();
bool cannotInline = false;
// For TR::instanceof, the opcode must be ificmpeq/ne.
if (!TR::comp()->getOption(TR_OptimizeForSpace) &&
firstChild->getOpCodeValue() == TR::instanceof &&
firstChild->getRegister() == NULL &&
node->getReferenceCount() <=1 &&
(value == 0 || value == 1))
{
TR_ASSERT(node->getOpCodeValue() == TR::ificmpeq || node->getOpCodeValue() == TR::ificmpne,
"Unexpected opcode");
TR_ASSERT(secondChild->getOpCode().isLoadConst(),
"Unexpected second child.\n");
if (OMR::ARM::TreeEvaluator::VMifInstanceOfEvaluator(node, cg) == NULL)
return NULL;
cannotInline = true;
TR::Node::recreate(firstChild, TR::icall);
}
src1Reg = cg->evaluate(firstChild);
if (cannotInline)
{
TR::Node::recreate(firstChild, TR::instanceof);
}
bool foundConst = false;
bool negated;
int32_t cmpValue;
if (secondChild->getOpCode().isLoadConst())
{
cmpValue = secondChild->getInt();
negated = cmpValue < 0 && cmpValue != 0x80000000; //the negative of the maximum negative int is itself so can not use cmn here
if(constantIsImmed8r(negated ? -cmpValue : cmpValue, &base, &rotate))
{
generateSrc1ImmInstruction(cg, negated ? ARMOp_cmn : ARMOp_cmp, node, src1Reg, base, rotate);
foundConst = true;
}
}
if(!foundConst)
generateSrc2Instruction(cg, ARMOp_cmp, node, src1Reg, cg->evaluate(secondChild));
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *thirdChild = node->getChild(2);
TR_ASSERT(thirdChild->getOpCodeValue() == TR::GlRegDeps,
"The third child of a compare must be a TR::GlRegDeps");
cg->evaluate(thirdChild);
// NB: must generate reg deps before the conditonal branch
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount(); // IS it correct to decReferenceCount before the instruction generation ?!!!
}
if (!sr)
{
result = generateConditionalBranchInstruction(cg, node, branchType, branchTarget, deps);
}
else
{
result = generateImmSymInstruction(cg, ARMOp_bl, node, (uintptr_t)sr->getMethodAddress(), deps, sr, NULL, NULL, branchType);
cg->machine()->setLinkRegisterKilled(true);
}
firstChild->decReferenceCount();
secondChild->decReferenceCount();
return result;
}
TR::Instruction *OMR::ARM::TreeEvaluator::compareIntsForEquality(TR_ARMConditionCode branchType,
TR::Node *node,
TR::CodeGenerator *cg,
TR::SymbolReference *sr)
{
if (virtualGuardHelper(node, cg))
return NULL;
TR::Compilation *comp = TR::comp();
TR::Node *secondChild = node->getSecondChild();
TR::Node *firstChild = node->getFirstChild();
#ifdef J9_PROJECT_SPECIFIC
if (cg->profiledPointersRequireRelocation() && node->isProfiledGuard() && secondChild->getOpCodeValue() == TR::aconst &&
(secondChild->isClassPointerConstant() || secondChild->isMethodPointerConstant()))
{
TR_VirtualGuard *virtualGuard = comp->findVirtualGuardInfo(node);
TR_AOTGuardSite *site = comp->addAOTNOPSite();
site->setType(TR_ProfiledGuard);
site->setGuard(virtualGuard);
site->setNode(node);
site->setAconstNode(secondChild);
}
#endif
TR::Register *src1Reg;
uint32_t base, rotate;
TR::LabelSymbol *branchTarget = sr ? NULL : node->getBranchDestination()->getNode()->getLabel();
TR::Instruction *result;
int32_t value = secondChild->getInt();
bool cannotInline = false;
// For TR::instanceof, the opcode must be ificmpeq/ne.
if (!TR::comp()->getOption(TR_OptimizeForSpace) &&
firstChild->getOpCodeValue() == TR::instanceof &&
firstChild->getRegister() == NULL &&
node->getReferenceCount() <=1 &&
(value == 0 || value == 1))
{
TR_ASSERT(node->getOpCodeValue() == TR::ificmpeq || node->getOpCodeValue() == TR::ificmpne,
"Unexpected opcode");
TR_ASSERT(secondChild->getOpCode().isLoadConst(),
"Unexpected second child.\n");
if (OMR::ARM::TreeEvaluator::VMifInstanceOfEvaluator(node, cg) == NULL)
return NULL;
cannotInline = true;
TR::Node::recreate(firstChild, TR::icall);
}
src1Reg = cg->evaluate(firstChild);
if (cannotInline)
{
TR::Node::recreate(firstChild, TR::instanceof);
}
bool foundConst = false;
bool negated;
int32_t cmpValue;
if (secondChild->getOpCode().isLoadConst())
{
cmpValue = secondChild->getInt();
negated = cmpValue < 0 && cmpValue != 0x80000000; //the negative of the maximum negative int is itself so can not use cmn here
if(constantIsImmed8r(negated ? -cmpValue : cmpValue, &base, &rotate))
{
generateSrc1ImmInstruction(cg, negated ? ARMOp_cmn : ARMOp_cmp, node, src1Reg, base, rotate);
foundConst = true;
}
}
if(!foundConst)
generateSrc2Instruction(cg, ARMOp_cmp, node, src1Reg, cg->evaluate(secondChild));
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *thirdChild = node->getChild(2);
TR_ASSERT(thirdChild->getOpCodeValue() == TR::GlRegDeps,
"The third child of a compare must be a TR::GlRegDeps");
cg->evaluate(thirdChild);
// NB: must generate reg deps before the conditonal branch
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount(); // IS it correct to decReferenceCount before the instruction generation ?!!!
}
if (!sr)
{
result = generateConditionalBranchInstruction(cg, node, branchType, branchTarget, deps);
}
else
{
result = generateImmSymInstruction(cg, ARMOp_bl, node, (uintptr_t)sr->getMethodAddress(), deps, sr, NULL, NULL, branchType);
cg->machine()->setLinkRegisterKilled(true);
}
firstChild->decReferenceCount();
secondChild->decReferenceCount();
return result;
}
static bool virtualGuardHelper(TR::Node *node, TR::CodeGenerator *cg)
{
#ifdef J9_PROJECT_SPECIFIC
TR::Compilation *comp = cg->comp();
if ((!node->isNopableInlineGuard() && !node->isHCRGuard()) ||
!cg->getSupportsVirtualGuardNOPing())
return false;
TR_VirtualGuard *virtualGuard = comp->findVirtualGuardInfo(node);
if (!((comp->performVirtualGuardNOPing() || node->isHCRGuard()) &&
comp->isVirtualGuardNOPingRequired(virtualGuard)) &&
virtualGuard->canBeRemoved())
return false;
if ( node->getOpCodeValue() != TR::ificmpne
&& node->getOpCodeValue() != TR::iflcmpne
&& node->getOpCodeValue() != TR::ifacmpne)
{
//TR_ASSERT(0, "virtualGuradHelper: not expecting reversed comparison");
return false;
}
TR_VirtualGuardSite *site = NULL;
if (comp->compileRelocatableCode())
{
site = (TR_VirtualGuardSite *)comp->addAOTNOPSite();
TR_AOTGuardSite *aotSite = (TR_AOTGuardSite *)site;
aotSite->setType(virtualGuard->getKind());
aotSite->setNode(node);
switch (virtualGuard->getKind())
{
case TR_DirectMethodGuard:
case TR_NonoverriddenGuard:
case TR_InterfaceGuard:
case TR_MethodEnterExitGuard:
case TR_HCRGuard:
aotSite->setGuard(virtualGuard);
break;
case TR_ProfiledGuard:
break;
default:
TR_ASSERT(0, "got AOT guard in node but virtual guard not one of known guards supported for AOT. Guard: %d", virtualGuard->getKind());
break;
}
}
else if (!node->isSideEffectGuard())
{
TR_VirtualGuard *virtualGuard = comp->findVirtualGuardInfo(node);
site = virtualGuard->addNOPSite();
}
else
site = comp->addSideEffectNOPSite();
TR::RegisterDependencyConditions *deps;
if (node->getNumChildren() == 3)
{
TR::Node *third = node->getChild(2);
cg->evaluate(third);
deps = generateRegisterDependencyConditions(cg, third, 0);
}
else
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 0, cg->trMemory());
if(virtualGuard->shouldGenerateChildrenCode())
cg->evaluateChildrenWithMultipleRefCount(node);
TR::LabelSymbol *label = node->getBranchDestination()->getNode()->getLabel();
generateVirtualGuardNOPInstruction(cg, node, site, deps, label);
cg->recursivelyDecReferenceCount(node->getFirstChild());
cg->recursivelyDecReferenceCount(node->getSecondChild());
return true;
#else
return false;
#endif
}
// also handles ificmpne ifacmpeq ifacmpne
// for ifacmpeq, opcode has been temporarily set to ificmpeq
TR::Register *OMR::ARM::TreeEvaluator::ificmpeqEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
compareIntsForEquality(TR::ificmpeq == node->getOpCodeValue() ? ARMConditionCodeEQ : ARMConditionCodeNE, node, cg);
return NULL;
}
// ificmpne handled by ificmpeqEvaluator
TR::Register *OMR::ARM::TreeEvaluator::ificmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
compareIntsForOrder(ARMConditionCodeLT, node, cg);
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::ificmpgeEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
compareIntsForOrder(ARMConditionCodeGE, node, cg);
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::ificmpgtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
compareIntsForOrder(ARMConditionCodeGT, node, cg);
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::ificmpleEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
compareIntsForOrder(ARMConditionCodeLE, node, cg);
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::ifiucmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
compareIntsForOrder(ARMConditionCodeCC, node, cg);
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::ifiucmpgeEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
compareIntsForOrder(ARMConditionCodeCS, node, cg);
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::ifiucmpgtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
compareIntsForOrder(ARMConditionCodeHI, node, cg);
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::ifiucmpleEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
compareIntsForOrder(ARMConditionCodeLS, node, cg);
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::iflcmpeqEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::LabelSymbol *destinationLabel = node->getBranchDestination()->getNode()->getLabel();
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount();
}
TR_ARMConditionCode condition = node->getOpCodeValue() == TR::iflcmpeq ? ARMConditionCodeEQ : ARMConditionCodeNE;
TR::Instruction *cursor;
// for eq, generate:
// cmp hi1, hi2
// cmpeq lo1, lo2
// beq <label>
// for ne, generate:
// cmp hi1, hi2
// cmpeq lo1, lo2 <- also eq because if the first compare
// failed, we're done
// bne <label>
cursor = generateSrc2Instruction(cg, ARMOp_cmp, node, src1Reg->getHighOrder(), src2Reg->getHighOrder());
cursor = generateSrc2Instruction(cg, ARMOp_cmp, node, src1Reg->getLowOrder(), src2Reg->getLowOrder());
cursor->setConditionCode(ARMConditionCodeEQ); // make the second instruction conditional
cursor = generateConditionalBranchInstruction(cg, node, condition, destinationLabel, deps);
return NULL;
}
static TR::Register *compareLongAndSetOrderedBoolean(TR_ARMConditionCode branchOp, TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *trgReg = cg->allocateRegister();
TR::Register *tempReg = cg->allocateRegister();
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount();
}
// Eventually the following test should be whether there is a register allocator that
// can handle registers being alive across basic block boundaries.
// For now we just generate pessimistic code.
if (true)
{
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::ARMControlFlowInstruction *cfop = generateControlFlowInstruction(cg, ARMOp_setblong, node, deps);
cfop->addTargetRegister(trgReg);
cfop->addTargetRegister(tempReg);
cfop->addSourceRegister(src1Reg->getLowOrder());
cfop->addSourceRegister(src1Reg->getHighOrder());
cfop->addSourceRegister(src2Reg->getLowOrder());
cfop->addSourceRegister(src2Reg->getHighOrder());
cfop->setConditionCode(branchOp);
firstChild->decReferenceCount();
secondChild->decReferenceCount();
node->setRegister(trgReg);
return trgReg;
}
}
static TR::Register *compareLongsForOrder(TR_ARMConditionCode branchOp, TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::LabelSymbol *destinationLabel = node->getBranchDestination()->getNode()->getLabel();
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount();
}
// Eventually the following test should be whether there is a register allocator that
// can handle registers being alive across basic block boundaries.
// For now we just generate pessimistic code.
static bool disableOOLForLongCompares = (feGetEnv("TR_DisableOOLForLongCompares") != NULL);
TR::Register *src2Reg = cg->evaluate(secondChild);
if (/* isSmall() || */ TR::comp()->getOption(TR_DisableOOL) || disableOOLForLongCompares)
{
TR::ARMControlFlowInstruction *cfop = generateControlFlowInstruction(cg, ARMOp_iflong, node, deps);
cfop->addSourceRegister(src1Reg->getHighOrder());
cfop->addSourceRegister(src1Reg->getLowOrder());
cfop->addSourceRegister(src2Reg->getHighOrder());
cfop->addSourceRegister(src2Reg->getLowOrder());
cfop->setLabelSymbol(destinationLabel);
cfop->setConditionCode(branchOp);
}
else
{
TR::LabelSymbol *startOOLLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *doneOOLLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *returnLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);;
TR_ARMOutOfLineCodeSection *outlinedSlowPath = NULL;
TR::Register *tempReg = cg->allocateRegister();
TR_Debug *debugObj = cg->getDebug();
int isGT = (branchOp == ARMConditionCodeGT);
TR::Instruction *cursor = generateSrc2Instruction(cg, ARMOp_cmp, node, src1Reg->getHighOrder(), src2Reg->getHighOrder());
cursor = generateConditionalBranchInstruction(cg, node, isGT ? ARMConditionCodeLE : ARMConditionCodeGE, startOOLLabel, deps, cursor);
if (debugObj)
debugObj->addInstructionComment(cursor, "Branch to OOL iflong sequence");
TR::Instruction *OOLBranchInstr = cursor;
outlinedSlowPath = new (cg->trHeapMemory()) TR_ARMOutOfLineCodeSection(startOOLLabel, doneOOLLabel, cg);
cg->getARMOutOfLineCodeSectionList().add(outlinedSlowPath);
// Hot path
cursor = generateTrg1ImmInstruction(cg, ARMOp_mov, node, tempReg, 1, 0, cursor); // Setting tempReg to 1
// Start OOL
// The compare result has to be live until the end of the last instruction in the mainline, so put it as a dependency
TR::RegisterDependencyConditions *tempDeps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(1, 1, cg->trMemory());
addDependency(tempDeps, tempReg, TR::RealRegister::NoReg, TR_GPR, cg);
//tempDeps->addPreCondition(tempReg, TR::RealRegister::NoReg);
if (deps)
deps = deps->clone(cg, tempDeps);
else
deps = tempDeps;
// Need the two sources for compare to survive until the returnLabel. Use a dependency to hold that, and hold
// until the compare for them are done.
TR::RegisterDependencyConditions *newDeps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(2, 2, cg->trMemory());
addDependency(newDeps, src1Reg->getLowOrder(), TR::RealRegister::NoReg, TR_GPR, cg);
addDependency(newDeps, src2Reg->getLowOrder(), TR::RealRegister::NoReg, TR_GPR, cg);
TR::RegisterDependencyConditions *oolDeps = deps->clone(cg, newDeps);
outlinedSlowPath->swapInstructionListsWithCompilation(); // OOL code to follow
TR::Instruction *cursorOOL = generateLabelInstruction(cg, ARMOp_label, node, startOOLLabel);
if (debugObj)
debugObj->addInstructionComment(cursorOOL, "Denotes start of OOL iflong sequence");
// XXX: Temporary fix, OOL instruction stream does not pick up live locals or monitors correctly.
TR_ASSERT(!cursorOOL->getLiveLocals() && !cursorOOL->getLiveMonitors(), "Expecting first OOL instruction to not have live locals/monitors info");
cursorOOL->setLiveLocals(OOLBranchInstr->getLiveLocals());
cursorOOL->setLiveMonitors(OOLBranchInstr->getLiveMonitors());
cursorOOL = generateTrg1ImmInstruction(cg, ARMOp_mov, node, tempReg, 0, 0, cursorOOL); // Setting tempReg to 0
cursorOOL = generateConditionalBranchInstruction(cg, node, isGT ? ARMConditionCodeLT : ARMConditionCodeGT, returnLabel, cursorOOL);
cursorOOL = generateSrc2Instruction(cg, ARMOp_cmp, node, src1Reg->getLowOrder(), src2Reg->getLowOrder(), cursorOOL);
cursorOOL = generateTrg1ImmInstruction(cg, ARMOp_mov, node, tempReg, 1, 0, cursorOOL); // Setting tempReg to 1
cursorOOL->setConditionCode(isGT ? ARMConditionCodeHI: ARMConditionCodeLS);
cursorOOL = generateLabelInstruction(cg, ARMOp_label, node, returnLabel, oolDeps, cursorOOL); // Need deps 3/21 change
cursorOOL = generateLabelInstruction(cg, ARMOp_b, node, doneOOLLabel, cursorOOL);
if (debugObj)
debugObj->addInstructionComment(cursorOOL, "Denotes end of OOL iflong sequence: return to mainline");
outlinedSlowPath->swapInstructionListsWithCompilation(); // Done with OOL code
cursor = generateLabelInstruction(cg, ARMOp_label, node, doneOOLLabel);
if (debugObj)
debugObj->addInstructionComment(cursor, "OOL iflong code return label");
// Test result and branch
cursor = generateSrc1ImmInstruction(cg, ARMOp_tst, node, tempReg, 1, 0, cursor);
cursor = generateConditionalBranchInstruction(cg, node, ARMConditionCodeNE, destinationLabel, deps, cursor);
cg->stopUsingRegister(tempReg);
}
firstChild->decReferenceCount();
secondChild->decReferenceCount();
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::iflcmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::Register *tempReg = cg->allocateRegister();
TR::LabelSymbol *destinationLabel = node->getBranchDestination()->getNode()->getLabel();
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount();
}
generateTrg1Src2Instruction(cg, ARMOp_sub_r, node, tempReg, src1Reg->getLowOrder(), src2Reg->getLowOrder());
generateTrg1Src2Instruction(cg, ARMOp_sbc_r, node, tempReg, src1Reg->getHighOrder(), src2Reg->getHighOrder());
generateConditionalBranchInstruction(cg, node, ARMConditionCodeLT, destinationLabel, deps);
firstChild->decReferenceCount();
secondChild->decReferenceCount();
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::iflcmpgeEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::Register *tempReg = cg->allocateRegister();
TR::LabelSymbol *destinationLabel = node->getBranchDestination()->getNode()->getLabel();
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount();
}
generateTrg1Src2Instruction(cg, ARMOp_sub_r, node, tempReg, src1Reg->getLowOrder(), src2Reg->getLowOrder());
generateTrg1Src2Instruction(cg, ARMOp_sbc_r, node, tempReg, src1Reg->getHighOrder(), src2Reg->getHighOrder());
generateConditionalBranchInstruction(cg, node, ARMConditionCodeGE, destinationLabel, deps);
firstChild->decReferenceCount();
secondChild->decReferenceCount();
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::iflucmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::Register *tempReg = cg->allocateRegister();
TR::LabelSymbol *destinationLabel = node->getBranchDestination()->getNode()->getLabel();
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount();
}
generateTrg1Src2Instruction(cg, ARMOp_sub_r, node, tempReg, src1Reg->getLowOrder(), src2Reg->getLowOrder());
generateTrg1Src2Instruction(cg, ARMOp_sbc_r, node, tempReg, src1Reg->getHighOrder(), src2Reg->getHighOrder());
generateConditionalBranchInstruction(cg, node, ARMConditionCodeCC, destinationLabel, deps);
firstChild->decReferenceCount();
secondChild->decReferenceCount();
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::iflucmpgeEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::Register *tempReg = cg->allocateRegister();
TR::LabelSymbol *destinationLabel = node->getBranchDestination()->getNode()->getLabel();
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount();
}
generateTrg1Src2Instruction(cg, ARMOp_sub_r, node, tempReg, src1Reg->getLowOrder(), src2Reg->getLowOrder());
generateTrg1Src2Instruction(cg, ARMOp_sbc_r, node, tempReg, src1Reg->getHighOrder(), src2Reg->getHighOrder());
generateConditionalBranchInstruction(cg, node, ARMConditionCodeCS, destinationLabel, deps);
firstChild->decReferenceCount();
secondChild->decReferenceCount();
return NULL;
}
TR::Register *OMR::ARM::TreeEvaluator::iflcmpgtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongsForOrder(ARMConditionCodeGT, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::iflcmpleEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongsForOrder(ARMConditionCodeLE, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::iflucmpgtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongsForOrder(ARMConditionCodeHI, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::iflucmpleEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongsForOrder(ARMConditionCodeLS, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::ifacmpeqEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node::recreate(node, TR::ificmpeq);
ificmpeqEvaluator(node, cg);
TR::Node::recreate(node, TR::ifacmpeq);
return NULL;
}
// ifacmpne handled by ificmpeqEvaluator
static TR::Register *icmpHelper(TR::Node *node, TR_ARMConditionCode cond, TR::CodeGenerator *cg)
{
TR::Register *trgReg = cg->allocateRegister();
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::Instruction *movInstr;
// TODO: add back immediate cases
generateTrg1ImmInstruction(cg, ARMOp_mov, node, trgReg, 0, 0);
generateSrc2Instruction(cg, ARMOp_cmp, node, src1Reg, src2Reg);
movInstr = generateTrg1ImmInstruction(cg, ARMOp_mov, node, trgReg, 1, 0);
movInstr->setConditionCode(cond); // tag previous move as conditional
node->setRegister(trgReg);
firstChild->decReferenceCount();
secondChild->decReferenceCount();
return trgReg;
}
// also handles acmpeq
// for acmpeq, opcode has been temporarily set to icmpeq
TR::Register *OMR::ARM::TreeEvaluator::icmpeqEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeEQ, cg);
}
// also handles acmpneq
// for acmpneq, opcode has been temporarily set to icmpneq
TR::Register *OMR::ARM::TreeEvaluator::icmpneEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeNE, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::icmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeLT, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::icmpleEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeLE, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::icmpgeEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeGE, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::icmpgtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeGT, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::iucmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeCC, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::iucmpleEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeLS, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::iucmpgeEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeCS, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::iucmpgtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return icmpHelper(node, ARMConditionCodeHI, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lcmpeqEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeEQ, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lcmpneEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeNE, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lcmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeLT, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lcmpgeEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeGE, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lcmpgtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeGT, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lcmpleEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeLE, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lucmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeCC, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lucmpgeEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeCS, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lucmpgtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeHI, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lucmpleEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return compareLongAndSetOrderedBoolean(ARMConditionCodeLS, node, cg);
}
TR::Register *OMR::ARM::TreeEvaluator::lcmpEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *trgReg = cg->allocateRegister();
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Node *secondChild = node->getSecondChild();
TR::Node *thirdChild;
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 0);
thirdChild->decReferenceCount();
}
// Eventually the following test should be whether there is a register allocator that
// can handle registers being alive across basic block boundaries.
// For now we just generate pessimistic code.
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::ARMControlFlowInstruction *cfop = generateControlFlowInstruction(cg, ARMOp_lcmp, node, deps);
cfop->addTargetRegister(trgReg);
cfop->addSourceRegister(src1Reg->getLowOrder());
cfop->addSourceRegister(src1Reg->getHighOrder());
cfop->addSourceRegister(src2Reg->getLowOrder());
cfop->addSourceRegister(src2Reg->getHighOrder());
firstChild->decReferenceCount();
secondChild->decReferenceCount();
node->setRegister(trgReg);
return trgReg;
}
TR::Register *OMR::ARM::TreeEvaluator::acmpeqEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node::recreate(node, TR::icmpeq);
TR::Register *trgReg = icmpeqEvaluator(node, cg);
TR::Node::recreate(node, TR::acmpeq);
return trgReg;
}
TR::Register *OMR::ARM::TreeEvaluator::lookupEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
switchDispatch(cg, node);
cg->decReferenceCount(node->getFirstChild());
return NULL;
}
static void mapGlRegDeps(TR::Node *node, TR_BitVector *vector)
{
for (int i = 0; i < node->getNumChildren(); i++)
vector->set(node->getChild(i)->getGlobalRegisterNumber());
}
static bool isGlDepsUnBalanced(TR::CodeGenerator *cg, TR::Node *node)
{
int32_t numChildren = node->getNumChildren();
TR::Node *defaultNode = node->getSecondChild();
TR::Node *defaultDeps = defaultNode->getNumChildren() > 0 ? defaultNode->getFirstChild() : NULL;
int32_t numDefDeps = defaultDeps ? defaultDeps->getNumChildren() : 0;
// Return true if the number of dependencies on any of the non-default
// cases does not agree with the number of those on the default case;
// otherwise return false if there are no dependencies to consider.
int i;
for (i = 2; i < numChildren; i++)
{
TR::Node *caseNode = node->getChild(i);
TR::Node *caseDeps = caseNode->getNumChildren() > 0 ? caseNode->getFirstChild() : NULL;
if ((!caseDeps && numDefDeps != 0) || (caseDeps && numDefDeps != caseDeps->getNumChildren()))
break;
}
if (i != numChildren)
{
return true;
}
if (numDefDeps == 0)
{
return false;
}
// The cases all have the same number (!= 0) of dependencies; see if
// they all describe the same set of global registers. Return true
// if they do not; otherwise return false.
TR_BitVector defDepMap, caseDepMap;
defDepMap.init(cg->getNumberOfGlobalRegisters(), cg->trMemory());
caseDepMap.init(cg->getNumberOfGlobalRegisters(), cg->trMemory());
mapGlRegDeps(defaultDeps, &defDepMap);