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FPTreeEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stddef.h>
#include <stdint.h>
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGeneratorUtils.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/UnresolvedDataSnippet.hpp"
#include "compile/Compilation.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "env/CompilerEnv.hpp"
#include "env/Processors.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "p/codegen/GenerateInstructions.hpp"
#include "p/codegen/PPCInstruction.hpp"
#include "p/codegen/PPCTableOfConstants.hpp"
#include "runtime/Runtime.hpp"
static void ifFloatEvaluator( TR::Node *node, TR::InstOpCode::Mnemonic branchOp1, TR::InstOpCode::Mnemonic branchOp2, TR::CodeGenerator *cg);
static TR::Register *compareFloatAndSetOrderedBoolean(TR::InstOpCode::Mnemonic branchOp1, TR::InstOpCode::Mnemonic branchOp2, int64_t imm, TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *singlePrecisionEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic OpCode, TR::CodeGenerator *cg);
static TR::Register *doublePrecisionEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic OpCode, TR::CodeGenerator *cg);
TR::Register *OMR::Power::TreeEvaluator::ibits2fEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *target = cg->allocateSinglePrecisionRegister();
if (child->getRegister() == NULL && child->getReferenceCount() == 1 &&
child->getOpCode().isLoadVar())
{
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(child, 4, cg);
#ifdef J9_PROJECT_SPECIFIC
if (node->getFirstChild()->getOpCodeValue() == TR::iriload)
{
tempMR->forceIndexedForm(child, cg);
generateTrg1MemInstruction(cg, TR::InstOpCode::lwbrx, node, target, tempMR);
}
else
#endif
generateTrg1MemInstruction(cg, TR::InstOpCode::lfs, node, target, tempMR);
tempMR->decNodeReferenceCounts(cg);
}
else
{
generateMvFprGprInstructions(cg, node, gprSp2fpr, cg->comp()->target().is64Bit(),target, cg->evaluate(child));
cg->decReferenceCount(child);
}
node->setRegister(target);
return target;
}
TR::Register *OMR::Power::TreeEvaluator::fbits2iEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *target = cg->allocateRegister();
TR::Register *floatReg;
bool childEval = true;
if (child->getRegister() == NULL && child->getReferenceCount() == 1 &&
child->getOpCode().isLoadVar())
{
childEval = false;
floatReg = cg->allocateSinglePrecisionRegister();
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(child, 4, cg);
generateTrg1MemInstruction(cg, TR::InstOpCode::lfs, node, floatReg, new (cg->trHeapMemory()) TR::MemoryReference(node, *tempMR, 0, 4, cg));
generateTrg1MemInstruction(cg, TR::InstOpCode::lwz, node, target, tempMR);
tempMR->decNodeReferenceCounts(cg);
}
else
{
floatReg = cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) ? cg->gprClobberEvaluate(child) : cg->evaluate(child);
generateMvFprGprInstructions(cg, node, fpr2gprSp, cg->comp()->target().is64Bit(),target, floatReg);
childEval = floatReg == child->getRegister();
cg->decReferenceCount(child);
}
// There's a special-case check for NaN values, which have to be
// normalized to a particular NaN value.
//
if (node->normalizeNanValues())
{
TR::Register *condReg = cg->allocateRegister(TR_CCR);
TR::LabelSymbol *nanNormalizeStartLabel = generateLabelSymbol(cg);
TR::LabelSymbol *nanNormalizeEndLabel = generateLabelSymbol(cg);
nanNormalizeStartLabel->setStartInternalControlFlow();
nanNormalizeEndLabel->setEndInternalControlFlow();
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 2, cg->trMemory());
deps->addPostCondition(condReg, TR::RealRegister::NoReg);
deps->addPostCondition(target, TR::RealRegister::NoReg);
generateTrg1Src2Instruction(cg, TR::InstOpCode::fcmpu, node, condReg, floatReg, floatReg);
generateLabelInstruction(cg, TR::InstOpCode::label, node, nanNormalizeStartLabel);
generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, PPCOpProp_BranchLikely, node, nanNormalizeEndLabel, condReg);
generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, target, 0x7fc0);
generateDepLabelInstruction(cg, TR::InstOpCode::label, node, nanNormalizeEndLabel, deps);
cg->stopUsingRegister(condReg);
}
if (!childEval)
cg->stopUsingRegister(floatReg);
node->setRegister(target);
return target;
}
TR::Register *OMR::Power::TreeEvaluator::lbits2dEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *target = cg->allocateRegister(TR_FPR);
if (child->getRegister() == NULL && child->getReferenceCount() == 1 &&
child->getOpCode().isLoadVar())
{
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(child, 8, cg);
#ifdef J9_PROJECT_SPECIFIC
if (child->getOpCodeValue() == TR::irlload && cg->comp()->target().is64Bit()) // 64-bit only
{
TR::Register *tmpReg = cg->allocateRegister();
tempMR->forceIndexedForm(child, cg);
generateTrg1MemInstruction(cg, TR::InstOpCode::ldbrx, node, tmpReg, tempMR);
generateMvFprGprInstructions(cg, node, gpr2fprHost64, true, target, tmpReg);
cg->stopUsingRegister(tmpReg);
}
else if (child->getOpCodeValue() == TR::irlload && cg->comp()->target().is32Bit()) // 32-bit
{
TR::Register *highReg = cg->allocateRegister();
TR::Register *lowReg = cg->allocateRegister();
TR::MemoryReference *tempMRLoad1 = new (cg->trHeapMemory()) TR::MemoryReference(child, *tempMR, 0, 4, cg);
TR::MemoryReference *tempMRLoad2 = new (cg->trHeapMemory()) TR::MemoryReference(child, *tempMR, 4, 4, cg);
tempMRLoad1->forceIndexedForm(child, cg);
tempMRLoad2->forceIndexedForm(child, cg);
generateTrg1MemInstruction(cg, TR::InstOpCode::lwbrx, node, lowReg, tempMRLoad1);
generateTrg1MemInstruction(cg, TR::InstOpCode::lwbrx, node, highReg, tempMRLoad2);
generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, target, highReg, lowReg);
tempMRLoad1->decNodeReferenceCounts(cg);
tempMRLoad2->decNodeReferenceCounts(cg);
cg->stopUsingRegister(highReg);
cg->stopUsingRegister(lowReg);
cg->decReferenceCount(child);
}
else
#endif
generateTrg1MemInstruction(cg, TR::InstOpCode::lfd, node, target, tempMR);
tempMR->decNodeReferenceCounts(cg);
}
else
{
if (cg->comp()->target().is64Bit())
generateMvFprGprInstructions(cg, node, gpr2fprHost64, true, target, cg->evaluate(child));
else
{
TR::Register *longReg = cg->evaluate(child);
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
{
TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, target, longReg->getHighOrder(), longReg->getLowOrder(), tmp1);
cg->stopUsingRegister(tmp1);
}
else
generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, target, longReg->getHighOrder(), longReg->getLowOrder());
}
cg->decReferenceCount(child);
}
node->setRegister(target);
return target;
}
TR::Register *OMR::Power::TreeEvaluator::dbits2lEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *lowReg = NULL;
TR::Register *highReg = NULL;
TR::Register *lReg = NULL;
TR::Register *doubleReg;
bool childEval = true;
if (child->getRegister() == NULL && child->getReferenceCount() == 1 &&
child->getOpCode().isLoadVar())
{
childEval = false;
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(child, 8, cg);
doubleReg = cg->allocateRegister(TR_FPR);
generateTrg1MemInstruction(cg, TR::InstOpCode::lfd, node, doubleReg, tempMR);
if (cg->comp()->target().is64Bit())
{
lReg = cg->allocateRegister();
TR::MemoryReference *tempMR2 = new (cg->trHeapMemory()) TR::MemoryReference(node, *tempMR, 0, 8, cg);
generateTrg1MemInstruction(cg, TR::InstOpCode::ld, node, lReg, tempMR2);
tempMR2->decNodeReferenceCounts(cg);
}
else
{
lowReg = cg->allocateRegister();
highReg = cg->allocateRegister();
TR::MemoryReference *highMem, *lowMem;
highMem = new (cg->trHeapMemory()) TR::MemoryReference(node, *tempMR, 0, 4, cg);
generateTrg1MemInstruction(cg, TR::InstOpCode::lwz, node, highReg, highMem);
lowMem = new (cg->trHeapMemory()) TR::MemoryReference(node, *tempMR, 4, 4, cg);
generateTrg1MemInstruction(cg, TR::InstOpCode::lwz, node, lowReg, lowMem);
highMem->decNodeReferenceCounts(cg);
lowMem->decNodeReferenceCounts(cg);
}
tempMR->decNodeReferenceCounts(cg);
}
else
{
doubleReg = cg->evaluate(child);
if (cg->comp()->target().is64Bit())
{
lReg = cg->allocateRegister();
generateMvFprGprInstructions(cg, node, fpr2gprHost64, true, lReg, doubleReg);
}
else
{
highReg = cg->allocateRegister();
lowReg = cg->allocateRegister();
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
{
TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
generateMvFprGprInstructions(cg, node, fpr2gprHost32, false, highReg, lowReg, doubleReg, tmp1);
cg->stopUsingRegister(tmp1);
}
else
generateMvFprGprInstructions(cg, node, fpr2gprHost32, false, highReg, lowReg, doubleReg);
}
cg->decReferenceCount(child);
}
// There's a special-case check for NaN values, which have to be
// normalized to a particular NaN value.
//
if (node->normalizeNanValues())
{
TR::Register *condReg = cg->allocateRegister(TR_CCR);
TR::LabelSymbol *nanNormalizeStartLabel = generateLabelSymbol(cg);
TR::LabelSymbol *nanNormalizeEndLabel = generateLabelSymbol(cg);
uint16_t numDeps = cg->comp()->target().is64Bit() ? 2 : 3;
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(numDeps, numDeps, cg->trMemory());
TR::addDependency(deps, condReg, TR::RealRegister::NoReg, TR_CCR, cg);
if (cg->comp()->target().is64Bit())
{
TR::addDependency(deps, lReg, TR::RealRegister::NoReg, TR_GPR, cg);
}
else
{
TR::addDependency(deps, lowReg, TR::RealRegister::NoReg, TR_GPR, cg);
TR::addDependency(deps, highReg, TR::RealRegister::NoReg, TR_GPR, cg);
}
generateTrg1Src2Instruction(cg, TR::InstOpCode::fcmpu, node, condReg, doubleReg, doubleReg);
generateLabelInstruction(cg, TR::InstOpCode::label, node, nanNormalizeStartLabel);
generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, PPCOpProp_BranchLikely, node, nanNormalizeEndLabel, condReg);
if (cg->comp()->target().is64Bit())
{
loadConstant(cg, node, (int64_t)CONSTANT64(0x7ff8000000000000), lReg);
}
else
{
generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, highReg, 0x7ff8);
generateTrg1ImmInstruction(cg, TR::InstOpCode::li, node, lowReg, 0);
}
generateDepLabelInstruction(cg, TR::InstOpCode::label, node, nanNormalizeEndLabel, deps);
cg->stopUsingRegister(condReg);
}
if (!childEval)
cg->stopUsingRegister(doubleReg);
if (cg->comp()->target().is64Bit())
{
node->setRegister(lReg);
return lReg;
}
else
{
TR::RegisterPair *target = cg->allocateRegisterPair(lowReg, highReg);
node->setRegister(target);
return target;
}
}
static TR::Register *fconstHandler(TR::Node *node, TR::CodeGenerator *cg, float value)
{
TR::Register *trgRegister = cg->allocateSinglePrecisionRegister();
TR::Register *srcRegister, *tempReg=NULL;
TR::Instruction *q[4];
int32_t offset;
TR::Compilation *comp = cg->comp();
if (cg->comp()->target().is64Bit())
{
offset = cg->findOrCreateFloatConstant(&value, TR::Float, NULL, NULL, NULL, NULL);
if (offset != PTOC_FULL_INDEX)
{
if (offset<LOWER_IMMED || offset>UPPER_IMMED)
{
srcRegister = cg->allocateRegister();
TR_ASSERT_FATAL_WITH_NODE(node, 0x00008000 != HI_VALUE(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, cg->getTOCBaseRegister(), HI_VALUE(offset));
generateTrg1MemInstruction(cg, TR::InstOpCode::lfs, node, trgRegister, new (cg->trHeapMemory()) TR::MemoryReference(srcRegister, LO_VALUE(offset), 4, cg));
cg->stopUsingRegister(srcRegister);
}
else
{
generateTrg1MemInstruction(cg, TR::InstOpCode::lfs, node, trgRegister, new (cg->trHeapMemory()) TR::MemoryReference(cg->getTOCBaseRegister(), offset, 4, cg));
}
}
}
if (cg->comp()->target().is32Bit() || offset==PTOC_FULL_INDEX)
{
srcRegister = cg->allocateRegister();
if (cg->comp()->target().is64Bit())
tempReg = cg->allocateRegister();
fixedSeqMemAccess(cg, node, 0, q, trgRegister, srcRegister, TR::InstOpCode::lfs, 4, NULL, tempReg);
cg->findOrCreateFloatConstant(&value, TR::Float, q[0], q[1], q[2], q[3]);
cg->stopUsingRegister(srcRegister);
if (cg->comp()->target().is64Bit())
cg->stopUsingRegister(tempReg);
}
node->setRegister(trgRegister);
return trgRegister;
}
TR::Register *OMR::Power::TreeEvaluator::fconstEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return fconstHandler(node, cg, node->getFloat());
}
TR::Register *OMR::Power::TreeEvaluator::dconstEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
double value = node->getDouble();
TR::InstOpCode::Mnemonic opcode = TR::InstOpCode::lfd;
bool splats = false;
TR::Compilation *comp = cg->comp();
if (node->getOpCodeValue() == TR::vsplats)
{
splats = true;
}
if (splats)
{
value = node->getFirstChild()->getDouble();
opcode = TR::InstOpCode::lxvdsx;
}
if (!splats)
{
if (value == ((double) ((float) value)))
return fconstHandler(node, cg, (float) value);
}
TR::Register *trgRegister;
if (splats)
trgRegister = cg->allocateRegister(TR_VSX_VECTOR);
else
trgRegister = cg->allocateRegister(TR_FPR);
TR::Register *srcRegister, *tempReg=NULL;
TR::Instruction *q[4];
int32_t offset;
if (cg->comp()->target().is64Bit())
{
offset = cg->findOrCreateFloatConstant(&value, TR::Double, NULL, NULL, NULL, NULL);
if (offset != PTOC_FULL_INDEX)
{
if (offset<LOWER_IMMED || offset>UPPER_IMMED)
{
srcRegister = cg->allocateRegister();
TR_ASSERT_FATAL_WITH_NODE(node, 0x00008000 != HI_VALUE(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, srcRegister, cg->getTOCBaseRegister(), HI_VALUE(offset));
TR::MemoryReference *memRef = new (cg->trHeapMemory()) TR::MemoryReference(srcRegister, LO_VALUE(offset), 8, cg);
if (splats)
memRef->forceIndexedForm(node, cg);
generateTrg1MemInstruction(cg, opcode, node, trgRegister, memRef);
cg->stopUsingRegister(srcRegister);
}
else
{
TR::MemoryReference *memRef = new (cg->trHeapMemory()) TR::MemoryReference(cg->getTOCBaseRegister(), offset, 8, cg);
if (splats)
memRef->forceIndexedForm(node, cg);
generateTrg1MemInstruction(cg, opcode, node, trgRegister, memRef);
}
}
}
if (cg->comp()->target().is32Bit() || offset==PTOC_FULL_INDEX)
{
srcRegister = cg->allocateRegister(TR_GPR);
if (cg->comp()->target().is64Bit())
tempReg = cg->allocateRegister(TR_GPR);
fixedSeqMemAccess(cg, node, 0, q, trgRegister, srcRegister, opcode, 8, NULL, tempReg);
cg->stopUsingRegister(srcRegister);
if (cg->comp()->target().is64Bit())
cg->stopUsingRegister(tempReg);
cg->findOrCreateFloatConstant(&value, TR::Double, q[0], q[1], q[2], q[3]);
}
node->setRegister(trgRegister);
return trgRegister;
}
// also handles TR::floadi
TR::Register *OMR::Power::TreeEvaluator::floadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *tempReg = node->setRegister(cg->allocateSinglePrecisionRegister());
TR::MemoryReference *tempMR;
bool needSync= node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP();
// If the reference is volatile or potentially volatile, the layout needs to be
// fixed for patching if it turns out to be not a volatile atfer all.
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, 4, cg);
generateTrg1MemInstruction(cg, TR::InstOpCode::lfs, node, tempReg, tempMR);
if (needSync)
{
TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, TR::InstOpCode::isync);
}
tempMR->decNodeReferenceCounts(cg);
return tempReg;
}
TR::Register *OMR::Power::TreeEvaluator::dloadHelper(TR::Node *node, TR::CodeGenerator *cg, TR::Register *tempReg, TR::InstOpCode::Mnemonic opcode)
{
TR::Compilation *comp = cg->comp();
TR::MemoryReference *tempMR;
bool needSync= node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP();
if (cg->comp()->target().is32Bit() && needSync && !cg->is64BitProcessor())
{
TR::Register *addrReg = cg->allocateRegister();
TR::SymbolReference *vrlRef = comp->getSymRefTab()->findOrCreateVolatileReadDoubleSymbolRef(comp->getMethodSymbol());
if (node->getSymbolReference()->isUnresolved())
{
#ifdef J9_PROJECT_SPECIFIC
// NOTE NOTE -- If the reference is volatile or potentially volatile, the layout
// needs to be fixed for patching if it turns out to be not a volatile after all.
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, 8, cg);
if (opcode == TR::InstOpCode::lxvdsx)
tempMR->forceIndexedForm(node, cg);
generateTrg1MemInstruction(cg, opcode, node, tempReg, tempMR);
tempMR->getUnresolvedSnippet()->setIsSpecialDouble();
tempMR->getUnresolvedSnippet()->setInSyncSequence();
#endif
}
else
{
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, 8, cg);
if (tempMR->getIndexRegister() != NULL)
generateTrg1Src2Instruction (cg, TR::InstOpCode::add, node, addrReg, tempMR->getBaseRegister(), tempMR->getIndexRegister());
else
generateTrg1MemInstruction (cg, TR::InstOpCode::addi2, node, addrReg, tempMR);
}
TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(5, 5, cg->trMemory());
TR::addDependency(dependencies, tempReg, TR::RealRegister::fp0, TR_FPR, cg);
TR::addDependency(dependencies, addrReg, TR::RealRegister::gr3, TR_GPR, cg);
TR::addDependency(dependencies, NULL, TR::RealRegister::gr11, TR_GPR, cg);
if (node->getSymbolReference()->isUnresolved())
{
if (tempMR->getBaseRegister() != NULL)
{
TR::addDependency(dependencies, tempMR->getBaseRegister(), TR::RealRegister::NoReg, TR_GPR, cg);
dependencies->getPreConditions()->getRegisterDependency(3)->setExcludeGPR0();
dependencies->getPostConditions()->getRegisterDependency(3)->setExcludeGPR0();
}
if (tempMR->getIndexRegister() != NULL)
TR::addDependency(dependencies, tempMR->getIndexRegister(), TR::RealRegister::NoReg, TR_GPR, cg);
}
generateDepImmSymInstruction(cg, TR::InstOpCode::bl, node,
(uintptr_t)vrlRef->getSymbol()->castToMethodSymbol()->getMethodAddress(),
dependencies, vrlRef);
// tempMR registers possibly repeatedly declared dead but no harm.
dependencies->stopUsingDepRegs(cg, tempReg);
cg->machine()->setLinkRegisterKilled(true);
}
else
{
// If the reference is volatile or potentially volatile, the layout needs to be
// fixed for patching if it turns out to be not a volatile after all.
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, 8, cg);
if (opcode == TR::InstOpCode::lxvdsx || opcode == TR::InstOpCode::lxsdx)
{
if (tempMR->hasDelayedOffset())
{
TR::Register *tmpReg = cg->allocateRegister();
generateTrg1MemInstruction(cg, TR::InstOpCode::addi2, node, tmpReg, tempMR);
tempMR->decNodeReferenceCounts(cg);
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(NULL, tmpReg, 16, cg);
}
else
{
tempMR->forceIndexedForm(node, cg);
}
}
generateTrg1MemInstruction(cg, opcode, node, tempReg, tempMR);
if (needSync)
{
TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, TR::InstOpCode::isync);
}
}
tempMR->decNodeReferenceCounts(cg);
return tempReg;
}
// also handles TR::dloadi
TR::Register *OMR::Power::TreeEvaluator::dloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *tempReg = node->setRegister(cg->allocateRegister(TR_FPR));
return TR::TreeEvaluator::dloadHelper(node, cg, tempReg, TR::InstOpCode::lfd);
}
TR::Register *OMR::Power::TreeEvaluator::vsplatsEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
static bool disableDirectMove = feGetEnv("TR_disableDirectMove") ? true : false;
if (node->getDataType() == TR::VectorInt8)
{
TR::SymbolReference *temp = cg->allocateLocalTemp(TR::VectorInt8);
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, temp, 1, cg);
TR::Register *srcReg = cg->evaluate(child);
generateMemSrc1Instruction(cg, TR::InstOpCode::stb, node, tempMR, srcReg);
TR::Register *tmpReg = cg->allocateRegister();
generateTrg1MemInstruction(cg, TR::InstOpCode::addi2, node, tmpReg, tempMR);
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(NULL, tmpReg, 16, cg);
cg->stopUsingRegister(tmpReg);
TR::Register *trgReg = cg->allocateRegister(TR_VRF);
generateTrg1MemInstruction(cg, TR::InstOpCode::lxvd2x, node, trgReg, tempMR);
#if defined(__LITTLE_ENDIAN__)
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::vspltb, node, trgReg, trgReg, 7);
#else
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::vspltb, node, trgReg, trgReg, 0);
#endif
node->setRegister(trgReg);
cg->decReferenceCount(child);
return trgReg;
}
else if (node->getDataType() == TR::VectorInt16)
{
TR::SymbolReference *temp = cg->allocateLocalTemp(TR::VectorInt16);
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, temp, 2, cg);
TR::Register *srcReg = cg->evaluate(child);
generateMemSrc1Instruction(cg, TR::InstOpCode::sth, node, tempMR, srcReg);
TR::Register *tmpReg = cg->allocateRegister();
generateTrg1MemInstruction(cg, TR::InstOpCode::addi2, node, tmpReg, tempMR);
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(NULL, tmpReg, 16, cg);
cg->stopUsingRegister(tmpReg);
TR::Register *trgReg = cg->allocateRegister(TR_VRF);
generateTrg1MemInstruction(cg, TR::InstOpCode::lxvd2x, node, trgReg, tempMR);
#if defined(__LITTLE_ENDIAN__)
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::vsplth, node, trgReg, trgReg, 3);
#else
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::vsplth, node, trgReg, trgReg, 0);
#endif
node->setRegister(trgReg);
cg->decReferenceCount(child);
return trgReg;
}
else if (node->getDataType() == TR::VectorInt32)
{
TR::Register *tempReg = cg->evaluate(child);
TR::Register *resReg = cg->allocateRegister(TR_VRF);
if (!disableDirectMove && cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
{
generateMvFprGprInstructions(cg, node, gprLow2fpr, false, resReg, tempReg);
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::xxspltw, node, resReg, resReg, 0x1);
}
else
{
TR::SymbolReference *localTemp = cg->allocateLocalTemp(TR::Int32);
generateMemSrc1Instruction(cg, TR::InstOpCode::stw, node, new (cg->trHeapMemory()) TR::MemoryReference(node, localTemp, 4, cg), tempReg);
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, localTemp, 4, cg);
tempMR->forceIndexedForm(node, cg);
generateTrg1MemInstruction(cg, TR::InstOpCode::lxsdx, node, resReg, tempMR);
tempMR->decNodeReferenceCounts(cg);
#if defined(__LITTLE_ENDIAN__)
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::xxspltw, node, resReg, resReg, 1);
#else
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::xxspltw, node, resReg, resReg, 0);
#endif
}
cg->stopUsingRegister(tempReg);
node->setRegister(resReg);
cg->decReferenceCount(child);
return resReg;
}
else if (node->getDataType() == TR::VectorInt64)
{
TR::Register *srcReg = cg->evaluate(child);
TR::Register *trgReg = cg->allocateRegister(TR_VRF);
if (!disableDirectMove && cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
{
if (cg->comp()->target().is64Bit())
{
generateMvFprGprInstructions(cg, node, gpr2fprHost64, false, trgReg, srcReg);
generateTrg1Src2ImmInstruction(cg, TR::InstOpCode::xxpermdi, node, trgReg, trgReg, trgReg, 0x0);
}
else
{
TR::Register *tempVectorReg = cg->allocateRegister(TR_VSX_VECTOR);
generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, trgReg, srcReg->getHighOrder(), srcReg->getLowOrder(), tempVectorReg);
generateTrg1Src2ImmInstruction(cg, TR::InstOpCode::xxpermdi, node, trgReg, trgReg, trgReg, 0x0);
cg->stopUsingRegister(tempVectorReg);
}
}
else
{
TR::SymbolReference *temp = cg->allocateLocalTemp(TR::Int64);
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, temp, 8, cg);
if (cg->comp()->target().is64Bit())
{
generateMemSrc1Instruction(cg, TR::InstOpCode::std, node, tempMR, srcReg);
}
else
{
TR::MemoryReference *tempMR2 = new (cg->trHeapMemory()) TR::MemoryReference(node, *tempMR, 4, 4, cg);
generateMemSrc1Instruction(cg, TR::InstOpCode::stw, node, tempMR, srcReg->getHighOrder());
generateMemSrc1Instruction(cg, TR::InstOpCode::stw, node, tempMR2, srcReg->getLowOrder());
}
TR::Register *tmpReg = cg->allocateRegister();
generateTrg1MemInstruction(cg, TR::InstOpCode::addi2, node, tmpReg, tempMR);
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(NULL, tmpReg, 16, cg);
cg->stopUsingRegister(tmpReg);
generateTrg1MemInstruction(cg, TR::InstOpCode::lxvdsx, node, trgReg, tempMR);
}
node->setRegister(trgReg);
cg->decReferenceCount(child);
return trgReg;
}
else if (node->getDataType() == TR::VectorFloat)
{
TR::Register *srcReg = cg->evaluate(child);
TR::Register *trgReg = cg->allocateRegister(TR_VRF);
generateTrg1Src1Instruction(cg, TR::InstOpCode::xscvdpsp, node, trgReg, srcReg);
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::xxspltw, node, trgReg, trgReg, 0);
node->setRegister(trgReg);
cg->decReferenceCount(child);
return trgReg;
}
TR_ASSERT(node->getDataType() == TR::VectorDouble, "unsupported splats type");
if (child->getOpCode().isLoadConst())
{
TR::Register *resReg = TR::TreeEvaluator::dconstEvaluator(node, cg);
cg->decReferenceCount(child);
return resReg;
}
else if (child->getRegister() == NULL &&
child->getOpCode().isLoadVar())
{
if (child->getReferenceCount() > 1)
{
TR::Node *newNode = child->duplicateTree(false);
cg->evaluate(child);
cg->decReferenceCount(child);
child = newNode;
}
TR::Register *resReg = node->setRegister(cg->allocateRegister(TR_VSX_VECTOR));
return TR::TreeEvaluator::dloadHelper(child, cg, resReg, TR::InstOpCode::lxvdsx);
}
else
{
TR::Register *srcReg = cg->evaluate(child);
TR::Register *resReg = node->setRegister(cg->allocateRegister(TR_VSX_VECTOR));
generateTrg1Src2ImmInstruction(cg, TR::InstOpCode::xxpermdi, node, resReg, srcReg, srcReg, 0x0);
cg->decReferenceCount(child);
return resReg;
}
return NULL;
}
TR::Register *OMR::Power::TreeEvaluator::vdgetelemEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *resReg = node->setRegister(cg->allocateRegister(TR_FPR));
if (secondChild->getOpCode().isLoadConst())
{
int elem = secondChild->getInt();
TR_ASSERT(elem == 0 || elem == 1, "Element can only be 0 or 1\n");
TR::Register *srcReg = cg->evaluate(firstChild);
if (elem == 1)
generateTrg1Src2ImmInstruction(cg, TR::InstOpCode::xxsldwi, node, resReg, srcReg, srcReg, 0x2);
else
generateTrg1Src2Instruction(cg, TR::InstOpCode::xxlor, node, resReg, srcReg, srcReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return resReg;
}
TR::Register *vectorReg = cg->evaluate(firstChild);
TR::Register *idxReg = cg->evaluate(secondChild);
TR::Register *condReg = cg->allocateRegister(TR_CCR);
TR::LabelSymbol *jumpLabel = generateLabelSymbol(cg);
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::cmpi4, node, condReg, idxReg, 0);
// copy vector register to result register
generateTrg1Src2Instruction(cg, TR::InstOpCode::xxlor, node, resReg, vectorReg, vectorReg);
generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, jumpLabel, condReg);
generateTrg1Src2ImmInstruction(cg, TR::InstOpCode::xxsldwi, node, resReg, vectorReg, vectorReg, 0x2);
TR::RegisterDependencyConditions *dep = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 4, cg->trMemory());
dep->addPostCondition(vectorReg, TR::RealRegister::NoReg);
dep->addPostCondition(idxReg, TR::RealRegister::NoReg);
dep->addPostCondition(resReg, TR::RealRegister::NoReg);
dep->addPostCondition(condReg, TR::RealRegister::NoReg);
generateDepLabelInstruction(cg, TR::InstOpCode::label, node, jumpLabel, dep);
cg->stopUsingRegister(condReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return resReg;
}
TR::Register *OMR::Power::TreeEvaluator::vdsetelemEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Node *thirdChild = node->getThirdChild();
TR::Register *vectorReg = cg->evaluate(firstChild);
TR::Register *resReg = node->setRegister(cg->allocateRegister(TR_VSX_VECTOR));
if (thirdChild->getOpCode().isLoadConst())
{
int elem = thirdChild->getInt();
TR_ASSERT(elem == 0 || elem == 1, "Element can only be 0 or 1\n");
if (secondChild->getRegister() == NULL &&
secondChild->getOpCode().isLoadVar())
{
if (secondChild->getReferenceCount() > 1)
{
TR::Node *newNode = secondChild->duplicateTree(false);
cg->evaluate(secondChild);
cg->decReferenceCount(secondChild);
secondChild = newNode;
}
TR::TreeEvaluator::dloadHelper(secondChild, cg, resReg, TR::InstOpCode::lxsdx);
}
else
{
TR::Register *fprReg = cg->evaluate(secondChild);
generateTrg1Src2Instruction(cg, TR::InstOpCode::xxlor, node, resReg, fprReg, fprReg);
cg->decReferenceCount(secondChild);
}
if (elem == 0)
generateTrg1Src2ImmInstruction(cg, TR::InstOpCode::xxpermdi, node, resReg, resReg, vectorReg, 0x1);
else
generateTrg1Src2ImmInstruction(cg, TR::InstOpCode::xxpermdi, node, resReg, vectorReg, resReg, 0x0);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(thirdChild);
return resReg;
}
TR::Register *idxReg = cg->evaluate(secondChild);
TR::Register *valueReg = cg->evaluate(thirdChild);
TR::Register *condReg = cg->allocateRegister(TR_CCR);
TR::LabelSymbol *doneLabel = generateLabelSymbol(cg);
// cmpwi index, 0
// xxpermdi result, value, vector, 1
// beq 1f
// xxmrghd result, vector, value
// 1:
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::cmpi4, node, condReg, idxReg, 0);
generateTrg1Src2ImmInstruction(cg, TR::InstOpCode::xxpermdi, node, resReg, valueReg, vectorReg, 0x1);
generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, doneLabel, condReg);
generateTrg1Src2ImmInstruction(cg, TR::InstOpCode::xxpermdi, node, resReg, vectorReg, valueReg, 0x0);
TR::RegisterDependencyConditions *dep = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 5, cg->trMemory());
dep->addPostCondition(vectorReg, TR::RealRegister::NoReg);
dep->addPostCondition(idxReg, TR::RealRegister::NoReg);
dep->addPostCondition(valueReg, TR::RealRegister::NoReg);
dep->addPostCondition(resReg, TR::RealRegister::NoReg);
dep->addPostCondition(condReg, TR::RealRegister::NoReg);
generateDepLabelInstruction(cg, TR::InstOpCode::label, node, doneLabel, dep);
cg->stopUsingRegister(condReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
cg->decReferenceCount(thirdChild);
return resReg;
}
//handles both fstore and ifstore
TR::Register *OMR::Power::TreeEvaluator::fstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
bool indirect = node->getOpCode().isIndirect();
int childIndex = indirect?1:0;
TR::Node *child = node->getChild(childIndex);
// Special case storing an int value into a float variable
//
if (child->getRegister()==NULL && child->getOpCodeValue() == TR::ibits2f)
{
if (child->getReferenceCount()>1)
node->setAndIncChild(childIndex, child->getFirstChild());
else
node->setChild(childIndex, child->getFirstChild());
TR::Node::recreate(node, indirect?TR::istorei:TR::istore);
TR::TreeEvaluator::istoreEvaluator(node, cg);
node->setChild(childIndex, child);
TR::Node::recreate(node, indirect?TR::fstorei:TR::fstore);
cg->decReferenceCount(child);
return NULL;
}
TR::Register *valueReg = cg->evaluate(child);
TR::MemoryReference *tempMR;
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
// If the reference is volatile or potentially volatile, the layout needs to be
// fixed for patching if it turns out to be not a volatile after all.
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, 4, cg);
if (needSync)
generateInstruction(cg, TR::InstOpCode::lwsync, node);
generateMemSrc1Instruction(cg, TR::InstOpCode::stfs, node, tempMR, valueReg);
if (needSync)
{
TR::TreeEvaluator::postSyncConditions(node, cg, valueReg, tempMR, TR::InstOpCode::sync);
}
cg->decReferenceCount(child);
tempMR->decNodeReferenceCounts(cg);
return NULL;
}
//handles both dstore and idstore
TR::Register* OMR::Power::TreeEvaluator::dstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
bool indirect = node->getOpCode().isIndirect();
int childIndex = indirect?1:0;
TR::Node *child = node->getChild(childIndex);
bool isUnresolved = node->getSymbolReference()->isUnresolved();
TR::Compilation *comp = cg->comp();
// Special case storing a long value into a double variable
//
if (child->getRegister()==NULL && child->getOpCodeValue() == TR::lbits2d)
{
if (child->getReferenceCount()>1)
node->setAndIncChild(childIndex, child->getFirstChild());
else
node->setChild(childIndex, child->getFirstChild());
TR::Node::recreate(node, indirect?TR::lstorei:TR::lstore);
TR::TreeEvaluator::lstoreEvaluator(node, cg);
node->setChild(childIndex, child);
TR::Node::recreate(node, indirect?TR::dstorei:TR::dstore);
cg->decReferenceCount(child);
return NULL;
}
TR::Register *valueReg = cg->evaluate(child);
bool needSync= node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP();
TR::MemoryReference *tempMR;
if (cg->comp()->target().is32Bit() && needSync && !cg->is64BitProcessor())
{
TR::Register *addrReg = cg->allocateRegister();
TR::SymbolReference *vrlRef = comp->getSymRefTab()->findOrCreateVolatileWriteDoubleSymbolRef(comp->getMethodSymbol());
TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(5, 5, cg->trMemory());
if (isUnresolved)
{
#ifdef J9_PROJECT_SPECIFIC
// NOTE NOTE -- If the reference is volatile or potentially volatile, the layout
// needs to be fixed for patching if it turns out to be not a volatile after all.
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, 8, cg);
generateMemSrc1Instruction(cg, TR::InstOpCode::stfd, node, tempMR, valueReg);
tempMR->getUnresolvedSnippet()->setIsSpecialDouble();
tempMR->getUnresolvedSnippet()->setInSyncSequence();
#endif
}
else
{
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, 8, cg);