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PPCBinaryEncoding.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stdint.h>
#include <stdio.h>
#include <algorithm>
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Relocation.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "env/CompilerEnv.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "env/CHTable.hpp"
#endif
#include "env/Processors.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/DataTypes.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/List.hpp"
#include "p/codegen/GenerateInstructions.hpp"
#include "p/codegen/PPCInstruction.hpp"
#include "p/codegen/PPCOpsDefines.hpp"
#include "runtime/Runtime.hpp"
class TR_OpaqueMethodBlock;
namespace TR { class Register; }
static bool reversedConditionalBranchOpCode(TR::InstOpCode::Mnemonic op, TR::InstOpCode::Mnemonic *rop);
static bool isValidInSignExtendedField(uint32_t value, uint32_t mask)
{
uint32_t signMask = ~(mask >> 1);
return (value & signMask) == 0 || (value & signMask) == signMask;
}
static bool canUseAsVsxRegister(TR::RealRegister *reg)
{
switch (reg->getKind())
{
case TR_FPR:
case TR_VRF:
case TR_VSX_SCALAR:
case TR_VSX_VECTOR:
return true;
default:
return false;
}
}
/**
* Fills in the RT field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +------+----------+--------------------------------------------+
* | | RT | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldRT(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RT field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RT field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRT(cursor);
}
/**
* Fills in the FRT field of a binary-encoded instruction with the provided floating-point
* register:
*
* +------+----------+--------------------------------------------+
* | | FRT | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldFRT(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill FRT field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_FPR, "Attempt to fill FRT field with %s, which is not an FPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRT(cursor);
}
/**
* Fills in the VRT field of a binary-encoded instruction with the provided vector register:
*
* +------+----------+--------------------------------------------+
* | | VRT | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldVRT(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill VRT field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_VRF, "Attempt to fill VRT field with %s, which is not a VR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRT(cursor);
}
/**
* Fills in the XT field of a binary-encoded instruction with the provided VSX register:
*
* +------+----------+---------------------------------------+----+
* | | XT | | XT |
* | 0 | 6 | 11 | 31 |
* +------+----------+---------------------------------------+----+
*/
static void fillFieldXT(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XT field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XT field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXT(cursor);
}
/**
* Fills in the RS field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +------+----------+--------------------------------------------+
* | | RS | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldRS(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RS field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RS field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRS(cursor);
}
/**
* Fills in the XS field of a binary-encoded instruction with the provided VSX register:
*
* +------+----------+---------------------------------------+----+
* | | XS | | XS |
* | 0 | 6 | 11 | 31 |
* +------+----------+---------------------------------------+----+
*/
static void fillFieldXS(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XS field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XS field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXS(cursor);
}
/**
* Fills in the RA field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +-----------------+----------+---------------------------------+
* | | RA | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*/
static void fillFieldRA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RA field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRA(cursor);
}
/**
* Fills in the FRA field of a binary-encoded instruction with the provided floating-point
* register:
*
* +-----------------+----------+---------------------------------+
* | | FRA | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*/
static void fillFieldFRA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill FRA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_FPR, "Attempt to fill FRA field with %s, which is not an FPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldFRA(cursor);
}
/**
* Fills in the VRA field of a binary-encoded instruction with the provided vector register:
*
* +-----------------+----------+---------------------------------+
* | | VRA | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*/
static void fillFieldVRA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill VRA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_VRF, "Attempt to fill VRA field with %s, which is not a VR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRA(cursor);
}
/**
* Fills in the XA field of a binary-encoded instruction with the provided VSX register:
*
* +-----------------+----------+------------------+----+---------+
* | | XA | | XA | |
* | 0 | 11 | 16 | 29 | 30 |
* +-----------------+----------+------------------+----+---------+
*/
static void fillFieldXA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XA field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXA(cursor);
}
/**
* Fills in the RB field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +------------------------+--------+----------------------------+
* | | RB | |
* | 0 | 16 | 21 |
* +------------------------+--------+----------------------------+
*/
static void fillFieldRB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RB field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRB(cursor);
}
/**
* Fills in the FRB field of a binary-encoded instruction with the provided floating-point
* register:
*
* +------------------------+--------+----------------------------+
* | | FRB | |
* | 0 | 16 | 21 |
* +------------------------+--------+----------------------------+
*/
static void fillFieldFRB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill FRB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_FPR, "Attempt to fill FRB field with %s, which is not an FPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldFRB(cursor);
}
/**
* Fills in the FRB field of a binary-encoded instruction with the provided floating-point
* register:
*
* +------------------------+--------+----------------------------+
* | | FRB | |
* | 0 | 16 | 21 |
* +------------------------+--------+----------------------------+
*/
static void fillFieldVRB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill VRB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_VRF, "Attempt to fill VRB field with %s, which is not a VR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRB(cursor);
}
/**
* Fills in the XB field of a binary-encoded instruction with the provided VSX register:
*
* +----------------------------+----------+------------+----+----+
* | | XB | | XB | |
* | 0 | 16 | 21 | 30 | 31 |
* +----------------------------+----------+------------+----+----+
*/
static void fillFieldXB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XB field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXB(cursor);
}
/**
* Fills in the RC field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +---------------------------------+--------+-------------------+
* | | RC | |
* | 0 | 21 | 26 |
* +---------------------------------+--------+-------------------+
*/
static void fillFieldRC(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RC field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RC field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRC(cursor);
}
/**
* Fills in the FRC field of a binary-encoded instruction with the provided floating-point
* register:
*
* +---------------------------------+--------+-------------------+
* | | FRC | |
* | 0 | 21 | 26 |
* +---------------------------------+--------+-------------------+
*/
static void fillFieldFRC(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill FRC field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_FPR, "Attempt to fill FRC field with %s, which is not an FPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldFRC(cursor);
}
/**
* Fills in the VRC field of a binary-encoded instruction with the provided vector register:
*
* +---------------------------------+--------+-------------------+
* | | VRC | |
* | 0 | 21 | 26 |
* +---------------------------------+--------+-------------------+
*/
static void fillFieldVRC(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill VRC field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_VRF, "Attempt to fill VRC field with %s, which is not a VR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRC(cursor);
}
/**
* Fills in the XC field of a binary-encoded instruction with the provided VSX register:
*
* +---------------------------+------+-----+----+--------------+
* | | XC | | XC | |
* | 0 | 21 | 26 | 28 | 29 |
* +---------------------------+------+-----+----+--------------+
*/
static void fillFieldXC(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XC field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XC field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXC(cursor);
}
/**
* Fills in the condition register part of the BI field of a binary-encoded instruction with the
* provided condition register:
*
* +------------+-----+-------------------------------------------+
* | | BI | |
* | 0 | 11 | 14 |
* +------------+-----+-------------------------------------------+
*
* Note that the ISA defines the BI field to also include the part which determines which bit of
* the condition register is checked. This needs to be filled in using separate means. Typically,
* this is done by including the correct value of that part of the field as part of the binary
* encoding template of an extended mnemonic, e.g. beq.
*/
static void fillFieldBI(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill BI field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_CCR, "Attempt to fill BI field with %s, which is not a CCR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldBI(cursor);
}
/**
* Fills in the BF field of a binary-encoded instruction with the provided condition register:
*
* +------+-----+-------------------------------------------------+
* | | BF | |
* | 0 | 6 | 9 |
* +------+-----+-------------------------------------------------+
*
* This can also be used to fill in the condition register part of the BT field, with the part
* determining which bit should being filled in by other means.
*/
static void fillFieldBF(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill BF field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_CCR, "Attempt to fill BF field with %s, which is not a CCR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRT(cursor);
}
/**
* Fills in the BFA field of a binary-encoded instruction with the provided condition register:
*
* +------------------+-----+-------------------------------------+
* | | BFA | |
* | 0 | 11 | 14 |
* +------------------+-----+-------------------------------------+
*
* This can also be used to fill in the condition register part of the BA field, with the part
* determining which bit should being filled in by other means.
*/
static void fillFieldBFA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill BFA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_CCR, "Attempt to fill BFA field with %s, which is not a CCR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRA(cursor);
}
/**
* Fills in the BFA field of a binary-encoded instruction with the provided immediate value:
*
* +------------------+-----+-------------------------------------+
* | | BFA | |
* | 0 | 11 | 14 |
* +------------------+-----+-------------------------------------+
*/
static void fillFieldBFA(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x7) == val, "0x%x is out-of-range for BFA field", val);
*cursor |= val << 18;
}
/**
* Fills in the BFB field of a binary-encoded instruction with the provided condition register:
*
* +------------------------+-----+-------------------------------+
* | | BFB | |
* | 0 | 14 | 17 |
* +------------------------+-----+-------------------------------+
*
* This can also be used to fill in the condition register part of the BB field, with the part
* determining which bit should being filled in by other means.
*/
static void fillFieldBFB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill BFB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_CCR, "Attempt to fill BFB field with %s, which is not a CCR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRB(cursor);
}
/**
* Fills in the U field of a binary-encoded instruction with the provided immediate value:
*
* +-----------------------+-----+--------------------------------+
* | | U | |
* | 0 | 16 | 20 |
* +-----------------------+-----+--------------------------------+
*/
static void fillFieldU(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xfu) == val, "0x%x is out-of-range for U field", val);
*cursor |= val << 12;
}
/**
* Fills in the BF and W fields of a binary-encoded instruction with the provided immediate value.
* The bottom 7 bits are used to populate the BF field, while the 8th bit is used to populate the
* W field.
*
* +------+-----+-----+----+--------------------------------------+
* | | BF | | W | |
* | 0 | 6 | 9 | 15 | 16 |
* +------+-----+-----+----+--------------------------------------+
*/
static void fillFieldBFW(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xfu) == val, "0x%x is out-of-range for BF/W field", val);
*cursor |= ((val ^ 0x8) & 0x8) << 13;
*cursor |= (val & 0x7) << 23;
}
/**
* Fills in the FLM field of a binary-encoded instruction with the provided immediate value:
*
* +------+---------+---------------------------------------------+
* | | FLM | |
* | 0 | 7 | 15 |
* +------+---------+---------------------------------------------+
*/
static void fillFieldFLM(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xffu) == val, "0x%x is out-of-range for FLM field", val);
*cursor |= val << 17;
}
/**
* Fills in the FXM field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------+----------+----------------------------+
* | | FXM | |
* | 0 | 12 | 20 |
* +----------------------+----------+----------------------------+
*/
static void fillFieldFXM(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xffu) == val, "0x%x is out-of-range for FXM field", val);
*cursor |= val << 12;
}
/**
* Fills in the FXM field of a binary-encoded instruction with the provided immediate value in the
* same way as fillFieldFXM, while also asserting that exactly one bit in that field should be set.
*/
static void fillFieldFXM1(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, populationCount(val) == 1, "0x%x is invalid for FXM field, expecting exactly 1 bit set", val);
fillFieldFXM(instr, cursor, val);
}
/**
* Fills in the DCM or DQM field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+--------+------------------------+
* | | DCM | |
* | 0 | 16 | 22 |
* +----------------------------+--------+------------------------+
*/
static void fillFieldDCM(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3fu) == val, "0x%x is out-of-range for DCM/DQM field", val);
*cursor |= val << 10;
}
/**
* Fills in a 5-bit SH field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+----------+----------------------+
* | | SH | |
* | 0 | 16 | 21 |
* +----------------------------+----------+----------------------+
*/
static void fillFieldSH5(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x1fu) == val, "0x%x is out-of-range for SH(5) field", val);
*cursor |= val << 11;
}
/**
* Fills in a 6-bit SH field (as as used in MD-form and XS-form instructions) of a binary-encoded
* instruction with the provided immediate value:
*
* +----------------------------+----------+------------+----+----+
* | | SH | | SH | |
* | 0 | 16 | 21 | 30 | 31 |
* +----------------------------+----------+------------+----+----+
*/
static void fillFieldSH6(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3fu) == val, "0x%x is out-of-range for SH(6) field", val);
*cursor |= (val & 0x1fu) << 11;
*cursor |= (val & 0x20u) >> 4;
}
/**
* Fills in the SIM field of a binary-encoded instruction with the provided immediate value:
*
* +-----------------+----------+---------------------------------+
* | | SIM | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*/
static void fillFieldSIM(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, isValidInSignExtendedField(val, 0x1fu), "0x%x is out-of-range for SIM field", val);
*cursor |= (val & 0x1f) << 16;
}
/**
* Fills in the 16-bit SI field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+---------------------------------+
* | | SI |
* | 0 | 16 |
* +----------------------------+---------------------------------+
*/
static void fillFieldSI16(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, isValidInSignExtendedField(val, 0xffffu), "0x%x is out-of-range for SI(16) field", val);
*cursor |= val & 0xffff;
}
/**
* Fills in the 5-bit SI field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+----------+----------------------+
* | | SI | |
* | 0 | 16 | 21 |
* +----------------------------+----------+----------------------+
*/
static void fillFieldSI5(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, isValidInSignExtendedField(val, 0x1fu), "0x%x is out-of-range for SI(5) field", val);
*cursor |= (val & 0x1f) << 11;
}
/**
* Fills in the UIM field of a binary-encoded instruction with the provided immediate value:
*
* +-----------------+----------+---------------------------------+
* | | UIM | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*
* The numBits argument specifies the bit length of the UIM field being filled.
*/
static void fillFieldUIM(TR::Instruction *instr, uint32_t *cursor, int32_t numBits, uint32_t val)
{
uint32_t fieldMask = (1u << numBits) - 1;
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & fieldMask) == val, "0x%x is out-of-range for UIM(%d) field", val, numBits);
*cursor |= val << 16;
}
/**
* Fills in the 16-bit UI field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+---------------------------------+
* | | UI |
* | 0 | 16 |
* +----------------------------+---------------------------------+
*/
static void fillFieldUI16(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
// TODO: This is a hack until PIC sites are reworked. Currently, the PIC site handling code
// assumes that the entire address is in the immediate of the instruction, so we can't chop it to
// 16 bits like we should.
if (!instr->cg()->comp()->isPICSite(instr))
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xffffu) == val, "0x%x is out-of-range for UI field", val);
*cursor |= val & 0xffff;
}
/**
* Fills in the me/mb field (as used in MD-form and MDS-form instructions) of a binary-encoded
* instruction with the provided immediate value:
*
* +------------------------------------+---------+---------------+
* | | MDM | |
* | 0 | 21 | 27 |
* +------------------------------------+---------+---------------+
*/
static void fillFieldMDM(TR::Instruction *instr, uint32_t *cursor, int32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3f) == val, "0x%x is out-of-range for me/mb field", val);
*cursor |= (val & 0x1f) << 6;
*cursor |= (val & 0x20);
}
/**
* Fills in the the MB field (as used in M-form instructions) of a binary-encoded instruction with
* the provided immediate value:
*
* +------------------------------------+---------+---------------+
* | | MB | |
* | 0 | 21 | 26 |
* +------------------------------------+---------+---------------+
*/
static void fillFieldMB(TR::Instruction *instr, uint32_t *cursor, int32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x1f) == val, "0x%x is out-of-range for MB field", val);
*cursor |= val << 6;
}
/**
* Fills in the ME field (as used in M-form instructions) of a binary-encoded instruction with the
* provided immediate value:
*
* +----------------------------------------------+----------+----+
* | | ME | |
* | 0 | 26 | 31 |
* +----------------------------------------------+----------+----+
*/
static void fillFieldME(TR::Instruction *instr, uint32_t *cursor, int32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x1f) == val, "0x%x is out-of-range for ME field", val);
*cursor |= val << 1;
}
/**
* Fills in the RMC field of a binary-encoded instruction with the provided immediate value:
*
* +---------------------------------------+-----+----------------+
* | | RMC | |
* | 0 | 21 | 23 |
* +---------------------------------------+-----+----------------+
*/
static void fillFieldRMC(TR::Instruction *instr, uint32_t *cursor, uint64_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3) == val, "0x%llx is out-of-range for RMC field", val);
*cursor |= static_cast<uint32_t>(val << 9);
}
/**
* Fills in the SHB field of a binary-encoded instruction with the provided immediate value:
*
* +--------------------------------------------+-----+-----------+
* | | SHB | |
* | 0 | 22 | 26 |
* +--------------------------------------------+-----+-----------+
*/
static void fillFieldSHB(TR::Instruction *instr, uint32_t *cursor, uint64_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xf) == val, "0x%llx is out-of-range for SHB field", val);
*cursor |= static_cast<uint32_t>(val << 6);
}
/**
* Fills in the DM field (as used in XX3-form instructions) of a binary-encoded instruction with
* the provided immediate value:
*
* +----------------------------------+-----+---------------------+
* | | DM | |
* | 0 | 22 | 24 |
* +----------------------------------+-----+---------------------+
*/
static void fillFieldDM(TR::Instruction *instr, uint32_t *cursor, uint64_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3) == val, "0x%llx is out-of-range for DM field", val);
*cursor |= static_cast<uint32_t>(val << 8);
}
/**
* Fills in the SHW field (as used in XX3-form instructions) of a binary-encoded instruction with
* the provided immediate value:
*
* +----------------------------------+-----+---------------------+
* | | SHW | |
* | 0 | 22 | 24 |
* +----------------------------------+-----+---------------------+
*/
static void fillFieldSHW(TR::Instruction *instr, uint32_t *cursor, uint64_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3) == val, "0x%llx is out-of-range for SHW field", val);
*cursor |= static_cast<uint32_t>(val << 8);
}
uint8_t *
OMR::Power::Instruction::generateBinaryEncoding()
{
uint8_t *instructionStart = self()->cg()->getBinaryBufferCursor();
uint8_t *cursor = instructionStart;
TR::InstOpCode& opCode = self()->getOpCode();
cursor = opCode.copyBinaryToBuffer(cursor);
self()->fillBinaryEncodingFields(reinterpret_cast<uint32_t*>(cursor));
cursor += opCode.getBinaryLength();
TR_ASSERT_FATAL_WITH_INSTRUCTION(
self(),
(cursor - instructionStart) <= self()->getEstimatedBinaryLength(),
"Estimated binary length was %u bytes, but actual length was %u bytes",
self()->getEstimatedBinaryLength(),
static_cast<uint32_t>(cursor - instructionStart)
);
self()->setBinaryLength(cursor - instructionStart);
self()->setBinaryEncoding(instructionStart);
return cursor;
}
void
OMR::Power::Instruction::fillBinaryEncodingFields(uint32_t *cursor)
{
switch (self()->getOpCode().getFormat())
{
case FORMAT_NONE:
break;
case FORMAT_DIRECT:
// TODO: Split genop into two instructions depending on version of Power in use
if (self()->getOpCodeValue() == TR::InstOpCode::genop)
{
TR::RealRegister *r = self()->cg()->machine()->getRealRegister(TR::Compiler->target.cpu.id() > TR_PPCp6 ? TR::RealRegister::gr2 : TR::RealRegister::gr1);
fillFieldRA(self(), cursor, r);
fillFieldRS(self(), cursor, r);
}
break;
default:
TR_ASSERT_FATAL_WITH_INSTRUCTION(self(), false, "Format %d cannot be binary encoded by Instruction", self()->getOpCode().getFormat());
}
}
int32_t
OMR::Power::Instruction::estimateBinaryLength(int32_t currentEstimate)
{
int8_t maxLength = self()->getOpCode().getMaxBinaryLength();
self()->setEstimatedBinaryLength(maxLength);
return currentEstimate + maxLength;
}
uint8_t *TR::PPCAlignmentNopInstruction::generateBinaryEncoding()
{
bool trace = cg()->comp()->getOption(TR_TraceCG);
uint32_t currentMisalign = reinterpret_cast<uintptr_t>(cg()->getBinaryBufferCursor()) % _alignment;
if (currentMisalign)
{
uint32_t nopsToAdd = (_alignment - currentMisalign) / PPC_INSTRUCTION_LENGTH;
// For performance reasons, the last nop added might be different than the others, e.g. on P6
// and above a group-ending nop is typically used. Since we add nops in reverse order, we add
// this special nop first. All other padding instructions will be regular nops.
TR::Instruction *lastNop = generateInstruction(cg(), getOpCodeValue(), getNode(), self());
lastNop->setEstimatedBinaryLength(PPC_INSTRUCTION_LENGTH);
if (trace)
traceMsg(cg()->comp(), "Expanding alignment nop %p into %u instructions: [ %p ", self(), nopsToAdd, lastNop);
for (uint32_t i = 1; i < nopsToAdd; i++)
{
TR::Instruction *nop = generateInstruction(cg(), TR::InstOpCode::nop, getNode(), self());
nop->setEstimatedBinaryLength(PPC_INSTRUCTION_LENGTH);
if (trace)
traceMsg(cg()->comp(), "%p ", nop);
}
if (trace)
traceMsg(cg()->comp(), "]\n");
}
else
{
if (trace)
traceMsg(cg()->comp(), "Eliminating alignment nop %p, since the next instruction is already aligned\n", self());
}
cg()->addAccumulatedInstructionLengthError(getEstimatedBinaryLength() - currentMisalign);
// When the trace log prints the list of instructions after binary encoding, we don't want this
// instruction to show up any more. Removing it from the linked list of instructions does this
// without affecting this instruction's next pointer, so the binary encoding loop can continue
// and encode the actual nops we emitted as if nothing happened.
self()->remove();
return cg()->getBinaryBufferCursor();
}
int32_t TR::PPCAlignmentNopInstruction::estimateBinaryLength(int32_t currentEstimate)
{
self()->setEstimatedBinaryLength(_alignment - PPC_INSTRUCTION_LENGTH);
return currentEstimate + self()->getEstimatedBinaryLength();
}
uint8_t TR::PPCAlignmentNopInstruction::getBinaryLengthLowerBound()
{
return 0;
}
void TR::PPCLabelInstruction::fillBinaryEncodingFields(uint32_t *cursor)
{
TR::LabelSymbol *label = getLabelSymbol();
switch (getOpCode().getFormat())
{
case FORMAT_NONE:
if (getOpCodeValue() == TR::InstOpCode::label)
label->setCodeLocation(reinterpret_cast<uint8_t*>(cursor));
break;
case FORMAT_I_FORM:
if (label->getCodeLocation())
cg()->apply24BitLabelRelativeRelocation(reinterpret_cast<int32_t*>(cursor), label);
else
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelRelative24BitRelocation(reinterpret_cast<uint8_t*>(cursor), label));
break;
default:
TR_ASSERT_FATAL_WITH_INSTRUCTION(self(), false, "Format %d cannot be binary encoded by PPCLabelInstruction", getOpCode().getFormat());
}
}
int32_t TR::PPCLabelInstruction::estimateBinaryLength(int32_t currentEstimate)
{
if (getOpCodeValue() == TR::InstOpCode::label)
getLabelSymbol()->setEstimatedCodeLocation(currentEstimate);
return self()->TR::Instruction::estimateBinaryLength(currentEstimate);
}
// TODO This should probably be refactored and moved onto OMR::Power::InstOpCode
static bool reversedConditionalBranchOpCode(TR::InstOpCode::Mnemonic op, TR::InstOpCode::Mnemonic *rop)
{
switch (op)
{
case TR::InstOpCode::bdnz:
*rop = TR::InstOpCode::bdz;
return(false);
case TR::InstOpCode::bdz:
*rop = TR::InstOpCode::bdnz;
return(false);
case TR::InstOpCode::beq:
*rop = TR::InstOpCode::bne;
return(false);
case TR::InstOpCode::beql:
*rop = TR::InstOpCode::bne;
return(true);
case TR::InstOpCode::bge:
*rop = TR::InstOpCode::blt;
return(false);
case TR::InstOpCode::bgel:
*rop = TR::InstOpCode::blt;
return(true);
case TR::InstOpCode::bgt:
*rop = TR::InstOpCode::ble;
return(false);
case TR::InstOpCode::bgtl:
*rop = TR::InstOpCode::ble;
return(true);
case TR::InstOpCode::ble:
*rop = TR::InstOpCode::bgt;
return(false);
case TR::InstOpCode::blel:
*rop = TR::InstOpCode::bgt;
return(true);
case TR::InstOpCode::blt:
*rop = TR::InstOpCode::bge;
return(false);
case TR::InstOpCode::bltl:
*rop = TR::InstOpCode::bge;
return(true);
case TR::InstOpCode::bne:
*rop = TR::InstOpCode::beq;
return(false);
case TR::InstOpCode::bnel:
*rop = TR::InstOpCode::beq;
return(true);
case TR::InstOpCode::bnun:
*rop = TR::InstOpCode::bun;
return(false);
case TR::InstOpCode::bun:
*rop = TR::InstOpCode::bnun;
return(false);
default:
TR_ASSERT(0, "New PPC conditional branch opcodes have to have corresponding reversed opcode: %d\n", (int32_t)op);
*rop = TR::InstOpCode::bad;
return(false);
}
}
void TR::PPCConditionalBranchInstruction::expandIntoFarBranch()
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(self(), getLabelSymbol(), "Cannot expand conditional branch without a label");
if (comp()->getOption(TR_TraceCG))
traceMsg(comp(), "Expanding conditional branch instruction %p into a far branch\n", self());
TR::InstOpCode::Mnemonic newOpCode;
bool wasLinkForm = reversedConditionalBranchOpCode(getOpCodeValue(), &newOpCode);
setOpCodeValue(newOpCode);
TR::LabelSymbol *skipBranchLabel = generateLabelSymbol(cg());
skipBranchLabel->setEstimatedCodeLocation(getEstimatedBinaryLocation() + 4);
TR::Instruction *branchInstr = generateLabelInstruction(cg(), wasLinkForm ? TR::InstOpCode::bl : TR::InstOpCode::b, getNode(), getLabelSymbol(), self());
branchInstr->setEstimatedBinaryLength(4);
TR::Instruction *labelInstr = generateLabelInstruction(cg(), TR::InstOpCode::label, getNode(), skipBranchLabel, branchInstr);
labelInstr->setEstimatedBinaryLength(0);
setLabelSymbol(skipBranchLabel);
setEstimatedBinaryLength(4);
reverseLikeliness();
_farRelocation = true;
}
void TR::PPCConditionalBranchInstruction::fillBinaryEncodingFields(uint32_t *cursor)
{
switch (getOpCode().getFormat())
{
case FORMAT_B_FORM:
{
TR::LabelSymbol *label = getLabelSymbol();
TR_ASSERT_FATAL_WITH_INSTRUCTION(self(), label, "B-form conditional branch has no label");
if (label->getCodeLocation())
cg()->apply16BitLabelRelativeRelocation(reinterpret_cast<int32_t*>(cursor), label);
else
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelRelative16BitRelocation(reinterpret_cast<uint8_t*>(cursor), label));
break;
}
case FORMAT_XL_FORM_BRANCH:
TR_ASSERT_FATAL_WITH_INSTRUCTION(self(), !getLabelSymbol(), "XL-form conditional branch has a label");
break;
default: