-
Notifications
You must be signed in to change notification settings - Fork 139
/
Copy pathPPCBinaryEncoding.cpp
2131 lines (1861 loc) · 83.6 KB
/
PPCBinaryEncoding.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stdint.h>
#include <stdio.h>
#include <algorithm>
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Relocation.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "env/CompilerEnv.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "env/CHTable.hpp"
#endif
#include "env/Processors.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/DataTypes.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/List.hpp"
#include "p/codegen/GenerateInstructions.hpp"
#include "p/codegen/PPCInstruction.hpp"
#include "p/codegen/PPCOpsDefines.hpp"
#include "runtime/Runtime.hpp"
class TR_OpaqueMethodBlock;
namespace TR { class Register; }
static bool reversedConditionalBranchOpCode(TR::InstOpCode::Mnemonic op, TR::InstOpCode::Mnemonic *rop);
static bool isValidInSignExtendedField(uint32_t value, uint32_t mask)
{
uint32_t signMask = ~(mask >> 1);
return (value & signMask) == 0 || (value & signMask) == signMask;
}
static bool canUseAsVsxRegister(TR::RealRegister *reg)
{
switch (reg->getKind())
{
case TR_FPR:
case TR_VRF:
case TR_VSX_SCALAR:
case TR_VSX_VECTOR:
return true;
default:
return false;
}
}
/**
* Fills in the RT field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +------+----------+--------------------------------------------+
* | | RT | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldRT(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RT field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RT field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRT(cursor);
}
/**
* Fills in the FRT field of a binary-encoded instruction with the provided floating-point
* register:
*
* +------+----------+--------------------------------------------+
* | | FRT | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldFRT(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill FRT field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_FPR, "Attempt to fill FRT field with %s, which is not an FPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRT(cursor);
}
/**
* Fills in the VRT field of a binary-encoded instruction with the provided vector register:
*
* +------+----------+--------------------------------------------+
* | | VRT | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldVRT(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill VRT field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_VRF, "Attempt to fill VRT field with %s, which is not a VR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRT(cursor);
}
/**
* Fills in the XT field of a binary-encoded instruction with the provided VSX register:
*
* +------+----------+---------------------------------------+----+
* | | XT | | XT |
* | 0 | 6 | 11 | 31 |
* +------+----------+---------------------------------------+----+
*/
static void fillFieldXT(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XT field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XT field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXT(cursor);
}
/**
* Fills in the RS field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +------+----------+--------------------------------------------+
* | | RS | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldRS(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RS field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RS field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRS(cursor);
}
/**
* Fills in the FRS field of a binary-encoded instruction with the provided floating-point
* register:
*
* +------+----------+--------------------------------------------+
* | | FRS | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldFRS(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill FRS field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_FPR, "Attempt to fill FRS field with %s, which is not an FPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRS(cursor);
}
/**
* Fills in the VRS field of a binary-encoded instruction with the provided vector register:
*
* +------+----------+--------------------------------------------+
* | | VRS | |
* | 0 | 6 | 11 |
* +------+----------+--------------------------------------------+
*/
static void fillFieldVRS(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill VRS field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_VRF, "Attempt to fill VRS field with %s, which is not a VR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRS(cursor);
}
/**
* Fills in the XS field of a binary-encoded instruction with the provided VSX register:
*
* +------+----------+---------------------------------------+----+
* | | XS | | XS |
* | 0 | 6 | 11 | 31 |
* +------+----------+---------------------------------------+----+
*/
static void fillFieldXS(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XS field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XS field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXS(cursor);
}
/**
* Fills in the RA field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +-----------------+----------+---------------------------------+
* | | RA | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*/
static void fillFieldRA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RA field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRA(cursor);
}
/**
* Fills in the FRA field of a binary-encoded instruction with the provided floating-point
* register:
*
* +-----------------+----------+---------------------------------+
* | | FRA | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*/
static void fillFieldFRA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill FRA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_FPR, "Attempt to fill FRA field with %s, which is not an FPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldFRA(cursor);
}
/**
* Fills in the VRA field of a binary-encoded instruction with the provided vector register:
*
* +-----------------+----------+---------------------------------+
* | | VRA | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*/
static void fillFieldVRA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill VRA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_VRF, "Attempt to fill VRA field with %s, which is not a VR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRA(cursor);
}
/**
* Fills in the XA field of a binary-encoded instruction with the provided VSX register:
*
* +-----------------+----------+------------------+----+---------+
* | | XA | | XA | |
* | 0 | 11 | 16 | 29 | 30 |
* +-----------------+----------+------------------+----+---------+
*/
static void fillFieldXA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XA field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXA(cursor);
}
/**
* Fills in the RB field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +------------------------+--------+----------------------------+
* | | RB | |
* | 0 | 16 | 21 |
* +------------------------+--------+----------------------------+
*/
static void fillFieldRB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RB field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRB(cursor);
}
/**
* Fills in the FRB field of a binary-encoded instruction with the provided floating-point
* register:
*
* +------------------------+--------+----------------------------+
* | | FRB | |
* | 0 | 16 | 21 |
* +------------------------+--------+----------------------------+
*/
static void fillFieldFRB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill FRB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_FPR, "Attempt to fill FRB field with %s, which is not an FPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldFRB(cursor);
}
/**
* Fills in the FRB field of a binary-encoded instruction with the provided floating-point
* register:
*
* +------------------------+--------+----------------------------+
* | | FRB | |
* | 0 | 16 | 21 |
* +------------------------+--------+----------------------------+
*/
static void fillFieldVRB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill VRB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_VRF, "Attempt to fill VRB field with %s, which is not a VR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRB(cursor);
}
/**
* Fills in the XB field of a binary-encoded instruction with the provided VSX register:
*
* +----------------------------+----------+------------+----+----+
* | | XB | | XB | |
* | 0 | 16 | 21 | 30 | 31 |
* +----------------------------+----------+------------+----+----+
*/
static void fillFieldXB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XB field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXB(cursor);
}
/**
* Fills in the RC field of a binary-encoded instruction with the provided general-purpose
* register:
*
* +---------------------------------+--------+-------------------+
* | | RC | |
* | 0 | 21 | 26 |
* +---------------------------------+--------+-------------------+
*/
static void fillFieldRC(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill RC field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_GPR, "Attempt to fill RC field with %s, which is not a GPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRC(cursor);
}
/**
* Fills in the FRC field of a binary-encoded instruction with the provided floating-point
* register:
*
* +---------------------------------+--------+-------------------+
* | | FRC | |
* | 0 | 21 | 26 |
* +---------------------------------+--------+-------------------+
*/
static void fillFieldFRC(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill FRC field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_FPR, "Attempt to fill FRC field with %s, which is not an FPR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldFRC(cursor);
}
/**
* Fills in the VRC field of a binary-encoded instruction with the provided vector register:
*
* +---------------------------------+--------+-------------------+
* | | VRC | |
* | 0 | 21 | 26 |
* +---------------------------------+--------+-------------------+
*/
static void fillFieldVRC(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill VRC field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_VRF, "Attempt to fill VRC field with %s, which is not a VR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRC(cursor);
}
/**
* Fills in the XC field of a binary-encoded instruction with the provided VSX register:
*
* +---------------------------+------+-----+----+--------------+
* | | XC | | XC | |
* | 0 | 21 | 26 | 28 | 29 |
* +---------------------------+------+-----+----+--------------+
*/
static void fillFieldXC(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill XC field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, canUseAsVsxRegister(reg), "Attempt to fill XC field with %s, which is not a VSR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldXC(cursor);
}
/**
* Fills in the condition register part of the BI field of a binary-encoded instruction with the
* provided condition register:
*
* +------------+-----+-------------------------------------------+
* | | BI | |
* | 0 | 11 | 14 |
* +------------+-----+-------------------------------------------+
*
* Note that the ISA defines the BI field to also include the part which determines which bit of
* the condition register is checked. This needs to be filled in using separate means. Typically,
* this is done by including the correct value of that part of the field as part of the binary
* encoding template of an extended mnemonic, e.g. beq.
*/
static void fillFieldBI(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill BI field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_CCR, "Attempt to fill BI field with %s, which is not a CCR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldBI(cursor);
}
/**
* Fills in the BF field of a binary-encoded instruction with the provided condition register:
*
* +------+-----+-------------------------------------------------+
* | | BF | |
* | 0 | 6 | 9 |
* +------+-----+-------------------------------------------------+
*
* This can also be used to fill in the condition register part of the BT field, with the part
* determining which bit should being filled in by other means.
*/
static void fillFieldBF(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill BF field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_CCR, "Attempt to fill BF field with %s, which is not a CCR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRT(cursor);
}
/**
* Fills in the BFA field of a binary-encoded instruction with the provided condition register:
*
* +------------------+-----+-------------------------------------+
* | | BFA | |
* | 0 | 11 | 14 |
* +------------------+-----+-------------------------------------+
*
* This can also be used to fill in the condition register part of the BA field, with the part
* determining which bit should being filled in by other means.
*/
static void fillFieldBFA(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill BFA field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_CCR, "Attempt to fill BFA field with %s, which is not a CCR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRA(cursor);
}
/**
* Fills in the BFA field of a binary-encoded instruction with the provided immediate value:
*
* +------------------+-----+-------------------------------------+
* | | BFA | |
* | 0 | 11 | 14 |
* +------------------+-----+-------------------------------------+
*/
static void fillFieldBFA(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x7) == val, "0x%x is out-of-range for BFA field", val);
*cursor |= val << 18;
}
/**
* Fills in the BFB field of a binary-encoded instruction with the provided condition register:
*
* +------------------------+-----+-------------------------------+
* | | BFB | |
* | 0 | 14 | 17 |
* +------------------------+-----+-------------------------------+
*
* This can also be used to fill in the condition register part of the BB field, with the part
* determining which bit should being filled in by other means.
*/
static void fillFieldBFB(TR::Instruction *instr, uint32_t *cursor, TR::RealRegister *reg)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg, "Attempt to fill BFB field with null register");
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, reg->getKind() == TR_CCR, "Attempt to fill BFB field with %s, which is not a CCR", reg->getRegisterName(instr->cg()->comp()));
reg->setRegisterFieldRB(cursor);
}
/**
* Fills in the U field of a binary-encoded instruction with the provided immediate value:
*
* +-----------------------+-----+--------------------------------+
* | | U | |
* | 0 | 16 | 20 |
* +-----------------------+-----+--------------------------------+
*/
static void fillFieldU(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xfu) == val, "0x%x is out-of-range for U field", val);
*cursor |= val << 12;
}
/**
* Fills in the BF and W fields of a binary-encoded instruction with the provided immediate value.
* The bottom 7 bits are used to populate the BF field, while the 8th bit is used to populate the
* W field.
*
* +------+-----+-----+----+--------------------------------------+
* | | BF | | W | |
* | 0 | 6 | 9 | 15 | 16 |
* +------+-----+-----+----+--------------------------------------+
*/
static void fillFieldBFW(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xfu) == val, "0x%x is out-of-range for BF/W field", val);
*cursor |= ((val ^ 0x8) & 0x8) << 13;
*cursor |= (val & 0x7) << 23;
}
/**
* Fills in the FLM field of a binary-encoded instruction with the provided immediate value:
*
* +------+---------+---------------------------------------------+
* | | FLM | |
* | 0 | 7 | 15 |
* +------+---------+---------------------------------------------+
*/
static void fillFieldFLM(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xffu) == val, "0x%x is out-of-range for FLM field", val);
*cursor |= val << 17;
}
/**
* Fills in the FXM field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------+----------+----------------------------+
* | | FXM | |
* | 0 | 12 | 20 |
* +----------------------+----------+----------------------------+
*/
static void fillFieldFXM(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xffu) == val, "0x%x is out-of-range for FXM field", val);
*cursor |= val << 12;
}
/**
* Fills in the FXM field of a binary-encoded instruction with the provided immediate value in the
* same way as fillFieldFXM, while also asserting that exactly one bit in that field should be set.
*/
static void fillFieldFXM1(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, populationCount(val) == 1, "0x%x is invalid for FXM field, expecting exactly 1 bit set", val);
fillFieldFXM(instr, cursor, val);
}
/**
* Fills in the DCM or DQM field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+--------+------------------------+
* | | DCM | |
* | 0 | 16 | 22 |
* +----------------------------+--------+------------------------+
*/
static void fillFieldDCM(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3fu) == val, "0x%x is out-of-range for DCM/DQM field", val);
*cursor |= val << 10;
}
/**
* Fills in a 5-bit SH field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+----------+----------------------+
* | | SH | |
* | 0 | 16 | 21 |
* +----------------------------+----------+----------------------+
*/
static void fillFieldSH5(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x1fu) == val, "0x%x is out-of-range for SH(5) field", val);
*cursor |= val << 11;
}
/**
* Fills in a 6-bit SH field (as as used in MD-form and XS-form instructions) of a binary-encoded
* instruction with the provided immediate value:
*
* +----------------------------+----------+------------+----+----+
* | | SH | | SH | |
* | 0 | 16 | 21 | 30 | 31 |
* +----------------------------+----------+------------+----+----+
*/
static void fillFieldSH6(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3fu) == val, "0x%x is out-of-range for SH(6) field", val);
*cursor |= (val & 0x1fu) << 11;
*cursor |= (val & 0x20u) >> 4;
}
/**
* Fills in the SIM field of a binary-encoded instruction with the provided immediate value:
*
* +-----------------+----------+---------------------------------+
* | | SIM | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*/
static void fillFieldSIM(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, isValidInSignExtendedField(val, 0x1fu), "0x%x is out-of-range for SIM field", val);
*cursor |= (val & 0x1f) << 16;
}
/**
* Fills in the 16-bit D field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+---------------------------------+
* | | D |
* | 0 | 16 |
* +----------------------------+---------------------------------+
*/
static void fillFieldD16(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, isValidInSignExtendedField(val, 0xffffu), "0x%x is out-of-range for D(16) field", val);
*cursor |= val & 0xffff;
}
/**
* Fills in the 16-bit DS field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+---------------------------+-----+
* | | DS | |
* | 0 | 16 | 30 |
* +----------------------------+---------------------------+-----+
*
* Note that the provided immediate value is expected to be a 4 byte aligned offset and only the
* upper 14 bits are used to fill in the DS field.
*/
static void fillFieldDS(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, isValidInSignExtendedField(val, 0xffffu), "0x%x is out-of-range for DS field", val);
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3u) == 0, "0x%x is misaligned for DS field", val);
*cursor |= val & 0xfffcu;
}
/**
* Fills in the 16-bit SI field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+---------------------------------+
* | | SI |
* | 0 | 16 |
* +----------------------------+---------------------------------+
*/
static void fillFieldSI16(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, isValidInSignExtendedField(val, 0xffffu), "0x%x is out-of-range for SI(16) field", val);
*cursor |= val & 0xffff;
}
/**
* Fills in the 5-bit SI field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+----------+----------------------+
* | | SI | |
* | 0 | 16 | 21 |
* +----------------------------+----------+----------------------+
*/
static void fillFieldSI5(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, isValidInSignExtendedField(val, 0x1fu), "0x%x is out-of-range for SI(5) field", val);
*cursor |= (val & 0x1f) << 11;
}
/**
* Fills in the UIM field of a binary-encoded instruction with the provided immediate value:
*
* +-----------------+----------+---------------------------------+
* | | UIM | |
* | 0 | 11 | 16 |
* +-----------------+----------+---------------------------------+
*
* The numBits argument specifies the bit length of the UIM field being filled.
*/
static void fillFieldUIM(TR::Instruction *instr, uint32_t *cursor, int32_t numBits, uint32_t val)
{
uint32_t fieldMask = (1u << numBits) - 1;
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & fieldMask) == val, "0x%x is out-of-range for UIM(%d) field", val, numBits);
*cursor |= val << 16;
}
/**
* Fills in the 16-bit UI field of a binary-encoded instruction with the provided immediate value:
*
* +----------------------------+---------------------------------+
* | | UI |
* | 0 | 16 |
* +----------------------------+---------------------------------+
*/
static void fillFieldUI16(TR::Instruction *instr, uint32_t *cursor, uint32_t val)
{
// TODO: This is a hack until PIC sites are reworked. Currently, the PIC site handling code
// assumes that the entire address is in the immediate of the instruction, so we can't chop it to
// 16 bits like we should.
if (!instr->cg()->comp()->isPICSite(instr))
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xffffu) == val, "0x%x is out-of-range for UI field", val);
*cursor |= val & 0xffff;
}
/**
* Fills in the me/mb field (as used in MD-form and MDS-form instructions) of a binary-encoded
* instruction with the provided immediate value:
*
* +------------------------------------+---------+---------------+
* | | MDM | |
* | 0 | 21 | 27 |
* +------------------------------------+---------+---------------+
*/
static void fillFieldMDM(TR::Instruction *instr, uint32_t *cursor, int32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3f) == val, "0x%x is out-of-range for me/mb field", val);
*cursor |= (val & 0x1f) << 6;
*cursor |= (val & 0x20);
}
/**
* Fills in the the MB field (as used in M-form instructions) of a binary-encoded instruction with
* the provided immediate value:
*
* +------------------------------------+---------+---------------+
* | | MB | |
* | 0 | 21 | 26 |
* +------------------------------------+---------+---------------+
*/
static void fillFieldMB(TR::Instruction *instr, uint32_t *cursor, int32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x1f) == val, "0x%x is out-of-range for MB field", val);
*cursor |= val << 6;
}
/**
* Fills in the ME field (as used in M-form instructions) of a binary-encoded instruction with the
* provided immediate value:
*
* +----------------------------------------------+----------+----+
* | | ME | |
* | 0 | 26 | 31 |
* +----------------------------------------------+----------+----+
*/
static void fillFieldME(TR::Instruction *instr, uint32_t *cursor, int32_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x1f) == val, "0x%x is out-of-range for ME field", val);
*cursor |= val << 1;
}
/**
* Fills in the RMC field of a binary-encoded instruction with the provided immediate value:
*
* +---------------------------------------+-----+----------------+
* | | RMC | |
* | 0 | 21 | 23 |
* +---------------------------------------+-----+----------------+
*/
static void fillFieldRMC(TR::Instruction *instr, uint32_t *cursor, uint64_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3) == val, "0x%llx is out-of-range for RMC field", val);
*cursor |= static_cast<uint32_t>(val << 9);
}
/**
* Fills in the SHB field of a binary-encoded instruction with the provided immediate value:
*
* +--------------------------------------------+-----+-----------+
* | | SHB | |
* | 0 | 22 | 26 |
* +--------------------------------------------+-----+-----------+
*/
static void fillFieldSHB(TR::Instruction *instr, uint32_t *cursor, uint64_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0xf) == val, "0x%llx is out-of-range for SHB field", val);
*cursor |= static_cast<uint32_t>(val << 6);
}
/**
* Fills in the DM field (as used in XX3-form instructions) of a binary-encoded instruction with
* the provided immediate value:
*
* +----------------------------------+-----+---------------------+
* | | DM | |
* | 0 | 22 | 24 |
* +----------------------------------+-----+---------------------+
*/
static void fillFieldDM(TR::Instruction *instr, uint32_t *cursor, uint64_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3) == val, "0x%llx is out-of-range for DM field", val);
*cursor |= static_cast<uint32_t>(val << 8);
}
/**
* Fills in the SHW field (as used in XX3-form instructions) of a binary-encoded instruction with
* the provided immediate value:
*
* +----------------------------------+-----+---------------------+
* | | SHW | |
* | 0 | 22 | 24 |
* +----------------------------------+-----+---------------------+
*/
static void fillFieldSHW(TR::Instruction *instr, uint32_t *cursor, uint64_t val)
{
TR_ASSERT_FATAL_WITH_INSTRUCTION(instr, (val & 0x3) == val, "0x%llx is out-of-range for SHW field", val);
*cursor |= static_cast<uint32_t>(val << 8);
}
uint8_t *
OMR::Power::Instruction::generateBinaryEncoding()
{
uint8_t *instructionStart = self()->cg()->getBinaryBufferCursor();
uint8_t *cursor = instructionStart;
TR::InstOpCode& opCode = self()->getOpCode();
cursor = opCode.copyBinaryToBuffer(cursor);
self()->fillBinaryEncodingFields(reinterpret_cast<uint32_t*>(cursor));
cursor += opCode.getBinaryLength();
TR_ASSERT_FATAL_WITH_INSTRUCTION(
self(),
(cursor - instructionStart) <= self()->getEstimatedBinaryLength(),
"Estimated binary length was %u bytes, but actual length was %u bytes",
self()->getEstimatedBinaryLength(),
static_cast<uint32_t>(cursor - instructionStart)
);
self()->setBinaryLength(cursor - instructionStart);
self()->setBinaryEncoding(instructionStart);
return cursor;
}
void
OMR::Power::Instruction::fillBinaryEncodingFields(uint32_t *cursor)
{
switch (self()->getOpCode().getFormat())
{
case FORMAT_NONE:
break;
case FORMAT_DIRECT:
// TODO: Split genop into two instructions depending on version of Power in use
if (self()->getOpCodeValue() == TR::InstOpCode::genop)
{
TR::RealRegister *r = self()->cg()->machine()->getRealRegister(TR::Compiler->target.cpu.id() > TR_PPCp6 ? TR::RealRegister::gr2 : TR::RealRegister::gr1);
fillFieldRA(self(), cursor, r);
fillFieldRS(self(), cursor, r);
}
break;
default:
TR_ASSERT_FATAL_WITH_INSTRUCTION(self(), false, "Format %d cannot be binary encoded by Instruction", self()->getOpCode().getFormat());
}
}
int32_t
OMR::Power::Instruction::estimateBinaryLength(int32_t currentEstimate)
{
int8_t maxLength = self()->getOpCode().getMaxBinaryLength();
self()->setEstimatedBinaryLength(maxLength);
return currentEstimate + maxLength;
}
uint8_t *TR::PPCAlignmentNopInstruction::generateBinaryEncoding()
{
bool trace = cg()->comp()->getOption(TR_TraceCG);
uint32_t currentMisalign = reinterpret_cast<uintptr_t>(cg()->getBinaryBufferCursor()) % _alignment;
if (currentMisalign)
{
uint32_t nopsToAdd = (_alignment - currentMisalign) / PPC_INSTRUCTION_LENGTH;
// For performance reasons, the last nop added might be different than the others, e.g. on P6
// and above a group-ending nop is typically used. Since we add nops in reverse order, we add
// this special nop first. All other padding instructions will be regular nops.
TR::Instruction *lastNop = generateInstruction(cg(), getOpCodeValue(), getNode(), self());
lastNop->setEstimatedBinaryLength(PPC_INSTRUCTION_LENGTH);
if (trace)
traceMsg(cg()->comp(), "Expanding alignment nop %p into %u instructions: [ %p ", self(), nopsToAdd, lastNop);
for (uint32_t i = 1; i < nopsToAdd; i++)
{
TR::Instruction *nop = generateInstruction(cg(), TR::InstOpCode::nop, getNode(), self());
nop->setEstimatedBinaryLength(PPC_INSTRUCTION_LENGTH);
if (trace)
traceMsg(cg()->comp(), "%p ", nop);
}
if (trace)
traceMsg(cg()->comp(), "]\n");
}
else
{
if (trace)
traceMsg(cg()->comp(), "Eliminating alignment nop %p, since the next instruction is already aligned\n", self());
}
cg()->addAccumulatedInstructionLengthError(getEstimatedBinaryLength() - currentMisalign);
// When the trace log prints the list of instructions after binary encoding, we don't want this
// instruction to show up any more. Removing it from the linked list of instructions does this
// without affecting this instruction's next pointer, so the binary encoding loop can continue
// and encode the actual nops we emitted as if nothing happened.
self()->remove();
return cg()->getBinaryBufferCursor();
}
int32_t TR::PPCAlignmentNopInstruction::estimateBinaryLength(int32_t currentEstimate)
{
self()->setEstimatedBinaryLength(_alignment - PPC_INSTRUCTION_LENGTH);
return currentEstimate + self()->getEstimatedBinaryLength();
}
uint8_t TR::PPCAlignmentNopInstruction::getBinaryLengthLowerBound()
{
return 0;
}
void TR::PPCLabelInstruction::fillBinaryEncodingFields(uint32_t *cursor)
{
TR::LabelSymbol *label = getLabelSymbol();
switch (getOpCode().getFormat())
{
case FORMAT_NONE:
if (getOpCodeValue() == TR::InstOpCode::label)
label->setCodeLocation(reinterpret_cast<uint8_t*>(cursor));
break;
case FORMAT_I_FORM:
if (label->getCodeLocation())
cg()->apply24BitLabelRelativeRelocation(reinterpret_cast<int32_t*>(cursor), label);
else
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelRelative24BitRelocation(reinterpret_cast<uint8_t*>(cursor), label));
break;
default:
TR_ASSERT_FATAL_WITH_INSTRUCTION(self(), false, "Format %d cannot be binary encoded by PPCLabelInstruction", getOpCode().getFormat());
}
}
int32_t TR::PPCLabelInstruction::estimateBinaryLength(int32_t currentEstimate)
{
if (getOpCodeValue() == TR::InstOpCode::label)
getLabelSymbol()->setEstimatedCodeLocation(currentEstimate);
return self()->TR::Instruction::estimateBinaryLength(currentEstimate);
}
// TODO This should probably be refactored and moved onto OMR::Power::InstOpCode
static bool reversedConditionalBranchOpCode(TR::InstOpCode::Mnemonic op, TR::InstOpCode::Mnemonic *rop)
{
switch (op)
{
case TR::InstOpCode::bdnz:
*rop = TR::InstOpCode::bdz;
return(false);
case TR::InstOpCode::bdz:
*rop = TR::InstOpCode::bdnz;
return(false);
case TR::InstOpCode::beq:
*rop = TR::InstOpCode::bne;
return(false);
case TR::InstOpCode::beql:
*rop = TR::InstOpCode::bne;
return(true);
case TR::InstOpCode::bge:
*rop = TR::InstOpCode::blt;
return(false);
case TR::InstOpCode::bgel:
*rop = TR::InstOpCode::blt;
return(true);
case TR::InstOpCode::bgt:
*rop = TR::InstOpCode::ble;
return(false);
case TR::InstOpCode::bgtl:
*rop = TR::InstOpCode::ble;
return(true);
case TR::InstOpCode::ble:
*rop = TR::InstOpCode::bgt;
return(false);
case TR::InstOpCode::blel:
*rop = TR::InstOpCode::bgt;
return(true);
case TR::InstOpCode::blt:
*rop = TR::InstOpCode::bge;
return(false);
case TR::InstOpCode::bltl:
*rop = TR::InstOpCode::bge;
return(true);
case TR::InstOpCode::bne:
*rop = TR::InstOpCode::beq;
return(false);
case TR::InstOpCode::bnel: