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OMRMemoryReference.cpp
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/*******************************************************************************
* Copyright IBM Corp. and others 2000
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at https://www.eclipse.org/legal/epl-2.0/
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] https://openjdk.org/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0-only WITH Classpath-exception-2.0 OR GPL-2.0-only WITH OpenJDK-assembly-exception-1.0
*******************************************************************************/
#include <stddef.h>
#include <stdint.h>
#include "codegen/AheadOfTimeCompile.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGeneratorUtils.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/Relocation.hpp"
#include "codegen/UnresolvedDataSnippet.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/Processors.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/StaticSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/List.hpp"
#include "p/codegen/GenerateInstructions.hpp"
#include "p/codegen/PPCAOTRelocation.hpp"
#include "p/codegen/PPCInstruction.hpp"
#include "p/codegen/PPCOpsDefines.hpp"
#include "p/codegen/PPCTableOfConstants.hpp"
#include "runtime/Runtime.hpp"
class TR_OpaqueClassBlock;
static TR::RealRegister::RegNum choose_rX(TR::Instruction *, TR::RealRegister *);
TR::MemoryReference *TR::MemoryReference::create(TR::CodeGenerator *cg)
{
return new (cg->trHeapMemory()) TR::MemoryReference(cg);
}
TR::MemoryReference *TR::MemoryReference::createWithLabel(TR::CodeGenerator *cg, TR::LabelSymbol *label, int64_t offset, int8_t length)
{
return new (cg->trHeapMemory()) TR::MemoryReference(label, offset, length, cg);
}
TR::MemoryReference *TR::MemoryReference::createWithIndexReg(TR::CodeGenerator *cg, TR::Register *baseReg, TR::Register *indexReg, uint8_t length)
{
return new (cg->trHeapMemory()) TR::MemoryReference(baseReg, indexReg, length, cg);
}
TR::MemoryReference *TR::MemoryReference::createWithDisplacement(TR::CodeGenerator *cg, TR::Register *baseReg, int64_t displacement, int8_t length)
{
return new (cg->trHeapMemory()) TR::MemoryReference(baseReg, displacement, length, cg);
}
TR::MemoryReference *TR::MemoryReference::createWithRootLoadOrStore(TR::CodeGenerator *cg, TR::Node *rootLoadOrStore, uint32_t length)
{
return new (cg->trHeapMemory()) TR::MemoryReference(rootLoadOrStore, length, cg);
}
TR::MemoryReference *TR::MemoryReference::createWithSymRef(TR::CodeGenerator *cg, TR::Node *node, TR::SymbolReference *symRef, uint32_t length)
{
return new (cg->trHeapMemory()) TR::MemoryReference(node, symRef, length, cg);
}
TR::MemoryReference *TR::MemoryReference::createWithMemRef(TR::CodeGenerator *cg, TR::Node *node, TR::MemoryReference& memRef, int32_t displacement, uint32_t length)
{
return new (cg->trHeapMemory()) TR::MemoryReference(node, memRef, displacement, length, cg);
}
OMR::Power::MemoryReference::MemoryReference(
TR::CodeGenerator *cg) :
_baseRegister(NULL),
_baseNode(NULL),
_indexRegister(NULL),
_indexNode(NULL),
_modBase(NULL), _length(0),
_staticRelocation(NULL),
_unresolvedSnippet(NULL),
_conditions(NULL),
_flag(0),
_label(NULL)
{
_symbolReference = new (cg->trHeapMemory()) TR::SymbolReference(cg->comp()->getSymRefTab());
_offset = _symbolReference->getOffset();
}
OMR::Power::MemoryReference::MemoryReference(
TR::LabelSymbol *label,
int64_t disp,
uint8_t len,
TR::CodeGenerator *cg) :
_baseRegister(NULL),
_baseNode(NULL),
_indexRegister(NULL),
_indexNode(NULL),
_modBase(NULL),
_unresolvedSnippet(NULL),
_staticRelocation(NULL),
_conditions(NULL),
_length(len),
_offset(disp),
_flag(0),
_label(label)
{
_symbolReference = new (cg->trHeapMemory()) TR::SymbolReference(cg->comp()->getSymRefTab());
}
OMR::Power::MemoryReference::MemoryReference(
TR::Register *br,
TR::Register *ir,
uint8_t len,
TR::CodeGenerator *cg) :
_baseRegister(br),
_baseNode(NULL),
_indexRegister(ir),
_indexNode(NULL),
_modBase(NULL),
_unresolvedSnippet(NULL),
_staticRelocation(NULL),
_conditions(NULL),
_length(len),
_flag(0),
_label(NULL)
{
_symbolReference = new (cg->trHeapMemory()) TR::SymbolReference(cg->comp()->getSymRefTab());
_offset = _symbolReference->getOffset();
}
OMR::Power::MemoryReference::MemoryReference(
TR::Register *br,
int64_t disp,
uint8_t len,
TR::CodeGenerator *cg) :
_baseRegister(br),
_baseNode(NULL),
_indexRegister(NULL),
_indexNode(NULL),
_modBase(NULL),
_unresolvedSnippet(NULL),
_staticRelocation(NULL),
_conditions(NULL),
_length(len),
_offset(disp),
_flag(0),
_label(NULL)
{
_symbolReference = new (cg->trHeapMemory()) TR::SymbolReference(cg->comp()->getSymRefTab());
}
//
// constructor called to generate a memory reference for all kinds of
// stores and non-constant(or address) loads
//
OMR::Power::MemoryReference::MemoryReference(TR::Node *rootLoadOrStore, uint32_t len, TR::CodeGenerator *cg)
: _baseRegister(NULL), _indexRegister(NULL), _unresolvedSnippet(NULL),
_modBase(NULL), _flag(0), _baseNode(NULL), _indexNode(NULL),
_symbolReference(rootLoadOrStore->getSymbolReference()), _offset(0),
_conditions(NULL), _length(len), _staticRelocation(NULL), _label(NULL)
{
TR::Compilation *comp = cg->comp();
TR::SymbolReference *ref = rootLoadOrStore->getSymbolReference();
TR::Symbol *symbol = ref->getSymbol();
bool isStore = rootLoadOrStore->getOpCode().isStore();
self()->checkRegisters(cg);
TR::MethodSymbol * methodSymbol = rootLoadOrStore->getSymbol()->getMethodSymbol();
if (rootLoadOrStore->getOpCode().isIndirect())
{
TR::Node *base = rootLoadOrStore->getFirstChild();
bool isLocalObject = ((base->getOpCodeValue() == TR::loadaddr) &&
base->getSymbol()->isLocalObject());
if (!ref->isUnresolved() && isLocalObject)
{
_baseRegister = cg->getStackPointerRegister();
_symbolReference = base->getSymbolReference();
self()->checkRegisters(cg);
_baseNode = base;
}
else
{
if (ref->isUnresolved())
{
// Stack late mapping forces us to evaluate local object's base into a register
// rather than getting the stack pointer as the base which is not correct.
if (isLocalObject)
cg->evaluate(base);
self()->setUnresolvedSnippet(new (cg->trHeapMemory()) TR::UnresolvedDataSnippet(cg, rootLoadOrStore, ref, isStore, false));
cg->addSnippet(self()->getUnresolvedSnippet());
}
// if an aconst feeds a iaload, we need to load the constant
if (base->getOpCode().isLoadConst())
{
cg->evaluate(base);
}
if (symbol->isMethodMetaData())
{
_baseRegister = cg->getMethodMetaDataRegister();
}
self()->populateMemoryReference(base, cg);
}
}
else
{
if (symbol->isStatic())
{
self()->accessStaticItem(rootLoadOrStore, ref, isStore, cg);
}
else
{
if (!symbol->isMethodMetaData())
{ // must be either auto or parm or error.
_baseRegister = cg->getStackPointerRegister();
}
else
{
_baseRegister = cg->getMethodMetaDataRegister();
}
}
}
if (cg->comp()->target().is32Bit() || !symbol->isConstObjectRef())
self()->addToOffset(rootLoadOrStore, ref->getOffset(), cg);
if (self()->getUnresolvedSnippet() != NULL)
self()->adjustForResolution(cg);
// TODO: aliasing sets?
}
OMR::Power::MemoryReference::MemoryReference(TR::Node *node, TR::SymbolReference *symRef, uint32_t len, TR::CodeGenerator *cg)
: _baseRegister(NULL), _indexRegister(NULL), _unresolvedSnippet(NULL),
_modBase(NULL), _flag(0), _baseNode(NULL), _indexNode(NULL),
_symbolReference(symRef), _offset(0),
_conditions(NULL), _length(len), _staticRelocation(NULL), _label(NULL)
{
TR::Symbol *symbol = symRef->getSymbol();
if (symbol->isStatic())
{
self()->accessStaticItem(node, symRef, false, cg);
}
if (symbol->isRegisterMappedSymbol())
{
if (!symbol->isMethodMetaData())
{ // must be either auto or parm or error.
_baseRegister = cg->getStackPointerRegister();
}
else
{
_baseRegister = cg->getMethodMetaDataRegister();
}
}
if (cg->comp()->target().is32Bit() || !symbol->isConstObjectRef())
self()->addToOffset(0, symRef->getOffset(), cg);
if (self()->getUnresolvedSnippet() != NULL)
self()->adjustForResolution(cg);
// TODO: aliasing sets?
}
OMR::Power::MemoryReference::MemoryReference(TR::Node *node, TR::MemoryReference& mr, int32_t displacement, uint32_t len, TR::CodeGenerator *cg)
{
_baseRegister = mr._baseRegister;
_baseNode = NULL;
_indexRegister = mr._indexRegister;
_indexNode = NULL;
_modBase = mr._modBase;
_symbolReference = mr._symbolReference;
_offset = mr.getOffset();
_flag = 0;
_length = len;
_staticRelocation = NULL;
_conditions = NULL;
mr._flag = 0;
_label = mr._label;
TR_ASSERT(mr.getStaticRelocation() == NULL, "Relocated memory reference should not be re-used.");
if (mr.getUnresolvedSnippet() != NULL)
{
_unresolvedSnippet = new (cg->trHeapMemory()) TR::UnresolvedDataSnippet(cg, node, _symbolReference, mr.getUnresolvedSnippet()->isUnresolvedStore(), false);
cg->addSnippet(_unresolvedSnippet);
self()->adjustForResolution(cg);
}
else
{
_unresolvedSnippet = NULL;
}
self()->addToOffset(0, displacement, cg);
}
bool OMR::Power::MemoryReference::useIndexedForm()
{
return((_indexRegister==NULL && !self()->isUsingDelayedIndexedForm()) ? false : true );
}
bool OMR::Power::MemoryReference::isTOCAccess()
{
// TODO: add checking for other type of TOC usages.
return(self()->isUsingStaticTOC());
}
int32_t OMR::Power::MemoryReference::getTOCOffset()
{
// TODO: add checking for other type of TOC usages.
if (self()->isUsingStaticTOC())
{
return _symbolReference->getSymbol()->getStaticSymbol()->getTOCIndex() * sizeof(intptr_t);
}
return 0;
}
void OMR::Power::MemoryReference::addToOffset(TR::Node * node, int64_t amount, TR::CodeGenerator *cg)
{
// in compressedRefs mode, amount maybe heapBase constant, which in
// most cases is quite large
//
TR::Compilation *comp = cg->comp();
if (self()->getUnresolvedSnippet() != NULL &&
(amount > LOWER_IMMED && amount < UPPER_IMMED))
{
self()->setOffset(self()->getOffset() + amount);
return;
}
if (amount == 0)
return;
if (_baseRegister!=NULL && _indexRegister!=NULL)
{
self()->consolidateRegisters(NULL, NULL, false, cg);
}
int64_t displacement = self()->getOffset() + amount;
if (((displacement<LOWER_IMMED || displacement>UPPER_IMMED) && !cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P10)) ||
(displacement < LOWER_IMMED_34 || displacement > UPPER_IMMED_34))
{
TR::Register *newBase;
intptr_t upper, lower;
self()->setOffset(0);
lower = (intptr_t)LO_VALUE(displacement);
upper = HI_VALUE(displacement);
if (_baseRegister!=NULL && self()->isBaseModifiable())
newBase = _baseRegister;
else
{
newBase = cg->allocateRegister();
if (_baseRegister && _baseRegister->containsInternalPointer())
{
newBase->setContainsInternalPointer();
newBase->setPinningArrayPointer(_baseRegister->getPinningArrayPointer());
}
}
if (!node)
node = cg->getAppendInstruction()->getNode();
if (_baseRegister != NULL)
{
if (node->getOpCode().isLoadConst() && node->getRegister())
{
generateTrg1Src2Instruction(cg, TR::InstOpCode::add, node, newBase, _baseRegister, node->getRegister());
}
else
{
if (cg->comp()->target().is64Bit() && (upper<LOWER_IMMED || upper>UPPER_IMMED))
{
TR::Register *tempReg = cg->allocateRegister();
loadActualConstant(cg, node, upper<<16, tempReg);
generateTrg1Src2Instruction(cg, TR::InstOpCode::add, node, newBase, _baseRegister, tempReg);
cg->stopUsingRegister(tempReg);
}
else
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, newBase, _baseRegister, (int16_t)upper);
if (lower != 0)
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi2, node, newBase, newBase, lower);
}
}
else
loadActualConstant(cg, node, displacement, newBase);
// the following "if" is just to avoid stopUsingRegister being called
// for newBase by decNodeReferenceCounts(cg);
if (_baseRegister == newBase && _baseNode == NULL) _baseRegister = NULL;
self()->decNodeReferenceCounts(cg);
_baseRegister = newBase;
_baseNode = NULL;
self()->setBaseModifiable();
}
else
{
self()->setOffset(displacement);
}
}
void OMR::Power::MemoryReference::forceIndexedForm(TR::Node * node, TR::CodeGenerator *cg, TR::Instruction *cursor)
{
if (self()->useIndexedForm())
return; // already X-form
TR_ASSERT(!self()->isTOCAccess(), "X-form TOC access not supported");
if (self()->getUnresolvedSnippet() != NULL)
{
// nothing to do except force an X-form at binary encoding time
self()->setUsingDelayedIndexedForm();
return;
}
if (self()->hasDelayedOffset())
{
self()->setUsingDelayedIndexedForm();
if (!self()->isBaseModifiable())
{
_indexRegister = cg->allocateRegister(); // for encoding time use
self()->setIndexModifiable();
}
return;
}
// true displacement available now
intptr_t displacement = self()->getOffset();
if (displacement == 0)
{
// force use of gr0 as RA in addressing
_indexRegister = _baseRegister;
_indexNode = _baseNode;
if (self()->isBaseModifiable())
{
self()->setIndexModifiable();
self()->clearBaseModifiable();
}
_baseRegister = NULL;
_baseNode = NULL;
return;
}
// load displacement into a register, make it the index
self()->setOffset(0);
TR::Register *newIndex = cg->allocateRegister();
if (!cursor)
cursor = cg->getAppendInstruction();
if (!node)
node = cursor->getNode();
loadActualConstant(cg, node, displacement, newIndex, cursor);
_indexRegister = newIndex;
_indexNode = NULL;
self()->setIndexModifiable();
cg->stopUsingRegister(newIndex);
}
void OMR::Power::MemoryReference::adjustForResolution(TR::CodeGenerator *cg)
{
_modBase = cg->allocateRegister();
_conditions = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(1, 1, cg->trMemory());
TR::addDependency(_conditions, _modBase, TR::RealRegister::gr11, TR_GPR, cg);
}
void OMR::Power::MemoryReference::decNodeReferenceCounts(TR::CodeGenerator *cg)
{
if (_baseRegister != NULL)
{
if (_baseNode != NULL)
{
cg->decReferenceCount(_baseNode);
}
else
cg->stopUsingRegister(_baseRegister);
}
if (_indexRegister != NULL)
{
if (_indexNode != NULL)
cg->decReferenceCount(_indexNode);
else
cg->stopUsingRegister(_indexRegister);
}
if (_modBase != NULL)
cg->stopUsingRegister(_modBase);
}
void OMR::Power::MemoryReference::bookKeepingRegisterUses(TR::Instruction *instr, TR::CodeGenerator *cg)
{
if (_baseRegister != NULL)
{
instr->useRegister(_baseRegister);
}
if (_indexRegister != NULL)
{
instr->useRegister(_indexRegister);
}
if (_modBase != NULL)
{
instr->useRegister(_modBase);
_conditions->bookKeepingRegisterUses(instr, cg);
}
}
static bool isLoadConstAndShift(TR::Node *subTree, TR::CodeGenerator *cg)
{
if (cg->comp()->target().is64Bit())
{
if (subTree->getOpCodeValue() == TR::lshl)
{
// lshl
// lconst
// iconst
if (subTree->getFirstChild()->getOpCode().isLoadConst() &&
subTree->getSecondChild()->getOpCode().isLoadConst())
return true;
// lshl
// i2l
// iconst
// iconst
else if (subTree->getFirstChild()->getOpCodeValue() == TR::i2l &&
subTree->getFirstChild()->getFirstChild()->getOpCode().isLoadConst() &&
subTree->getSecondChild()->getOpCode().isLoadConst())
return true;
else
return false;
}
else
return false;
}
else // 32-bit
{
if (subTree->getOpCodeValue() == TR::ishl &&
subTree->getFirstChild()->getOpCode().isLoadConst() &&
subTree->getSecondChild()->getOpCode().isLoadConst())
return true;
else
return false;
}
}
void OMR::Power::MemoryReference::populateMemoryReference(TR::Node *subTree, TR::CodeGenerator *cg)
{
if (cg->comp()->useCompressedPointers())
{
if ((subTree->getOpCodeValue() == TR::l2a) &&
(subTree->getReferenceCount() == 1) &&
(subTree->getRegister() == NULL) &&
!self()->getUnresolvedSnippet()) // If there is unresolved data snippet, l2a cannot be skipped
{
cg->decReferenceCount(subTree);
subTree = subTree->getFirstChild();
}
}
// Skip sign extension if the offset is known to be >= 0; this is only safe to do if the child is the result of a load, otherwise the upper 32 bits may be undefined
if (subTree->getOpCodeValue() == TR::i2l && subTree->isNonNegative() && subTree->getFirstChild()->getOpCode().isLoadVar() && subTree->getReferenceCount() == 1 && subTree->getRegister() == NULL)
{
if (performTransformation(cg->comp(), "O^O PPC Evaluator: Skip unecessary sign extension on index [%p].\n", subTree))
{
static bool dontSkipIndexSignExt = feGetEnv("TR_dontSkipIndexSignExt") != NULL;
if (!dontSkipIndexSignExt)
{
cg->decReferenceCount(subTree);
subTree = subTree->getFirstChild();
}
}
}
if (subTree->getReferenceCount()>1 || subTree->getRegister()!=NULL)
{
if (_baseRegister != NULL)
{
self()->consolidateRegisters(cg->evaluate(subTree), subTree, false, cg);
}
else
{
_baseRegister = cg->evaluate(subTree);
_baseNode = subTree;
}
}
else
{
if (subTree->getOpCode().isArrayRef() ||
(subTree->getOpCodeValue() == TR::iadd || subTree->getOpCodeValue() == TR::ladd))
{
TR::Node *addressChild = subTree->getFirstChild();
TR::Node *integerChild = subTree->getSecondChild();
if (integerChild->getOpCode().isLoadConst())
{
self()->populateMemoryReference(addressChild, cg);
if (cg->comp()->target().is64Bit())
{
int64_t amount = (integerChild->getOpCodeValue() == TR::iconst) ?
integerChild->getInt() :
integerChild->getLongInt();
self()->addToOffset(integerChild, amount, cg);
}
else
self()->addToOffset(subTree, integerChild->getInt(), cg);
cg->decReferenceCount(integerChild);
}
else if (integerChild->getEvaluationPriority(cg)>addressChild->getEvaluationPriority(cg) &&
!(subTree->getOpCode().isArrayRef() && cg->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6)))
{
self()->populateMemoryReference(integerChild, cg);
self()->populateMemoryReference(addressChild, cg);
}
else
{
self()->populateMemoryReference(addressChild, cg);
self()->populateMemoryReference(integerChild, cg);
}
cg->decReferenceCount(subTree);
}
else if (isLoadConstAndShift(subTree, cg))
{
if (cg->comp()->target().is64Bit())
{ // 64-bit
int64_t amount = (subTree->getSecondChild()->getOpCodeValue() == TR::iconst) ?
subTree->getSecondChild()->getInt() :
subTree->getSecondChild()->getLongInt();
// lshl
// lconst
// iconst(lconst)
if (subTree->getFirstChild()->getOpCode().isLoadConst())
self()->addToOffset(subTree, subTree->getFirstChild()->getLongInt() << amount, cg);
else
// lshl
// i2l
// iconst
// iconst(lconst)
{
self()->addToOffset(subTree, subTree->getFirstChild()->getFirstChild()->getInt() << amount,
cg);
cg->decReferenceCount(subTree->getFirstChild()->getFirstChild());
}
}
else
self()->addToOffset(subTree, subTree->getFirstChild()->getInt() <<
subTree->getSecondChild()->getInt(), cg);
cg->decReferenceCount(subTree->getFirstChild());
cg->decReferenceCount(subTree->getSecondChild());
}
else if ((subTree->getOpCodeValue() == TR::loadaddr) && !cg->comp()->compileRelocatableCode())
{
TR::SymbolReference *ref = subTree->getSymbolReference();
TR::Symbol *symbol = ref->getSymbol();
bool isStore = subTree->getOpCode().isStore();
_symbolReference = ref;
self()->checkRegisters(cg);
if (symbol->isStatic())
{
self()->accessStaticItem(subTree, ref, isStore, cg);
}
if (symbol->isRegisterMappedSymbol())
{
if (_baseRegister != NULL)
{
TR::Register *tempReg;
if (!symbol->isMethodMetaData())
{ // must be either auto or parm or error.
tempReg = cg->getStackPointerRegister();
}
else
{
tempReg = cg->getMethodMetaDataRegister();
}
self()->consolidateRegisters(tempReg, NULL, false, cg);
}
else
{
if (!symbol->isMethodMetaData())
{ // must be either auto or parm or error.
_baseRegister = cg->getStackPointerRegister();
}
else
{
_baseRegister = cg->getMethodMetaDataRegister();
}
_baseNode = NULL;
}
}
if (cg->comp()->target().is32Bit() || !symbol->isConstObjectRef())
self()->addToOffset(subTree, subTree->getSymbolReference()->getOffset(), cg);
// TODO: aliasing sets?
cg->decReferenceCount(subTree); // need to decrement ref count because
// nodes weren't set on memoryreference
}
else if (subTree->getOpCodeValue() == TR::aconst ||
subTree->getOpCodeValue() == TR::iconst || // subTree->getOpCode().isLoadConst ?
subTree->getOpCodeValue() == TR::lconst)
{
int64_t amount = (subTree->getOpCodeValue() == TR::iconst) ?
subTree->getInt() : subTree->getLongInt();
self()->addToOffset(subTree, amount, cg);
}
else
{
if (_baseRegister != NULL)
{
self()->consolidateRegisters(cg->evaluate(subTree), subTree, cg->canClobberNodesRegister(subTree), cg);
}
else
{
_baseRegister = cg->evaluate(subTree);
_baseNode = subTree;
if (cg->canClobberNodesRegister(subTree)) self()->setBaseModifiable();
}
}
}
}
void OMR::Power::MemoryReference::consolidateRegisters(TR::Register *srcReg, TR::Node *srcTree, bool srcModifiable, TR::CodeGenerator *cg)
{
TR::Register *tempTargetRegister;
TR::Compilation *comp = cg->comp();
TR::Node *tempNode = (srcTree==NULL)?cg->getAppendInstruction()->getNode():srcTree;
if (self()->getUnresolvedSnippet() != NULL)
{
if (srcReg == NULL)
return;
if (_indexRegister != NULL)
{
if (self()->isIndexModifiable())
tempTargetRegister = _indexRegister;
else if ((srcReg && (srcReg->containsCollectedReference() || srcReg->containsInternalPointer())) ||
(_indexRegister && (_indexRegister->containsCollectedReference() || _indexRegister->containsInternalPointer())))
{
if (srcTree!=NULL && srcTree->isInternalPointer() &&
srcTree->getPinningArrayPointer())
{
tempTargetRegister = cg->allocateRegister();
tempTargetRegister->setContainsInternalPointer();
tempTargetRegister->setPinningArrayPointer(srcTree->getPinningArrayPointer());
}
else
tempTargetRegister = cg->allocateCollectedReferenceRegister();
}
else
{
tempTargetRegister = cg->allocateRegister();
}
generateTrg1Src2Instruction(cg, TR::InstOpCode::add, tempNode, tempTargetRegister, _indexRegister, srcReg);
if (_indexRegister != tempTargetRegister)
{
if (_indexNode != NULL)
cg->decReferenceCount(_indexNode);
else
cg->stopUsingRegister(_indexRegister);
_indexNode = NULL;
}
if (srcTree != NULL)
cg->decReferenceCount(srcTree);
else
cg->stopUsingRegister(srcReg);
_indexRegister = tempTargetRegister;
self()->setIndexModifiable();
}
else
{
_indexRegister = srcReg;
_indexNode = srcTree;
if (srcModifiable)
self()->setIndexModifiable();
else
self()->clearIndexModifiable();
}
}
else
{
if (_indexRegister != NULL)
{
if (self()->isBaseModifiable())
tempTargetRegister = _baseRegister;
else if ((_baseRegister && (_baseRegister->containsCollectedReference() || _baseRegister->containsInternalPointer())) ||
(_indexRegister && (_indexRegister->containsCollectedReference() || _indexRegister->containsInternalPointer())))
{
if (srcTree!=NULL && srcTree->isInternalPointer() &&
srcTree->getPinningArrayPointer())
{
tempTargetRegister = cg->allocateRegister();
tempTargetRegister->setContainsInternalPointer();
tempTargetRegister->setPinningArrayPointer(srcTree->getPinningArrayPointer());
}
else
tempTargetRegister = cg->allocateCollectedReferenceRegister();
}
else
{
tempTargetRegister = cg->allocateRegister();
}
generateTrg1Src2Instruction(cg, TR::InstOpCode::add, tempNode, tempTargetRegister, _baseRegister, _indexRegister);
if (_baseRegister != tempTargetRegister)
{
self()->decNodeReferenceCounts(cg);
_baseNode = NULL;
}
else
{
if (_indexNode != NULL)
cg->decReferenceCount(_indexNode);
else
cg->stopUsingRegister(_indexRegister);
}
_baseRegister = tempTargetRegister;
self()->setBaseModifiable();
}
else if (srcReg!=NULL && (self()->getOffset(*comp)!=0 || self()->hasDelayedOffset()))
{
if (self()->isBaseModifiable())
tempTargetRegister = _baseRegister;
else if (srcModifiable)
tempTargetRegister = srcReg;
else if ((srcReg && (srcReg->containsCollectedReference() || srcReg->containsInternalPointer())) ||
(_baseRegister && (_baseRegister->containsCollectedReference() || _baseRegister->containsInternalPointer())))
{
if (srcTree!=NULL && srcTree->isInternalPointer() &&
srcTree->getPinningArrayPointer())
{
tempTargetRegister = cg->allocateRegister();
tempTargetRegister->setContainsInternalPointer();
tempTargetRegister->setPinningArrayPointer(srcTree->getPinningArrayPointer());
}
else
tempTargetRegister = cg->allocateCollectedReferenceRegister();
}
else
{
tempTargetRegister = cg->allocateRegister();
}
generateTrg1Src2Instruction(cg, TR::InstOpCode::add, tempNode, tempTargetRegister, _baseRegister, srcReg);
if (_baseRegister != tempTargetRegister)
{
self()->decNodeReferenceCounts(cg);
_baseNode = NULL;
}
if (srcReg == tempTargetRegister)
{
self()->decNodeReferenceCounts(cg);
_baseNode = srcTree;
}
else
{
if (srcTree != NULL)
cg->decReferenceCount(srcTree);
else
cg->stopUsingRegister(srcReg);
}
_baseRegister = tempTargetRegister;
self()->setBaseModifiable();
srcReg=NULL;
srcTree=NULL;
srcModifiable=false;
}
_indexRegister = srcReg;
_indexNode = srcTree;
if (srcModifiable)
self()->setIndexModifiable();
else
self()->clearIndexModifiable();
}
}
void OMR::Power::MemoryReference::assignRegisters(TR::Instruction *currentInstruction, TR::CodeGenerator *cg)
{
TR::Machine *machine = cg->machine();
TR::RealRegister *assignedBaseRegister;
TR::RealRegister *assignedIndexRegister;
if (_modBase != NULL)
{
if (_baseRegister != NULL)
{
_baseRegister->block();
}
if (_indexRegister != NULL)
{
_indexRegister->block();
}
_conditions->assignPostConditionRegisters(currentInstruction, _modBase->getKind(), cg);
_conditions->assignPreConditionRegisters(currentInstruction->getPrev(), _modBase->getKind(), cg);
if (_baseRegister != NULL)
{
_baseRegister->unblock();
}
if (_indexRegister != NULL)
{
_indexRegister->unblock();
}
}
if (_baseRegister != NULL)
{
assignedBaseRegister = _baseRegister->getAssignedRealRegister();
if (_indexRegister != NULL)
{
_indexRegister->block();
}
if (_modBase != NULL)
{
_modBase->block();
}
if ((assignedBaseRegister != NULL) &&
(toRealRegister(assignedBaseRegister)->getRegisterNumber() ==
TR::RealRegister::gr0))
{
TR::RealRegister *alternativeRegister;
if ((alternativeRegister = machine->findBestFreeRegister(currentInstruction, TR_GPR, true, false, _baseRegister)) == NULL)
{
alternativeRegister = machine->freeBestRegister(currentInstruction, _baseRegister, NULL, true);
}
machine->coerceRegisterAssignment(currentInstruction, _baseRegister, toRealRegister(alternativeRegister)->getRegisterNumber());
assignedBaseRegister = alternativeRegister;
}
else
{
if (assignedBaseRegister == NULL)
{
assignedBaseRegister = machine->assignOneRegister(currentInstruction, _baseRegister, true);
}
}
if (_indexRegister != NULL)
{
_indexRegister->unblock();
}
if (_modBase != NULL)
{
_modBase->unblock();
}
}
if (_indexRegister != NULL)
{
if (_baseRegister != NULL)
{
_baseRegister->block();
}
if (_modBase != NULL)
{
_modBase->block();
}